Light emitting diode chip and preparation method thereof

Abstract

The invention provides a preparation method of a light-emitting diode chip, and the preparation method comprises the steps: providing a sapphire substrate, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer on the sapphire substrate as epitaxial layers; preparing an N-type semiconductor layer conductive step on the P-type semiconductor layer; preparing a current expansion layer on the P-type semiconductor layer; preparing a current blocking layer on the current expansion layer, and then preparing a current blocking layer through hole in the current blocking layer; preparing a first semiconductor layer on the current blocking layer; the sapphire substrate is thinned, then the thinned sapphire substrate is peeled off through laser, and PSS on the bottom of the N-type semiconductor layer is exposed; preparing an isolation groove on the PSS at the bottom of the N-type semiconductor layer; preparing a second insulating layer on the PSS at the bottom of the N-type semiconductor layer; and preparing a second insulating layer through hole on the second insulating layer, and then preparing a P-type bonding pad on the second insulating layer through hole.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a light emitting diode chip and a preparation method thereof. BACKGROUND

[0002] The light emitting diode chip is widely used in the fields of lighting and display with energy saving and high efficiency, and many aspects thereof involve the application of great power, such as outdoor lighting and automobile lighting, etc. The light emitting diode chip of great power needs to apply a vertical structure light emitting diode chip.

[0003] In the prior art, the existing vertical structure light emitting diode chip preparation process needs to use an inductively coupled plasma etching process to etch an epitaxial layer to prepare an isolation groove. However, in the process of preparing the isolation groove, after laser peeling, the PSS wave peak and the PSS wave valley will form a pit due to the depth difference. The existing etching method will copy the pit caused by the depth difference between the PSS wave peak and the PSS wave valley to the current blocking layer. If the depth difference between the PSS wave peak and the PSS wave valley is too large, it will cause over-etching of the current blocking layer. The etching ions will react with the metal layer below the current blocking layer, causing the light emitting diode chip to fail. The existing solution to the above problem is to thicken the thickness of the current blocking layer. However, this will reduce the luminous brightness of the light emitting diode chip. SUMMARY

[0004] Therefore, the present application aims to provide a light emitting diode chip and a preparation method thereof, which can effectively solve the above problems in the prior art.

[0005] A preparation method of a light emitting diode chip, the preparation method comprising: S1, providing a sapphire substrate, depositing an N-type semiconductor layer, an active light emitting layer and a P-type semiconductor layer as an epitaxial layer on the sapphire substrate in sequence; S2, preparing an N-type semiconductor layer conductive step on the P-type semiconductor layer; S3, preparing a current spreading layer on the P-type semiconductor layer; S4, preparing a current blocking layer on the current spreading layer, the P-type semiconductor layer not covered by the current spreading layer and the N-type semiconductor layer conductive step not covered by the current spreading layer, and then preparing a current blocking layer via on the current blocking layer; S5, preparing a first semiconductor layer on the current blocking layer and the current blocking layer via; S6, thinning the sapphire substrate, and then laser peeling the thinned sapphire substrate to expose the PSS on the bottom of the N-type semiconductor layer; S7, coating photoresist on the PSS at the bottom of the N-type semiconductor layer, then exposing and developing to remove part of the photoresist, exposing the PSS of the removed photoresist, and then removing the exposed PSS and the epitaxial layer under the PSS by using a first inductively coupled plasma etching process to form an isolation groove; The first inductively coupled plasma etching process comprises a first etching step, a second etching step, a third etching step, a fourth etching step, and a fifth etching step for increasing the material etching selectivity ratio. The etching upper power SRF and the etching lower power BRF of the first etching step are both greater than the etching upper power SRF and the etching lower power BRF of the second etching step. The ratio of the etching upper power SRF to the etching lower power BRF of the first etching step is less than the ratio of the etching upper power SRF to the etching lower power BRF of the second etching step. The etching upper power SRF and the etching lower power BRF of the third etching step are both greater than the etching upper power SRF and the etching lower power BRF of the fourth etching step. The ratio of the etching upper power SRF to the etching lower power BRF of the third etching step is less than the ratio of the etching upper power SRF to the etching lower power BRF of the fourth etching step. The difference between the ratio of the etching upper power SRF to the etching lower power BRF of the first etching step and the ratio of the etching upper power SRF to the etching lower power BRF of the second etching step is less than the difference between the ratio of the etching upper power SRF to the etching lower power BRF of the third etching step and the ratio of the etching upper power SRF to the etching lower power BRF of the fourth etching step. S8, preparing a second insulating layer on the PSS at the bottom of the N-type semiconductor layer, the current blocking layer, and the isolation groove; S9, preparing a second insulating layer via hole on the second insulating layer, and then preparing a P-type pad on the second insulating layer via hole; Further, in the first etching step, the etching upper power SRF of the first etching step is 1000W-1200W, the etching lower power BRF of the first etching step is 800W-1000W, the ratio S / B of the etching upper power SRF to the etching lower power BRF of the first etching step is 1-1.5, and the etching time of the first etching step is 100S-150S.

[0006] Further, in the second etching step, the upper power SRF of the second etching step is 400W-600W, the lower power BRF of the second etching step is 100W-150W, the ratio S / B of the upper power SRF of the second etching step to the lower power BRF of the second etching step is 4-6, the etching time of the second etching step is determined by the etching depth, and the total depth etched by the first etching step and the second etching step is 20%-30% of the entire isolation groove depth.

[0007] Further, the difference between the ratio of the upper power SRF to the lower power BRF of the first etching step and the ratio of the upper power SRF to the lower power BRF of the second etching step is greater than or equal to 3.

[0008] Further, in the third etching step, the upper power SRF of the third etching step is 1000W-1200W, the lower power BRF of the third etching step is 800W-1000W, the ratio S / B of the upper power SRF of the third etching step to the lower power BRF of the third etching step is 1-1.5, and the etching time of the third etching step is 100S-150S.

[0009] Further, in the fourth etching step, the upper power SRF of the fourth etching step is 200W-400W, the lower power BRF of the fourth etching step is 30W-50W, the ratio S / B of the upper power SRF of the fourth etching step to the lower power BRF of the fourth etching step is 6-8, the etching time of the fourth etching step is determined by the etching depth, and the total depth etched by the third etching step and the fourth etching step is 60%-65% of the entire isolation groove depth. Further, the difference between the ratio of the upper power SRF to the lower power BRF of the third etching step and the ratio of the upper power SRF to the lower power BRF of the fourth etching step is greater than or equal to 5.

[0010] Further, in the fifth etching step, the upper power SRF of the fifth etching step is 100W-300W, the lower power BRF of the fifth etching step is 30W-100W, the ratio S / B of the upper power of the fifth etching step to the lower power of the fifth etching step is 3-4, and the depth etched by the fifth etching step is 5%-20% of the entire isolation groove depth.

[0011] Further, the first semiconductor layer comprises a P-type reflective metal layer, a P-type conductive metal layer, a first insulating layer, a first insulating layer via, an N-type conductive metal layer, a first bonding layer, a second bonding layer and a conductive silicon wafer arranged in sequence on the current blocking layer.

[0012] The application further provides a light emitting diode chip prepared by the preparation method of the light emitting diode chip.

[0013] Compared with the prior art, the application has the following beneficial effects: In the first etching step, the etching up power SRF and the etching down power BRF of the first etching step are both greater than the etching up power SRF and the etching down power BRF of the second etching step, and the ratio of the etching up power SRF to the etching down power BRF of the first etching step is less than the ratio of the etching up power SRF to the etching down power BRF of the second etching step, so that the etching has a good bombardment effect, the bombardment effect on the PSS wave peak position is much greater than the bombardment effect on the PSS wave valley position, and the depth difference between the PSS wave peak and the PSS wave valley is reduced. In the second etching step, the etching up power SRF and the etching down power BRF of the second etching step are both less than the etching up power SRF and the etching down power BRF of the second etching step, and the ratio of the etching up power SRF to the etching down power BRF of the second etching step is greater than the ratio of the etching up power SRF to the etching down power BRF of the second etching step, so that the etching power is reduced and the ratio of the etching up power to the etching down power is increased, thereby the etching rate of the PSS wave peak is greater than the etching rate of the PSS wave valley, and the depth difference between the PSS wave peak and the PSS wave valley is further reduced. In the third etching step, the etching up power SRF and the etching down power BRF of the third etching step are both greater than the etching up power SRF and the etching down power BRF of the fourth etching step, and the ratio of the etching up power SRF to the etching down power BRF of the third etching step is less than the ratio of the etching up power SRF to the etching down power BRF of the fourth etching step, so that the third etching step has the same effect as the first etching step. In the fourth etching step, the etching up power SRF and the etching down power BRF of the third etching step are both less than the etching up power SRF and the etching down power BRF of the fourth etching step, and the ratio of the etching up power SRF to the etching down power BRF of the second etching step is greater than the ratio of the etching up power SRF to the etching down power BRF of the second etching step, so that the fourth etching step has the same effect as the second etching step. The difference between the ratio of etching up power SRF to etching down power BRF in the first etching step and the ratio of etching up power SRF to etching down power BRF in the second etching step is smaller than the difference between the ratio of etching up power SRF to etching down power BRF in the third etching step and the ratio of etching up power SRF to etching down power BRF in the fourth etching step, thus achieving better results. After the first, second, third and fourth etching steps are completed, the PSS peak is completely eliminated and the PSS peak and PSS valley are located on the same horizontal plane. This can avoid the reaction between the etching ions and the metal layer under the current blocking layer caused by the large depth difference between the PSS peak and PSS valley, which would cause the light-emitting diode chip to fail. The fifth etching step increases the etching selectivity ratio of SiO2 and GaN materials, meaning that the etching parameters for SiO2 are much higher than those for GaN. This further reduces the over-etching of the current blocking layer caused by the preparation of the isolation trench, thus eliminating the need to thicken the current blocking layer and avoiding a decrease in the luminous brightness of the LED chip. Attached Figure Description

[0014] Fig. 1 This is a flowchart of the fabrication method of the light-emitting diode chip in Embodiment 1 of the present invention; Fig. 2 This is a cross-sectional schematic diagram of the light-emitting diode chip in Embodiment 1 of the present invention; Fig. 3 This is a cross-sectional schematic diagram of the semi-finished product after completing step S2 in Embodiment 1 of the present invention; Explanation of key component symbols:

[0015] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0016] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0017] It should be understood that when an element as a layer, region or plate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In addition, it should be understood that when an element is referred to as being "connected" to or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] Embodiment 1 Referring to Figs. 1-3 The preparation method of the LED chip in the embodiment of the application comprises the following steps: S1, providing a sapphire substrate 10, and sequentially depositing an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113 as an epitaxial layer 11 on the sapphire substrate 10; S2, preparing an N-type semiconductor layer conductive step 114 on the P-type semiconductor layer 113; In the embodiment, the specific steps for preparing the N-type semiconductor layer conductive step 114 include: applying photoresist on the surface of the P-type semiconductor layer 113, then removing part of the photoresist by exposure and development to expose part of the P-type semiconductor layer, then removing the exposed P-type semiconductor layer and the active light-emitting layer under the P-type semiconductor layer by a second inductively coupled plasma etching process until the N-type semiconductor layer is exposed to form the N-type semiconductor layer conductive step 114, and then removing the excess photoresist.

[0020] S3, preparing a current spreading layer 12 on the P-type semiconductor layer 113; In the embodiment, the specific steps for preparing the current spreading layer 12 include: applying photoresist on the surface of the P-type semiconductor layer 113, then removing part of the photoresist by exposure and development to expose part of the P-type semiconductor layer, then removing the exposed P-type semiconductor layer and the active light-emitting layer under the P-type semiconductor layer by a second inductively coupled plasma etching process until the N-type semiconductor layer is exposed to form the N-type semiconductor layer conductive step 114, and then removing the excess photoresist.

[0021] S4, a current blocking layer 13 is prepared on the current spreading layer 12, the conductive steps of the P-type semiconductor layer not covered by the current spreading layer 12 and the N-type semiconductor layer not covered by the current spreading layer 12, and then a current blocking layer via hole 131 is prepared on the current blocking layer 13; Specifically in the embodiment, the specific steps of preparing the current blocking layer 13 and the current blocking layer via hole 131 include: SiO2 is deposited as the current blocking layer 13 on the current spreading layer 12, the conductive steps of the P-type semiconductor layer not covered by the current spreading layer 12 and the N-type semiconductor layer not covered by the current spreading layer 12 by using a PECVD process, and then photoresist is coated on the surface of the current blocking layer 13, and then part of the photoresist is removed by using exposure and development to expose the current blocking layer under the photoresist, and then the exposed current blocking layer is removed by using a BOE etching solution to form the current blocking layer via hole 131, and then the photoresist is removed.

[0022] S5, a first semiconductor layer is prepared on the current blocking layer 13 and the current blocking layer via hole 131. Further, the first semiconductor layer includes a P-type reflective metal layer 14, a P-type conductive metal layer 15, a first insulating layer 16, a first insulating layer via hole 161, an N-type conductive metal layer 17, a first bonding layer 181, a second bonding layer 182 and a conductive silicon wafer 19 which are sequentially arranged on the current blocking layer 13.

[0023] Specifically in the embodiment, the specific steps of preparing the P-type reflective metal layer 14 include: Negative photoresist is coated on the surface of the current blocking layer via hole 131 and the current blocking layer 13, and then part of the photoresist is removed by using exposure and development, and then Ag metal with a thickness of 1500Å-2000Å, Ni metal with a thickness of 300Å-500Å and Ti metal with a thickness of 300Å-500Å are sequentially evaporated by using an electron beam evaporation process, and then the metal on the photoresist is removed by using a lift-Off process, and then the photoresist is removed to form the P-type reflective metal layer 14.

[0024] Specifically in the embodiment, the specific steps of preparing the P-type conductive metal layer 15 include: The P-type conductive metal layer 15 is prepared by the following steps: coating a negative photoresist on the surface of the P-type reflective metal layer 14 and the surface of the current blocking layer not covered by the P-type reflective metal layer 14, then removing part of the photoresist by exposure and development, then sequentially evaporating Ti metal with a thickness of 200-300 angstrom, Pt metal with a thickness of 1500-2000 angstrom, Au metal with a thickness of 4000-8000 angstrom and Cr metal with a thickness of 200-500 angstrom by electron beam evaporation, then removing the metal on the photoresist by Lift-Off process, and then removing the photoresist.

[0025] In particular, the specific steps for preparing the first insulating layer 16 in this embodiment include: The P-type conductive metal layer 15 is prepared by the following steps: coating a negative photoresist on the surface of the P-type reflective metal layer 14 and the surface of the current blocking layer not covered by the P-type reflective metal layer 14, then removing part of the photoresist by exposure and development, then sequentially evaporating Ti metal with a thickness of 200-300 angstrom, Pt metal with a thickness of 1500-2000 angstrom, Au metal with a thickness of 4000-8000 angstrom and Cr metal with a thickness of 200-500 angstrom by electron beam evaporation, then removing the metal on the photoresist by Lift-Off process, and then removing the photoresist.

[0026] In particular, the specific steps for preparing the first insulating layer via hole 161 in this embodiment include: The P-type conductive metal layer 15 is prepared by the following steps: coating a negative photoresist on the surface of the P-type reflective metal layer 14 and the surface of the current blocking layer not covered by the P-type reflective metal layer 14, then removing part of the photoresist by exposure and development, then sequentially evaporating Ti metal with a thickness of 200-300 angstrom, Pt metal with a thickness of 1500-2000 angstrom, Au metal with a thickness of 4000-8000 angstrom and Cr metal with a thickness of 200-500 angstrom by electron beam evaporation, then removing the metal on the photoresist by Lift-Off process, and then removing the photoresist.

[0027] In particular, the specific steps for preparing the N-type conductive metal layer 17 in this embodiment include: The P-type conductive metal layer 15 is prepared by the following steps: coating a negative photoresist on the surface of the P-type reflective metal layer 14 and the surface of the current blocking layer not covered by the P-type reflective metal layer 14, then removing part of the photoresist by exposure and development, then sequentially evaporating Ti metal with a thickness of 200-300 angstrom, Pt metal with a thickness of 1500-2000 angstrom, Au metal with a thickness of 4000-8000 angstrom and Cr metal with a thickness of 200-500 angstrom by electron beam evaporation, then removing the metal on the photoresist by Lift-Off process, and then removing the photoresist.

[0028] In particular, the specific steps for preparing the first bonding layer 181 in this embodiment include: A metal Ti with a thickness of 3000-4000 angstroms and 2-5 groups of Sn metal and Ni metal are sequentially evaporated on the N-type conductive metal layer 17 by an electron beam evaporation process to form the first bonding layer 181, and the thickness of the Sn metal in each group is 5000-10000 angstroms, and the thickness of the Ni metal is 2000-4000 angstroms.

[0029] In particular, the specific steps for preparing the second bonding layer 182 in the embodiment include: A conductive silicon wafer 19 is provided, and then a metal Ti with a thickness of 3000-4000 angstroms and 2-5 groups of Sn metal and Ni metal are sequentially evaporated on the conductive silicon wafer 19 by an electron beam evaporation process to form the second bonding layer 182, and the thickness of the Sn metal in each group is 5000-10000 angstroms, and the thickness of the Ni metal is 2000-4000 angstroms. Then, the conductive silicon wafer 19 is hot-pressed and bonded to the first bonding layer 181 by a hot-press bonding process through the second bonding layer 182.

[0030] S6, the sapphire substrate 10 is thinned, and then the thinned sapphire substrate is laser peeled to expose the PSS on the bottom of the N-type semiconductor layer 111; In particular, the specific steps of the step S6 in the embodiment include: The sapphire substrate 10 is thinned by a grinding process, and the remaining thickness after thinning is 200-350 microns. Then, the thinned sapphire substrate is removed by a laser peeling process. The laser peeling process uses a 266 nm ultraviolet laser to irradiate from the sapphire surface, so that the energy of the laser causes the GaN at the bonding surface between part of the sapphire substrate and the N-type semiconductor layer 111 to decompose, generating metallic gallium and nitrogen gas, thereby decomposing and removing the thinned sapphire substrate to expose the PSS on the bottom of the N-type semiconductor layer 111. The laser peeling process has a laser spot radius of 12-16 microns, a laser spot moving speed of 2500-3000 mm / s, and a laser power of 80-100 W.

[0031] S7, the photoresist is coated on the PSS on the bottom of the N-type semiconductor layer 111, and then exposed and developed to remove part of the photoresist to expose the PSS, and then a first inductively coupled plasma etching process is used to remove the exposed PSS and the epitaxial layer below the PSS to form an isolation groove 20; The first inductive coupled plasma etching process includes a first etching step, a second etching step, a third etching step, a fourth etching step, and a fifth etching step for increasing material etching selectivity. The etching upper power SRF and the etching lower power BRF of the first etching step are greater than the etching upper power SRF and the etching lower power BRF of the second etching step. The ratio of the etching upper power SRF to the etching lower power BRF of the first etching step is less than the ratio of the etching upper power SRF to the etching lower power BRF of the second etching step. The etching upper power SRF and the etching lower power BRF of the third etching step are greater than the etching upper power SRF and the etching lower power BRF of the fourth etching step. The ratio of the etching upper power SRF to the etching lower power BRF of the third etching step is less than the ratio of the etching upper power SRF to the etching lower power BRF of the fourth etching step. The difference between the ratio of the etching upper power SRF to the etching lower power BRF of the first etching step and the ratio of the etching upper power SRF to the etching lower power BRF of the second etching step is less than the difference between the ratio of the etching upper power SRF to the etching lower power BRF of the third etching step and the ratio of the etching upper power SRF to the etching lower power BRF of the fourth etching step. Further, in the first etching step, the etching upper power SRF of the first etching step is 1000W-1200W, the etching lower power BRF of the first etching step is 800W-1000W, the ratio S / B of the etching upper power SRF to the etching lower power BRF of the first etching step is 1-1.5, and the etching time of the first etching step is 100S-150S.

[0032] Specifically, in the embodiment, the etching upper power SRF of the first etching step is 1000W, the etching lower power BRF of the first etching step is 1000W, and the ratio S / B of the etching upper power SRF to the etching lower power BRF of the first etching step is 1.

[0033] Further, in the second etching step, the etching upper power SRF of the second etching step is 400W-600W, the etching lower power BRF of the second etching step is 100W-150W, the ratio S / B of the etching upper power SRF to the etching lower power BRF of the second etching step is 4-6, the etching time of the second etching step is determined by the etching depth, and the total depth etched by the first etching step and the second etching step is 20%-30% of the entire isolation groove depth.

[0034] Specifically in the embodiment, the upper power SRF of the second etching step is 400 W, the lower power BRF of the second etching step is 100 W, and the ratio S / B of the upper power SRF of the second etching step to the lower power BRF of the second etching step is 4.

[0035] Further, the ratio of the upper power SRF to the lower power BRF of the first etching step is greater than or equal to 3.

[0036] Specifically in the embodiment, the ratio of the upper power SRF to the lower power BRF of the first etching step is 3.

[0037] Further, in the third etching step, the upper power SRF of the third etching step is 1000 W-1200 W, the lower power BRF of the third etching step is 800 W-1000 W, the ratio S / B of the upper power SRF of the third etching step to the lower power BRF of the third etching step is 1-1.5, and the etching time of the third etching step is 100 S-150 S.

[0038] Specifically in the embodiment, the upper power SRF of the third etching step is 1000 W, the lower power BRF of the third etching step is 1000 W, and the ratio S / B of the upper power SRF of the third etching step to the lower power BRF of the third etching step is 1.

[0039] Further, in the fourth etching step, the upper power SRF of the fourth etching step is 200 W-400 W, the lower power BRF of the fourth etching step is 30 W-50 W, the ratio S / B of the upper power SRF of the fourth etching step to the lower power BRF of the fourth etching step is 6-8, the etching time of the fourth etching step is determined by the etching depth, and the total depth etched by the third etching step and the fourth etching step is 60%-65% of the entire isolation groove depth. Specifically in the embodiment, the upper power SRF of the fourth etching step is 200 W, the lower power BRF of the fourth etching step is 30 W, and the ratio S / B of the upper power SRF of the fourth etching step to the lower power BRF of the fourth etching step is 20 / 3.

[0040] Further, the ratio of the etching upper power SRF to the etching lower power BRF in the third etching step is greater than or equal to 5 than the ratio of the etching upper power SRF to the etching lower power BRF in the fourth etching step.

[0041] In particular, in the embodiment, the ratio of the etching upper power SRF to the etching lower power BRF in the third etching step is 17 / 3 than the ratio of the etching upper power SRF to the etching lower power BRF in the fourth etching step.

[0042] Further, in the fifth etching step, the etching upper power SRF in the fifth etching step is 100W-300W, the etching lower power BRF in the fifth etching step is 30W-100W, the ratio of the etching upper power in the fifth etching step to the etching lower power in the fifth etching step S / B is 3-4, and the depth etched by the fifth etching step is 5%-20% of the entire isolation groove depth.

[0043] In particular, in the embodiment, the etching upper power SRF in the fifth etching step is 100W, the etching lower power BRF in the fifth etching step is 30W, and the ratio of the etching upper power in the fifth etching step to the etching lower power in the fifth etching step S / B is 10 / 3.

[0044] It should be noted that, in the embodiment, the first etching step, the second etching step, the third etching step, and the fourth etching step all etch the maximum depth, and the fifth etching step can only etch the minimum depth; the first etching step, the second etching step, the third etching step, and the fourth etching step all etch the minimum depth, and the fifth etching step can only etch the maximum depth.

[0045] In the first etching step, the etching upper power SRF and the etching lower power BRF in the first etching step are both greater than the etching upper power SRF and the etching lower power BRF in the second etching step, and the ratio of the etching upper power SRF to the etching lower power BRF in the first etching step is less than the ratio of the etching upper power SRF to the etching lower power BRF in the second etching step. The greater etching power and the smaller ratio of the etching upper power to the etching lower power make the etching have a good bombardment effect, at which time the bombardment effect on the PSS wave peak position is much greater than the bombardment effect on the PSS wave valley position, reducing the depth difference between the PSS wave peak and the PSS wave valley. In the second etching step, the etching up power SRF and the etching down power BRF of the second etching step are both set to be smaller than the etching up power SRF and the etching down power BRF of the second etching step, and the ratio of the etching up power SRF to the etching down power BRF of the second etching step is set to be larger than the ratio of the etching up power SRF to the etching down power BRF of the second etching step, so that the etching power is reduced and the ratio of the etching up power to the etching down power is increased, thereby making the etching rate of the PSS wave peak larger than the etching rate of the PSS wave valley, and further reducing the depth difference between the PSS wave peak and the PSS wave valley; In the third etching step, the etching up power SRF and the etching down power BRF of the third etching step are both set to be larger than the etching up power SRF and the etching down power BRF of the fourth etching step, and the ratio of the etching up power SRF to the etching down power BRF of the third etching step is set to be smaller than the ratio of the etching up power SRF to the etching down power BRF of the fourth etching step, so that the third etching step has the same effect as the first etching step; In the fourth etching step, the etching up power SRF and the etching down power BRF of the third etching step are both set to be smaller than the etching up power SRF and the etching down power BRF of the fourth etching step, and the ratio of the etching up power SRF to the etching down power BRF of the second etching step is set to be larger than the ratio of the etching up power SRF to the etching down power BRF of the second etching step, so that the fourth etching step has the same effect as the second etching step; The difference between the ratio of the etching up power SRF to the etching down power BRF of the first etching step and the ratio of the etching up power SRF to the etching down power BRF of the second etching step is smaller than the difference between the ratio of the etching up power SRF to the etching down power BRF of the third etching step and the ratio of the etching up power SRF to the etching down power BRF of the fourth etching step, thereby achieving better effect; After the first etching step, the second etching step, the third etching step and the fourth etching step are completed, the PSS wave peak is completely eliminated, and the PSS wave peak and the PSS wave valley are located on the same horizontal plane, thereby avoiding the reaction between the etching ions and the metal layer under the current blocking layer caused by the too large depth difference between the PSS wave peak and the PSS wave valley, and causing the failure of the light emitting diode chip; The fifth etching step increases the etching selectivity of SiO2 and GaN materials, that is, the etching parameters have a much larger etching rate on SiO2 material than on GaN material, so as to further reduce the over-etching amount of the etching current blocking layer caused by the preparation of the isolation groove, thereby avoiding the need to thicken the current blocking layer and reducing the luminous brightness of the light emitting diode chip; S8, a second insulating layer 21 is prepared on the PSS at the bottom of the N-type semiconductor layer 111, the current blocking layer 13 and the isolation groove 20; In particular, in the present embodiment, the specific steps of preparing the second insulating layer 21 include: Al2O3 is deposited on the PSS at the bottom of the N-type semiconductor layer 111, the current blocking layer 13 and the isolation groove 20 as the second insulating layer 21.

[0046] S9, a second insulating layer via hole 211 is prepared on the second insulating layer 21, and then a P-type pad 22 is prepared on the second insulating layer via hole 211; In particular, in the present embodiment, the specific steps of preparing the second insulating layer via hole 211 and the P-type pad 22 include: A negative photoresist is coated on the surface of the second insulating layer 21, and then exposed and developed to remove part of the photoresist, exposing part of the second insulating layer, and then etching away the exposed part of the second insulating layer and the current blocking layer under the exposed part of the second insulating layer with a BOE etching solution until the P-type conductive metal layer, forming the second insulating layer via hole 211; then Ti metal with a thickness of 500 Å, Pt metal with a thickness of 1000 Å, Au metal with a thickness of 5000 Å, Ni metal with a thickness of 2000 Å and Au metal with a thickness of 10000 Å are sequentially evaporated by using an electron beam evaporation process, followed by removing the metal above the photoresist by using a Lift-Off process, and then removing the photoresist, forming the P-type pad layer.

[0047] Please refer to Fig. 2 , which shows a cross-sectional schematic diagram of a light emitting diode chip prepared by the method for preparing a light emitting diode chip according to an embodiment of the present application.

[0048] Embodiment 2 A light emitting diode chip, which is different from the light emitting diode chip prepared in Embodiment 1, in that: The upper power SRF of the first etching step is 1200 W, the lower power BRF of the first etching step is 1000 W, and the ratio S / B of the upper power SRF of the first etching step to the lower power BRF of the first etching step is 1.2.

[0049] The upper power SRF of the second etching step is 600 W, the lower power BRF of the second etching step is 125 W, and the ratio S / B of the upper power SRF of the second etching step to the lower power BRF of the second etching step is 4.8.

[0050] The difference between the ratio of the upper etching power SRF and the lower etching power BRF of the first etching step and the ratio of the upper etching power SRF and the lower etching power BRF of the second etching step is 3.6.

[0051] The upper etching power SRF of the third etching step is 1200W, the lower etching power BRF of the third etching step is 1000W, and the ratio S / B of the upper etching power SRF of the third etching step and the lower etching power BRF of the third etching step is 1.2.

[0052] The upper etching power SRF of the fourth etching step is 300W, the lower etching power BRF of the fourth etching step is 40W, and the ratio S / B of the upper etching power SRF of the fourth etching step and the lower etching power BRF of the fourth etching step is 7.5.

[0053] The difference between the ratio of the upper etching power SRF and the lower etching power BRF of the third etching step and the ratio of the upper etching power SRF and the lower etching power BRF of the fourth etching step is 6.3.

[0054] The upper etching power SRF of the fifth etching step is 175W, the lower etching power BRF of the fifth etching step is 50W, and the ratio S / B of the upper etching power of the fifth etching step and the lower etching power of the fifth etching step is 3.5.

[0055] Example 3 A light emitting diode chip, which is different from the light emitting diode chip prepared in Example 1 in that: The upper etching power SRF of the first etching step is 1200W, the lower etching power BRF of the first etching step is 800W, and the ratio S / B of the upper etching power SRF of the first etching step and the lower etching power BRF of the first etching step is 1.5.

[0056] The upper etching power SRF of the second etching step is 600W, the lower etching power BRF of the second etching step is 100W, and the ratio S / B of the upper etching power SRF of the second etching step and the lower etching power BRF of the second etching step is 6.

[0057] The difference between the ratio of the upper etching power SRF and the lower etching power BRF of the first etching step and the ratio of the upper etching power SRF and the lower etching power BRF of the second etching step is 4.5.

[0058] The upper power SRF of the third etching step is 1200 W, the lower power BRF of the third etching step is 800 W, and the ratio S / B of the upper power SRF of the third etching step to the lower power BRF of the third etching step is 1.5.

[0059] The upper power SRF of the fourth etching step is 400 W, the lower power BRF of the fourth etching step is 50 W, and the ratio S / B of the upper power SRF of the fourth etching step to the lower power BRF of the fourth etching step is 8.

[0060] The difference between the ratio of the upper power SRF to the lower power BRF of the third etching step and the ratio of the upper power SRF to the lower power BRF of the fourth etching step is 6.5.

[0061] The upper power SRF of the fifth etching step is 300 W, the lower power BRF of the fifth etching step is 75 W, and the ratio S / B of the upper power of the fifth etching step to the lower power of the fifth etching step is 4.

[0062] Comparative Example 1 A light emitting diode chip, which is different from the light emitting diode chip prepared in Embodiment 1 in that: In step S7, the first inductively coupled plasma etching process only includes a sixth etching step, the upper power SRF of the sixth etching step is 1100 W, and the lower power BRF of the sixth etching step is 550 W.

[0063] Based on the light emitting diode chips in Embodiments 1, 2, 3 and Comparative Example 1, the same test current is applied to the light emitting diode chips prepared in Embodiments 1, 2 and 3 and the light emitting diode chip in Comparative Example 1 for comparison of the current blocking layer thickness, chip brightness and chip voltage, and the corresponding test results are shown in the following table:

[0064] It should be noted that, in order to ensure the reliability of the verification results, when the same test current is applied to the light emitting diode chips prepared in Embodiments 1, 2 and 3 and the light emitting diode chip in Comparative Example 1 for comparison of the current blocking layer thickness, chip brightness and chip voltage, in addition to the above-mentioned different parameters, other processes and parameters should be kept consistent.

[0065] In summary, the preparation method of the light emitting diode chip in the above embodiment of the present application has the following advantages. In the first etching step, the etching up power SRF and the etching down power BRF of the first etching step are both greater than the etching up power SRF and the etching down power BRF of the second etching step, and the ratio of the etching up power SRF to the etching down power BRF of the first etching step is less than the ratio of the etching up power SRF to the etching down power BRF of the second etching step. The greater etching power and the smaller ratio of the etching up power to the etching down power make the etching have a good bombardment effect. At this time, the bombardment effect on the PSS wave peak position is much greater than the bombardment effect on the PSS wave valley position, and the depth difference between the PSS wave peak and the PSS wave valley is reduced. In the second etching step, the etching up power SRF and the etching down power BRF of the second etching step are both less than the etching up power SRF and the etching down power BRF of the second etching step, and the ratio of the etching up power SRF to the etching down power BRF of the second etching step is greater than the ratio of the etching up power SRF to the etching down power BRF of the second etching step. The reduction of the etching power and the increase of the ratio of the etching up power to the etching down power make the etching rate of the PSS wave peak greater than the etching rate of the PSS wave valley, and the depth difference between the PSS wave peak and the PSS wave valley is further reduced. In the third etching step, the etching up power SRF and the etching down power BRF of the third etching step are both greater than the etching up power SRF and the etching down power BRF of the fourth etching step, and the ratio of the etching up power SRF to the etching down power BRF of the third etching step is less than the ratio of the etching up power SRF to the etching down power BRF of the fourth etching step. Such a setting makes the third etching step have the same effect as the first etching step. In the fourth etching step, the etching up power SRF and the etching down power BRF of the third etching step are both less than the etching up power SRF and the etching down power BRF of the fourth etching step, and the ratio of the etching up power SRF to the etching down power BRF of the second etching step is greater than the ratio of the etching up power SRF to the etching down power BRF of the second etching step. Such a setting makes the fourth etching step have the same effect as the second etching step. The difference between the ratio of the etching up power SRF to the etching down power BRF of the first etching step and the ratio of the etching up power SRF to the etching down power BRF of the second etching step is less than the difference between the ratio of the etching up power SRF to the etching down power BRF of the third etching step and the ratio of the etching up power SRF to the etching down power BRF of the fourth etching step, so that the effect is better.After the first etching step, the second etching step, the third etching step and the fourth etching step are completed, the PSS wave peak is completely eliminated, the PSS wave peak and the PSS wave valley are located in the same horizontal plane, thereby the depth difference between the PSS wave peak and the PSS wave valley is avoided to be too large to cause the etching ion to react with the metal layer under the current blocking layer, thereby causing the failure of the light emitting diode chip; the etching selectivity of SiO2 and GaN material is increased through the fifth etching step, that is, the etching parameter of the fifth etching step is far greater than the etching rate of the GaN material, so as to further reduce the over-etching amount of the etching current blocking layer caused by the preparation of the isolation groove, thereby the thickness of the current blocking layer does not need to be thickened, and the luminous brightness of the light emitting diode chip is avoided to be reduced.

[0066] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0067] The above-described embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it cannot be understood as the limitation of the patent scope of the present application. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A light-emitting diode chip, characterized in that, include: The epitaxial layer, N-type semiconductor layer conductive steps, current spreading layer, current blocking layer, current blocking layer via, and first semiconductor layer are arranged sequentially from top to bottom. The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer arranged sequentially from top to bottom. An isolation trench is provided on the outside of the epitaxial layer. A second insulating layer is provided on top of the epitaxial layer, the isolation trench, and the current blocking layer not covered by the epitaxial layer. A second insulating layer via is provided on the second insulating layer, and a P-type pad is provided in the second insulating layer via. A laser-lifted sapphire substrate-based PSS is disposed between the side of the N-type semiconductor layer away from the active light-emitting layer and the second insulating layer. The thickness of the epitaxial layer plus the current blocking layer is greater than the thickness of the isolation trench plus the depth of the PSS.

2. The light-emitting diode chip according to claim 1, characterized in that, The first semiconductor layer includes a P-type reflective metal layer, a P-type conductive metal layer, a first insulating layer, a first insulating layer via, an N-type conductive metal layer, a first bonding layer, a second bonding layer, and a conductive silicon wafer, which are sequentially disposed on the current blocking layer.

3. A method for fabricating a light-emitting diode chip, characterized in that, The preparation method includes the following steps: S1, a sapphire substrate is provided, and an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer are sequentially deposited on the sapphire substrate as an epitaxial layer; S2, an N-type semiconductor layer conductive step is prepared on the P-type semiconductor layer; S3, a current spreading layer is prepared on the P-type semiconductor layer; S4, a current blocking layer is formed on the current spreading layer, the P-type semiconductor layer not covered by the current spreading layer, and the N-type semiconductor layer conductive steps not covered by the current spreading layer, and then a current blocking layer via is formed on the current blocking layer. S5, a first semiconductor layer is formed on the current blocking layer and the via of the current blocking layer; S6, the sapphire substrate is thinned, and then the thinned sapphire substrate is laser-lifted to expose the PSS on the bottom of the N-type semiconductor layer; S7, photoresist is coated on the PSS at the bottom of the N-type semiconductor layer, and then exposed and developed to remove part of the photoresist, exposing the PSS with the photoresist removed. Then, the exposed PSS and the epitaxial layer below the PSS are removed by the first inductively coupled plasma etching process to form an isolation trench. The first inductively coupled plasma etching process includes a first etching step, a second etching step, a third etching step, a fourth etching step, and a fifth etching step to increase the material etching selectivity. The etching up power (SRF) and etching down power (BRF) of the first etching step are both greater than those of the second etching step. The ratio of the etching up power (SRF) to the etching down power (BRF) of the first etching step is less than that of the second etching step. The etching up power (SRF) and etching down power (BRF) of the third etching step are both greater than those of the second etching step. In the fourth etching step, the ratio of the etching power SRF to the etching power BRF in the third etching step is less than the ratio of the etching power SRF to the etching power BRF in the fourth etching step. The difference between the ratio of the etching power SRF to the etching power BRF in the first etching step and the ratio of the etching power SRF to the etching power BRF in the second etching step is less than the difference between the ratio of the etching power SRF to the etching power BRF in the third etching step and the ratio of the etching power SRF to the etching power BRF in the fourth etching step. S8, a second insulating layer is prepared on the PSS at the bottom of the N-type semiconductor layer, the current blocking layer and the isolation trench; S9, a second insulating layer via is prepared on the second insulating layer, and then a P-type pad is prepared on the second insulating layer via.

4. The method for fabricating a light-emitting diode chip according to claim 3, characterized in that, In the first etching step, the etching up power SRF of the first etching step is 1000W-1200W, the etching down power BRF of the first etching step is 800W-1000W, the ratio S / B of the etching up power SRF and the etching down power BRF of the first etching step is 1-1.5, and the etching time of the first etching step is 100S-150S.

5. The method for fabricating a light-emitting diode chip according to claim 4, characterized in that, In the second etching step, the etching power SRF of the second etching step is 400W-600W, the etching power BRF of the second etching step is 100W-150W, the ratio S / B of the etching power SRF of the second etching step to the etching power BRF of the second etching step is 4-6, the etching time of the second etching step is determined by the etching depth, and the total etching depth of the first etching step and the second etching step is 20%-30% of the depth of the entire isolation trench.

6. The method for fabricating a light-emitting diode chip according to claim 3, characterized in that, The difference between the ratio of etching power SRF to etching power BRF in the first etching step and the ratio of etching power SRF to etching power BRF in the second etching step is greater than or equal to 3.

7. The method for fabricating a light-emitting diode chip according to claim 3, characterized in that, In the third etching step, the etching power SRF of the third etching step is 1000W-1200W, the etching power BRF of the third etching step is 800W-1000W, the ratio S / B of the etching power SRF of the third etching step to the etching power BRF of the third etching step is 1-1.5, and the etching time of the third etching step is 100S-150S.

8. The method for fabricating a light-emitting diode chip according to claim 7, characterized in that, In the fourth etching step, the etching power SRF is 200W-400W, the etching power BRF is 30W-50W, the ratio S / B of the etching power SRF to the etching power BRF is 6-8, the etching time of the fourth etching step is determined by the etching depth, and the total etching depth of the third and fourth etching steps is 60%-65% of the depth of the entire isolation trench.

9. The method for fabricating a light-emitting diode chip according to claim 3, characterized in that, The difference between the ratio of etching up power SRF to etching down power BRF in the third etching step and the ratio of etching up power SRF to etching down power BRF in the fourth etching step is greater than or equal to 5.

10. The method for fabricating a light-emitting diode chip according to claim 3, characterized in that, In the fifth etching step, the etching power SRF of the fifth etching step is 100W-300W, the etching power BRF of the fifth etching step is 30W-100W, the ratio S / B of the etching power of the fifth etching step and the etching power of the fifth etching step is 3-4, and the etching depth of the fifth etching step is 5%-20% of the depth of the entire isolation trench.

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