Power amplifier

Abstract

This power amplifier is provided with a carrier amplifier module (5), a balanced amplifier module (4), a first delay line (80), and a second delay line (81). The thermal resistance in the first amplifier (10) from the active element (12) to the back side of the package is less than the thermal resistance from the active element (22) of the second amplifier (20) and the active element (32) of the third amplifier (30) to the back side of the package. The sum of the electrical length from the input terminal (2) to the first internal output terminal (90) and the electrical length from the first internal input terminal (91) to the output terminal (3) is equal to the sum of the electrical length from the input terminal (2) to the second internal output terminal (92) and the electrical length from the second internal input terminal (93) to the output terminal (3). The first delay line (80) and the second delay line (81) have the same electrical length.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a power amplifier for wireless communication that amplifies power at high frequencies. In particular, it relates to a power amplifier that employs an LMBA circuit. BACKGROUND

[0002] In wireless communication, in order to cope with high-speed large-capacity communication, a digital modulation signal having a large PAPR (Peak to Average Power Ratio) is used. One of the circuits for signal amplification of such a modulation signal having a large PAPR with low distortion and high efficiency is an LMBA (Load Modulated Balanced Amplifier). For example, the circuit and operation of the LMBA are described in Non-Patent Literature 1.

[0003] Figure 5 is a diagram showing the circuit described in Non-Patent Literature 1, and the operation of the LMBA is described using this diagram. In the LMBA 500, a signal input from the outside to the input terminal 502 is distributed to the carrier amplifier 510 and the balanced amplifier 520 by the distribution circuit 60.

[0004] The carrier amplifier 510 is constituted by an input matching circuit 11, an active element 12 biased to the AB stage, and an output matching circuit 13, and its output is connected to the coupled terminal P1 of the hybrid coupler 41.

[0005] In the balanced amplifier 520, two amplifiers, that is, an amplifier 20 constituted by an input matching circuit 21, an active element 22 biased to the C stage, and an output matching circuit 23, and an amplifier 30 constituted by an input matching circuit 31, an active element 32 biased to the C stage, and an output matching circuit 33, are combined through the hybrid couplers 40 and 41.

[0006] The output matching circuits 23 and 33 are designed so that the impedance viewed from the output matching circuit 23 and 33 side of the hybrid coupler 41 becomes an open circuit. In addition, the hybrid couplers 40 and 41 are designed so that the reflection with respect to a 50Ω load becomes the minimum.

[0007] Here, the pass phase of the path from the input terminal 502 to the output terminal 504 through the balanced amplifier 520 is set to θ1, and the pass phase of the path from the input terminal 502 to the output terminal 504 through the carrier amplifier 510 is set to θ2.

[0008] The phase adjustment circuit 530 connected between the distribution circuit 60 and the balanced amplifier 520 is designed so that the electrical length thereof is the same as that of θ1 and θ2.

[0009] Based on this structure, when a large input signal is received, the impedance of the hybrid coupler 41 observed from P1 is 50Ω. The impedances of the hybrid coupler 41 observed from P2 and P3 are expressed by the following formula.

[0010] [Formula 1]

[0011]

[0012] The balanced amplifier and the carrier amplifier operate, and their power is combined via a hybrid coupler to achieve high output. Here, Ic and Ib represent the current supplied from the carrier amplifier and the balanced amplifier to the hybrid coupler 41, respectively.

[0013] On the other hand, when the LMBA500 is receiving a small input signal, the impedance of the hybrid coupler 41 observed from P1 is the same as that when receiving a large signal, which is 50Ω. When the impedance of the hybrid coupler 41 is observed from P2 and P3, it is ∞. The balanced amplifier biased to level C does not operate, and only the carrier amplifier operates, thus achieving high efficiency at low output.

[0014] However, since power amplifiers for wireless base stations typically require small size, they are usually integrated into a single package as modular PAs. On the other hand, reducing the thermal resistance of the carrier amplifier is preferable for higher performance. This, in turn, necessitates the use of expensive package constructions, thus increasing overall cost.

[0015] In particular, LMBA circuits are typically large in size. In the case of modularization, the balanced amplifier and carrier amplifier are all integrated on the same PKG, thus making cost reduction a problem.

[0016] As a solution to this problem, one could consider using different packages for the main amplifier and the peak amplifier, as described in existing literature 1. Specifically, one could consider using a low-thermal-resistance package in the carrier amplifier module to reduce costs, and a high-thermal-resistance but inexpensive package in the balanced amplifier module.

[0017] Patent Document 1: Japanese Patent Publication No. 2008-535321

[0018] Non-patent document 1: "Pseudo-Doherty Load-Modulated Balanced Amplifier WithWide Bandwidth and Extended Power Back-Off Range", IEEE Transactions on Microwave Theory and Techniques, vol.68, no.7, July 2020.

[0019] As mentioned above, the amplifier that requires a low thermal resistance package is the carrier amplifier. Therefore, in order to reduce the package area, it is optimal in terms of cost to divide it into two modules: one that integrates only the carrier amplifier and the other that integrates the distribution circuitry and the balance amplifier as other components.

[0020] However, when the carrier amplifier and balanced amplifier are separated into two modules, wiring is required on both the input and output sides to connect the two modules to each other. This wiring introduces phase shifts, resulting in synthesis losses and a significant deterioration in high-frequency characteristics. Summary of the Invention

[0021] In view of the aforementioned problems, the purpose of this disclosure is to provide a power amplifier that uses a high-performance, low-cost LMBA circuit composed of two modular amplifiers and with easy inter-module connection.

[0022] The power amplifier disclosed herein is a power amplifier comprising a carrier amplifier module, a balanced amplifier module, a first delay line, and a second delay line.

[0023] The carrier amplifier module includes: a first internal output terminal and a second internal output terminal, an input terminal connected to the input of a power amplifier, a distribution circuit, and a first amplifier mounted in the package. For the distribution circuit, the input is connected to the input terminal, the output of one side is connected to the input of the first amplifier, and the output of the other side is connected to the first internal output terminal. The first amplifier has a power amplification transistor mounted in the package, and its output is connected to the second internal output terminal.

[0024] The balanced amplifier module has: a first internal input terminal and a second internal input terminal, an output terminal connected to the output of the power amplifier, a second amplifier and a third amplifier mounted in the package, and a first hybrid coupler and a second hybrid coupler.

[0025] For the first hybrid coupler, the first terminal is connected to the first internal input terminal, the second terminal is connected to the input of the second amplifier, the third terminal is connected to the input of the third amplifier, and the fourth terminal forms a termination.

[0026] For the second hybrid coupler, the first terminal is connected to the second internal input terminal, the second terminal is connected to the output of the second amplifier, the third terminal is connected to the output of the third amplifier, and the fourth terminal is connected to the output terminal.

[0027] The second and third amplifiers each have power amplification transistors mounted in a package.

[0028] The first delay line is connected to the first internal output terminal and the first internal input terminal, and the second delay line is connected to the second internal output terminal and the second internal input terminal.

[0029] Furthermore, the power amplifier disclosed herein is characterized in that the thermal resistance from the transistor to the back of the package in the first amplifier is less than the thermal resistance from the transistor to the back of the package in the second and third amplifiers.

[0030] Furthermore, the power amplifier disclosed herein is characterized in that the sum of the electrical length from the input terminal to the first internal output terminal and the electrical length from the first internal input terminal to the output terminal is equal to the sum of the electrical length from the input terminal to the second internal output terminal and the electrical length from the second internal input terminal to the output terminal, and the electrical lengths of the first delay line and the second delay line are equal.

[0031] According to this disclosure, a power amplifier using a high-performance, low-cost LMBA circuit with easy inter-module connections can be provided. Attached Figure Description

[0032] Figure 1 This is a diagram illustrating the power amplifier 100 of Embodiment 1.

[0033] Figure 2 This is a graph showing the calculated efficiency of the power amplifier 100 according to Embodiment 1.

[0034] Figure 3 This is a diagram illustrating the power amplifier of Embodiment 2.

[0035] Figure 4 This is a top view of the power amplifier 100 according to embodiment 3.

[0036] Figure 5 This is a diagram showing the circuit described in Non-Patent Document 1.

[0037] Figure 6 This is a diagram illustrating the power amplifier 600 of Comparative Example 1.

[0038] Figure 7 This is a diagram illustrating the power amplifier 700 of Comparative Example 2.

[0039] Figure 8 This is a diagram illustrating the power amplifier 800 of Comparative Example 3. Detailed Implementation

[0040] Implementation Method 1

[0041] The power amplifier according to embodiments of the present disclosure will be described with reference to the accompanying drawings. Where the same or corresponding components are labeled with the same reference numerals, repeated descriptions are omitted.

[0042] Figure 1 This is a diagram illustrating the power amplifier 100 according to Embodiment 1 of this disclosure. The power amplifier 100 is an LMBA consisting of a balanced amplifier module 4, a carrier amplifier module 5, a first delay line 80 and a second delay line 81 on a printed circuit board (PCB).

[0043] The power amplifier 100 has an input terminal 102 and an output terminal 104.

[0044] The carrier amplifier module 5 has an input terminal 2, a first internal output terminal 90, and a second internal output terminal 92. Additionally, the carrier amplifier module 5 includes a first amplifier 10, a distribution circuit 60, and a package 55 (not shown). The first amplifier 10 is a carrier amplifier. The distribution circuit 60 and the first amplifier 10 are integrated and mounted in the package 55.

[0045] Input terminal 2 is connected to input terminal 102 of power amplifier 100. The input of distribution circuit 60 is connected to input terminal 2. One output of distribution circuit 60 is connected to the first internal output terminal 90, and the other output is connected to the input side of first amplifier 10. Distribution circuit 60 distributes the signal input to input terminal 2 to the first internal output terminal 90 and the first amplifier 10. The output side of the first amplifier 10 is connected to the second internal output terminal 92.

[0046] The first amplifier 10 is a power amplifier operating under microwave conditions, comprising: an active element 12, an input matching circuit 11 connected to the input side of the active element 12, and an output matching circuit 13 connected to the output side of the active element 12. The input matching circuit 11 and the output matching circuit 13 are matching circuits for impedance matching between the active element 12 and external components. The active element 12 is biased at level A and B. Furthermore, Figure 1 The bias circuit is not shown in the figure. The signal input from the distribution circuit 60 to the first amplifier 10 is transmitted to the active element 12 via the input matching circuit 11, amplified by the active element 12, and output to the second internal output terminal 92 via the output matching circuit 13.

[0047] The balanced amplifier module 4 includes: a package 44 (not shown), a hybrid coupler 40 mounted in the package 44 as a first hybrid coupler, a hybrid coupler 41 as a second hybrid coupler, a second amplifier 20, a third amplifier 30, and a terminating resistor 50.

[0048] The balanced amplifier module 4 includes: a first internal input terminal 91 and a second internal input terminal 93 for receiving power from the carrier amplifier module 5, and an output terminal 3 for outputting the amplified power. Port P1 of the hybrid coupler 40 is connected to the first internal input terminal 91. Port P1 of the hybrid coupler 41 is connected to the second internal input terminal 93. The output terminal 3 is connected to the output terminal 104 of the power amplifier 100.

[0049] The inputs of the second amplifier 20 and the third amplifier 30 are connected to ports P2 and P3 of the hybrid coupler 40, respectively, and the outputs of the second amplifier 20 and the third amplifier 30 are connected to ports P2 and P3 of the hybrid coupler 41, respectively, so that the two amplifiers are combined in parallel.

[0050] Port P4 of hybrid coupler 40 is terminated by terminating resistor 50. Port P4 of hybrid coupler 41 is connected to output terminal 3.

[0051] Output matching circuits 23 and 33 are designed such that their impedance is an open circuit when viewed from the hybrid coupler 41. Furthermore, hybrid couplers 40 and 41 are designed to minimize reflections relative to a 50Ω load.

[0052] Hybrid couplers 40 and 41 can be constructed from a resin substrate, a GaAs substrate, or microstrip lines formed on a Si substrate, or they can be constructed using lumped constant circuits.

[0053] Here, the operation of hybrid couplers 40 and 41 is explained in advance. Hybrid couplers 40 and 41 are typical 90-degree hybrid circuits with four input / output ports, such as branch couplers composed of microstrip lines.

[0054] The four input / output ports are designated as port P1, port P2, port P3, and port P4. Ideally, when an input signal is input to port P1, the input signal is evenly distributed to ports P2 and P3 for output, and no signal is output from port P4. The phase of the output signal at port P2 is delayed by 90° compared to the phase of the input signal, and the phase of the output signal at port P3 is delayed by 180° compared to the phase of the input signal. Assuming that the losses of hybrid couplers 40 and 41 are negligible, the power values ​​of the output signals are each half the power values ​​of the input signals.

[0055] Similarly, if the input signal is input to port P2, signals with equal power values ​​and phase delays of 90° and 180° are output from ports P1 and P4 respectively, while no signal is output from port P3.

[0056] If the input signal is input to port P3, then the output signals from ports P4 and P1 have equal power values ​​and are delayed by 90° and 180° respectively, while no signal is output from port P2.

[0057] If the input signal is input to port P4, then the output signals from ports P3 and P2 have equal power values ​​and are delayed by 90° and 180° respectively, while no signal is output from port P1.

[0058] The second amplifier 20 is a power amplifier operating under microwave conditions, and includes: an active element 22, an input matching circuit 21 connected to the input of the active element 22, and an output matching circuit 23 connected to the output of the active element 22. The input matching circuit 21 and the output matching circuit 23 are matching circuits for impedance matching between the active element 22 and external components. The active element 22 is biased to class C. Figure 1 The bias circuit is not shown in the figure. The signal input from port P2 of the hybrid coupler 40 to the input matching circuit 21 is amplified by the active element 22 and output to port P2 of the hybrid coupler 41 via the output matching circuit 23.

[0059] The third amplifier 30 is a power amplifier operating under microwave conditions, comprising: an active element 32, an input matching circuit 31 connected to the input of the active element 32, and an output matching circuit 33 connected to the output of the active element 32. The input matching circuit 31 and the output matching circuit 33 are matching circuits for impedance matching between the active element 32 and external components. The active element 32 is biased to Class C. Figure 1 The bias circuit is not shown in the figure. The signal input from port P3 of the hybrid coupler 40 to the input matching circuit 31 is amplified by the active element 32 and output to port P3 of the hybrid coupler 41 via the output matching circuit 33.

[0060] Active components 12, 22, and 32 are, for example, GaN (Gallium Nitride)-based HEMTs (High Electron Mobility Transistors) formed on SiC (Silicon Carbide) substrates. They are not limited to this; they can be transistors using other compound semiconductors, or silicon-based LD-MOSFETs, etc.

[0061] The input matching circuits 11, 21, and 31, and the output matching circuits 13, 23, and 33, can be, for example, circuits integrated on inexpensive semiconductor substrates such as gallium arsenide (GaAs) or silicon (Si), or circuits composed of small chip inductors and chip capacitors disposed on a resin substrate. Active components 22 and 32 can also be biased to Class B or a deep Class AB.

[0062] The package 55 constituting the carrier amplifier module 5 has a different construction than the package 44 constituting the balanced amplifier module 4. The construction of the package 55 is chosen such that the thermal resistance from the back of the active element 12 of the carrier amplifier module 5 to the back of the package 55 is lower than the thermal resistance from the back of the active elements 22 and 32 of the balanced amplifier module 4 to the back of the package 44.

[0063] The package 44 of the balanced amplifier module 4 is constructed, for example, using a multilayer substrate made of FR4 material with a substrate thickness of 200–500 μm. The back sides of the active components 22 and 32, which are transistor chips, are mounted to the surface of the multilayer substrate using solder or conductive adhesive. For heat dissipation of the active components, thermal vias can be provided that extend from the surface side of the multilayer substrate corresponding to the back sides of the active components 22 and 32 to the back side, or are thermally connected. Such a construction allows for inexpensive package configuration, but it is generally difficult to sufficiently reduce thermal resistance.

[0064] The carrier amplifier module 5 package 55 is constructed similarly to package 44, using a multilayer substrate with a substrate thickness of 200–500 μm and made of FR4 material. However, the portion of the multilayer substrate where the active element 12, the transistor chip, is mounted is cut out, and a heat sink made of a thin metal plate is attached to the back of package 55. The active element 12 is directly chip-bonded to the heat sink on its back side. The back side of the heat sink becomes the back side of package 55. Although this construction is more expensive than package 44, it reduces the thermal resistance from the back side of the active element 12 to the back side of package 55.

[0065] The first internal output terminal 90 and the first internal input terminal 91 are connected via a first delay line 80. The second internal output terminal 92 and the second internal input terminal 93 are connected via a second delay line 81. The first delay line 80 and the second delay line 81 are each set to a characteristic impedance of 50Ω and have the same electrical length. The absolute value of the electrical length can be arbitrary.

[0066] In embodiment 1, the first delay line 80 and the second delay line 81 are composed of microstrip lines formed on the PCB, but they can also be any type such as coplanar lines, slot lines or coaxial lines.

[0067] The sum of the electrical length from input terminal 2 to the first internal output terminal 90 and the electrical length from the first internal input terminal 91 to the output terminal 3 is defined as θ_b. Furthermore, the sum of the electrical length from input terminal 2 to the second internal output terminal 92 and the electrical length from the second internal input terminal 93 to the output terminal 3 is defined as θ_c.

[0068] The input matching circuits 11, 21 and 31 and the output matching circuits 13, 23 and 33 are set to θ_b = θ_c.

[0069] Figure 2 This is the calculated efficiency result of the power amplifier 100 in Implementation Method 1. Figure 2 The calculation results of the efficiency of the power amplifier 100 are shown in overlapping view when the electrical lengths of delay lines 80 and 81 are the same and vary in 10-degree steps within the range of 0 to 30 degrees. Figure 2 The horizontal axis represents output power. Figure 2 The vertical axis represents the power load efficiency (PAE). The almost overlapping results indicate that in power amplifier 100, if the electrical lengths of the two delay lines 80 and 81 are the same, the PAE remains almost unchanged even if the absolute value of the electrical length is altered, and the characteristics do not deteriorate. Furthermore, since it is independent of the absolute value of the electrical length, connections between modules are easy.

[0070] As described above, the power amplifier 100 in Embodiment 1 of this disclosure is a power amplifier comprising a carrier amplifier module 5, a balanced amplifier module 4, a first delay line 80, and a second delay line 81. Furthermore, the power amplifier 100 is configured as follows.

[0071] The carrier amplifier module 5 has an input terminal 2, a first internal output terminal 90, and a second internal output terminal 92, and includes a distribution circuit 60 and a first amplifier 10 mounted in the package 55.

[0072] Input terminal 2 is connected to the input terminal of power amplifier 100. In the distribution circuit 60, the input is connected to input terminal 2, and the output is connected to the input and the first internal output terminal 90 of the first amplifier 10, respectively. The first amplifier 10 has an active element 12 biased to AB level for power amplification, and its output is connected to the second internal output terminal 92.

[0073] The balanced amplifier module 4 has a first internal input terminal 91, a second internal input terminal 93, and an output terminal 3. It also includes a second amplifier 20 and a third amplifier 30 mounted in a package 44, as well as a hybrid coupler 40 as a first hybrid coupler and a hybrid coupler 41 as a second hybrid coupler. The output terminal 3 is connected to the output terminal 3 of the power amplifier 100.

[0074] In the first hybrid coupler 40, the first terminal P1 is connected to the first internal input terminal 91, the second terminal P2 is connected to the input of the second amplifier 20, the third terminal P3 is connected to the input of the third amplifier 30, and the fourth terminal P4 forms a terminal.

[0075] In the second hybrid coupler 41, the first terminal P1 is connected to the second internal input terminal 93, the second terminal P2 is connected to the output of the second amplifier 20, the third terminal P3 is connected to the output of the third amplifier 30, and the fourth terminal P4 is connected to the output terminal 3.

[0076] The second amplifier 20 and the third amplifier 30 each have active power amplification elements 22 and 32 that are biased to class C and mounted in package 44.

[0077] The first delay line 80 is connected to the first internal output terminal 90 and the first internal input terminal 91, and the second delay line 81 is connected to the second internal output terminal 92 and the second internal input terminal 93.

[0078] Moreover, the thermal resistance from the active element 12 of the first amplifier 10 to the back of the package 55 is less than the thermal resistance from the active element 22 of the second amplifier 20 and the active element 32 of the third amplifier 30 to the back of the package 44.

[0079] Furthermore, the sum of the electrical length from input terminal 2 to the first internal output terminal 90 and the electrical length from the first internal input terminal 91 to the output terminal 3 is equal to the sum of the electrical length from input terminal 2 to the second internal output terminal 92 and the electrical length from the second internal input terminal 93 to the output terminal 3.

[0080] Furthermore, the electrical lengths of the first delay line 80 and the second delay line 81 are equal.

[0081] That is, in Embodiment 1, the balanced amplifier module 4 uses an inexpensive package 44, and the distribution circuit 60 is integrated into the carrier amplifier module 5. This allows for cost optimization of the package structure in both the carrier amplifier and the balanced amplifier, thus achieving a cost-saving effect.

[0082] In addition, in the path from the input terminal 2 to the output terminal 3, the electrical length of the path through the first amplifier 10 is set to be the same as the electrical length of the path through the second amplifier 20 and the third amplifier 30, and the electrical lengths of the two delay lines 80 and 81 connecting the balanced amplifier module 4 and the carrier amplifier module 5 are set to be the same.

[0083] According to this structure, the delays in the two delay lines 80 and 81 are generated equally regardless of the absolute value of their electrical lengths. Therefore, the delays generated in the path through the balanced amplifier and the path through the carrier amplifier cancel each other out, and the phase difference between the paths becomes zero. This achieves the effect of not causing degradation of high-frequency characteristics.

[0084] In addition, it leverages the ease of connection between the two modules, the flexibility in module configuration, and the ability to utilize modules regardless of their spacing, even when bypass capacitors are configured around the modules.

[0085] Figure 6 This is a diagram illustrating the power amplifier 600 of Comparative Example 1. The power amplifier 600 is a structure in which a carrier amplifier module 5, which integrates only the carrier amplifier, and a balanced amplifier module 4, which integrates the distribution circuit 60 and the balanced amplifier, are connected by delay lines 85 and 86 on a PCB.

[0086] In this case, relative to the phase θ1 on the balanced amplifier side, the phase θ2 on the carrier amplifier side delays the sum of the electrical lengths θm1 and θm2 of the delay line 85 (θm1 + θm2), thus creating a difference between θ1 and θ2. This phase shift results in synthesis losses and significantly degrades the high-frequency characteristics of the power amplifier, thus becoming a problem.

[0087] Alternatively, it can be argued that by taking this effect into account in advance and integrating the delay line into the balanced amplifier module, the delay of the through phase on the carrier amplifier side can be eliminated.

[0088] Figure 7 This is a diagram illustrating the power amplifier 700 of Comparative Example 2. Unlike Comparative Example 1, in the power amplifier 700, a delay line 710 is provided in the balanced amplifier module 4 to cancel the phase delay of delay lines 85 and 86. However, in this case, there is a problem that the circuit size of the balanced amplifier module 4 becomes larger.

[0089] Alternatively, as another countermeasure, one could consider connecting a phase-leading circuit on the PCB to eliminate the delay phase in a delay line.

[0090] Figure 8 This is a diagram illustrating the power amplifier 800 of Comparative Example 3. Unlike Comparative Examples 1 and 2, in the power amplifier 800, the balanced amplifier module 4 and the carrier amplifier module 5 are connected via a phase lead circuit 810 and a delay line 86. Here, the phase of the phase lead circuit 810 is designed to be phase ahead to compensate for the delay caused by the delay line 86.

[0091] However, this method requires designing a phase lead circuit based on the length of the delay line, and the bandwidth that can cancel the phase is also limited, so there are concerns about complexity and degradation of high-frequency characteristics.

[0092] In addition, the characteristic impedances of hybrid coupler 40 and hybrid coupler 41 do not need to be 50Ω, and can be any impedance Zc, Zd.

[0093] In this case, setting the characteristic impedance of the hybrid coupler 40 and the delay line 80 to Zc, and setting the characteristic impedance of the hybrid coupler 41 and the delay line 81 to Zd, yields the same effect as previously described. Zc and Zd can be the same or different.

[0094] Implementation Method 2

[0095] Figure 3 This is a diagram illustrating the power amplifier of Embodiment 2. The difference from Embodiment 1 is that the output matching circuit 13 of the first amplifier 10 in the power amplifier 100 is divided into an output matching circuit 210 and an output matching circuit 212. The output matching circuit 210 is disposed in the carrier amplifier module 5, and the output matching circuit 212 is disposed in the balanced amplifier module 4.

[0096] Here, the impedance observed from the second internal input terminal 93 on the balanced amplifier module 4 side is set to Zm. The output matching circuit 212 is configured such that Zm has only a real component and no imaginary component, or that the imaginary component is sufficiently small compared to the real component to be practically considered to have a real component. The characteristic impedance of the delay line 81 is set to Zm. Other parts are omitted from the description.

[0097] In the power amplifier 200 configured in this way, similar to the power amplifier 100 of Embodiment 1, the package structure is optimized in terms of cost in the carrier amplifier module and the balanced amplifier module respectively, thus achieving the effect of cost reduction, and the connection between modules is easy and does not cause degradation of high frequency characteristics, thereby achieving high performance.

[0098] Furthermore, in the power amplifier 200 of Embodiment 1, a portion of the output matching circuit of the first amplifier 10 installed in the carrier amplifier module 5 is integrated into the balanced amplifier module 4, thus achieving the effect of reducing the size of the carrier amplifier module 5 which uses expensive packaging and further reducing costs.

[0099] Implementation Method 3

[0100] Embodiment 3 defines the planar layout of the balanced amplifier module 4, carrier amplifier module 5, first internal output terminal 90, second internal output terminal 92, first internal input terminal, second internal input terminal 93, first delay line 80, and second delay line 81 of the power amplifier 100 of Embodiment 1. Everything else is the same as in Embodiment 1.

[0101] Figure 4 This is a top view of the power amplifier 100 of Embodiment 3, showing the configuration of the balanced amplifier module 4, carrier amplifier module 5, and delay lines 80 and 81 from above. In the figure, the shape and configuration of the electrode pads (terminals) disposed on the back of the balanced amplifier module 4 and carrier amplifier module 5 are shown from above with dashed lines.

[0102] exist Figure 4 In the diagram, the ground terminal 120 of the balanced amplifier module 4 and the ground terminal 122 of the carrier amplifier module 5 are shown as dashed rectangles. Additionally, signal terminals including the first internal output terminal 90, the second internal output terminal 92, the first internal input terminal 91, and the second internal input terminal 93 are shown as dashed squares.

[0103] Microstrip line 112 connects input terminal 2 and input terminal 102 (not shown), and microstrip line 112 connects output terminal 3 and output terminal 104 (not shown).

[0104] On the periphery of the back of the balanced amplifier module 4, signal terminals including a first internal input terminal 91 and a second internal input terminal 93 are arranged around the ground terminal 120. The first internal input terminal 91 and the second internal input terminal 93 are arranged along the same side 124 of the quadrilateral balanced amplifier module 4.

[0105] On the periphery of the back of the carrier amplifier module 5, signal terminals including a first internal output terminal 90 and a second internal output terminal 92 are arranged surrounding the ground terminal 122. The first internal output terminal 90 and the second internal output terminal 92 are arranged along the same side 126 of the quadrilateral-shaped carrier amplifier module 5.

[0106] The balanced amplifier module 4 and the carrier amplifier module 5 are arranged facing each other so that side 124 and side 126 are parallel to each other, and the first internal input terminal 91 and the second internal input terminal 93 are located at positions that are exactly facing the first internal output terminal 90 and the second internal output terminal 92, respectively.

[0107] The first internal output terminal 90 and the first internal input terminal 91 are connected linearly via delay line 80, and the second internal output terminal 92 and the second internal input terminal 93 are connected via delay line 81, i.e., connected with the shortest possible distance. Preferably, the spacing between the first internal input terminal 91 and the first internal output terminal 90 is the same as the spacing between the second internal input terminal 93 and the second internal output terminal 92. Other parts are omitted from the description.

[0108] In the power amplifier 100 configured in this way, as in the power amplifier 100 of embodiment 1, the packaging structure is optimized in terms of cost in the carrier amplifier module and the balanced amplifier module respectively, thus achieving the effect of cost reduction, and the connection between modules is easy and does not cause degradation of high frequency characteristics, thereby achieving high performance.

[0109] Furthermore, in the power amplifier 100 of Embodiment 3, the positions of the balanced amplifier module 4, the carrier amplifier module 5, the first internal output terminal 90, the second internal output terminal 92, the first internal input terminal, and the second internal input terminal 93 are defined as described above.

[0110] Therefore, by simply connecting the two modules by arranging the first delay line 80 and the second delay line 81 in a straight line, the electrical lengths of the first delay line 80 and the second delay line 81 can be made the same, thus achieving the effect of more easily connecting the modules to each other.

[0111] Furthermore, in Embodiment 3, the power amplifier 100 was described as an example, but the shape and arrangement of the modules, pads (terminals), etc. in Embodiment 3 can also be applied to the power amplifier 200.

[0112] This disclosure is not limited to the embodiments described above, but includes various modifications. For example, the embodiments described above have been given in detail for ease of understanding of this disclosure, and are not limited to having all the structures described.

[0113] Furthermore, a portion of the structure of one embodiment can be replaced with the structure of another embodiment; additionally, the structure of another embodiment can be added to the structure of one embodiment. Furthermore, for a portion of the structure of each embodiment, other structures can be added, deleted, or replaced.

[0114] Explanation of reference numerals in the attached figures

[0115] 2…Input terminal; 3…Output terminal; 4…Balanced amplifier module; 5…Carrier amplifier module; 10…First amplifier; 11, 21, 31…Input matching circuit; 12, 22…Active components; 13, 23, 33, 210, 212…Output matching circuit; 20…Second amplifier; 30…Third amplifier; 40…First hybrid coupler; 41…Second hybrid coupler; 50…Termination resistor; 60…Distribution circuit; 80…First delay line; 81…Second delay line; 90…First internal output terminal; 91…First internal input terminal; 92…Second internal output terminal; 93…Second internal input terminal; 100, 200…Power amplifier; 102…Input terminal; 104…Output terminal; 120, 122…Ground terminal; 124, 126…Side.

Claims

1. A power amplifier comprising: a carrier amplifier module, a balanced amplifier module, a first delay line, and a second delay line, characterized in that, The carrier amplifier module includes: a first internal output terminal and a second internal output terminal, an input terminal connected to the input of the power amplifier, a distribution circuit, and a first amplifier mounted in a package. For the distribution circuit, the input is connected to the input terminal, the output of one side is connected to the input of the first amplifier, and the output of the other side is connected to the first internal output terminal. The first amplifier has a power amplification transistor mounted in the package, and its output is connected to the second internal output terminal. The balanced amplifier module includes: a first internal input terminal and a second internal input terminal, an output terminal connected to the output of the power amplifier, a second amplifier and a third amplifier mounted in a package, and a first hybrid coupler and a second hybrid coupler. For the first hybrid coupler, the first terminal is connected to the first internal input terminal, the second terminal is connected to the input of the second amplifier, the third terminal is connected to the input of the third amplifier, and the fourth terminal forms a termination. For the second hybrid coupler, the first terminal is connected to the second internal input terminal, the second terminal is connected to the output of the second amplifier, the third terminal is connected to the output of the third amplifier, and the fourth terminal is connected to the output terminal. The second amplifier and the third amplifier each have power amplification transistors mounted in the package. The first delay line is connected to the first internal output terminal and the first internal input terminal, and the second delay line is connected to the second internal output terminal and the second internal input terminal. The thermal resistance from the transistor to the back of the package in the first amplifier is less than the thermal resistance from the transistor to the back of the package in the second amplifier and the third amplifier. The sum of the electrical length from the input terminal to the first internal output terminal and the electrical length from the first internal input terminal to the output terminal is equal to the sum of the electrical length from the input terminal to the second internal output terminal and the electrical length from the second internal input terminal to the output terminal. The electrical length of the first delay line is equal to the electrical length of the second delay line.

2. The power amplifier according to claim 1, characterized in that, The characteristic impedance of the first delay line is equal to the impedance of the first hybrid coupler, and the characteristic impedance of the second delay line is equal to the impedance of the second hybrid coupler.

3. The power amplifier according to claim 1, characterized in that, The balanced amplifier module also includes a matching circuit that connects the first terminal of the second hybrid coupler to the second internal input terminal. The matching circuit is configured such that the first impedance of the balanced amplifier module, when viewed from the second internal input terminal, does not have an imaginary component. The characteristic impedance of the second delay line is equal to that of the first impedance.

4. The power amplifier according to claim 3, characterized in that, The characteristic impedance of the first delay line is equal to the impedance of the first hybrid coupler.

5. The power amplifier according to any one of claims 1 to 4, characterized in that, The first internal input terminal and the second internal input terminal are arranged along the same side of the balanced amplifier module on the peripheral portion of the rear side. The first internal output terminal and the second internal output terminal are arranged along the same side of the carrier amplifier module on the peripheral portion of the rear side. One side of the balanced amplifier module is arranged parallel to and directly opposite one side of the carrier amplifier module. The first internal input terminal and the first internal output terminal are linearly connected through the first delay line, and the second internal input terminal and the second internal output terminal are linearly connected through the second delay line.

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