Semiconductor device

Abstract

And the snapback phenomenon in the RC-IGBT is inhibited. In a semiconductor device (100) having an IGBT region (21) and a diode region (22) in the same chip, an IGBT in the IGBT region (21) has a drift layer (1) of a first conductivity type, a trench (3), a gate electrode (5) provided in the trench (3), a body layer (2) of a second conductivity type, an emitter layer (7) of the first conductivity type, a gate insulating film (insulating film (4)), and a collector layer (11) of the second conductivity type. The diode in the diode region (22) has a drift layer (1), a first semiconductor layer (12) of a second conductivity type provided closer to the front surface side than the drift layer (1), and a second semiconductor layer (13) of the first conductivity type provided closer to the back surface side than the drift layer (1). The IGBT region (21) has a boundary pillar layer (8A) of the second conductivity type at a boundary with the diode region (22), the boundary pillar layer (8A) penetrating the drift layer (1) and being in contact with the body layer (2) and the collector layer (11).

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] An RC-IGBT (RC: Reverse-Conducting IGBT) that integrates both an IGBT (Insulated Gate Bipolar Transistor) and a diode within the same chip allows for shared termination regions between the IGBT and diode, thus reducing chip size. Furthermore, because the IGBT and diode operate at different timings, heat generated by losses in one region (the IGBT area or the diode area) is dissipated to the other, contributing to overall chip heat dissipation and reducing thermal resistance.

[0003] On the other hand, when the IGBT is turned on, especially when electrons injected from the surface side of the IGBT near the boundary with the diode, they do not detach from the collector layer (p-layer) on the back side of the IGBT, but instead detach to the cathode layer (n+ layer) of the diode to perform MOS operation. If a voltage higher than the built-in voltage of the pn junction on the back side is not applied, hole injection from the p-layer on the back side will not occur. Therefore, when the IGBT is turned on, there is a problem of a sudden voltage drop after a voltage rise.

[0004] Here, although the technology relates to SJ-RC-IGBTs, which incorporate IGBTs and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) instead of the conventional RC-IGBT with built-in IGBTs and diodes, and are further described as having an SJ (Super Junction) structure, Patent Document 1 is a technique for suppressing quick-return phenomena. Patent Document 1 describes how, in an SJ-RC-IGBT, by adjusting the repeating spacing of the SJ structure, the thickness of the repeating structure, the impurity concentration of the SJ structure, the thickness and impurity concentration of the buffer layer, and the repeating spacing of the IGBT and MOSFET, a small quick-return voltage is achieved, enabling MOSFET operation even at high current densities.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: International Publication No. 2013 / 179379 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] However, in Patent Document 1, such as Patent Document 1... Figure 1 As shown, under the SJ structure formed by the repeated N-drift layer (1) and P-drift layer (2), there is an N-buffer layer (11). Therefore, the electrons injected into the IGBT as charge carriers may not detach from the P-collector layer (12) but instead detach from the N-buffer layer (11) to the N-collector layer (13) of the MOSFET. Therefore, there is a limit to the reduction of the backlash phenomenon.

[0010] The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing the sudden return phenomenon in RC-IGBT.

[0011] Methods for solving problems

[0012] To address the aforementioned issues, the semiconductor device of the present invention is a semiconductor device having an IGBT region and a diode region within the same chip. The IGBT region comprises: a drift layer of a first conductivity type; a trench; a gate electrode disposed within the trench; a body layer of a second conductivity type disposed adjacent to the trench on a surface side relative to the drift layer; an emitter layer of the first conductivity type disposed on the surface side of the body layer; a gate insulating film disposed between the body layer, the emitter layer, and the gate electrode; and a collector layer of the second conductivity type disposed on a back side relative to the drift layer. The diode region comprises the drift layer, a first semiconductor layer of the second conductivity type disposed on a surface side relative to the drift layer, and a second semiconductor layer of the first conductivity type disposed on a back side relative to the drift layer. The IGBT region has a boundary pillar layer of the second conductivity type at its boundary with the diode region, which penetrates the drift layer and connects to the body layer and the collector layer.

[0013] Invention Effects

[0014] According to the present invention, the movement of charge carriers from the IGBT region to the diode region can be suppressed by the boundary pillar layer, thus suppressing the backflow phenomenon in the RC-IGBT. Attached Figure Description

[0015] Figure 1 This is a cross-sectional view illustrating the general structure of the semiconductor device of Example 1.

[0016] Figure 2 Explain the current and voltage characteristics of the quick-return phenomenon in RC-IGBT.

[0017] Figure 3 This is a cross-sectional view illustrating the general structure of the semiconductor device of Example 2.

[0018] Figure 4 This is a cross-sectional view illustrating the general structure of the semiconductor device of Example 3.

[0019] Figure 5 This is a cross-sectional view illustrating the general structure of the semiconductor device in Example 4. Detailed Implementation

[0020] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In the various figures and embodiments, the same or similar constituent elements are labeled with the same reference numerals, and repeated descriptions are omitted.

[0021] Example 1

[0022] Figure 1 This is a cross-sectional view illustrating the general structure of the semiconductor device in Embodiment 1.

[0023] The semiconductor device 100 of Embodiment 1 is an RC-IGBT, which has an IGBT region 21 and a diode region 22 within the same chip (on the same semiconductor substrate).

[0024] An IGBT is formed in the IGBT region 21. The IGBT has, for example, a drift layer 1 of a first conductivity type, a trench 3, a gate electrode 5 disposed in the trench 3, a body layer 2 of a second conductivity type disposed adjacent to the trench 3 on the surface side of the drift layer 1, an emitter layer 7 of the first conductivity type disposed on the surface side of the body layer 2, an insulating film 4 disposed between the body layer 2, the emitter layer 7 and the gate electrode 5, which functions as a gate insulating film, and a collector layer 11 of the second conductivity type disposed on the back side side of the drift layer 1.

[0025] A diode is formed in diode region 22. The diode has, for example, a drift layer 1, a first semiconductor layer 12 of a second conductivity type disposed on a side of the drift layer 1 that is closer to the surface than the drift layer 1, and a second semiconductor layer 13 of a first conductivity type disposed on a side of the drift layer 1 that is closer to the back surface than the drift layer 1.

[0026] In addition, Figure 1 The example described uses an example where the first conductivity type is n-type and the second conductivity type is p-type. In this case, the first semiconductor layer 12 becomes the anode layer and the second semiconductor layer 13 becomes the cathode layer. However, it is not limited to this; the first conductivity type can also be p-type and the second conductivity type n-type. In this case, electrons and holes, which are charge carriers, are opposite, and the first semiconductor layer 12 becomes the cathode layer and the second semiconductor layer 13 becomes the anode layer.

[0027] In addition, the semiconductor device 100 is shared in the IGBT region 21 and the diode region 22, and has a surface electrode (not shown) disposed on the surface side and a back electrode (not shown) disposed on the back side.

[0028] The surface electrode is located in IGBT region 21 and diode region 22, and is connected to the main body layer 2 and the first semiconductor layer 12 via contact holes (not shown) and a second conductivity contact layer. The surface electrode is also connected to the emitter layer 7. The surface electrode has an emitter potential E and also an anode potential A.

[0029] The back electrode is connected to the collector layer 11 and the second semiconductor layer 13. The back electrode is at the collector potential and also at the cathode potential.

[0030] In IGBT region 21, the gate electrode 5 is adjacent to the body layer 2 and the emitter layer 7 via an insulating film 4 formed in the trench 3. The insulating film 4 in contact with the gate electrode 5 functions as a gate insulating film. The gate electrode 5 is insulated from the surface electrode by an interlayer insulating film 9. In this embodiment, an example is shown where the interlayer insulating film 9 is formed in the trench 3, but it is also possible to configure an interlayer insulating film (not shown) to be formed on the outside of the trench 3 as well. A gate potential G is supplied to the gate electrode 5 by a gate drive circuit (not shown) or the like.

[0031] The diode region 22 also has a trench 3, within which an insulating film 4 and a dummy electrode 6 are disposed. The dummy electrode 6 may be supplied with an emitter potential E, for example, but is not limited to this; it may also be supplied with other potentials such as a gate potential G. Furthermore, since no emitter layer 7 is disposed on the first semiconductor layer 12 of the diode region 22, the dummy electrode 6 does not function as a gate electrode.

[0032] In this embodiment and other embodiments described below, examples of impurity concentrations for each layer, such as a low concentration of n- for drift layer 1, a high concentration of n+ for emitter layer 7, a high concentration of n+ for second semiconductor layer 13, and n or p for others, have been described. However, this is not a limitation and can be appropriately changed within the scope of enabling the intended actions in each embodiment.

[0033] In the semiconductor device 100 of Embodiment 1, the IGBT region 21 has a second conductivity type pillar layer 8, namely a boundary pillar layer 8A, at the boundary with the diode region 22, which is connected to the main body layer 2 and the collector layer 11 through the drift layer 1. Through this boundary pillar layer 8A, the movement of electrons 33, which are charge carriers, from the IGBT region 21 to the diode region 22 can be suppressed, thereby suppressing the backlash phenomenon in the RC-IGBT.

[0034] Figure 2 This describes the current-voltage characteristics that explain the quick-return phenomenon in RC-IGBTs. Figure 2 In the diagram, the horizontal axis represents voltage V, and the vertical axis represents current I. Figure 2In the diagram, the characteristic 31 without sudden reversal is illustrated with a dashed line, and the characteristic 32 with sudden reversal is illustrated with a solid line.

[0035] IGBTs typically exhibit characteristics 31 without sudden return, where the pn junction on the back side (in) Figure 1 When the p-type collector layer 11 and the n-type drift layer 1) are above the built-in voltage, hole injection begins and the IGBT starts operating, and the current I rises in a curved manner relative to the voltage V.

[0036] However, in an RC-IGBT, when the IGBT is turned on, the initial pn junction on the back side is lower than the built-in voltage. Therefore, near the boundary between the IGBT region 21 and the diode region 22, electrons 33 injected from the main body layer 2 on the surface side of the IGBT will not detach from the collector layer 11 (p layer) on the back side of the IGBT, but will instead detach to the second semiconductor layer 13 of the diode (in... Figure 1 The IGBT (with the cathode layer in the middle, i.e., the n+ layer) initially exhibits a linear increase in current I relative to voltage V, as shown in characteristic 32. This is because the p-layer on the back side of the IGBT is an n+ layer, similar to the structure of a MOSFET. Subsequently, when the voltage applied to the pn junction on the back side rises and exceeds the built-in voltage, the IGBT begins to operate. At this point, since the characteristics revert to the same as those without a sudden return (31), the voltage V temporarily decreases after the rise, as shown in characteristic 32 with a sudden return. This phenomenon is called the sudden return phenomenon. If a sudden return phenomenon occurs, the voltage becomes higher in MOS operation compared to the waveform in normal IGBT operation, resulting in a corresponding increase in losses.

[0037] In contrast, such as Figure 1 As shown, in the semiconductor device 100 of Embodiment 1, the boundary pillar layer 8A serves as a potential barrier for electrons 33, which are charge carriers, thereby suppressing the movement of electrons 33 from the IGBT region 21 to the diode region 22, and thus suppressing the backlash phenomenon in the RC-IGBT.

[0038] Example 2

[0039] Figure 3 This is a cross-sectional view illustrating the general structure of the semiconductor device of Example 2.

[0040] Example 2 is a variation of Example 1, differing from Example 1 in that the diode region 22 has: a second conductivity pillar layer 8, i.e., a diode pillar layer 8B, disposed inside the drift layer 1 and connected to the first semiconductor layer 12; and a low-lifetime region 14 disposed inside the drift layer 1 and closer to the second semiconductor layer 13 than the first semiconductor layer 12. Furthermore, in Figure 3The example shown is of diode pillar layer 8B in contact with second semiconductor layer 13, but it is not limited to this; a drift layer 1 may also exist between diode pillar layer 8B and second semiconductor layer 13. Furthermore, although in Figure 3 An example is shown where the low-lifetime region 14 is also located within the IGBT region 21, but this is not a limitation, as long as it is located at least within the diode region 22. Otherwise, it is the same as in Embodiment 1.

[0041] The low lifetime region 14 is a region where lattice defects are formed by irradiation with light ions such as protons or helium, which can shorten the lifetime of charge carriers.

[0042] Typically, the diode pillar layer 8B is not provided. Furthermore, to reduce the peak current during diode recovery, light ion irradiation is performed from the surface side of the semiconductor device 100, forming a low-lifetime region 14 inside the drift layer 1 and near the first semiconductor layer 12. The reason for forming this location is that at the moment the peak current occurs during diode recovery, the voltage between the anode and cathode of the diode is rising, therefore the depletion layer in the drift layer 1 hardly emerges from the pn junction on the surface side (…). Figure 3 The middle part is the junction between the p-type first semiconductor layer 12 and the n-type drift layer 1.

[0043] However, if light ion irradiation is performed from the surface side, the insulating film 4 (gate insulating film) of the IGBT region 21 is also irradiated, generating boundary charges on the insulating film 4 (gate insulating film) and causing fluctuations in the threshold voltage of the IGBT gate. Furthermore, although it is possible to avoid light ion irradiation of the IGBT region 21 using a metal mask, this requires equipment such as a metal mask, increasing manufacturing costs. Additionally, if light ion irradiation is performed from the back side and a low-lifetime region 14 is formed near the first semiconductor layer 12, the injection energy needs to be increased, resulting in greater dispersion, and if there are deviations in wafer thickness, irradiation position deviations occur.

[0044] Therefore, in this embodiment, by configuring the diode region 22 with an SJ structure in which a diode pillar layer 8B is provided inside the drift layer 1, when a voltage is applied to the diode, the depletion layer also extends laterally from the diode pillar layer 8B connected to the first semiconductor layer 12. Thus, even at low voltages, the drift layer 1 is depleted, and the depletion layer extends to the vicinity of the back side. Therefore, it is sufficient to provide the low-lifetime region 14, which reduces the peak current during diode recovery, near the back side inside the drift layer 1, and the irradiation of light ions used to form the low-lifetime region 14 only needs to be performed from the back side towards the vicinity of the back side. This suppresses threshold voltage fluctuations at the IGBT gate and prevents deviations in the irradiation position of light ions.

[0045] Example 3

[0046] Figure 4 This is a cross-sectional view illustrating the general structure of the semiconductor device of Example 3.

[0047] Example 3 is a variation of Example 2, differing from Example 2 in that the IGBT region 21 has a buffer layer 10 of a first conductivity type between the drift layer 1 and the collector layer 11, except for the boundary pillar layer 8A, and the diode region 22 has a buffer layer 10 between the drift layer 1 and the second semiconductor layer 13. Furthermore, in this example, an example is shown where the diode pillar layer 8B is in contact with the buffer layer 10. Otherwise, it is the same as Example 2.

[0048] According to this embodiment, by providing the buffer layer 10, the depletion layer is difficult to reach the back side, thus ensuring withstand voltage. In addition, in the IGBT region 21, the buffer layer 10 is provided in the region other than the boundary pillar layer 8A, thus preventing the charge carriers, i.e. electrons 33, injected in the IGBT region 21 from detaching from the diode region 22 through the buffer layer 10.

[0049] Furthermore, in bipolar devices like IGBTs, unlike unipolar devices like MOSFETs, even if the drift layer 1 is made into an SJ structure to increase its density, the effect of reducing the on-state voltage is not very good. The current path is narrowed and the amount of pillar layer 8 is increased. Therefore, the pillar layer 8 in the IGBT region 21 is preferably only the boundary pillar layer 8A.

[0050] Example 4

[0051] Figure 5 This is a cross-sectional view illustrating the general structure of the semiconductor device in Embodiment 4.

[0052] Example 4 is a variation of Example 3, differing from Example 3 in that the diode pillar layer 8B and the buffer layer 10 are not in contact, and a drift layer 1 exists between the diode pillar layer 8B and the buffer layer 10. Furthermore, the low-lifetime region 14 is preferably located between the diode pillar layer 8B and the buffer layer 10, but is not limited thereto. Otherwise, it is the same as Example 3.

[0053] In the configuration of Example 3, during diode recovery, after the peak current flows, the current immediately returns to a stable value without any tail current. The reason for this is that during diode recovery, if the diode pillar layer 8B is present, the carriers in that portion disappear due to depletion at low voltage. If depletion progresses to the second semiconductor layer 13 in this state, after the peak current flows, since there are no remaining carriers, no tail current flows, and the current immediately returns to a stable value. This results in a larger rate of change of current (di / dt), generating surge voltage jumps and causing voltage and current waveform oscillations.

[0054] Therefore, in this embodiment, by configuring a drift layer 1 between the diode pillar layer 8B and the buffer layer 10, residual charge carriers are present in the drift layer 1 of this portion during diode recovery. Because of the presence of these residual charge carriers, a tail current is generated after the peak current flows during diode recovery, which can suppress voltage jumps and voltage / current waveform oscillations.

[0055] Furthermore, by setting a low-lifetime region 14 in this section, it is possible to suppress the tail current from becoming too large, thereby suppressing the waveform oscillation of voltage jumps and voltage-current, and reducing the tail current.

[0056] The embodiments of the present invention have been described above, but the present invention is not limited to the structures described in the embodiments, and various changes can be made within the scope of the technical concept of the present invention. In addition, some or all of the structures described in each embodiment can also be combined and applied.

[0057] Symbol Explanation

[0058] 1: Drift layer, 2: Main layer, 3: Trench, 4: Insulating film, 5: Gate electrode, 6: Dummy electrode, 7: Emitter layer, 8: Pillar layer, 8A: Boundary pillar layer, 8B: Diode pillar layer, 9: Interlayer insulating film, 10: Buffer layer, 11: Collector layer, 12: First semiconductor layer, 13: Second semiconductor layer, 14: Low lifetime region, 21: IGBT region, 22: Diode region, 31: No cyclic characteristic, 32: Cyclic characteristic, 33: Electron, 100: Semiconductor device, G: Gate potential, E: Emitter potential, A: Anode potential, I: Current, V: Voltage.

Claims

1. A semiconductor device having an IGBT region and a diode region within the same chip, characterized in that, The IGBT in the IGBT region has: a drift layer of the first conductivity type; trench; A gate electrode is disposed within the trench; a second conductivity type body layer is disposed adjacent to the trench on the surface side compared to the drift layer; and a first conductivity type emitter layer is disposed on the surface side of the body layer. A gate insulating film disposed between the body layer and the emitter layer and the gate electrode; and a collector layer of a second conductivity type disposed on the back side compared to the drift layer. The diode in the diode region has the drift layer, a first semiconductor layer of a second conductivity type disposed on a side closer to the surface of the drift layer, and a second semiconductor layer of a first conductivity type disposed on a side closer to the back surface of the drift layer. The IGBT region has a boundary pillar layer of a second conductivity type at the boundary with the diode region, which penetrates the drift layer and is connected to the body layer and the collector layer.

2. The semiconductor device according to claim 1, characterized in that, The diode region has: a diode pillar layer of a second conductivity type disposed inside the drift layer and in contact with the first semiconductor layer; and a low lifetime region disposed inside the drift layer and closer to the second semiconductor layer than the first semiconductor layer.

3. The semiconductor device according to claim 2, characterized in that, The IGBT region, located between the drift layer and the collector layer, has a buffer layer of a first conductivity type in the region other than the boundary pillar layer. The diode region has the buffer layer between the drift layer and the second semiconductor layer.

4. The semiconductor device according to claim 3, characterized in that, The diode pillar layer is connected to the buffer layer.

5. The semiconductor device according to claim 3, characterized in that, The drift layer exists between the diode pillar layer and the buffer layer.

6. The semiconductor device according to claim 5, characterized in that, The low-lifetime region is located between the diode pillar layer and the buffer layer.

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