Semiconductor device and method for manufacturing semiconductor device

Abstract

An IGBT chip (1) is provided with: an n-type semiconductor substrate (6); a p-type diffusion layer (8) partially formed on a surface portion of the n-type semiconductor substrate (6); an interlayer insulating film (9) in contact with the n-type semiconductor substrate (6) and the p-type diffusion layer (8); and a field plate electrode (12) in contact with the p-type diffusion layer (8) and the interlayer insulating film (9). The field plate electrode (12) has, on the surface thereof, an AlN-based modified layer (21) comprising an inorganic film containing a nitride, and the interlayer insulating film (9) has, on the surface thereof, a SiON-based modified layer (22) comprising an inorganic film containing a nitride.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. BACKGROUND

[0002] As one of the causes of the deterioration of the withstand voltage of the power semiconductor chip, there is an electric field concentration at the chip terminal portion. If a junction is formed on the surface of the power semiconductor chip, when a reverse bias is applied, a depletion layer expands in a fan shape at the terminal portion. The electric lines of force of the charges in the fan-shaped region concentrate at the chip terminal portion, and a so-called electric field concentration occurs. As a result, avalanche breakdown (insulation breakdown) occurs at a voltage much lower than the theoretical withstand voltage.

[0003] In order to alleviate the electric field concentration at the chip terminal portion, it is necessary to disperse the destination of the electric lines of force of the charges from the depletion layer region that expands in a fan shape when a reverse bias is applied from the chip terminal portion to the entire terminal structure (hereinafter, also referred to as a terminal region).

[0004] Power semiconductors are used in various severe environments, and thus it is necessary to satisfy a plurality of reliability items. As one of the required reliability items, there is a high-temperature high-humidity bias test (H3TRB) resistance in which a certain voltage is continuously applied in a high-temperature high-humidity environment.

[0005] It is known that in a power semiconductor having a field plate structure formed of an Al electrode, the Al electrode is corroded due to moisture in a high-temperature high-humidity environment, and this causes an increase in leakage current and deterioration of the withstand voltage.

[0006] In Patent Literature 1, a semiconductor device provided with a semiconductor portion, a terminal insulating film, a first protective film, a second electrode, a terminal electrode, a first insulating film, and a second protective film is described. The semiconductor device described in Patent Literature 1 describes that a passivation region formed of an inorganic film that prevents the intrusion of moisture is formed on the Al electrode.

[0007] PRIOR ART DOCUMENTS

[0008] PATENT LITERATURE

[0009] Patent Literature 1: Japanese Patent Application Publication No. 2022-047410 SUMMARY

[0010] PROBLEMS TO BE SOLVED BY THE INVENTION

[0011] The passivation film that forms the passivation region is mostly a film of a silicon nitride film system that has excellent moisture resistance. However, the stress of the silicon nitride film is large, and depending on the film thickness, there is a risk of cracks occurring due to thermal stress generated by heat treatment in processes after the passivation film is formed, stress at the time of mounting, and the like. If cracks occur, the function of preventing moisture is lost, and this leads to a decrease in H3TRB resistance.

[0012] In addition, in the active region provided on the main surface of the semiconductor substrate, the passivation film needs to be removed. Therefore, a process for removing the passivation film needs to be provided, resulting in an increase in the number of processes.

[0013] The present application has been achieved in view of such circumstances, and has an object to provide a semiconductor device capable of suppressing generation of cracks caused by film stress and achieving improvement in high-temperature high-humidity bias test resistance.

[0014] Means for solving the problem

[0015] To solve the above problem, the semiconductor device of the present application is characterized by comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type, which is partially formed on a surface portion of the first semiconductor layer; an interlayer insulating film, which is in contact with the first semiconductor layer and the second semiconductor layer; and a field plate electrode, which is in contact with the second semiconductor layer and the interlayer insulating film, the field plate electrode having a first modification layer composed of an inorganic film containing a nitride on a surface, and the interlayer insulating film having a second modification layer composed of an inorganic film containing the nitride on a surface.

[0016] Effects of the Invention

[0017] According to the present application, generation of cracks caused by film stress can be suppressed, and improvement in high-temperature high-humidity bias test resistance can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a plan view showing the appearance of the semiconductor device of the first embodiment of the present application.

[0019] Figure 2 is Figure 1 A-A' sectional view of

[0020] Figure 3A is a sectional view of a manufacturing process before formation of a surface electrode of the semiconductor device of the embodiment of the present application.

[0021] Figure 3B is a sectional view of a manufacturing process after formation of the surface electrode of Figure 3A

[0022] Figure 3C is a sectional view of a manufacturing process after plasma nitriding treatment of Figure 3B

[0023] Figure 3D is a sectional view of a manufacturing process after formation of an organic protective film of Figure 3C

[0024] Figure 3E is a sectional view of a manufacturing process after formation of a surface electrode of Figure 3D ​​​A cross-sectional view of the manufacturing process after the removal of the modified layer in the active region.

[0025] Figure 4 This is a top view showing the appearance of the semiconductor device according to the second embodiment of the present invention.

[0026] Figure 5 yes Figure 4 The B-B' sectional view.

[0027] Figure 6A This is a cross-sectional view of the manufacturing process prior to the formation of the surface electrode of the semiconductor device according to an embodiment of the present invention.

[0028] Figure 6B It continues Figure 6A A cross-sectional view of the manufacturing process after the surface electrode is formed.

[0029] Figure 6C It continues Figure 6B A cross-sectional view of the manufacturing process after plasma nitriding treatment.

[0030] Figure 6D It continues Figure 6C A cross-sectional view of the manufacturing process after the formation of the organic protective film.

[0031] Figure 6E It continues Figure 6D A cross-sectional view of the manufacturing process after the removal of the modified layer in the active region. Detailed Implementation

[0032] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, the same reference numerals are used to denote the same structures in each drawing, and detailed descriptions of repeated parts are omitted.

[0033] (First Implementation)

[0034] Figure 1 and Figure 2 This is a diagram illustrating the structure of a semiconductor device according to a first embodiment of the present invention. Figure 1 This is a top view showing the appearance of the semiconductor device according to this embodiment. Figure 2 yes Figure 1 A-A' sectional view.

[0035] The following description uses an IGBT (Insulated Gate Bipolar Transistor) chip as an example of a semiconductor device, but the scope of this invention is not limited to this, and can also be applied to diodes, thyristors, power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), DMOSFETs (Double-Diffused MOSFETs), etc. Examples of its application to diodes will be described later.

[0036] like Figure 1 As shown, the IGBT chip 1 (semiconductor device) includes an active region 5 disposed on the main surface of a semiconductor substrate and a termination region 4 disposed around the active region 5. An emitter electrode 2 and a gate electrode pad 3 are formed on the active region 5. The termination region 4 is a termination structure, i.e., an electric field mitigation region, that mitigates electric field concentration in the chip termination portion of the IGBT chip 1.

[0037] like Figure 2 As shown, the terminal region 4, for example, includes: multiple guard rings 7 (second semiconductor layers of the second conductivity type) formed on the main surface of an n-type semiconductor substrate 6 (first semiconductor layer of the first conductivity type); a p-type diffusion layer 8 (second semiconductor layer of the second conductivity type); an interlayer insulating film 9 formed on the main surface of the semiconductor substrate 6; a gate wiring 10 formed in the interlayer insulating film 9; a gate electrode 11 formed on the interlayer insulating film 9 and connected to the gate wiring 10 through an opening formed in the interlayer insulating film 9; a field plate electrode 12 formed on the interlayer insulating film 9 and connected to the guard rings 7 through an opening formed in the interlayer insulating film 9; an emitter electrode 2 formed on the interlayer insulating film 9 and connected to the p-type diffusion layer 8 through an opening formed in the interlayer insulating film 9; and an organic protective film 13 formed to cover the interlayer insulating film 9 and the Al electrodes (emitter electrode 2, gate electrode 11, and field plate electrode 12). The gate electrode 11 and... Figure 1 The gate electrode pad 3 shown is electrically connected.

[0038] The IGBT chip 1 has: an active portion 31 as an active region for energizing current; a gate finger portion 32 as a region having a gate wiring 10 and a gate electrode 11; and a terminal portion 33 as a terminal region for maintaining withstand voltage.

[0039] The gate finger portion 32 has a well region (P-well) as a diffusion layer and a gate electrode 11 electrically connected to the well region, and the terminal region (terminal portion 33) has a well region (P-well) as a diffusion layer and a field plate electrode 12 electrically connected to the well region.

[0040] The n-type semiconductor substrate 6 is a Si substrate. The n-type semiconductor substrate 6 can also use a SiC substrate, a GaN substrate, or the like.

[0041] The guard ring 7 and the p-type diffusion layer 8 are p-type diffusion layers formed on the surface of the semiconductor substrate 6 by ion implantation.

[0042] The interlayer insulating film 9 is composed of a gate oxide film to be described later, which is formed by high-temperature oxidation or the like, and an interlayer film such as a TEOS (TetraEthoxy Silane) film, a BPSG (Boron-phospho silicate glass) film, or the like, all of which are silicon oxide films (SiO2).

[0043] The field plate electrode 12 is an electrode film composed of a laminated film of, for example, Ti / (in the following description, " / " indicates "or") TiN / Al, MoSi / Al, or the like, and is formed in the same layer as the emitter electrode 2, the gate electrode pad 3 (gate electrode 11), and the gate wiring 10 of the active region (active portion 31). Figure 1 ) of the semiconductor substrate 6.

[0044] The emitter electrode 2, the gate wiring 10, the gate electrode 11, and the field plate electrode 12 are composed of Al electrodes (Al-based electrodes).

[0045] The Al electrode itself of the surface of each electrode of the emitter electrode 2, the gate electrode 11, and the field plate electrode 12 of the non-active region is subjected to plasma nitriding treatment (for example, N2 plasma, NH3 plasma treatment), and an AlN-based modification layer 21 (first modification layer) is formed. That is, the emitter electrode 2, the gate electrode 11, and the field plate electrode 12 of the non-active region have the AlN-based modification layer 21 formed by plasma nitriding treatment in the surface portion.

[0046] In the present embodiment, plasma nitriding treatment is used, but nitriding treatment other than plasma, such as thermal nitriding treatment, ion nitriding treatment, radical nitriding treatment, can also be used.

[0047] The AlN-based modification layer 21 modifies only the surface of each electrode, and thus the film thickness of each electrode is the same as before the plasma nitriding treatment.

[0048] In the case where the AlN-based modification layer 21 is formed on the surface of the emitter electrode 2, the gate electrode 11, and the field plate electrode 12 by the above-described plasma nitriding treatment, a SiON-based modification layer 22 (second modification layer) is also formed on the surface of the interlayer insulating film between the electrodes at the same time.

[0049] That is, in the plasma nitriding process of one process, the AlN-based modification layer 21 is formed on the surfaces of the emitter electrode 2, the gate electrode 11, and the field plate electrode 12, and the SiON-based modification layer 22 is formed on the surface of the interlayer insulating film 9 between the electrodes.

[0050] The organic protective film 13 is formed of, for example, a polyimide film.

[0051] On the back surface of the semiconductor substrate 6, the n-type buffer layer 14, the p-type collector layer 15, and the collector 16 are formed in this order from the substrate side.

[0052] Hereinafter, the operation of the IGBT chip 1 configured as described above will be described.

[0053] (Operation of IGBT chip 1)

[0054] In the active region (active portion 31), if a voltage is applied between the gate electrode 11 and the emitter electrode 2, an n-channel inversion layer is formed just below the gate oxide film of the gate wiring 10, and the MOSFET portion becomes ON. Also, if a voltage is applied between the collector 16 and the emitter electrode 2, an avalanche of holes occurs from the collector 16 toward the emitter electrode 2, a current flows between the collector 16 and the emitter electrode 2, and the IGBT is turned on. If the voltage between the gate electrode 11 and the emitter electrode 2 is returned to 0 (zero), the inversion layer disappears, the n-channel of the MOSFET portion is cut off, and the IGBT becomes off.

[0055] (Method of manufacturing IGBT chip 1)

[0056] Figures 3A-3E is a cross-sectional view showing a manufacturing process of the IGBT chip 1. Figure 3A is a cross-sectional view of a manufacturing process before the surface electrodes are formed, Figure 3B is a cross-sectional view of a manufacturing process after the surface electrodes are formed, Figure 3C is a cross-sectional view of a manufacturing process after the plasma nitriding process, Figure 3D is a cross-sectional view of a manufacturing process after the organic protective film is formed, Figure 3E is a cross-sectional view of a manufacturing process after the modification layers of the active region are removed.

[0057] In addition, in each drawing, a cross section showing a manufacturing process of the termination region (termination portion 33) is mainly shown.

[0058] First, a gate oxide film (SiO2) (not shown) is formed on the main surface of an n-type semiconductor substrate 6 using dry oxidation with dry oxygen (O2) and selective oxidation using water vapor based on the combustion reaction of oxygen (O2) and hydrogen (H2) (high-temperature oxidation). Then, a polycrystalline silicon film (Poly-Si) (not shown) is formed on this gate oxide film using a low-pressure CVD apparatus or the like. Finally, a gate electrode is formed by photolithography-based patterning and etching. Figure 2 (symbol 11). Next, p-type impurities such as boron (B) are implanted into the main surface of the semiconductor substrate 6 by ion implantation to form p-type diffusion layers 7 and 8. This p-type diffusion layer 7 serves as a protective ring ( Figure 2 The symbol 7) plays a function.

[0059] Next, as Figure 3A As shown, an interlayer insulating film (SiO2) 9, such as a TEOS film and a BPSG film, is formed on the main surface of the semiconductor substrate 6 using a plasma CVD apparatus, an atmospheric pressure CVD apparatus, or the like, to cover the gate oxide film (not shown) and the gate wiring 10. Then, through photolithography-based patterning and etching, an opening (contact hole) 17 is formed in the interlayer insulating film 9, extending to the p-type diffusion layer 8 and the protective ring 7. At this time, an opening (contact hole) 17 is also formed on the gate wiring 10.

[0060] Next, as Figure 3B As shown, an electrode film (not shown) composed of, for example, Ti / TiN / Al or MoSi / Al is formed on the main surface of the semiconductor substrate 6 by means of a plasma CVD apparatus, a sputtering apparatus, etc., covering the interlayer insulating film 9 and embedding it in the openings (contact holes) 17 formed in the interlayer insulating film 9. Then, through photolithography-based patterning and etching, the emitter electrode 2, the gate electrode 11, and the field electrode 12 are formed. Figure 2 ).

[0061] Next, as Figure 3C As shown, by using plasma nitriding treatment with N2 plasma and NH3 plasma, modified layers (AlN-based modified layer 21 and SiON-based modified layer 22) are formed on the surfaces of the Al electrodes (emitter electrode 2, gate electrode 11, and field plate electrode 12) and the interlayer insulating film 9. That is, through a single plasma nitriding process, AlN-based modified layer 21 is formed on the surfaces of the emitter electrode 2, gate electrode 11, and field plate electrode 12, and SiON-based modified layer 22 is formed on the surface of the interlayer insulating film 9 between the electrodes.

[0062] The AlN-based modified layer 21 only modifies the surface of each electrode, so the film thickness of each electrode is the same as before plasma nitriding treatment.

[0063] Next, asFigure 3D As shown, an organic protective film (polyimide film) 13 is applied on the main surface of the semiconductor substrate 6 so as to cover the emitter electrode 2, the gate electrode 11, and the field plate electrode 12 having the AlN-based modification layer 21, by an application device.

[0064] Next, as shown in FIG. 2B, the AlN-based modification layer 21 on the surface of the emitter electrode 2 of the active region is removed by patterning based on photolithography and etching. Figure 3E

[0065] Finally, on the back surface of the semiconductor substrate 6, as a back surface process, an n-type buffer layer 14, a p-type collector layer 15, and a collector electrode 16 are sequentially formed from the substrate side.

[0066] Through the above manufacturing process, the terminal structure shown in FIG. 1 is formed. Figure 2

[0067] As described above, the IGBT chip 1 (semiconductor device) of the present embodiment Figure 1 , Figure 2 has: an n-type semiconductor substrate 6 (first semiconductor layer of a first conductive type); a p-type diffusion layer 8 (second semiconductor layer of a second conductive type) partially formed on a surface portion of the n-type semiconductor substrate 6; an interlayer insulating film 9 in contact with the n-type semiconductor substrate 6 and the p-type diffusion layer 8; and a field plate electrode 12 in contact with the p-type diffusion layer 8 and the interlayer insulating film 9, the field plate electrode 12 having an AlN-based modification layer 21 (first modification layer) composed of an inorganic film formed by plasma nitriding treatment on the surface, and the interlayer insulating film 9 having a SiON-based modification layer 22 (second modification layer) composed of an inorganic film formed by nitriding treatment (e.g., plasma nitriding treatment) on the surface.

[0068] In addition, the manufacturing method of the IGBT chip 1 Figures 3A-3E has: a process of partially forming the p-type diffusion layer 8 (second semiconductor layer of a second conductive type) on a surface portion of the n-type semiconductor substrate 6 (first semiconductor layer of a first conductive type); a process of forming the interlayer insulating film 9 in contact with the n-type semiconductor substrate 6 and the p-type diffusion layer 8; a process of forming the field plate electrode 12 in contact with the p-type diffusion layer 8 and the interlayer insulating film 9; and a process of performing nitriding treatment (e.g., plasma nitriding treatment) on the field plate electrode 12 and the interlayer insulating film 9 to form a modification layer (AlN-based modification layer 21, SiON-based modification layer 22) containing nitride on the surface.

[0069] ​​Thus, after the field plate electrode 12 is formed, plasma nitriding treatment (for example, N2 plasma, NH3 plasma, or the like) is performed on the Al electrodes (the emitter electrode 2, the gate electrode 11, and the field plate electrode 12) themselves. By the plasma nitriding treatment, the AlN-based modification layer 21 is formed on the surfaces of the emitter electrode 2, the gate electrode 11, and the field plate electrode 12, and the SiON-based modification layer 22 is also formed on the surface of the interlayer insulating film 9 between the electrodes.

[0070] The AlN-based modification layer 21 of the IGBT chip 1 of the present embodiment Figure 1 , Figure 2 ) improves the moisture resistance of the surface of the Al electrode, and thus can prevent corrosion of the Al electrode and improve H3TRB resistance.

[0071] The AlN-based modification layer 21 modifies only the surface of each Al electrode, and thus the film thickness of each electrode is the same as before the plasma nitriding treatment. Thus, the generation of cracks due to film stress can be suppressed.

[0072] In addition, the SiO2 of the interlayer insulating film 9 is also simultaneously subjected to the nitriding treatment, and the surface becomes a SiON layer. Thus, moisture that has intruded through the interlayer insulating film 9 can also be prevented, and an improvement in H3TRB resistance can be expected.

[0073] As described above, the generation of cracks due to film stress can be suppressed, and moisture can be reliably prevented from penetrating from the surface side of the IGBT chip 1, and an improvement in high-temperature high-humidity bias test resistance can be achieved.

[0074] In addition, in the active region provided on the main surface of the semiconductor substrate, a process of removing the passivation film is not required, and the number of processes can be reduced.

[0075] In the IGBT chip 1 of the present embodiment Figure 1 , Figure 2 ), the emitter electrode 2 is provided in contact with the p-type diffusion layer 8 (second semiconductor layer) and the interlayer insulating film 9, and the emitter electrode 2 has the AlN-based modification layer 21 formed on the surface thereof by plasma nitriding treatment.

[0076] Thus, the IGBT chip 1 improves the moisture resistance of the surface of the emitter electrode 2 by the AlN-based modification layer 21 (first modification layer), and thus can prevent corrosion of the emitter electrode 2 and improve H3TRB resistance. In addition, in the emitter electrode 2, the generation of cracks due to film stress can be suppressed.

[0077] In the IGBT chip 1 of the present embodiment Figure 1 , Figure 2 ), the field plate electrode 12 is an aluminum electrode, and the AlN-based modification layer 21 is aluminum nitride obtained by modifying the aluminum electrode by plasma nitriding treatment.

[0078] Thus, the IGBT chip 1 can prevent corrosion of the emitter electrode 2 and improve H3TRB resistance by improving the moisture resistance of the surface of the emitter electrode 2 through the AlN-based modification layer 21.

[0079] In the IGBT chip 1 of the present embodiment, Figure 1 , Figure 2 The SiON-based modification layer 22 (second modification layer) is silicon oxynitride.

[0080] Thus, the IGBT chip 1 can improve H3TRB resistance by preventing moisture from the SiON-based modification layer 22 from intruding through the interlayer insulating film 9.

[0081] In the IGBT chip 1 of the present embodiment, Figure 1 , Figure 2 The active region (active part 31) disposed on the main surface of the semiconductor substrate and the termination region (termination part 33) disposed on the main surface so as to surround the active region are provided, and the termination region has the field plate electrode 12 and the interlayer insulating film 9.

[0082] Thus, the IGBT chip 1 can improve the high-temperature high-humidity bias resistance of the termination structure (termination region) of the chip in a relatively simple manner, and realize a semiconductor device with high reliability that can suppress the influence on the device characteristics.

[0083] In the IGBT chip 1 of the present embodiment, Figure 1 , Figure 2 The AlN-based modification layer 21 (first modification layer) of the emitter electrode 2 of the active region disposed on the main surface of the semiconductor substrate is removed.

[0084] Thus, the IGBT chip 1 can realize electrical connection with the emitter electrode 2 by removing the AlN-based modification layer 21 of the emitter electrode 2 of the active region.

[0085] (Second Embodiment)

[0086] Figure 4 and Figure 5 are diagrams showing the structure of a semiconductor device of the second embodiment of the present application. Figure 4 is a plan view showing the appearance of the semiconductor device of the present embodiment, Figure 5 is Figure 4 a B-B' sectional view of FIG. 1. As a semiconductor device, it is an example applied to a diode.

[0087] As Figure 4As shown, the diode 50 (semiconductor device) has an active region 55 disposed on a main surface of a semiconductor substrate and a termination region 54 disposed so as to surround the active region 55. The termination region 54 is a termination structure that mitigates concentration of an electric field in a chip termination portion of the diode 50, i.e., an electric field mitigation region.

[0088] As shown, the termination region 54 has, for example, a plurality of guard rings 57 formed on a main surface of an n-type semiconductor substrate 56, a P layer 58, an interlayer insulating film 59 formed on the main surface of the semiconductor substrate 56, a field plate electrode 61 formed on the interlayer insulating film 59 and connected to the guard rings 57 through an opening formed in the interlayer insulating film 59, an anode electrode 60 formed on the interlayer insulating film 59 and connected to the P layer 58 through an opening formed in the interlayer insulating film 59, and an organic protective film 63 formed so as to cover the interlayer insulating film 59 and the Al electrodes (anode electrode 60, field plate electrode 61). Figure 4

[0089] The diode 50 has an active portion 81 that is an active region through which current flows and a termination portion 82 that is a termination region that maintains a withstand voltage.

[0090] The active region (active portion 81) has the P layer 58 and the anode electrode 60. The termination region (termination portion 82) has a well region (P-well) that is a diffusion layer and the field plate electrode 61 that is electrically connected to the well region.

[0091] The n-type semiconductor substrate 56 is a Si substrate. The n-type semiconductor substrate 56 can also use a SiC substrate, a GaN substrate, or the like.

[0092] The guard rings 57 are p-type diffusion layers formed on the surface of the semiconductor substrate 56 by ion implantation.

[0093] The P layer 58 is connected to the anode electrode 60 and becomes an anode of the diode 50.

[0094] The interlayer insulating film 59 is composed of a gate oxide film formed by high-temperature oxidation or the like, and an interlayer film such as a TEOS film, a BPSG film, or the like, all of which are silicon oxide films (SiO2).

[0095] The field plate electrode 61 is, for example, an electrode film composed of a laminated film of Ti / TiN / Al, MoSi / Al, or the like, and is formed in the same layer as the anode electrode 60 of the active region (active portion 81).

[0096] The anode electrode 60 and the field plate electrode 61 are composed of Al electrodes (Al-based electrodes).

[0097] ​The surface of each electrode of the anode electrode 60 and the field plate electrode 61 of the non-active region is subjected to plasma nitriding treatment (for example, N2 plasma, NH3 plasma treatment) to form an AlN-based modification layer 71. That is, the anode electrode 60 and the field plate electrode 61 of the non-active region have the AlN-based modification layer 71 formed by the plasma nitriding treatment at the surface portion.

[0098] The AlN-based modification layer 71 modifies only the surface of each electrode, and thus the film thickness of each electrode is the same as before the plasma nitriding treatment.

[0099] In the case where the AlN-based modification layer 71 is formed on the surfaces of the anode electrode 60 and the field plate electrode 61 by the above-described plasma nitriding treatment, the SiON-based modification layer 72 is also formed on the surface of the interlayer insulating film between the electrodes.

[0100] That is, in the one-step plasma nitriding treatment step, the AlN-based modification layer 71 is formed on the surfaces of the anode electrode 60 and the field plate electrode 61, and the SiON-based modification layer 72 is formed on the surface of the interlayer insulating film 59 between the electrodes.

[0101] The organic-based protective film 63 is, for example, a polyimide film.

[0102] On the back surface of the semiconductor substrate 6, an n-type buffer layer 64, an N + layer 65, and a cathode electrode 66 are sequentially formed from the substrate side.

[0103] Next, a manufacturing method of the diode 50 configured as described above will be described.

[0104] Figures 6A-6E is a cross-sectional view showing a manufacturing step of the diode 50. Figure 6A is a cross-sectional view of a manufacturing step before formation of the surface electrode, Figure 6B is a cross-sectional view of a manufacturing step after formation of the surface electrode, Figure 6C is a cross-sectional view of a manufacturing step after plasma nitriding treatment, Figure 6D is a cross-sectional view of a manufacturing step after formation of the organic-based protective film, Figure 6E is a cross-sectional view of a manufacturing step after removal of the modification layer of the active region.

[0105] In addition, in each drawing, a cross section showing a manufacturing process of the terminal region (terminal portion 82) is mainly shown.

[0106] First, a gate oxide film (SiO2) (not shown) is formed on the main surface of an n-type semiconductor substrate 56 using dry oxidation with dry oxygen (O2) and selective oxidation using water vapor based on the combustion reaction of oxygen (O2) and hydrogen (H2) (high-temperature oxidation). Then, a polycrystalline silicon film (Poly-Si) (not shown) is formed on this gate oxide film using a low-pressure CVD apparatus or the like. Finally, a gate electrode is formed by photolithography-based patterning and etching. Figure 2 (symbol 11). Next, p-type impurities such as boron (B) are implanted into the main surface of the semiconductor substrate 56 by ion implantation to form a p-type diffusion layer 57 and a P layer 58. The p-type diffusion layer 57 serves as a protective ring ( Figure 5 The symbol 57) performs its function. The P layer 58 becomes the anode of the diode 50.

[0107] Next, as Figure 6A As shown, interlayer insulating films (SiO2) 59, such as TEOS films and BPSG films, are formed on the main surface of the semiconductor substrate 56 using plasma CVD equipment, atmospheric pressure CVD equipment, etc. Subsequently, through photolithography-based patterning and etching, openings (contact holes) 67 extending to the protective ring 57 are formed in the interlayer insulating film 9.

[0108] Next, as Figure 6B As shown, an electrode film (not shown) composed of, for example, Ti / TiN / Al or MoSi / Al is formed on the main surface of the semiconductor substrate 56 by means of a plasma CVD apparatus, a sputtering apparatus, etc., covering the interlayer insulating film 59 and embedding it in the openings (contact holes) 67 formed in the interlayer insulating film 59. Then, an anode electrode 60 and a field electrode 61 are formed by photolithography-based patterning and etching. Figure 5 ).

[0109] Next, as Figure 6C As shown, by using plasma nitriding treatment with N2 plasma and NH3 plasma, modified layers (AlN-based modified layer 71 and SiON-based modified layer 72) are formed on the surfaces of the Al electrodes (anode electrode 60 and field plate electrode 61) and the interlayer insulating film 9. That is, through a single plasma nitriding treatment step, AlN-based modified layer 71 is formed on the surfaces of the anode electrode 60 and the field plate electrode 61, and SiON-based modified layer 72 is formed on the surface of the interlayer insulating film 59 between the electrodes.

[0110] The AlN-based modified layer 71 only modifies the surface of each electrode, so the film thickness of each electrode is the same as before plasma nitriding treatment.

[0111] Next, as Figure 6DAs shown, using a coating apparatus, an organic protective film (polyimide film) 63 is coated on the main surface of the semiconductor substrate 56 in such a way that the anode electrode 60 having an AlN-based modified layer 71 and the field plate electrode 61 are covered.

[0112] Next, as Figure 6E As shown, the AlN-based modified layer 71 on the surface of the anode electrode 60 in the active region is removed by photolithography-based patterning and etching.

[0113] Finally, on the back side of the semiconductor substrate 56, as a back-side process, an n-type buffer layer 64 and an N-type buffer layer 65 are sequentially formed from the substrate side. + Layer 65, cathode electrode 66.

[0114] After the manufacturing process described above, it is formed Figure 5 The terminal structure shown.

[0115] As explained above, the diode 50 (semiconductor device) of this embodiment ( Figure 4 , Figure 5 The device comprises: an n-type semiconductor substrate 56 (a first semiconductor layer of a first conductivity type); a p-type diffusion layer 57 (a second semiconductor layer of a second conductivity type) partially formed on the surface of the n-type semiconductor substrate 56; an interlayer insulating film 59 in contact with the n-type semiconductor substrate 56 and the p-type diffusion layer 57; and a field plate electrode 61 in contact with the p-type diffusion layer 57 and the interlayer insulating film 59. The field plate electrode 61 has an AlN-based modified layer 71 (a first modified layer) on its surface, which is an inorganic film (containing nitrides) formed by nitriding treatment (e.g., plasma nitriding treatment). The interlayer insulating film 59 has a SiON-based modified layer 72 (a second modified layer) on its surface, which is an inorganic film (containing nitrides) formed by nitriding treatment (e.g., plasma nitriding treatment).

[0116] In addition, the manufacturing method of diode 50 ( Figures 6A-6E The process includes: partially forming a p-type diffusion layer 57 (a second semiconductor layer of a second conductivity type) on the surface of an n-type semiconductor substrate 56 (a first semiconductor layer of a first conductivity type); forming an interlayer insulating film 59 in contact with the n-type semiconductor substrate 56 and the p-type diffusion layer 57; forming a field plate electrode 61 in contact with the p-type diffusion layer 57 and the interlayer insulating film 59; and performing a nitriding treatment (e.g., plasma nitriding treatment) on the field plate electrode 61 and the interlayer insulating film 59 to form a modified layer (AlN-based modified layer 71, SiON-based modified layer 72) on the surface, which is composed of an inorganic film containing nitrides.

[0117] Therefore, the diode 50 of this embodiment ( Figure 4 , Figure 5) and the IGBT chip 1 of the first embodiment Figure 1 、 Figure 2 ) Also, the AlN-based modification layer 71 improves the moisture resistance of the surface of the Al electrode, thereby being able to prevent corrosion of the Al electrode and improve the H3TRB resistance.

[0118] The AlN-based modification layer 71 modifies only the surface of each Al electrode, and thus the film thickness of each electrode is the same as before the plasma nitriding treatment. Therefore, the generation of cracks due to film stress can be suppressed.

[0119] In addition, the SiO2 of the interlayer insulating film 59 is also simultaneously subjected to the nitriding treatment, and the surface becomes a SiON layer, whereby moisture that has intruded through the interlayer insulating film 59 can also be prevented, and an improvement in the H3TRB resistance can be expected.

[0120] As described above, the generation of cracks due to film stress can be suppressed, and moisture can be reliably prevented from being infiltrated from the surface side of the diode 50, and an improvement in the high-temperature high-humidity bias test resistance can be achieved.

[0121] In addition, in the active region disposed on the main surface of the semiconductor substrate, a process of removing the passivation film is not required, and the number of processes can be reduced.

[0122] In the diode 50 of the present embodiment ( Figure 4 、 Figure 5 ), the anode electrode 60 that is in contact with the p-type diffusion layer 57 (second semiconductor layer) and the interlayer insulating film 59 is provided, and the anode electrode 60 has an AlN-based modification layer 71 formed on the surface thereof by the plasma nitriding treatment.

[0123] Thus, the diode 50 improves the moisture resistance of the surface of the emitter electrode 2 by the AlN-based modification layer 71 (first modification layer), thereby being able to prevent corrosion of the anode electrode 60 and improve the H3TRB resistance. In addition, in the anode electrode 60, the generation of cracks due to film stress can be suppressed.

[0124] In the diode 50 of the present embodiment ( Figure 4 、 Figure 5 ), the AlN-based modification layer 71 (first modification layer) of the anode electrode 60 of the active region disposed on the main surface of the semiconductor substrate is removed.

[0125] Thus, the diode 50 is able to be electrically connected to the anode electrode 60 by removing the AlN-based modification layer 71 of the anode electrode 60 of the active region.

[0126] In addition, the present application is particularly effective for high-voltage products having the configuration in which the guard rings 7, 57 and the field plate electrodes 12, 61 are provided in the terminal regions as described above, but is not necessarily limited thereto. It can also be applied to semiconductor chips having other terminal configurations that do not use the guard rings 7, 57 and the field plate electrodes 12, 61, and to products having relatively low voltage.

[0127] In addition, the present application is not limited to the above-described embodiments, and includes various modifications. For example, the above-described embodiments are described in detail in order to facilitate understanding of the present application, and are not necessarily limited to having all the structures described. In addition, a part of the structure of one embodiment can be replaced with the structure of another embodiment, and in addition, the structure of one embodiment can be added to the structure of another embodiment. In addition, with respect to a part of the structure of each embodiment, addition, deletion, and replacement of other structures can be performed.

[0128] For example, an IGBT is used, but is not limited thereto, and other types of elements can also be applied. In addition, depending on the device, the names of the main terminal and the sensing terminal are called "drain" and "source" instead of the above-described "collector" and "emitter".

[0129] Symbol explanation

[0130] 1: IGBT chip (semiconductor device), 2: emitter electrode, 3: gate electrode pad, 6, 56: semiconductor substrate (first semiconductor layer of first conductivity type), 7, 57: guard ring, 8: p-type diffusion layer (second semiconductor layer of second conductivity type), 9, 59: interlayer insulating film, 10: gate wire, 11: gate electrode, 12, 61: field plate electrode, 13, 63: organic protective film, 14: n-type buffer layer, 15: p-type collector layer, 16: collector, 21, 71: AlN-based modification layer (first modification layer), 22, 72: SiON-based modification layer (second modification layer), 31, 81: active part (active region), 32: gate finger, 33, 82: terminal part (terminal region), 50: diode (semiconductor device), 58: P layer, 64: n-type buffer layer, 65: N + layer, 66: cathode electrode.

Claims

1. A semiconductor device, characterized by comprising: Possessing: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type, partially formed on a surface portion of the first semiconductor layer; an interlayer insulating film, in contact with the first semiconductor layer and the second semiconductor layer; and a field plate electrode, in contact with the second semiconductor layer and the interlayer insulating film, the field plate electrode has a first modification layer on a surface, composed of an inorganic film containing a nitride, the interlayer insulating film has a second modification layer on a surface, composed of an inorganic film containing the nitride.

2. The semiconductor device according to claim 1, wherein Possessing: an emitter electrode, in contact with the second semiconductor layer and the interlayer insulating film, the emitter electrode has the first modification layer on a surface, composed of the nitride.

3. The semiconductor device according to claim 1, wherein Possessing: an anode electrode, in contact with the second semiconductor layer and the interlayer insulating film, the anode electrode has the first modification layer on a surface, composed of the nitride.

4. The semiconductor device according to claim 1, wherein the field plate electrode is an aluminum electrode, the first modification layer is aluminum nitride, which is a modification of the aluminum electrode by nitriding.

5. The semiconductor device according to claim 1, wherein the second modification layer is silicon oxynitride.

6. The semiconductor device according to claim 1, wherein Possessing: an active region, disposed on a main surface of a semiconductor substrate; and a termination region, disposed on the main surface so as to surround the active region, the termination region possesses the field plate electrode and the interlayer insulating film.

7. The semiconductor device according to claim 2, wherein the first modification layer of the emitter electrode of the active region disposed on a main surface of a semiconductor substrate is removed.

8. The semiconductor device according to claim 3, wherein the first modification layer of the anode electrode of the active region disposed on a main surface of a semiconductor substrate is removed.

9. A method for manufacturing a semiconductor device, characterized by Having: a step of partially forming a second semiconductor layer of a second conductivity type on a surface portion of a first semiconductor layer; a step of forming an interlayer insulating film, in contact with the first semiconductor layer and the second semiconductor layer; a step of forming a field plate electrode, in contact with the second semiconductor layer and the interlayer insulating film; and a step of nitriding the field plate electrode and the interlayer insulating film, to form a modification layer on a surface, composed of an inorganic film containing a nitride.

Images