Semiconductor device

Abstract

A semiconductor device (1) is provided with: a semiconductor layer (40) having a semiconductor substrate (32) on the rear surface side and divided into three regions, namely a first region (A1), a second region (A2), and a third region (A3), which do not overlap each other in a planar view of the semiconductor device (1); a first vertical MOS transistor (10) formed in a first region (A1) of the semiconductor layer (40); a second vertical MOS transistor (20) formed in a second region (A2) of the semiconductor layer (40); and a drain pad (151) connected to the semiconductor substrate (32) at a position included in the third region (A3) in a planar view of the semiconductor device (1), the third region (A3) being sandwiched between the first region (A1) and the second region (A2) in the planar view of the semiconductor device (1), and the area of the first region (A1) being larger than the area of the second region (A2) in the planar view of the semiconductor device (1).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, and particularly relates to a chip size package type semiconductor device. BACKGROUND

[0002] A vertical MOS transistor is sometimes used in a circuit in which two systems having different specification current values are integrated into one system.

[0003] PRIOR ART DOCUMENT PATENT DOCUMENT Patent Document 1: Japanese Patent No. 7475569 SUMMARY

[0004] PROBLEMS TO BE SOLVED BY THE INVENTION Miniaturization of a circuit in which a vertical MOS transistor is used is required.

[0005] MEANS FOR SOLVING THE PROBLEMS To solve the above problem, a semiconductor device of one embodiment of the present disclosure is a chip size package type semiconductor device capable of face-down mounting, and includes a semiconductor layer including a semiconductor substrate on the back side, the semiconductor layer being divided into three regions, i.e., a first region, a second region, and a third region, which do not overlap with and are not dispersedly arranged with each other in plan view of the semiconductor device; a first vertical MOS transistor formed in the first region of the semiconductor layer; a second vertical MOS transistor formed in the second region of the semiconductor layer; and a metal layer formed in contact with the back side of the semiconductor layer; the semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, in the plan view, a first source pad and a first gate pad of the first vertical MOS transistor are formed at a position included in the first region, in the plan view, a second source pad and a second gate pad of the second vertical MOS transistor are formed at a position included in the second region, in the plan view, a drain pad connected to the common drain region is formed at a position included in the third region, in the plan view of the semiconductor layer, the first region and the second region are arranged with the third region therebetween, in the plan view, the third region is adjacent to the first region and the second region, and in the plan view, an area of the first region is larger than that of the second region.

[0006] EFFECTS OF THE INVENTION By using the above-described double-structure vertical MOS transistor in a circuit in which two conduction paths having different specification current values are integrated into one, for example, the area required for the circuit can be reduced compared to the related art.

[0007] According to the semiconductor device described above, miniaturization of a circuit using a vertical MOS transistor can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a cross-sectional schematic view showing an example of a configuration of a semiconductor device according to an embodiment.

[0009] Figure 2A is a plan schematic view showing an example of a configuration of a semiconductor device according to an embodiment.

[0010] Figure 2B is a plan schematic view showing an example of a configuration of a semiconductor device according to an embodiment.

[0011] Figure 3 is a cross-sectional schematic view showing an example of a configuration of a semiconductor device according to a modification of the embodiment.

[0012] Figure 4A is a plan schematic view showing a substantially unit structure of a first transistor according to the embodiment.

[0013] Figure 4B is a perspective schematic view showing a substantially unit structure of a first transistor according to the embodiment.

[0014] Figure 5A is a cross-sectional schematic view showing a first conduction path of a semiconductor device according to the embodiment.

[0015] Figure 5B is a cross-sectional schematic view showing a second conduction path of a semiconductor device according to the embodiment.

[0016] Figure 6 is a circuit diagram showing a use example of a semiconductor device according to the embodiment.

[0017] Figure 7 is a circuit diagram showing a use example of a semiconductor device according to a comparative example.

[0018] Figure 8A is a plan schematic view showing an example of a configuration of a transistor according to a comparative example.

[0019] Figure 8B is a plan schematic view showing an example of a configuration of a transistor according to a comparative example.

[0020] Figure 9A is a plan schematic view showing an example of a configuration of a transistor according to a comparative example.

[0021] Figure 9B is a plan schematic view showing an example of a configuration of a transistor according to a comparative example.

[0022] Figure 10is a plan view schematically showing an example of a configuration of a transistor of a modification example of the embodiment.

[0023] Figure 11 is a plan view schematically showing an example of a configuration of a transistor of a modification example of the embodiment.

[0024] Figure 12A is a plan view schematically showing an example of a configuration of a transistor of a modification example of the embodiment.

[0025] Figure 12B is a plan view schematically showing an example of a configuration of a transistor of a modification example of the embodiment.

[0026] Figure 13 is a plan view schematically showing a drain contact region of a semiconductor device of the embodiment.

[0027] Figure 14 is a graph showing a relationship between a configuration of a drain contact region of a semiconductor device of the embodiment and a conduction resistance of each of a first conduction path and a second conduction path. DETAILED DESCRIPTION

[0028] The embodiments described below each represent one specific example of the present disclosure. Numerical values, shapes, materials, configurations, positions of constituent elements, and the like shown in the following embodiments are one example, and are not intended to limit the present disclosure.

[0029] In the present disclosure, "A is electrically connected to B" includes a case where A and B are directly connected via a wiring, a case where A and B are directly connected without a wiring, and a case where A and B are indirectly connected via a resistance component (a resistance element, a resistance wiring).

[0030] (Embodiment) [1. Configuration of Semiconductor Device] Hereinafter, a configuration of a semiconductor device of the embodiment will be described. The semiconductor device of the embodiment is a chip size package (CSP) type semiconductor device capable of face-down mounting, in which two longitudinal MOS (Metal Oxide Semiconductor) transistors of a double structure are formed in a semiconductor substrate. The two longitudinal MOS transistors are power transistors, and are so-called trench MOS type FETs (Field Effect Transistors).

[0031] Figure 1 is a cross-sectional view schematically showing an example of a configuration of the semiconductor device 1 of the embodiment. Figure 2A 、 Figure 2Bis a plan view schematically showing the configuration of the semiconductor device 1 according to an embodiment. In Figure 2A , Figure 2B , the size and shape of the semiconductor device 1 are one example. In addition, the size, shape, and arrangement of the pads and electrodes are also one example.

[0032] Figure 1 is a cross section when the semiconductor device 1 is cut along I-I of Figure 2A .

[0033] As shown in Figure 1 , the semiconductor device 1 has a semiconductor substrate 32, a metal layer 41, and a low-concentration impurity layer 33 formed on the semiconductor substrate 32. In the present disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as a semiconductor layer 40.

[0034] The semiconductor substrate 32 is arranged on the back surface side of the semiconductor layer 40 and is composed of silicon of a first conductivity type containing an impurity at a first concentration. The semiconductor layer 40 has the low-concentration impurity layer 33 of the first conductivity type containing an impurity at a second concentration lower than the first concentration, which is formed in contact with the semiconductor substrate 32. The low-concentration impurity layer 33 is formed on the semiconductor substrate 32, for example, by epitaxial growth.

[0035] As shown in Figure 1 and Figure 2A , the semiconductor device 1 has a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") formed entirely within a first region Al of the semiconductor layer 40, and a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") formed entirely within a second region A2 of the semiconductor layer 40.

[0036] By the transistor 10 formed entirely within the first region Al, it is meant that, when viewed in plan, all elements constituting the transistor 10 are included within the interior of the first region Al and are not included in a region other than the first region Al. Similarly, by the transistor 20 formed entirely within the second region A2, it is meant that, when viewed in plan, all elements constituting the transistor 20 are included within the interior of the second region A2 and are not included in a region other than the second region A2.

[0037] As shown in Figure 2A , when viewed in plan, the surface side of the semiconductor layer 40 is divided into the first region Al, the second region A2, and the third region A3, which are arranged separately from each other without overlapping. Here, the first region Al, the second region A2, and the third region A3 are arranged separately from each other without being dispersed, which means that the first region Al, the second region A2, and the third region A3 are not accompanied by islands, respectively. In Figure 2AIn the diagram, dashed lines represent the imaginary boundary lines 90 that divide the first region A1, the second region A2, and the third region A3. For ease of understanding, the dashed lines representing the boundary lines 90 are shown extending to the outside of the semiconductor layer 40, but the actual boundary lines 90 terminate at the outer periphery of the semiconductor layer 40 when viewed in a plane (in...). Figure 2A , Figure 2B For convenience, the termination points of boundary line 90 are designated as P1, P2, and P3 respectively. Boundary line 90 will be discussed later.

[0038] In addition, Figure 2A In the diagram, for ease of understanding, the dashed lines representing the first region A1, the second region A2, and the third region A3 are not strictly aligned with the outer perimeter and boundary line 90 of the semiconductor layer 40. Instead, they are separated by several blank areas on the inside. However, in reality, the outer perimeters of the first region A1, the second region A2, and the third region A3 are aligned with the outer perimeter and boundary line 90 of the semiconductor layer 40.

[0039] The metal layer 41 is formed in contact with the back side of the semiconductor layer 40, and as a non-limiting example, it can be made of silver (Ag) or copper (Cu). In addition, the metal layer 41 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material.

[0040] like Figure 1 as well as Figure 2A As shown, in the first region A1 of the low-concentration impurity layer 33, a first body region 18 of a second conductivity type different from the first conductivity type is formed. A first source region 14 of the first conductivity type is formed in the first body region 18.

[0041] Furthermore, a plurality of first gate trenches 17 are formed in the first region A1. These first gate trenches 17 are formed to a depth extending from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a portion of the low-concentration impurity layer 33. A first gate conductor 15 is formed on the first gate insulating film 16 inside the first gate trenches 17. The first gate conductor 15 is a buried gate electrode embedded within the semiconductor layer 40. The first gate conductor 15 is electrically connected to the first gate electrode 19 via a first gate wiring (see reference). Figure 2B ).

[0042] The first source electrode 11 includes a portion 12 and a portion 13, wherein the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13.

[0043] The portion 12 of the first source electrode 11 is a layer that is joined with solder at the time of reflow in face-down mounting, and can be composed of a metal material containing any one or more of nickel, titanium, tungsten, and palladium, for example. A plating layer of gold or the like can be applied to the surface of the portion 12.

[0044] The portion 13 of the first source electrode 11 is a layer that connects the portion 12 and the semiconductor layer 40, and can be composed of a metal material containing any one or more of aluminum, copper, gold, and silver, for example.

[0045] Similarly, in the second region A2 of the low-concentration impurity layer 33, a second body region 28 of a second conductivity type different from the first conductivity type is formed. A second source region 24 of the first conductivity type is formed in the second body region 28.

[0046] Further, in the second region A2, a plurality of second gate trenches 27 are formed, which are formed to a depth that reaches the second source region 24 and the second body region 28 from the upper surface of the semiconductor layer 40 to a portion of the low-concentration impurity layer 33, and further, a second gate conductor 25 is formed on a second gate insulating film 26 inside the second gate trench 27. The second gate conductor 25 is a buried gate electrode that is buried inside the semiconductor layer 40. The second gate conductor 25 is electrically connected to a second gate electrode 29 via a second gate wiring (refer to Figure 2B ). The second source electrode 21 includes a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23.

[0047] The portion 22 of the second source electrode 21 is a layer that is joined with solder at the time of reflow in face-down mounting, and can be composed of a metal material containing any one or more of nickel, titanium, tungsten, and palladium, for example. A plating layer of gold or the like can be applied to the surface of the portion 22.

[0048] The portion 23 of the second source electrode 21 is a layer that connects the portion 22 and the semiconductor layer 40, and can be composed of a metal material containing any one or more of aluminum, copper, gold, and silver, for example.

[0049] Figure 2B A state after the portion 13 of the first source electrode 11, the first gate electrode 19, the first gate wiring, the portion 23 of the second source electrode 21, the second gate electrode 29, the second gate wiring, and the portion 83 of the surface drain electrode 81 described later, which are on the surface side of the semiconductor layer 40, of the semiconductor device 1 of the present embodiment are formed is shown in FIG. 8. In Figure 2B , a pad that should not be seen at this point in time is indicated by a broken line for easy understanding.

[0050] AsFigure 1 As shown, the first body region 18 is covered with the interlayer insulating layer 34 having an opening, and a portion 13 of the first source electrode 11 connected with the first source region 14 via the opening of the interlayer insulating layer 34 is provided. The interlayer insulating layer 34 and the portion 13 of the first source electrode 11 are covered with the passivation layer 35 having an opening, and a portion 12 connected with the portion 13 of the first source electrode 11 via the opening of the passivation layer 35 is provided.

[0051] Likewise, the second body region 28 is covered with the interlayer insulating layer 34 having an opening, and a portion 23 of the second source electrode 21 connected with the second source region 24 via the opening of the interlayer insulating layer 34 is provided. The interlayer insulating layer 34 and the portion 23 of the second source electrode 21 are covered with the passivation layer 35 having an opening, and a portion 22 connected with the portion 23 of the second source electrode 21 via the opening of the passivation layer 35 is provided.

[0052] Therefore, as according to Figure 2B As also known, the first source pad 111 and the second source pad 121 respectively refer to portions of the first source electrode 11 and the second source electrode 21 which are partially exposed on the surface of the semiconductor device 1, i.e. terminals. Likewise, the first gate pad 119 and the second gate pad 129 respectively refer to portions of the first gate electrode 19 and the second gate electrode 29 which are partially exposed on the surface of the semiconductor device 1, i.e. terminals.

[0053] The number of the first source pad 111 and the second source pad 121 respectively is not necessarily limited to Figure 2A the number exemplified. In addition, the shape of the first source pad 111 and the second source pad 121 respectively is not necessarily limited to Figure 2A the circular shape exemplified, and can be, for example, a rectangular shape, an elliptical shape. In addition, the arrangement of the first source pad 111 and the second source pad 121 respectively is not limited to Figure 2A the arrangement exemplified.

[0054] The number of the first gate pad 119 and the second gate pad 129 respectively is not necessarily limited to Figure 2A the number exemplified, and can be a plurality of two or more. In addition, the shape of the first gate pad 119 and the second gate pad 129 respectively is not necessarily limited to Figure 2A the circular shape exemplified, and can be, for example, a rectangular shape, an elliptical shape.

[0055] By the above structure of the transistor 10 and the transistor 20, the range in the vicinity of the directly upper portion of the semiconductor substrate 32 in the semiconductor substrate 32 and the low-concentration impurity layer 33 is a common drain region which is common to the first drain region of the transistor 10 and the second drain region of the transistor 20.

[0056] The metal layer 41 is a common drain electrode (hereinafter referred to as the back drain electrode 41) that makes the first drain electrode of transistor 10 and the second drain electrode of transistor 20 common.

[0057] like Figure 1 As shown, a drain pull-up region 38 is formed in the third region A3 of the semiconductor layer 40 to pull the current from the common drain region (semiconductor substrate 32) and the back drain electrode 41 toward the surface side of the semiconductor layer 40. The drain pull-up region 38 contains impurities with a higher concentration than the first concentration of the semiconductor substrate 32 and is of a first conductivity type. The drain pull-up region 38 is formed at a depth from the upper surface of the semiconductor layer 40 to a portion of the semiconductor substrate 32.

[0058] On the surface side of semiconductor layer 40, at a location included within the third region A3 in planar view, a surface drain electrode 81 connected to the drain pull-up region 38 is formed. The term "surface" is used to distinguish it from the back drain electrode 41, which is the same drain electrode.

[0059] The surface drain electrode 81 includes a portion 82 and a portion 83, wherein portion 82 is connected to the low-concentration impurity layer 33 and / or the drain pull-up region 38 via portion 83.

[0060] The portion 82 of the surface drain electrode 81 is a layer that bonds with the solder during reflow when mounted face down. As a non-limiting example, it can be made of any one or more metallic materials including nickel, titanium, tungsten, and palladium. A plating layer such as gold can be applied to the surface of the portion 82.

[0061] The portion 83 of the surface drain electrode 81 is a layer that connects the portion 82 to the semiconductor layer 40. As a non-limiting example, it may be made of any one or more metallic materials including aluminum, copper, gold, and silver.

[0062] The drain pull-up region 38 is covered by an interlayer insulating layer 34 with an opening, and a portion 83 of a surface drain electrode 81 is provided that is connected to the drain pull-up region 38 through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 83 of the surface drain electrode 81 are covered by a passivation layer 35 with an opening, and a portion 82 is provided that is connected to the portion 83 of the surface drain electrode 81 through the opening of the passivation layer 35.

[0063] Therefore, as Figure 2B As shown, the drain pad 151 refers to the area where the surface drain electrode 81 is partially exposed on the surface of the semiconductor device 1, i.e., the portion of the terminal.

[0064] The number of drain pads 151 is not necessarily limited to Figure 2A The number is shown in the example. Additionally, the shape of the drain pad 151 is not limited to...Figure 2A The elliptical shape illustrated, for example, can also be a rectangular shape, a circular shape.

[0065] In Figure 2A In the example shown, the drain pad 151 is configured so that its center coincides with the center of the third region A3, but even if the center of the drain pad 151 does not coincide with the center of the third region A3, the effect of the present disclosure is not at all hindered.

[0066] Further, in the present disclosure, the center of the shape in plan view is defined as follows. As Figure 2A As with the first source pad 111 and the first gate pad 119 in the first embodiment, the circular shape refers to the center thereof. As with the third region A3, the rectangular shape refers to the intersection of the diagonal lines thereof. As with the drain pad 151, the oblong shape refers to the intersection of the symmetry axis of the line symmetry in the length direction thereof and the symmetry axis of the line symmetry in the width direction thereof.

[0067] The portion of the drain pull-up region 38 that is in contact with the portion 83 of the surface drain electrode 81 is referred to as the drain contact region 39. In plan view, the drain contact region 39 is the overlapping portion between the region of the drain pull-up region 38 that is exposed on the surface side of the semiconductor layer 40 and the opening region of the interlayer insulating layer 34. In Figure 1 In the case like the example shown, the width of the drain pull-up region 38 is greater than the width of the opening of the interlayer insulating layer 34 (in plan view, the area of the drain pull-up region 38 that is exposed on the surface side of the semiconductor layer 40 is greater than the opening area of the interlayer insulating layer 34), so the drain contact region 39 coincides with the opening region of the interlayer insulating layer 34 in plan view.

[0068] Figure 3 is a cross-sectional schematic view of a portion cut from the semiconductor device 1 of the first deformation example 1 in which only the shape of the drain pull-up region 38 is deformed, of the semiconductor device 1 of the embodiment. As Figure 3 As shown, the width of the drain pull-up region 38 can also be smaller than the opening width of the interlayer insulating layer 34, and in such a case, the drain contact region 39 coincides with the region of the drain pull-up region 38 that is exposed on the surface side of the semiconductor layer 40 in plan view.

[0069] In summary, in order to reduce the on-resistance, the area of the drain contact region 39 in plan view can be larger. Typically, in plan view, in the third region A3, the area in which the portion 83 of the surface drain electrode 81 is in contact with the semiconductor layer 40 (the area of the opening region of the interlayer insulating layer 34) and the area in which the drain pull-up region 38 is exposed on the surface side of the semiconductor layer 40 are different in size, and it is also possible to expand them to the same degree.

[0070] In addition, as Figure 2AAs shown, the first region A1 and the second region A2 are arranged with a third region A3 between them. In this embodiment, "the first region A1 and the second region A2 are separated by the third region A3" means that the first region A1 and the third region A3 are adjacent to each other without any other regions between them, and the second region A2 and the third region A3 are adjacent to each other without any other regions between them. Therefore, when the semiconductor layer 40 is viewed in a planar view, the third region A3 is adjacent to both the first region A1 and the second region A2.

[0071] In planar observation, the concepts of "adjacent" and "opposite" mean that the outer perimeters of two regions are aligned at a 90° boundary line. Hereinafter, the length of this 90° boundary line is sometimes referred to as the "opposite length."

[0072] like Figure 2B As shown, the boundary line 90 between the first region A1 and the third region A3 can be understood as an imaginary line along the central position of the interval between the portion 13 of the first source electrode 11 and the portion 83 of the surface drain electrode 81. Furthermore, although it has a finite width, it can also be understood as the interval itself. Even with this interval, it can be identified as a line to the naked eye or at low magnification. The boundary line 90 between the first region A1 and the third region A3... Figure 2A , Figure 2B The example shown is a dashed line from P1 to P4.

[0073] Similarly, the boundary line 90 between the second region A2 and the third region A3 can be understood as an imaginary line along the central position of the interval between the portion 23 of the second source electrode 21 and the portion 83 of the surface drain electrode 81. Furthermore, although it has a finite width, it can also be understood as the interval itself. The boundary line 90 between the second region A2 and the third region A3... Figure 2A , Figure 2B The example shown is a dashed line from P2 to P4.

[0074] In such Figure 2B When the first region A1 and the second region A2 are adjacent as shown, the boundary line 90 between them can be understood as an imaginary line along the central position of the interval between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Furthermore, although it has a finite width, it can also be understood as the interval itself. Figure 2A , Figure 2B In the example shown, the boundary line 90 between the first region A1 and the second region A2 is a dashed line from P4 to P3.

[0075] like Figure 2A , Figure 2BAs shown, the area al of the first region Al in plan view is larger than the area a2 of the second region A2 in plan view (al > a2). In other words, the first region Al and the second region A2 do not bisect the area remaining after the third region A3 is removed from the semiconductor layer 40 in plan view (al ≠ a2). Therefore, the length (opposite length, length from PI to P4) of the boundary line 90 of the first region Al and the third region A3 is longer than the length (opposite length, length from P2 to P4) of the boundary line 90 of the second region A2 and the third region A3.

[0076] In the example of the embodiment shown, the first region Al is configured to have an outer periphery that coincides with at least a portion of each of the four sides of the semiconductor layer 40 in plan view. In contrast, the second region A2 is configured such that its outer periphery coincides with only a portion of each of two of the four sides of the rectangular semiconductor layer 40. Figure 2A Figure 2B In the example of the embodiment shown, the first region Al is configured to have an outer periphery that coincides with at least a portion of each of the four sides of the semiconductor layer 40 in plan view. In contrast, the second region A2 is configured such that its outer periphery coincides with only a portion of each of two of the four sides of the rectangular semiconductor layer 40.

[0077] In the example of the embodiment shown, the second gate pad 129 is disposed closest to the corner formed by the two sides of the outer periphery of the second region A2 that are not adjacent to the first region Al in plan view. The second gate pad 129 is disposed in the second region A2 so as to be farthest from the boundary line 90 of the first region Al. Furthermore, in the embodiment, the phrase "closest to the corner" means that no other pad is disposed between the pad and the corner. Figure 2A Figure 2B In addition, the first gate pad 119 is disposed at a position opposite the second gate pad 129 with the drain pad 151 interposed therebetween in plan view.

[0078]

[0079] Figure 4A Figure 4B are plan and perspective schematic views of a substantially unit structure of the transistor 10 or the transistor 20 repeatedly formed in the X direction and the Y direction of the semiconductor device 1 of the embodiment. In Figure 4A Figure 4B In the drawings, the semiconductor substrate 32 and the metal layer 41, and the passivation layer 35 and the first source electrode 11 or the second source electrode 21, the interlayer insulating layer 34 are not shown for ease of understanding.

[0080] Furthermore, the Y direction refers to a direction parallel to the surface of the semiconductor layer 40 and in which the first gate trench 17 extends. In addition, the X direction refers to a direction parallel to the surface of the semiconductor layer 40 and orthogonal to the Y direction. The Z direction refers to a direction orthogonal to both the X direction and the Y direction and representing the height direction of the semiconductor device.

[0081] As shown in Figure 4A Figure 4B ​​​​​​As shown, the transistor 10 has a first connecting portion 18a that electrically connects the first body region 18 and the first source electrode 11. The first connecting portion 18a is a region of the first body region 18 in which the first source region 14 is not formed, and is the same second conductivity type as the first body region 18. The first source region 14 and the first connecting portion 18a are alternately and periodically arranged along the Y direction. The same applies to the transistor 20.

[0082] In the semiconductor device 1 of the present disclosure, the first conductivity type is set to N type, the second conductivity type is set to P type, the first source region 14, the second source region 24, the drain pull region 38, the semiconductor substrate 32, and the low-concentration impurity layer 33 are N-type semiconductors, and the first body region 18, the first connecting portion 18a, the second body region 28, and the second connecting portion 28a are P-type semiconductors.

[0083] [2. Operation of semiconductor device] Hereinafter, the operation of the semiconductor device 1 will be described with reference to the drawings. Figure 5A Figure 5B The first conduction path and the second conduction path of the semiconductor device 1 and the driving method of the semiconductor device 1 will be described. Figure 5A Figure 5B is a cross-sectional view schematically showing the conduction path of the semiconductor device 1 according to the embodiment.

[0084] In the semiconductor device 1 of the embodiment, it is assumed that a current flows with one of the first source pad 111 of the first region A1 or the second source pad 121 of the second region A2 as an inlet and with the drain pad 151 of the third region A3 as an outlet via the common drain region and the back surface drain electrode 41. That is, in the embodiment, driving in which a current flows in a path from the first source pad 111 to the second source pad 121 and / or a reverse path thereof is not assumed.

[0085] In the semiconductor device 1, a conduction path in which a current flows with the first source pad 111 of the first region A1 as an inlet and with the drain pad 151 of the third region A3 as an outlet is referred to as a first conduction path. A conduction path in which a current flows with the second source pad 121 of the second region A2 as an inlet and with the drain pad 151 of the third region A3 as an outlet is referred to as a second conduction path.

[0086] In the semiconductor device 1 of the embodiment, the first conduction path and the second conduction path are formed. Figure 5A ​​The current flows as follows in the first conduction path. In the semiconductor device 1, a high voltage is applied to the first source electrode 11, a low voltage is applied to the surface drain electrode 81, and a voltage exceeding the threshold is applied to the first gate electrode 19 (the first gate conductor 15) with the first source electrode 11 as a reference (ON control), so that a conduction channel is formed in the vicinity of the first gate insulating film 16 in the first body region 18. If the conduction channel is formed, the current flows in the path of the first source electrode 11 - the first source region 14 - the conduction channel formed in the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the drain pull-up region 38 - the surface drain electrode 81, and the semiconductor device 1 becomes in the ON state.

[0087] When the potential of the first source electrode 11 is sufficiently high with respect to the potential of the surface drain electrode 81, it is not necessary to apply a voltage exceeding the threshold to the first gate electrode 19 (the first gate conductor 15) (ON control). In this case, although the conduction channel is not formed in the vicinity of the first gate insulating film 16 in the first body region 18, the current flows in the path of the first source electrode 11 - the first connection portion 18a - the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the drain pull-up region 38 - the surface drain electrode 81, and the semiconductor device 1 becomes in the ON state.

[0088] The above are all the first conduction paths. In the latter case, a PN junction exists at the contact surface of the first body region 18 and the low-concentration impurity layer 33, so that the conduction resistance becomes relatively high. In the former case, since the conduction channel is passed through, the conduction resistance becomes relatively low.

[0089] In summary, it should be noted that, when the first conduction path is made to be in the ON state, the PN junction at the contact surface of the second body region 28 and the low-concentration impurity layer 33 in the transistor 20 functions as a body diode. Therefore, conduction from the first source pad 111 to the second source pad 121 does not occur. In the case where only the first conduction path is used in the semiconductor device 1, it is preferable that a voltage exceeding the threshold is not applied to the second gate electrode 29 (the second gate conductor 25) of the transistor 20 (OFF control).

[0090] In Figure 5BIn the second conduction path shown, current flows as follows. In semiconductor device 1, a high voltage is applied to the second source electrode 21, a low voltage is applied to the surface drain electrode 81, and a voltage above a threshold (ON control) is applied to the second gate electrode 29 (second gate conductor 25) with reference to the second source electrode 21, thereby forming a conduction channel near the second gate insulating film 26 in the second body region 28. If a conduction channel is formed, current flows along the path of second source electrode 21 - second source region 24 - conduction channel formed in second body region 28 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - drain pull-up region 38 - surface drain electrode 81, and semiconductor device 1 becomes in a conducting state.

[0091] When the potential of the second source electrode 21 is sufficiently high relative to the potential of the surface drain electrode 81, it is not necessary to apply a voltage above the threshold to the second gate electrode 29 (second gate conductor 25) (ON control). In this case, although no conductive channel is formed near the second gate insulating film 26 in the second body region 28, the current flows along the path of second source electrode 21 - second connection portion 28a - second body region 28 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - drain pull-up region 38 - surface drain electrode 81, and the semiconductor device 1 becomes conductive.

[0092] The above are all examples of the second conduction path. In the latter case, a PN junction exists at the contact surface between the second body region 28 and the low-concentration impurity layer 33, thus the on-resistance is relatively higher. In the former case, since it is via a conduction channel, the on-resistance is relatively lower.

[0093] In summary, it should be noted that when the second conduction path is turned on, the PN junction at the contact surface between the first body region 18 and the low-concentration impurity layer 33 in the transistor 10 functions as a body diode. Therefore, conduction does not occur from the second source pad 121 to the first source pad 111. When only the second conduction path is used in the semiconductor device 1, it is preferable not to apply a voltage exceeding a threshold value (OFF control) to the first gate electrode 19 (first gate conductor 15) of the transistor 10.

[0094] In addition, such as Figure 5A and Figure 5B As shown, in the first and second conduction paths, the current flowing horizontally inside the semiconductor device 1 almost entirely passes through the low resistivity metal layer 41, but some of it also flows through the semiconductor substrate 32.

[0095] [3. Examples of Semiconductor Device Use] Figure 6This is a circuit diagram showing a portion of a power supply circuit in which current flows from a detachable first power source 51 and a second power source 52 to a load 6 via the semiconductor device 1 of the embodiment. Here, the potential of the first power source 51 is set to be higher than the potential of the second power source 52, with the potential of the load 6 as a reference.

[0096] The semiconductor device 1 in the embodiment is configured to perform the following function: combine the power supply from a first power supply 51 at a high potential and the power supply from a second power supply 52 at a lower potential, and combine them into a single system for the load 6 downstream at a low potential.

[0097] The maximum value of the current flowing through the power supplied from the first power supply 51 at a high potential is defined as I1[A], and the maximum value of the current flowing through the power supplied from the second power supply 52 at a potential lower than that of the first power supply 51 is defined as I2[A]. I1 and I2 can be understood as the maximum current values ​​specified in the first conduction path and the second conduction path as recorded in the product data sheet of the semiconductor device 1 of the embodiment.

[0098] Based on the potential relationship between the first power supply 51 and the second power supply 52, there exists a relationship of I1 > I2. The side of the first power supply 51, which is energized by a relatively large current I1, is connected to the first source pad 111 of the transistor 10, which has a large area when viewed from the planar perspective in the semiconductor device 1. The side of the second power supply 52, which is energized by a relatively small current I2, is connected to the second source pad 121 of the transistor 20, which has a small area when viewed from the planar perspective in the semiconductor device 1.

[0099] Furthermore, a switching element 7 (e.g., a single-weight vertical MOS transistor) is connected between the semiconductor device 1 and the load 6. Additionally, a switching element 8 (e.g., a single-weight vertical MOS transistor) is connected between the semiconductor device 1 and the second power supply 52. ​​A control IC 4 is connected to the switching elements 7, 8, 10, and 20, respectively, and the control IC 4 independently controls their ON / OFF states.

[0100] First, regarding the state where only the first power supply 51 is connected and the second power supply 52 is not connected ( Figure 6 The following describes the state where the second power supply 52 is not present. In this state, the switching element 7 is turned on by the control IC4, and the transistor 20 is turned off, allowing power to be supplied from the first power supply 51 to the load 6 via the first conduction path within the semiconductor device 1. Furthermore, if the transistor 10 is turned on by the control IC4, the on-resistance in the first conduction path can be reduced.

[0101] The first conduction path is a conduction path inside the semiconductor device 1, and is a conduction path in which the transistor 10 is caused to flow current with the first source pad 111 as an inflow port and the drain pad 151 as an outflow port as explained above. When only the first conduction path is caused to conduct, the transistor 20 is controlled to be in the off state. Since the transistor 20 is controlled to be in the off state, current flowing by power supply from the first power supply 51 can be prevented from flowing to the second power supply 52 side.

[0102] Next, a state in which only the second power supply 52 is connected and the first power supply 51 is not connected (a state in which the first power supply 51 is not present) will be explained. At this time, the switching element 7 is controlled to be in the on state by the control IC 4, and the transistor 10 is controlled to be in the off state, and power supply from the second power supply 52 to the load 6 is performed via the second conduction path inside the semiconductor device 1. Furthermore, if the transistor 20 is controlled to be in the on state by the control IC 4, the on resistance in the second conduction path can be reduced. Figure 6

[0103] The second conduction path is a conduction path inside the semiconductor device 1, and is a conduction path in which the transistor 20 is caused to flow current with the second source pad 121 as an inflow port and the drain pad 151 as an outflow port as explained above. When only the second conduction path is caused to conduct, the transistor 10 is controlled to be in the off state. Since the transistor 10 is controlled to be in the off state, current flowing by power supply from the second power supply 52 can be prevented from flowing to the first power supply 51 side.

[0104] In a state in which both the first power supply 51 and the second power supply 52 are connected (a state in which the first power supply 51 is present), Figure 6 by the control IC 4, first, the switching element 8 is controlled to be in the off state, and a state in which power supply is performed only from the first power supply 51 is constituted. This is because the first power supply 51 is at a high potential, and is superior in terms of power supply. Furthermore, the switching element 7 is controlled to be in the on state, and the transistor 20 is controlled to be in the off state, and power supply from the first power supply 51 to the load 6 via the first conduction path is performed. If the transistor 10 is controlled to be in the on state by the control IC 4, the on resistance in the first conduction path can be reduced.

[0105] [4. Effects of the Semiconductor Device] In Figure 7 a comparative example in which the semiconductor device 1 of the embodiment is not used in the power supply circuit shown in Figure 6 In the comparative example, instead of the semiconductor device 1 of the embodiment, for example, a single structure vertical MOS transistor 10B (hereinafter referred to as transistor 10B) in which an example of the configuration is represented by a plan view in Figure 8A , Figure 8B Figure 9A , Figure 9B ​​A plan view schematically shows an example of the configuration of the single-well longitudinal MOS transistor 20B (hereinafter referred to as transistor 20B).

[0106] In the transistor 10B and the transistor 20B, for the same constituent elements as those of the semiconductor device 1 of the embodiment, the same reference numerals are used with the addition of B to the corresponding reference numerals. However, for the sake of distinction, for the drain pad, the reference numerals are distinguished as the transistor 10B (having a drain pad 151B) and the transistor 20B (having a drain pad 152B).

[0107] In Figure 8B , Figure 9B , the same as in the case shown in the plan view schematic of the semiconductor device 1 of the embodiment Figure 2B , the case after the portion 13B (23B) of the source electrode, the gate electrode 19B (29B), the gate wiring, and the portion 83B of the surface drain electrode are formed on the surface side of the semiconductor layer 40 is shown. In Figure 8B , Figure 9B , for the sake of easy understanding, the pads that should not be seen at this point in time are shown by broken lines.

[0108] The area of the portion 13B of the source electrode of the transistor 10B when viewed in plan is the same as the area of the portion 13 of the first source electrode 11 possessed by the transistor 10 of the semiconductor device 1 of the embodiment when viewed in plan. Therefore, the on-resistance of the path from the first power supply 51 to the load 6 via the transistor 10B in Figure 7 can be understood to be the same as the on-resistance of the first on-path of the semiconductor device 1 of the embodiment in Figure 6 .

[0109] In addition, the area of the portion 23B of the source electrode of the transistor 20B when viewed in plan is the same as the area of the portion 23 of the second source electrode 21 possessed by the transistor 20 of the semiconductor device 1 of the embodiment when viewed in plan. Therefore, the on-resistance of the path from the second power supply 52 to the load 6 via the transistor 20B in Figure 7 can be understood to be the same as the on-resistance of the second on-path of the semiconductor device 1 of the embodiment in Figure 6 .

[0110] In Figure 7 , the power supply circuit shown in Figure 7In the absence of the second power supply 52, transistor 20B is cut off to prevent current flowing from the first power supply 51 to the second power supply 52 side. Regarding transistor 10B, it is turned on by applying a voltage above a threshold to the gate pad 119B, allowing current flowing from the first power supply 51 to flow into the source pad 111B and out through the drain pad 151B. Figure 8A , Figure 8B As shown, the area of ​​transistor 10B when viewed in a planar manner (the area of ​​the source electrode portion 13B) is relatively large because the current flowing through the power supply from the first power source 51 is relatively large.

[0111] exist Figure 7 In the power supply circuit, only the second power supply 52 is connected ( Figure 7 In the absence of the first power supply 51, transistor 10B is cut off to prevent current flowing from the second power supply 52 to the first power supply 51 side. Regarding transistor 20B, it is turned on by applying a voltage above a threshold to its gate pad 129B, allowing current flowing from the second power supply 52 to enter from the source pad 121B and exit from the drain pad 152B. Figure 9A , Figure 9B As shown, the area of ​​transistor 20B when viewed in a planar manner (the area of ​​the source electrode portion 23B) is relatively small because the current flowing through the power supply from the second power supply 52 is relatively small.

[0112] As mentioned above, in Figure 7 In the power supply circuit of the comparative example shown, transistor 10B functions in conjunction with... Figure 6 The transistor 10 in the semiconductor device 1 of the embodiment in the power supply circuit has the same function. Similarly, in Figure 7 In the power supply circuit of the comparative example shown, transistor 20B functions in conjunction with... Figure 6 The transistor 20 in the semiconductor device 1 of the embodiment of the power supply circuit has the same function as the transistor 20.

[0113] However, when equipped Figure 7 In the circuit board of the power supply circuit shown in the comparative example, it is necessary to ensure the area of ​​each transistor 10B and transistor 20B, and a certain margin must be provided between them. In addition, transistors 10B and 20B have drain pads (151B and 152B) respectively when viewed in planar view, so they are structures that require a certain area.

[0114] On the other hand, in carrying Figure 6In the circuit substrate of the power supply circuit shown, by using the semiconductor device 1 of the embodiment, the transistor 10B and the transistor 20B of the comparative example can be combined. Thus, a certain installation margin that is required to be installed between the transistor 10B and the transistor 20B in the circuit substrate of the power supply circuit of the comparative example is not required, and further, the drain pads (151B, 152B) respectively possessed by the transistor 10B and the transistor 20B can be commonized into one, and thus the area required for the circuit substrate can be reduced. In the circuit substrate of the power supply circuit shown, compared with the comparative example, the substrate itself can be reduced, and further, other components can be installed in the remaining part. Figure 6

[0115] Thus, the semiconductor device 1 of the embodiment is a chip size package type semiconductor device 1 that can be mounted face down, characterized by including: a semiconductor layer 40 having a semiconductor substrate 32 on a back surface side, divided into three regions, a first region Al, a second region A2, and a third region A3, which do not overlap and are not dispersed in plan view of the semiconductor device 1; a first vertical MOS transistor 10 formed entirely in the first region Al of the semiconductor layer 40; a second vertical MOS transistor 20 formed entirely in the second region A2 of the semiconductor layer 40; and a metal layer 41 formed in contact with the back surface side of the semiconductor layer 40; the semiconductor substrate 30 is a common drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20, in plan view, a first source pad 111 and a first gate pad 119 of the first vertical MOS transistor 10 are formed at a position included in the first region Al, in plan view, a second source pad 121 and a second gate pad 129 of the second vertical MOS transistor 20 are formed at a position included in the second region A2, in plan view, a drain pad 151 connected to the common drain region is formed at a position included in the third region A3, in plan view, the first region Al and the second region A2 are disposed with the third region A3 interposed therebetween, in plan view, the third region A3 is adjacent to the first region Al and the second region A2, and in plan view, an area of the first region Al is larger than an area of the second region A2.

[0116] ​In the semiconductor device 1 of this embodiment, the first conduction path uses the first source pad 111 of the first region A1 as the inlet and the drain pad 151 of the third region A3 as the outlet. Therefore, if the first region A1 and the third region A3 are adjacent when viewed in a planar view, the first conduction path is shortened, which can reduce the on-resistance, and is therefore preferred. Similarly, the second conduction path uses the second source pad 121 of the second region A2 as the inlet and the drain pad 151 of the third region A3 as the outlet. Therefore, if the second region A2 and the third region A3 are adjacent when viewed in a planar view, the second conduction path is shortened, which can reduce the on-resistance, and is therefore preferred.

[0117] Therefore, it is preferable that, when viewed in a plane, the first region A1 and the second region A2 are arranged with the third region A3 in between, and the third region A3 is adjacent to the first region A1 and the second region A2.

[0118] In the semiconductor device 1 of the embodiment, it is important to reduce the on-resistance of the first conduction path. Therefore, as Figure 2A or Figure 2B As shown, it is preferably configured such that, when viewed in a plane, the opposing lengths of the first region A1 and the third region A3 are longer than the opposing lengths of the second region A2 and the third region A3. If the semiconductor device 1 is configured as described above when viewed in a plane, the portion with the highest current density in the first conduction path can be expanded (by increasing the opposing length), thus reducing the on-resistance.

[0119] For example in Figure 10 The same effect can be obtained in the modified example 2 shown above. Figure 10 This is a plan view showing a change in the configuration ratio of the first region A1 and the second region A2 in the semiconductor device 1 of the embodiment.

[0120] In addition, such as Figure 2A , Figure 2B As shown, it can also be configured such that, when viewed in a plane, the semiconductor layer 40 is rectangular, and the first region A1 has at least a portion of its outer periphery that coincides with the four sides of the semiconductor layer 40. By configuring the semiconductor device 1 as described above when viewed in a plane, not only can the area of ​​the first region A1 be increased, but also, since the first conduction path is provided in all directions, it is possible to prevent the formation of localized high-temperature areas due to current concentration.

[0121] For example in Figure 11 The same effect can be obtained in the modified example 3 shown above. Figure 11 This is a plan view showing a change in the configuration ratio of the first region A1 and the second region A2 in the semiconductor device 1 of the embodiment.

[0122] In addition, such as Figure 2BAs shown, the portion where the second gate electrode 29 is provided cannot contribute to conduction. Therefore, it is preferable that the second gate electrode 29 be provided in such a manner that it is farthest from an obstacle that can become a second conduction path in the plan view. Thus, it is preferable that the second gate electrode 29 be provided as far as possible from the boundary line 90 between the second region A2 and the third region A3, where the current density is highest in the second conduction path.

[0123] Therefore, in the plan view, the second gate electrode 29, i.e., the second gate pad 129 is preferably provided closest to the corner portion formed by two sides of the outer periphery of the second region A2 that are not adjacent to the third region A3. In Figure 2B In the example shown, the second gate pad 129 is provided closest to the upper right corner portion in the plan view.

[0124] The above-described effects can also be obtained in Modification Example 4 shown in Figure 12A 、 Figure 12B . Figure 12A 、 Figure 12B is a plan view of Modification Example 2 of the semiconductor device 1 of the embodiment, in which the positions of the first gate electrode 19 and the first gate pad 119, and the second gate electrode 29 and the second gate pad 129 are changed. In Figure 12B , the state after the portion 13 of the first source electrode, the portion 23 of the second source electrode, the first gate electrode 19, the second gate electrode 29, the first gate wire, the second gate wire, and the portion 83 of the surface drain electrode are formed on the surface side of the semiconductor layer is shown. In Figure 12B , for easy understanding, the pads that should not be seen at this point in time are indicated by broken lines.

[0125] If Modification Example 4 shown in Figure 12B is compared with the example shown in Figure 2B , in Modification Example 4, in the second region A2, the second gate pad 129 is provided closest to the boundary line 90 (broken line from P3 to P4) between the first region A1 and the second region A2 in the plan view. Therefore, the region along the boundary line 90 (broken line from P2 to P4) between the second region A2 and the third region A3, where the current density is highest in the second conduction path, can be widely and flexibly utilized.

[0126] Further, regarding Modification 4, it can also be said that the second gate pad 129 is positioned, in plan view, in the corner portion closest to the outer periphery of the second region A2, in the corner portion farthest from the drain pad 151. Thus, the region along the boundary line 90 (dotted line from P2 to P4) between the second region A2 and the third region A3 can be flexibly utilized widely. Similarly, the first gate pad 119 is positioned, in plan view, in the corner portion closest to the outer periphery of the first region Al, in the corner portion farthest from the drain pad 151. Thus, the region along the boundary line 90 (dotted line from PI to P4) between the first region Al and the third region A3 can be flexibly utilized widely.

[0127] Returning to the semiconductor device 1 using the embodiment Figure 6 In the transistor in the on state, generally, the total gate width increases when the area of the transistor in plan view is large, and thus the on resistance becomes low. That is, the area of the transistor in plan view and the on resistance are approximately in inverse proportion.

[0128] In the semiconductor device 1, the area al of the transistor 10 forming the first conduction path in plan view is larger than the area a2 of the transistor 20 forming the second conduction path in plan view. Thus, the on resistance of the first conduction path is low, and the path suitable for flowing a relatively large current is formed.

[0129] The on resistance Rl [Ω] of the first conduction path can be determined by considering the maximum value Ii [A] of the current flowing by the supply from the first power supply 51. Similarly, the on resistance R2 [Ω] of the second conduction path can be determined by considering the maximum value I2 [A] of the current flowing by the supply from the second power supply 52. Thus, in the semiconductor device 1 of the embodiment, it is preferable to determine the areas of the transistor 10 and the transistor 20 so as to realize the on resistances suitable for the first conduction path and the second conduction path, respectively.

[0130] However, if the area a2 of the transistor 20 in plan view, which is calculated as described above, is too small, the ESD (Electro Static Discharge) resistance in the transistor 20 decreases, and sometimes the ESD guarantee value cannot be maintained in the semiconductor device 1 as a whole. If the area a2 of the transistor 20 in plan view is increased in order to be able to maintain the ESD guarantee value, the on resistance of the second conduction path excessively decreases, and it is difficult to limit the current from the second power supply 52 to a desired size.

[0131] Therefore, the inventors found that, in the semiconductor device 1, by appropriately designing the size (area) and position of the drain contact region 39 in the third region A3 in plan view, the on-resistance in the second conduction path is controlled separately from the area a2 in plan view of the transistor 20.

[0132] Hereinafter, in the semiconductor device 1 of the embodiment, the description will be made assuming that the area a2 in plan view of the transistor 20 is increased by an amount required to be able to maintain the ESD guarantee value. That is, in the semiconductor device 1 of the embodiment, it can be considered that the on-resistance of the second conduction path is excessively reduced.

[0133] Figure 13 is a plan view of the semiconductor device 1 shown in Figure 2B .

[0134] As shown in Figure 1 and Figure 3 , the drain contact region 39 is a region where the drain pull region 38 is connected to the portion 83 of the surface drain electrode 81. Therefore, in plan view, the drain contact region 39 is a portion included in the third region A3.

[0135] In the example shown in Figure 13 , the third region A3 and the drain contact region 39 are each rectangular in plan view. In plan view, the direction along the short side of the third region A3 (the X direction in Figure 13 ) is set as the first direction, and the direction along the long side of the third region A3 (the Y direction in Figure 13 ) is set as the second direction. The first direction and the second direction are orthogonal to each other.

[0136] In plan view, the length of the side in the first direction of the third region A3 is set as L1 [μm], and the length of the side in the second direction is set as L2 [μm]. Further, in plan view, the length of the side in the first direction of the drain contact region 39 is set as l1 [μm], and the length of the side in the second direction is set as l2 [μm].

[0137] The inventors set the condition of l1≤L1 / 4 and l2≈L2 for the area of the drain contact region 39 in plan view for the purpose of avoiding excessive reduction of the on-resistance in the second conduction path.

[0138] As for l2≈L2, to be more precise, as shown in Figure 13As shown, l2 is the size of the setting margin at both ends in the second direction, which is smaller than L2. The condition l1≤L1 / 4 is to reduce the area of ​​the drain contact region 39 to at least 1 / 4 of the area of ​​the third region A3, thereby allowing the position of the drain contact region 39 in planar observation to be adjusted by the distance from the second region A2.

[0139] Based on these considerations, the study was conducted in Figure 6 The circuit diagram shown uses the size and shape of the drain contact region 39 when viewed in planar view, as shown in the figure. Figure 13 The case of semiconductor device 1 set up as shown. Figure 14 The graph shown illustrates the results of calculating the on-resistance R1 of the first conduction path when transistor 10 is turned on and transistor 20 is turned off, and the on-resistance R2 of the second conduction path when transistor 20 is turned on and transistor 10 is turned off. The on-resistance R1 of the first conduction path is represented by a circle and plotted on the left vertical axis. The on-resistance R2 of the second conduction path is represented by a diamond and plotted on the right vertical axis.

[0140] Figure 14 The horizontal axis represents the position along the first direction within the third region A3 when viewed from a plane. The reference point for this position is... Figure 13 The center is set at the left end of the third region A3, that is, on the boundary line 90 between the first region A1 and the third region A3. In addition, the horizontal axis is drawn with the center of the drain contact region 39 as the reference point.

[0141] Figure 14 The arrows shown at the top, from left to right in the first direction, indicate the reference position, the position at distance L1 / 4 from the reference, the position at distance L1 / 2 from the reference, the position at distance 3×L1 / 4 from the reference, and the position at distance L1 from the reference, which is the position on the boundary line 90 between the third region A3 and the second region A2. When viewed in a plane, the third region A3 is divided into four equal areas at the above-mentioned positions, which are called the fourth region, the fifth region, the sixth region, and the seventh region from left to right in the first direction.

[0142] In addition, Figure 14 In the calculation of the results plotted by the curve, it is assumed that the semiconductor device 1 is a square with one side of 1.5 mm when viewed in a plane. The division of the first region A1, the second region A2, and the third region A3, as well as the shape and arrangement of each pad and electrode, are as follows: Figure 2A , Figure 2B As shown. The dimensions of the third region A3 when viewed from a plane are L1 = 450 [μm] and L2 = 1000 [μm]. Additionally, l1 = 3 [μm] and l2 = 980 [μm].

[0143] In addition,Figure 14 In the embodiment, the data is plotted at a certain distance from the left end and the right end on the horizontal axis because, when viewed in plan, a margin is considered for the portion 83 of the surface drain electrode 81 inside the third region A3.

[0144] According to Figure 14 It is known that if the drain contact region 39 is disposed near the center of the third region A3 when viewed in plan, both R1 and R2 are extremely small. Here, near the center means the fifth region or the sixth region. The drain contact region 39 is located in the fourth region, for example, means that the center of the drain contact region 39 is located in the fourth region when viewed in plan. It does not mean that the entire region of the drain contact region 39 is necessarily included in the fourth region.

[0145] Further, from Figure 14 It is known that in the case where the drain contact region 39 is away from the second region A2 (the position becomes the fourth region side) when viewed in plan, there is a tendency that R2 increases. Regarding Figure 14 It is seen in the tendency that the smaller the area of the drain contact region 39 is, the more significant the tendency is, and when the area of the drain contact region 39 increases to more than 1 / 4 of the area of the third region A3, the tendency is difficult to see.

[0146] Therefore, in the semiconductor device 1 of the embodiment, it is preferable that the semiconductor substrate 32 is of a first conductivity type including impurities of a first concentration, the semiconductor layer 40 has a low-concentration impurity layer 33 of the first conductivity type formed on the semiconductor substrate 32 in contact therewith, including impurities of a second concentration lower than the first concentration, a drain pull-up region 38 of the first conductivity type is formed in the third region A3 of the semiconductor layer 40 when viewed in plan, the drain pull-up region 38 of the first conductivity type includes impurities of a concentration higher than the first concentration and is connected to the common drain region (semiconductor substrate 32), a portion 83 of a surface drain electrode 81 which is in contact with the surface of the semiconductor layer 40 and is connected to the drain pull-up region 38 is formed at a position included in the third region A3 when viewed in plan, and the area of a drain contact region 39 of the portion 83 of the surface drain electrode 81 connected to the drain pull-up region 38 is 1 / 4 or less of the area of the third region A3 when viewed in plan.

[0147] In addition, if the shape of the drain contact region 39 when viewed in plan is a substantially rectangular shape having a long side direction in the second direction, substantially the same effect can be obtained.

[0148] Therefore, it is preferable that, in plan view, the third region A3 is a rectangle, the maximum width l1 of the drain contact region 39 in a first direction parallel to the short side L1 of the third region A3 is smaller than the maximum width l2 of the drain contact region 39 in a second direction orthogonal to the first direction and parallel to the long side L2 of the third region A3, and the maximum width l1 of the drain contact region 39 in the first direction is 1 / 4 or less of the length of the short side L1 of the third region, in plan view.

[0149] Further, according to Figure 14 In the case where the drain contact region 39 is located in the fifth region, the conduction resistance R1 of the first conduction path is substantially fixed and extremely small. On the other hand, the more the drain contact region 39 is disposed toward the side close to the fourth region, the greater the conduction resistance R2 of the second conduction path becomes. Therefore, in the case where the drain contact region 39 is provided in the fifth region, it is possible to increase only R2 while maintaining the state where R1 is reduced.

[0150] Therefore, it can be that, in plan view, the third region is divided into four fourth regions, fifth regions, sixth regions, and seventh regions, each having an equal area, in the first direction, the fourth regions, the fifth regions, the sixth regions, and the seventh regions are arranged in order along the first direction from the boundary line 90 between the first region Al and the third region A3 to the boundary line 90 between the second region A2 and the third region A3, in plan view, the center of the drain contact region 39 is provided in the fifth region.

[0151] More preferably, the drain contact region 39 is preferably provided in the vicinity of the boundary with the fourth region in the fifth region. For example, the drain contact region 39 can be provided so as to include the boundary between the fourth region and the fifth region. By thus providing the drain contact region 39, it is possible to avoid excessive reduction of R2.

[0152] The drain contact region 39 is located in the fourth region, and further, the more the drain contact region 39 is disposed toward the side close to the boundary line 90 between the first region Al and the third region A3 (reference position in the first direction), the greater both R1 and R2 become. However, the proportion of increase in R2 is greater. This is because the drain contact region 39 is farther from the boundary line 90 between the second region A2 and the third region A3.

[0153] Therefore, it can be that, in plan view, the third region is divided into four fourth regions, fifth regions, sixth regions, and seventh regions, each having an equal area, in the first direction, the fourth regions, the fifth regions, the sixth regions, and the seventh regions are arranged in order along the first direction from the boundary line 90 between the first region Al and the third region A3 to the boundary line 90 between the second region A2 and the third region A3, in plan view, the center of the drain contact region 39 is provided in the fourth region.

[0154] More preferably, the greater the configuration is closer to one side of the boundary line 90 between the first region Al and the third region A3, the greater the difference between Rl and R2 can be expanded. By thus providing the drain contact region 39, it is possible to avoid excessive reduction of R2 corresponding to expansion of the area in plan view of the second region A2.

[0155] Further, in the case where the drain contact region 39 is provided in the sixth region, both Rl and R2 are maintained at substantially small values, and thus it is preferable in the case where it is desired that both Rl and R2 achieve low values.

[0156] Therefore, it can also be that the third region is divided into a fourth region, a fifth region, a sixth region, and a seventh region each having an equal area in the first direction in plan view, the fourth region, the fifth region, the sixth region, and the seventh region are arranged in order along the first direction from the boundary line 90 between the first region Al and the third region A3 to the boundary line 90 between the second region A2 and the third region A3 in plan view, and the center of the drain contact region 39 is provided in the sixth region in plan view.

[0157] As described above, in the semiconductor device 1 of the embodiment, after the areas in plan view of the first region Al and the second region A2 are determined, it is possible to adjust the on-resistance Rl of the first conduction path and the on-resistance R2 of the second conduction path in accordance with the size (area) of the drain contact region 39 and the position where it is provided. In particular, in the transistor 20 of a small area, even if the second region A2 is expanded in order to achieve the required ESD resistance, it is possible to achieve the on-resistance R2 of the second conduction path at a desired high value. Therefore, it is possible to make the current flowing through the first conduction path and the current flowing through the second conduction path be of a desired size.

[0158] The semiconductor device of one embodiment of the present disclosure has been described above on the basis of the embodiment, Modification 1 to Modification 4, and the comparative example, but the present disclosure is not limited to the embodiment. As long as the spirit of the present disclosure is not deviated from, a mode obtained by applying various modifications that can be thought by those skilled in the art to these embodiments, a mode constructed by combining components in different embodiments and modification examples can also be included in the range of one or plural modes of the present disclosure.

[0159] Industrial Applicability The semiconductor device of one embodiment of the present disclosure can be widely utilized as a device that controls the on state of a current path.

[0160] Glossary 1, 1A Semiconductor device 4 Control IC 6 Load 7, 8 Switching element 10, 10A, 10B transistor (first vertical MOS transistor) 11 first source electrode 12, 13, 22, 23 portion 14 first source region 15 first gate conductor 16 first gate insulating film 17 first gate trench 18 first body region 18a first connecting portion 19 first gate electrode 20, 20B transistor (second vertical MOS transistor) 21 second source electrode 24 second source region 25 second gate conductor 26 second gate insulating film 27 second gate trench 28 second body region 28a second connecting portion 29 second gate electrode 32 semiconductor substrate 33 low-concentration impurity layer 34 interlayer insulating layer 35 passivation layer 38 drain pull-up region 40 semiconductor layer 41 metal layer (back surface drain electrode) 51 first power supply 52 second power supply 81 surface drain electrode 82, 83 portion 90 boundary line 111 first source pad 111B, 121B source pad 119 first gate pad 119B, 129B gate pad 121 second source pad 129 second gate pad 151, 151B, 152B drain pad A1 first region A2 second region A3 third region

Claims

1. A chip-size packaged semiconductor device capable of being mounted face-down, characterized in that, have: The semiconductor layer has a semiconductor substrate on the back side and is divided into three regions, namely the first region, the second region, and the third region, which are arranged in a non-overlapping and non-dispersed manner in planar view of the semiconductor device. The first vertical MOS transistor is integrally formed in the first region of the semiconductor layer; The second vertical MOS transistor is integrally formed in the second region of the semiconductor layer; as well as A metal layer is formed in contact with the back side of the semiconductor layer. The semiconductor substrate is the common drain region of the first vertical MOS transistor and the second vertical MOS transistor. When viewed in the planar view, the first source pad and the first gate pad of the first vertical MOS transistor are formed in a position contained within the first region. When viewed in the planar view, the second source pad and the second gate pad of the second vertical MOS transistor are formed in a position contained within the second region. When viewed in the planar view, the drain pad connected to the common drain region is formed in a position contained within the third region. When viewed in the plane, the first region and the second region are positioned with the third region between them. When viewed from the plane, the third region is adjacent to both the first and second regions. When viewed from the plane, the area of ​​the first region is larger than the area of ​​the second region.

2. The semiconductor device according to claim 1, characterized in that, When viewed in the plane, the opposition length between the first region and the third region is greater than the opposition length between the second region and the third region.

3. The semiconductor device according to claim 2, characterized in that, When viewed from the plane, the semiconductor layer is rectangular. When viewed in the plane, the first region is configured to have an outer periphery that is at least partially aligned with the four sides of the semiconductor layer.

4. The semiconductor device according to claim 2, characterized in that, The second gate pad is positioned as close as possible to the corner formed by the two sides of the outer periphery of the second region that are not adjacent to the third region when viewed in the plane.

5. The semiconductor device according to claim 2, characterized in that, The second gate pad is positioned closest to the corner furthest from the drain pad in the corner formed by the outer periphery of the second region when viewed in the plane.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor substrate is of a first conductivity type containing a first concentration of impurities. The semiconductor layer has a low-concentration impurity layer of the first conductivity type, which is formed on the semiconductor substrate in contact with the ground, and the low-concentration impurity layer contains impurities of a second concentration lower than the first concentration. When viewed in the planar view, a drain pull-up region of the first conductivity type is formed in the third region of the semiconductor layer, which is connected to the common drain region. This drain pull-up region contains a higher concentration of impurities than the first concentration. When viewed in the planar view, a surface drain electrode is formed at a location included in the third region, which is in surface contact with the semiconductor layer and connected to the drain pull-up region. When viewed in the plane, the area of ​​the drain contact area where the surface drain electrode connects to the drain pull-up region is less than 1 / 4 of the area of ​​the third region.

7. The semiconductor device according to claim 6, characterized in that, When viewed in the plane, the third region is rectangular. The maximum width of the drain contact region in the first direction, which is parallel to the short side of the third region, is less than the maximum width of the drain contact region in the second direction, which is orthogonal to the first direction and parallel to the long side of the third region, when viewed in the plane. When viewed in the plane, the maximum width of the drain contact region in the first direction is less than 1 / 4 of the length of the short side of the third region.

8. The semiconductor device according to claim 7, characterized in that, When viewed from the plane, the third region is divided into four equal regions—a fourth region, a fifth region, a sixth region, and a seventh region—with equal areas in the first direction. When viewed from the plane, the fourth region, the fifth region, the sixth region, and the seventh region are arranged sequentially along the first direction, starting from the boundary line between the first region and the third region and ending at the boundary line between the second region and the third region. When viewed in the plane, the center of the drain contact area is located in the fifth region.

9. The semiconductor device according to claim 7, characterized in that, When viewed from the plane, the third region is divided into four equal regions—a fourth region, a fifth region, a sixth region, and a seventh region—with equal areas in the first direction. When viewed from the plane, the fourth region, the fifth region, the sixth region, and the seventh region are arranged sequentially along the first direction, starting from the boundary line between the first region and the third region and ending at the boundary line between the second region and the third region. When viewed in the plane, the center of the drain contact area is located in the fourth region.

10. The semiconductor device according to claim 7, characterized in that, When viewed from the plane, the third region is divided into four equal regions—a fourth region, a fifth region, a sixth region, and a seventh region—with equal areas in the first direction. When viewed from the plane, the fourth region, the fifth region, the sixth region, and the seventh region are arranged sequentially along the first direction, starting from the boundary line between the first region and the third region and ending at the boundary line between the second region and the third region. When viewed in the plane, the center of the drain contact area is located in the sixth region.

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