Semiconductor device

Abstract

A semiconductor device is provided with: one and the other wiring groups arranged at intervals in a first direction X, the one and the other wiring groups each including a plurality of first lower wirings and a plurality of second lower wirings arranged in a stripe shape extending in the first direction X; a first pad wiring disposed on one and the other wiring groups and electrically connected to at least one of the first lower wirings of each of the wiring groups; and a second pad wiring that is disposed on the one and the other wiring groups at a distance from the first pad wiring in a second direction Y intersecting the first direction X, and that is electrically connected to at least one of the second lower wiring of each of the wiring groups.

Description

TECHNICAL FIELD

[0001] This application claims priority to Patent Application No. 2023-056610 filed in Japan Patent Office on March 30, 2023, Patent Application No. 2023-056611 filed in Japan Patent Office on March 30, 2023, Patent Application No. 2023-056612 filed in Japan Patent Office on March 30, 2023, and Patent Application No. 2023-056613 filed in Japan Patent Office on March 30, 2023, the contents of which are incorporated herein by reference in their entirety. The present invention relates to a semiconductor device. BACKGROUND

[0002] Patent Document 1 (US 2008 / 0093638 Al) discloses a semiconductor device including a source pad electrode, a drain pad electrode, a plurality of source electrodes, and a plurality of drain electrodes which are two-dimensionally arranged on the same insulating film. The plurality of source electrodes are drawn out from the source pad electrode in a comb shape on the insulating film, and penetrate the insulating film to be electrically connected with a source region.

[0003] The plurality of drain electrodes are drawn out from the drain pad electrode in a comb shape engaged with the plurality of source electrodes on the insulating film, and penetrate the insulating film to be electrically connected with a drain region. The semiconductor device has a relatively long wiring distance and a relatively high wiring resistance between the source pad electrode and the drain pad electrode.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT DOCUMENTS

[0006] Patent Document 1: US Patent Application Publication No. 2008 / 0093638 Al SUMMARY

[0007] The present invention provides a semiconductor device having a new wiring layout.

[0008] The present invention provides a semiconductor device including: a wiring group including a plurality of first lower wirings and a plurality of second lower wirings arranged in a stripe shape extending in a first direction X; a first pad wiring disposed on at least one of the first lower wirings; a second pad wiring disposed on at least one of the second lower wirings at a spacing apart from the first pad wiring in a second direction Y crossing the first direction X; at least one first lead-out wiring drawn out from the first pad wiring in the second direction Y and electrically connected with at least one of the first lower wirings in a region between the first pad wiring and the second pad wiring; and at least one second lead-out wiring drawn out from the second pad wiring in the second direction Y and electrically connected with at least one of the second lower wirings in the region between the first pad wiring and the second pad wiring.

[0009] A semiconductor device includes: one and the other wiring groups arranged at intervals in a first direction X, the one and the other wiring groups each including a plurality of first lower wiring lines and a plurality of second lower wiring lines arranged in a stripe shape extending in the first direction X; a first pad wiring line arranged above the one and the other wiring groups and electrically connected to at least one of the first lower wiring lines of each of the wiring groups; and a second pad wiring line arranged above the one and the other wiring groups at intervals with the first pad wiring line in a second direction Y intersecting the first direction X, and electrically connected to at least one of the second lower wiring lines of each of the wiring groups.

[0010] A semiconductor device includes: one and the other wiring groups arranged at intervals in a first direction X, the one and the other wiring groups each including a plurality of first lower wiring lines and a plurality of second lower wiring lines arranged in a stripe shape extending in the first direction X; a first pad wiring line arranged above the one and the other wiring groups and electrically connected to at least one of the first lower wiring lines of each of the wiring groups; and a second pad wiring line arranged above the one and the other wiring groups at intervals with the first pad wiring line in a second direction Y intersecting the first direction X, and electrically connected to at least one of the second lower wiring lines of each of the wiring groups.

[0011] A semiconductor device includes: one and the other wiring groups arranged at intervals in a first direction X, the one and the other wiring groups each including a plurality of first lower wiring lines and a plurality of second lower wiring lines arranged in a stripe shape extending in the first direction X; a first pad wiring line arranged above the one and the other wiring groups and electrically connected to at least one of the first lower wiring lines of each of the wiring groups; and a second pad wiring line arranged above the one and the other wiring groups at intervals with the first pad wiring line in a second direction Y intersecting the first direction X, and electrically connected to at least one of the second lower wiring lines of each of the wiring groups.

[0012] A semiconductor device includes: one and the other wiring groups arranged at intervals in a first direction X, the one and the other wiring groups each including a plurality of first lower wiring lines and a plurality of second lower wiring lines arranged in a stripe shape extending in the first direction X; a first pad wiring line arranged above the one and the other wiring groups and electrically connected to at least one of the first lower wiring lines of each of the wiring groups; and a second pad wiring line arranged above the one and the other wiring groups at intervals with the first pad wiring line in a second direction Y intersecting the first direction X, and electrically connected to at least one of the second lower wiring lines of each of the wiring groups.

[0013] The present application provides a semiconductor device including: a wiring group including a plurality of first lower wirings and a plurality of second lower wirings arranged in a stripe shape extending in a first direction X; a first pad wiring disposed over at least one of the first lower wirings; a second pad wiring disposed over at least one of the second lower wirings at a spacing apart from the first pad wiring in a second direction Y intersecting the first direction X; an inter-pad region partitioned between the first pad wiring and the second pad wiring; a first side wiring leading from the first pad wiring to a region opposite the inter-pad region on one side in the first direction X and electrically connected to at least one of the first lower wirings passing through the inter-pad region; and a second side wiring leading from the second pad wiring to a region opposite the inter-pad region on one side in the first direction X and electrically connected to at least one of the second lower wirings passing through the inter-pad region.

[0014] The present application provides a semiconductor device including: a chip having a first main face of one side and a second main face of the other side; a base layer of a first conductivity type formed in the chip on the second main face side; a drift layer of a second conductivity type formed in the chip on the first main face side; a plurality of gate structures of a trench electrode type formed on the first main face in a manner located within the drift layer; a plurality of drain-source regions of the second conductivity type formed in regions between the plurality of gate structures, respectively, in a surface layer portion of the drift layer; and a plurality of impurity regions of the first conductivity type formed in regions along lower end portions of the plurality of gate structures, respectively.

[0015] The above and other objects, features and effects are apparent from the detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a plan view showing a semiconductor device of a first mode.

[0017] Figure 2 is a plan view showing a semiconductor device of a first mode. Figure 1 is a sectional view along the line II-II shown in

[0018] Figure 3 is a plan view showing a layout example of a first main face.

[0019] Figure 4 is an enlarged plan view showing a main portion of a first main face.

[0020] Figure 5 is an enlarged plan view showing a main portion of a first main face.

[0021] Figure 6 is an enlarged plan view showing a main portion of a first main face.

[0022] Figure 7 is a sectional view along the line VII-VII shown in Fig. 7. Figure 5

[0023] Figure 8 is a sectional view along the line VIII-VIII shown in Fig. 8. Figure 5

[0024] Figure 9 is a sectional view along the line IX-IX shown in Fig. 9. Figure 5

[0025] Figure 10 is a sectional view along the line X-X shown in Fig. 10. Figure 5

[0026] Figure 11 is a sectional view along the line XI-XI shown in Fig. 11. Figure 6

[0027] Figure 12 is a sectional view along the line XII-XII shown in Fig. 12. Figure 6

[0028] Figure 13 is a sectional view along the line XIII-XIII shown in Fig. 13. Figure 6

[0029] Figure 14 is a plan view showing a layout example of the first layer wiring.

[0030] Figure 15 is a plan view showing a layout example of the second layer wiring.

[0031] Figure 16A is an enlarged plan view showing the first wiring unit of the first example.

[0032] Figure 16B is an enlarged plan view showing the first wiring unit of the second example.

[0033] Figure 16C is an enlarged plan view showing the first wiring unit of the third example.

[0034] Figure 16D is an enlarged plan view showing the first wiring unit of the fourth example.

[0035] Figure 16E is an enlarged plan view showing the first wiring unit of the fifth example.

[0036] Figure 16F is an enlarged plan view showing the first wiring unit of the sixth example.

[0037] Figure 16G ​​​​​​​This is an enlarged top view of the first wiring unit in the seventh example.

[0038] Figure 16H This is an enlarged top view of the first wiring unit in the eighth example.

[0039] Figure 16I This is an enlarged top view of the first wiring unit in the ninth example.

[0040] Figure 16J This is an enlarged top view of the first wiring unit in the tenth example.

[0041] Figure 17A This is an enlarged top view of the second wiring unit in the first example.

[0042] Figure 17B This is an enlarged top view of the second wiring unit in the second example.

[0043] Figure 17C This is an enlarged top view of the second wiring unit in the third example.

[0044] Figure 18 This is an enlarged top view showing an example of the third wiring unit.

[0045] Figure 19 This is an enlarged top view showing an example of the fourth wiring unit.

[0046] Figure 20 This is an enlarged top view of the first wiring unit of the semiconductor device of the second type.

[0047] Figure 21 It means Figure 20 An enlarged top view of the main part of the first wiring unit shown.

[0048] Figure 22 This is a top view showing a first layout example of the second layer wiring of a third-party semiconductor device.

[0049] Figure 23 It means Figure 22 A top view of the second layout example of the second layer wiring shown.

[0050] Figure 24 It means Figure 23 An enlarged top view of the main part of the second layer wiring shown.

[0051] Figure 25 It means Figure 23 An enlarged top view of the main part of the second layer wiring shown.

[0052] Figure 26 It means Figure 23 An enlarged top view of the main part of the second layer wiring shown.

[0053] Figure 27 It means Figure 23 An enlarged top view of the main part of the second layer wiring shown.

[0054] Figure 28 This is a top view showing a first variant of a semiconductor device of type one to three.

[0055] Figure 29 This is an enlarged plan view showing the main part of the second layer wiring.

[0056] Figure 30 This is a top view showing a second variation of the semiconductor device of the first to third types.

[0057] Figure 31 This is a top view representing a fourth type of semiconductor device.

[0058] Figure 32 It is along Figure 31 The cross-sectional view of line XXXII-XXXII is shown.

[0059] Figure 33 This is a plan view showing an example layout of the first main surface.

[0060] Figure 34 It is an enlarged plan view showing a major part of the first primary surface.

[0061] Figure 35 It is an enlarged plan view showing a major part of the first primary surface.

[0062] Figure 36 It is along Figure 35 The cross-sectional view of line XXXVI-XXXVI is shown.

[0063] Figure 37 It is along Figure 35 The cross-sectional view of line XXXVII-XXXVII is shown.

[0064] Figure 38 It is along Figure 35 The cross-sectional view of the XXXVIII-XXXVIII line is shown.

[0065] Figure 39 It is along Figure 35 The cross-sectional view of the XXXIX-XXXIX line is shown.

[0066] Figure 40 This is a floor plan showing an example of the layout of the first layer of wiring.

[0067] Figure 41 This is a floor plan showing an example of the layout for the second-layer wiring.

[0068] Figure 42A is an enlarged plan view of the first wiring unit of the first example.

[0069] Figure 42B is an enlarged plan view of the first wiring unit of the second example.

[0070] Figure 42C is an enlarged plan view of the first wiring unit of the third example.

[0071] Figure 42D is an enlarged plan view of the first wiring unit of the fourth example.

[0072] Figure 42E is an enlarged plan view of the first wiring unit of the fifth example.

[0073] Figure 42F is an enlarged plan view of the first wiring unit of the sixth example.

[0074] Figure 42G is an enlarged plan view of the first wiring unit of the seventh example.

[0075] Figure 42H is an enlarged plan view of the first wiring unit of the eighth example.

[0076] Figure 42I is an enlarged plan view of the first wiring unit of the ninth example.

[0077] Figure 42J is an enlarged plan view of the first wiring unit of the tenth example.

[0078] Figure 43A is an enlarged plan view of the second wiring unit of the first example.

[0079] Figure 43B is an enlarged plan view of the second wiring unit of the second example.

[0080] Figure 43C is an enlarged plan view of the second wiring unit of the third example.

[0081] Figure 44 is an enlarged plan view of the third wiring unit of the example.

[0082] Figure 45 is an enlarged plan view of the fourth wiring unit of the example.

[0083] Figure 46 is a plan view of a modification example of the semiconductor device of the fourth mode. DETAILED DESCRIPTION

[0084] [DETAILED DESCRIPTION]

[0085] Hereinafter, a specific mode will be described in detail with reference to the drawings. The drawings are schematic and not strictly to scale, and the relative positional relationship, scale, ratio, angle, and the like are not necessarily consistent. Corresponding configurations are denoted by the same reference numerals among the drawings, and repeated description is omitted or simplified. As for the configurations whose description is omitted or simplified, the description made before the omission or simplification can be applied.

[0086] In the case where the phrase "substantially" is used in the present specification, the phrase includes a numerical error (a form error) in a range of ±10% from a numerical value (a form) of a comparison target in addition to a numerical value (a form) equal to the numerical value (the form) of the comparison target. In the following description, the phrases "first", "second", "third", and the like are used, but they are signs attached to the names of the respective configurations for the purpose of clarifying the order of description and do not denote the main purpose of limiting the names of the respective configurations.

[0087] In the following description, "p-type" or "n-type" is used to indicate the conductivity type of a semiconductor (an impurity), but "p-type" can be referred to as "first conductivity type" and "n-type" can be referred to as "second conductivity type". Of course, "n-type" can be referred to as "first conductivity type" and "p-type" can be referred to as "second conductivity type". "P-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0088] Figure 1 is a plan view of the semiconductor device 1A of the first mode. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1 . Figure 3 is a plan view of a layout example of the first main surface 3. Figure 4 is an enlarged plan view of one main portion of the first main surface 3. Figure 5 is an enlarged plan view of one main portion (a different main portion from Figure 4 . Figure 6 is an enlarged plan view of one main portion of the first main surface 3 (a different main portion from Figure 4 and Figure 5 .

[0089] Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 5 . Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 5 . Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 5A cross-sectional view taken along the line IX-IX shown. Figure 10 is a cross-sectional view taken along Figure 5 A cross-sectional view taken along the line X-X shown. Figure 11 is a cross-sectional view taken along Figure 6 A cross-sectional view taken along the line XI-XI shown. Figure 12 is a cross-sectional view taken along Figure 6 A cross-sectional view taken along the line XII-XII shown. Figure 13 is a cross-sectional view taken along Figure 6 A cross-sectional view taken along the line XIII-XIII shown. Figure 14 is a plan view showing a layout example of the first layer wiring 74. Figure 15 is a plan view showing a layout example of the second layer wiring 75.

[0090] The semiconductor device 1A is a semiconductor switching device provided with a transistor configuration Tr (field effect transistor) of a lateral drain-source common type as an example of a device configuration. Referring to Figures 1-15 , the semiconductor device 1A includes a chip 2 of a hexahedral shape (specifically, a cuboid shape). The chip 2 can also be referred to as a "semiconductor chip". The chip 2 has a single-layer configuration composed of a single-crystal silicon substrate (semiconductor substrate) in this embodiment.

[0091] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in plan (hereinafter, simply referred to as "plan") from a normal direction Z thereof. The normal direction Z is also a thickness direction of the chip 2.

[0092] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3, and are opposed to each other in a second direction Y along the first main surface 3 which intersects the first direction X. Specifically, the second direction Y is orthogonal to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y, and are opposed to each other in the first direction X. In the following description, one side of the first direction X refers to the third side surface 5C side, and the other side of the first direction X refers to the fourth side surface 5D side. In addition, one side of the second direction Y refers to the first side surface 5A side, and the other side of the second direction Y refers to the second side surface 5B side.

[0093] The semiconductor device 1A includes a plurality (six in this embodiment) of active regions 6 provided at intervals in the first direction X on the first main surface 3. The plurality of active regions 6 are sequentially arranged from the third side surface 5C side as first to sixth active regions 6A to 6F. The plurality of active regions 6 are regions in which the transistor configuration Tr (device configuration) is respectively formed.

[0094] The plurality of active regions 6 are provided at the inner side of the first main surface 3 at intervals from the periphery (the first to fourth side surfaces 5A to 5D) of the first main surface 3, and are each divided into a strip shape extending in the second direction Y. Specifically, the plurality of active regions 6 are each divided into a polygonal shape (in this case, a quadrangular shape) having four sides parallel to the periphery of the chip 2 in plan view. The planar shape of the active region 6 is arbitrary.

[0095] The semiconductor device 1A includes an outer region 7 of a region provided outside the plurality of active regions 6 in the first main surface 3. In this case, the outer region 7 includes a plurality of boundary regions 7a and one outer peripheral region 7b. The plurality of boundary regions 7a are each divided into a strip shape extending in the second direction Y in a region between the plurality of active regions 6 adjacent in the first direction X.

[0096] The outer peripheral region 7b is provided in a region between the periphery of the first main surface 3 and the plurality of active regions 6, and extends in a strip shape along the periphery of the first main surface 3 and the plurality of active regions 6. In this case, the outer peripheral region 7b collectively surrounds the plurality of active regions 6 in plan view, and is divided into a polygonal ring shape (in this case, a quadrangular ring shape) having four sides parallel to the periphery of the chip 2. The outer peripheral region 7b is connected to the plurality of boundary regions 7a.

[0097] The semiconductor device 1A includes a base layer 8 (base region) of p type formed inside the chip 2. The base layer 8 can also have a p type impurity concentration of 1 x 10 13 cm -3 cm 16 cm -3 cm

[0098] The base layer 8 is formed in the entire region of the thickness range of the chip 2 in a region between the first main surface 3 and the second main surface 4. The base layer 8 extends in a layer shape along the first main surface 3 and the second main surface 4, and forms the first main surface 3, the second main surface 4, and the first to fourth side surfaces 5A to 5D. In this case, the chip 2 is formed of a semiconductor substrate of p type (semiconductor chip of p type), and the base layer 8 is formed using the chip 2 of p type.

[0099] The base layer 8 can also have a thickness of 1 μm or more and 800 μm or less. The thickness of the base layer 8 can have a value in at least one range of 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, and 700 μm or more and 800 μm or less.

[0100] The semiconductor device 1A includes at least one (in this mode, one) n-type drift layer 9 (drift region) formed in the surface layer portion of the first main face 3. In this mode, the drift layer 9 is an impurity region in which the conductivity type of the base layer 8 is replaced from p-type to n-type by an ion implantation method. Of course, the drift layer 9 can also be an epitaxial layer of n-type laminated on the semiconductor substrate (base layer 8) of p-type. The drift layer 9 can also have a thickness of 1 x 10 14 cm -3 1 x 10 18 cm -3 or more and 1 x 10

[0101] The drift layer 9 is formed in the plurality of active regions 6 at intervals from the second main face 4 (bottom of the base layer 8) toward the first main face 3 side, and extends in a layer shape along the first main face 3. The drift layer 9 has a portion drawn out from the plurality of active regions 6 to the outer side region 7 and located in the outer side region 7. In this mode, the drift layer 9 is formed in the surface layer portion of the first main face 3 in the entire region of the first main face 3, and is exposed from the first to fourth side faces 5A to 5D.

[0102] Of course, the drift layer 9 can also be formed in the surface layer portion of the first main face 3 at intervals from the first to fourth side faces 5A to 5D toward the inner side. Of course, the plurality of drift layers 9 can also be formed in a one-to-one correspondence with respect to the plurality of active regions 6. In this case, the plurality of drift layers 9 are formed at intervals in the first direction X in a manner to be respectively located in the plurality of active regions 6, and are respectively formed in a strip shape extending in the second direction Y.

[0103] The depth of the drift layer 9 can be 0.1 μm or more and 10 μm or less. The depth of the drift layer 9 can have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the drift layer 9 is preferably 2 μm or less.

[0104] The semiconductor device 1A includes outer side insulating films 10, 11 that cover the outer surface of the chip 2. The outer side insulating films 10, 11 include a first outer side insulating film 10 and a second outer side insulating film 11. The outer side insulating films 10, 11 do not necessarily need to include both the first outer side insulating film 10 and the second outer side insulating film 11, and can be composed of only either one of the first outer side insulating film 10 and the second outer side insulating film 11. Of course, the presence or absence of the outer side insulating films 10, 11 is arbitrary, and a structure having no outer side insulating films 10, 11 can be adopted.

[0105] The first outer side insulating film 10 covers the second main surface 4 in a film shape. That is, the first outer side insulating film 10 covers the base layer 8 exposed from the second main surface 4. In this mode, the first outer side insulating film 10 covers the entire region of the second main surface 4, and insulates and reinforces the chip 2 from the second main surface 4 side.

[0106] The second outer side insulating film 11 covers at least one of the first to fourth side surfaces 5A to 5D in a film shape. That is, the second outer side insulating film 11 covers the base layer 8 and the drift layer 9 exposed from at least one of the first to fourth side surfaces 5A to 5D. In this mode, the second outer side insulating film 11 covers all of the first to fourth side surfaces 5A to 5D, and insulates and reinforces the chip 2 from the first to fourth side surfaces 5A to 5D side. The second outer side insulating film 11 is continuous with the first outer side insulating film 10 at the periphery of the second main surface 4.

[0107] The outer side insulating films 10, 11 can have a single-layer structure or a layered structure including either one or both of an inorganic insulating film and an organic insulating film. In the case where the outer side insulating films 10, 11 having a layered structure are adopted, the outer side insulating films 10, 11 can include an inorganic insulating film and an organic insulating film that are sequentially layered from the chip 2 side.

[0108] For example, the inorganic insulating film can include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. For example, the organic insulating film can include at least one of polyimide, polyamide, polybenzoxazole, and an epoxy resin.

[0109] The semiconductor device 1A includes a plurality of transistor structures Tr formed in the first main surface 3 in the plurality of active regions 6, respectively. The structure of the plurality of transistor structures Tr will be described specifically below. The semiconductor device 1A includes a plurality of gate structures 12 (control terminals) of a trench electrode type formed in the first main surface 3 in each of the active regions 6. The gate structure 12 can also be referred to as a "trench gate structure". The plurality of gate structures 12 are given a gate potential (gate signal) as a control potential.

[0110] The plurality of gate structures 12 are formed in a strip shape extending in the first direction X in each of the active regions 6, respectively, and are arranged at intervals in the second direction Y. That is, the plurality of gate structures 12 are arranged in a stripe shape extending in the first direction X. The plurality of gate structures 12 each have a first end portion on one side of the first direction X and a second end portion on the other side of the first direction X. The first end portion and the second end portion are led out to the outside region 7 from the active region 6.

[0111] In the first active region 6A, the first end portions of the plurality of gate structures 12 are led out to the outer peripheral region 7b, and the second end portions of the plurality of gate structures 12 are led out to the boundary region 7a. In the second to fifth active regions 6B to 6E, the first end portions of the plurality of gate structures 12 are led out to one boundary region 7a, and the second end portions of the plurality of gate structures 12 are led out to the other boundary region 7a. In the sixth active region 6F, the first end portions of the plurality of gate structures 12 are led out to the boundary region 7a, and the second end portions of the plurality of gate structures 12 are led out to the outer peripheral region 7b.

[0112] With respect to the plurality of active regions 6, the plurality of gate structures 12 face each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the first end portions of the plurality of gate structures 12 arranged in the other active region 6 face the second end portions of the plurality of gate structures 12 arranged in the one active region 6 in a one-to-one corresponding relationship.

[0113] In this manner, the plurality of gate structures 12 are located inside the drift layer 9 in a cross-sectional view. Specifically, the plurality of gate structures 12 are formed at intervals with respect to the depth position of the bottom of the drift layer 9 on the first main surface 3 side, have a side wall and a bottom wall located inside the drift layer 9. The plurality of gate structures 12 can also be formed in a tapered shape in which the opening width narrows toward the bottom wall in a cross-sectional view.

[0114] The plurality of gate structures 12 can also penetrate the bottom of the drift layer 9 in a manner reaching the base layer 8. That is, the plurality of gate structures 12 can also have a portion (a side wall) located within the drift layer 9 and a portion (a bottom wall) located within the base layer 8. The bottom wall of the plurality of gate structures 12 preferably has a flat portion extending substantially in parallel with the first main face 3. The bottom wall of the plurality of gate structures 12 can also be curved in a circular arc shape toward the second main face 4 side.

[0115] The interval of the plurality of gate structures 12 can also be 0.1 μm or more and 5 μm or less. The interval of the gate structures 12 can also have a value belonging to at least one range of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The interval of the gate structures 12 is preferably 3 μm or less.

[0116] The width of the gate structures 12 can also be 0.1 μm or more and 5 μm or less. The width of the gate structures 12 can also have a value belonging to at least one range of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the gate structures 12 is preferably 3 μm or less.

[0117] The depth of the gate structures 12 can also be 0.1 μm or more and 10 μm or less. The depth of the gate structures 12 can also have a value belonging to at least one range of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the gate structures 12 is preferably 3 μm or less.

[0118] The structure of one gate structure 12 will be described below. The gate structure 12 includes a trench 13, an insulating film 14, a buried electrode 15, and a buried insulator 16. The trench 13 is referred to as a "gate trench", the insulating film 14 is referred to as a "gate insulating film", and the buried electrode 15 is also referred to as a "gate electrode". The trench 13 is dug from the first main face 3 toward the second main face 4, dividing a side wall and a bottom wall of the gate structure 12.

[0119] The insulating film 14 covers the wall surface of the trench 13 in a film shape. The insulating film 14 can include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 14 preferably has a single-layer structure. The insulating film 14 preferably includes a silicon oxide film composed of an oxide of the chip 2.

[0120] The buried electrode 15 is buried in the trench 13 through the insulating film 14. The buried electrode 15 can also include conductive polysilicon. The buried electrode 15 includes a buried portion 15a and at least one (in this case, a plurality of) lead-out portions 15b.

[0121] The buried portion 15a is spaced apart from the bottom wall side of the trench 13 and buried in the bottom wall side of the trench 13 in the active region 6 from the first main face 3. The buried portion 15a is preferably spaced apart from the middle portion of the trench 13 and buried in the bottom wall side of the trench 13 from the middle portion of the trench 13, and has an electrode surface located more on the bottom wall side than the middle portion of the trench 13.

[0122] The plurality of lead-out portions 15b include a lead-out portion 15b located at the first end portion of the trench 13 in the outer side region 7, and a lead-out portion 15b located at the second end portion of the trench 13 in the outer side region 7. The plurality of lead-out portions 15b are led out from the bottom wall side (buried portion 15a side) of the trench 13 toward the opening side of the trench 13. The plurality of lead-out portions 15b divide an electrode groove 17 in the opening side of the trench 13 together with the buried portion 15a. The electrode groove 17 extends in a band shape in the first direction X along the trench 13.

[0123] The plurality of lead-out portions 15b have electrode surfaces located in the vicinity of the first main face 3. The electrode surface of the lead-out portion 15b can also be formed in the same plane as the first main face 3. The electrode surface of the lead-out portion 15b can also be located on the bottom wall side of the trench 13 with respect to the first main face 3. The electrode surface of the lead-out portion 15b can also protrude more upward than the first main face 3.

[0124] The buried insulator 16 is buried in the opening side of the trench 13. Specifically, the buried insulator 16 is buried in the electrode recess 17, covering the buried portion 15a in the trench 13. The buried insulator 16 can also be buried in the trench 13 with the insulating film 14 interposed therebetween. The buried insulator 16 can also be buried in the trench 13 without the insulating film 14 interposed therebetween, in a manner of directly covering the side wall of the trench 13. The buried insulator 16 extends in a band shape in the first direction X when viewed from above. The buried insulator 16 is provided as a field insulator for mitigating an electric field to the trench 13. The cross-sectional area of the buried insulator 16 is preferably larger than that of the buried portion 15a.

[0125] The buried insulator 16 has an insulating surface located in the vicinity of the first main surface 3. The insulating surface can also be formed in the same plane as the first main surface 3. The insulating surface can also be located on the bottom wall side of the trench 13 with respect to the first main surface 3. The insulating surface can also protrude upward more than the first main surface 3.

[0126] The buried insulator 16 can also contain at least one of silicon oxide, silicon nitride, and silicon oxynitride. The buried insulator 16 can also have a single-layer configuration. The buried insulator 16 can also be formed of the same insulating material as the insulating film 14. In this case, the buried insulator 16 is preferably composed of a vapor deposit accumulated by a CVD (Chemical Vapor Deposition) method or the like, having a different density of compaction from that of the insulating film 14.

[0127] The semiconductor device 1A includes a plurality of gate units GU1, GU2 in each active region 6. The plurality of gate units GU1, GU2 includes a plurality of first gate units GU1 and a plurality of second gate units GU2.

[0128] The plurality of first gate units GU1 is respectively composed of at least 2 (in this case, 2) gate structures 12 adjacent to each other in the second direction Y in each active region 6. The plurality of first gate units GU1 is arranged in the second direction Y in each active region 6 alternately with the at least 2 (in this case, 2) gate structures 12.

[0129] With respect to the plurality of active regions 6, the plurality of first gate units GU1 opposes each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of first gate units GU1 disposed in the other active region 6 opposes the plurality of first gate units GU1 disposed in the one active region 6 in a one-to-one corresponding relationship.

[0130] The plurality of second gate units GU2 are each formed of at least two (in this case, two) gate formations 12 other than the plurality of gate formations 12 that form the plurality of first gate units GU1 among the plurality of gate formations 12 in each active region 6. The plurality of second gate units GU2 are each formed of at least two gate formations 12 adjacent in the second direction Y in each active region 6. The plurality of second gate units GU2 are arranged in the second direction Y alternately with the plurality of first gate units GU1 in each active region 6.

[0131] With respect to the plurality of active regions 6, the plurality of second gate units GU2 oppose each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of second gate units GU2 disposed in the other active region 6 oppose the plurality of second gate units GU2 disposed in the one active region 6 in a one-to-one corresponding relationship.

[0132] The semiconductor device 1A includes a plurality of cell spaces US each divided in a region between the plurality of first gate units GU1 and the plurality of second gate units GU2 adjacent in the second direction Y in each active region 6. Each cell space US is divided in a region between one gate formation 12 of the first gate unit GU1 and one gate formation 12 of the second gate unit GU2, including the drift layer 9.

[0133] The semiconductor device 1A includes a plurality of connection formations 21, 22 of the trench electrode type formed in the outer region 7 of the first main face 3. The plurality of connection formations 21, 22 connect at least two gate formations 12 adjacent in the second direction Y. The plurality of connection formations 21, 22 are imparted with a gate potential. The connection formations 21, 22 can also be referred to as "gate connection formations".

[0134] The plurality of connection formations 21, 22 are respectively connected to the first end portions and the second end portions of the plurality of gate formations 12 in the corresponding gate units GU1, GU2. Thereby, the plurality of connection formations 21, 22 respectively form, together with the corresponding plurality of gate formations 12, the plurality of gate units GU1, GU2 in a ring shape or a ladder shape (in this case, a quadrilateral ring shape).

[0135] The plurality of connection formations 21, 22 include a plurality of first connection formations 21 disposed on the first end portion side of the plurality of gate formations 12, and a plurality of second connection formations 22 disposed on the second end portion side of the plurality of gate formations 12.

[0136] The plurality of first connection structures 21 are each formed in a strip shape extending in the second direction Y, and are arranged at intervals in the second direction Y. The plurality of first connection structures 21 are arranged in a row in the second direction Y. The plurality of first connection structures 21 are each connected to the first end portions of a pair of the plurality of gate structures 12 adjacent in the second direction Y. In this way, the plurality of first connection structures 21 are each connected to the first end portions of a pair of the plurality of gate structures 12 adjacent in the second direction Y.

[0137] The plurality of second connection structures 22 are each formed in a strip shape extending in the second direction Y, and are arranged at intervals in the second direction Y. The plurality of second connection structures 22 are arranged in a row in the second direction Y. The plurality of second connection structures 22 are each connected to the second end portions of the plurality of gate structures 12 unitized by the first connection structures 21. In this way, the plurality of second connection structures 22 are each connected to the second end portions of a pair of the plurality of gate structures 12 adjacent in the second direction Y.

[0138] With respect to the first active region 6A, the plurality of first connection structures 21 are each connected to the first end portions of the plurality of gate structures 12 adjacent in the second direction Y in the outer peripheral region 7b, and the plurality of second connection structures 22 are each connected to the second end portions of the plurality of gate structures 12 unitized by the first connection structures 21 in the boundary region 7a.

[0139] With respect to the second to fifth active regions 6B to 6E, the plurality of first connection structures 21 are each connected to the first end portions of the plurality of gate structures 12 adjacent in the second direction Y in one of the boundary regions 7a, and the plurality of second connection structures 22 are each connected to the second end portions of the plurality of gate structures 12 unitized by the first connection structures 21 in the other of the boundary regions 7a.

[0140] With respect to the sixth active region 6F, the plurality of first connection structures 21 are each connected to the first end portions of the plurality of gate structures 12 adjacent in the second direction Y in the boundary region 7a, and the plurality of second connection structures 22 are each connected to the second end portions of the plurality of gate structures 12 unitized by the first connection structures 21 in the outer peripheral region 7b. In each of the boundary regions 7a, the plurality of second connection structures 22 are each formed at intervals in the first direction X from the plurality of first connection structures 21, and are each opposed to the plurality of first connection structures 21 in a one-to-one corresponding relationship in the first direction X.

[0141] In this way, the plurality of connection structures 21, 22 are located within the drift layer 9 in a cross-sectional view. Specifically, the plurality of connection structures 21, 22 are each formed at intervals in a depth position from a bottom of the drift layer 9 on the first main surface 3 side, and have a side wall and a bottom wall located within the drift layer 9. The plurality of connection structures 21, 22 can also be formed in a tapered shape in which an opening width narrows toward the bottom wall in a cross-sectional view.

[0142] The plurality of connection formations 21, 22 can also penetrate the bottom of the drift layer 9 in a manner reaching the base layer 8 and have a bottom wall located within the base layer 8. That is, the plurality of connection formations 21, 22 can also have a portion (a side wall) located within the drift layer 9 and a portion (a bottom wall) located within the base layer 8. The bottom wall of the plurality of connection formations 21, 22 preferably has a flat portion extending substantially in parallel with the first main face 3. Of course, the bottom wall of the plurality of connection formations 21, 22 can also be curved in a circular arc shape toward the second main face 4 side.

[0143] In this manner, the width of the connection formation 21, 22 is greater than the width of the gate formation 12. The width of the connection formation 21, 22 can also be substantially equal to the width of the gate formation 12. The width of the connection formation 21, 22 can also be smaller than the width of the gate formation 12.

[0144] The width of the connection formation 21, 22 can also be 0.1 μm or more and 5 μm or less. The width of the connection formation 21, 22 can also have a value belonging to at least one range of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0145] In this manner, the depth of the connection formation 21, 22 is greater than the depth of the gate formation 12. The depth of the connection formation 21, 22 can also be substantially equal to the depth of the gate formation 12. The depth of the connection formation 21, 22 can also be smaller than the depth of the gate formation 12.

[0146] The depth of the connection formation 21, 22 can also be 0.1 μm or more and 10 μm or less. The depth of the connection formation 21, 22 can also have a value belonging to at least one range of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less.

[0147] The following describes the structure of a connection formation 21, 22. The connection formation 21, 22 includes a connection trench 23, a connection insulating film 24, and a connection electrode 25. The connection trench 23 is excavated from the first main face 3 toward the second main face 4, and divides the side wall and the bottom wall of the connection formation 21, 22. The connection trench 23 is connected to a plurality of trenches 13 adjacent in the second direction Y.

[0148] The connection insulating film 24 covers the wall surface of the connection trench 23 in a film shape. The connection insulating film 24 is connected to the insulating film 14 and the buried insulator 16 in the communication portion of the trench 13 and the connection trench 23. The connection insulating film 24 can include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The connection insulating film 24 preferably has a single-layer structure. The connection insulating film 24 preferably includes a silicon oxide film composed of the oxide of the chip 2. The connection insulating film 24 is preferably formed of the same insulating material as the insulating film 14.

[0149] The connection electrode 25 is buried in the connection trench 23 through the connection insulating film 24. The connection electrode 25 can also include conductive polysilicon. The connection electrode 25 is formed in a band shape extending in the second direction Y in plan view, and is connected to the buried electrode 15 in the communication portion of the trench 13 and the connection trench 23.

[0150] The connection electrode 25 can be regarded as a portion of the buried electrode 15 (the lead-out portion 15b) that is led out into the connection trench 23. The connection portion of the buried electrode 15 and the connection electrode 25 can be regarded as one constituent element of the gate formation 12, or as one constituent element of the connection formation 21, 22.

[0151] The connection electrode 25 has an electrode face located in the vicinity of the first main face 3. The electrode face of the connection electrode 25 can also be formed in coplanar with the first main face 3. The electrode face of the connection electrode 25 can also be located on the bottom wall side of the connection trench 23 with respect to the first main face 3. The electrode face of the connection electrode 25 can also protrude more upward than the first main face 3. The planar area of the electrode face of the connection electrode 25 is preferably larger than the planar area of the electrode face of the buried portion 15a.

[0152] The semiconductor device 1A includes a plurality of mesa portions 26, 27 that respectively divide a plurality of active regions 6 in the first main face 3. The plurality of mesa portions 26, 27 are respectively divided by a plurality of gate units GU1, GU2. That is, each mesa portion 26, 27 is composed of a portion surrounded by the plurality of gate formations 12 and the plurality of connection formations 21, 22. The plurality of mesa portions 26, 27 respectively extend in a band shape in the first direction X, and are divided at intervals in the second direction Y. That is, the plurality of mesa portions 26, 27 are divided into a stripe shape extending in the first direction X.

[0153] The plurality of mesa portions 26, 27 includes a plurality of first mesa portions 26 and a plurality of second mesa portions 27. The plurality of first mesa portions 26 is divided by the plurality of first gate units GU1 respectively and is given a region (first application end) of a first drain source potential as a first potential (high potential).

[0154] With respect to the plurality of active regions 6, the plurality of first mesa portions 26 opposes each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of first mesa portions 26 divided in the other active region 6 opposes the plurality of first mesa portions 26 divided in one active region 6 in a one-to-one corresponding relationship.

[0155] The plurality of second mesa portions 27 is divided by the plurality of second gate units GU2 respectively and is given a region (second application end) of a second drain source potential as a second potential (low potential) different from the first potential. That is, the plurality of second mesa portions 27 is divided in the second direction Y alternately with the plurality of first mesa portions 26 with the plurality of cell spaces US therebetween. The second drain source potential can be the same potential as the base potential or a different potential from the base potential.

[0156] With respect to the plurality of active regions 6, the plurality of second mesa portions 27 opposes each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of second mesa portions 27 divided in the other active region 6 opposes the plurality of second mesa portions 27 divided in one active region 6 in a one-to-one corresponding relationship.

[0157] The semiconductor device 1A includes a plurality of drain source regions 28, 29 of n type formed in a surface layer portion of the first main face 3 (drift layer 9) in each active region 6. The plurality of drain source regions 28, 29 is formed in the plurality of mesa portions 26, 27. That is, the plurality of drain source regions 28, 29 is formed in a region between the plurality of gate structures 12 in the corresponding gate unit GU1, GU2 respectively. The plurality of drain source regions 28, 29 has an n type impurity concentration higher than that of the drift layer 9. The n type impurity concentration of the plurality of drain source regions 28, 29 can be 1 x 1018 cm-3 or more. 16 cm -3 The above and 1 x 1018 cm-3 or more. 21 cm -3 The above and 1 x 1018 cm-3 or more.

[0158] The plurality of drain source regions 28, 29 includes a plurality of first drain source regions 28 and a plurality of second drain source regions 29. The plurality of first drain source regions 28 is a region (first application end) given the first drain source potential and is formed in a strip shape extending in the first direction X in the plurality of first mesa portions 26.

[0159] With respect to the plurality of active regions 6, the plurality of first drain-source regions 28 oppose each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of first drain-source regions 28 disposed in the other active region 6 oppose the plurality of first drain-source regions 28 disposed in the one active region 6 in a one-to-one correspondence.

[0160] The plurality of second drain-source regions 29 are regions to which the second drain-source potential is applied (second application terminal) and are formed in a strip shape extending in the first direction X in the plurality of second mesa portions 27. That is, the plurality of second drain-source regions 29 are formed in the second direction Y alternately with the plurality of first drain-source regions 28. In addition, the plurality of drain-source regions 28, 29 are arranged in a stripe shape extending in the first direction X.

[0161] With respect to the plurality of active regions 6, the plurality of second drain-source regions 29 oppose each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of second drain-source regions 29 disposed in the other active region 6 oppose the plurality of second drain-source regions 29 disposed in the one active region 6 in a one-to-one correspondence.

[0162] Hereinafter, the structure of one drain-source region 28, 29 will be described. The drain-source region 28, 29 is formed on the first main surface 3 side spaced apart from the bottom wall of the plurality of gate structures 12 and opposes the base layer 8 across a portion of the drift layer 9. Specifically, the drain-source region 28, 29 is formed on the first main surface 3 side spaced apart from the depth position of the electrode surface of the plurality of buried electrodes 15 and opposes the plurality of buried insulators 16 in the horizontal direction along the first main surface 3.

[0163] Such a structure is effective in suppressing a decrease in the breakdown voltage caused by a decrease in the voltage between the gate structure 12 and the drain-source region 28, 29. The drain-source region 28, 29 can also be in contact with the plurality of gate structures 12. That is, the drain-source region 28, 29 can also be in contact with the portion of the plurality of gate structures 12 in which the buried insulator 16 is disposed.

[0164] The drain-source regions 28, 29 are formed at intervals in the first direction X from the first end portion and the second end portion of the plurality of gate structures 12, without being continuous with portions of the plurality of gate structures 12 in which the lead-out portions 15b are provided. That is, the drain-source regions 28, 29 are formed at intervals in the first direction X from the plurality of connection structures 21, 22 located on both sides. Such a structure is effective in suppressing a decrease in breakdown voltage caused by a decrease in voltage between the end portions (connection structures 21, 22) of the gate structures 12 and the drain-source regions 28, 29.

[0165] The drain-source regions 28, 29 are preferably formed at a region interval of 0.1 μm or more and 2 μm or less from the end portions (connection structures 21, 22) of the gate structures 12. The region interval can have a value in at least one range of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0166] The semiconductor device 1A includes a plurality of isolation structures 31, 32 of a trench electrode type formed in the first main surface 3 in each active region 6. The plurality of isolation structures 31, 32 are supplied with a gate potential. The isolation structures 31, 32 can also be referred to as "gate isolation structures". The plurality of isolation structures 31, 32 are respectively connected to a plurality of gate structures 12 adjacent in the second direction Y in the corresponding gate unit GU1, GU2.

[0167] The plurality of isolation structures 31, 32 are respectively provided in regions between the end portions of the plurality of gate structures 12 and the plurality of drain-source regions 28, 29, and physically and electrically isolate the plurality of drain-source regions 28, 29 from the end portions of the plurality of gate structures 12. That is, the plurality of isolation structures 31, 32 physically and electrically isolate the plurality of drain-source regions 28, 29 from the plurality of connection structures 21, 22.

[0168] The plurality of isolation structures 31, 32 divide the boundary portion of the active region 6 and the outer region 7 in the first main surface 3, while increasing the distance along the surface between the end portions (connection structures 21, 22) of the gate structures 12 and the drain-source regions 28, 29. In this way, the plurality of isolation structures 31, 32 include a plurality of first isolation structures 31 provided on the first end portion side and a plurality of second isolation structures 32 provided on the second end portion side.

[0169] The first isolation structures 31 are arranged on the drain-source regions 28, 29 side at intervals from the first end portions (the first connection structures 21). The first isolation structures 31 each extend in the second direction Y in a strip shape, and are connected to the gate structures 12 adjacent in the second direction Y, respectively. The first isolation structures 31 are arranged in a row in the second direction Y. The first isolation structures 31 can also be connected to the drain-source regions 28, 29.

[0170] The second isolation structures 32 are arranged on the drain-source regions 28, 29 side at intervals from the second end portions (the second connection structures 22). The second isolation structures 32 each extend in the second direction Y in a strip shape, and are connected to the gate structures 12 adjacent in the second direction Y, respectively. The second isolation structures 32 are arranged in a row in the second direction Y. The second isolation structures 32 can also be connected to the drain-source regions 28, 29.

[0171] In this way, the isolation structures 31, 32 are located in the drift layer 9 in a cross-sectional view. Specifically, the isolation structures 31, 32 are formed at intervals from the depth position of the bottom of the drift layer 9 on the first main surface 3 side, and have a side wall and a bottom wall located in the drift layer 9. The isolation structures 31, 32 can also be formed in a tapered shape in which the opening width is narrowed toward the bottom wall in a cross-sectional view.

[0172] The isolation structures 31, 32 can also reach the base layer 8 through the bottom of the drift layer 9. That is, the isolation structures 31, 32 can have a portion (side wall) located in the drift layer 9 and a portion (bottom wall) located in the base layer 8. The bottom wall of the isolation structures 31, 32 preferably has a flat portion extending substantially parallel to the first main surface 3. Of course, the bottom wall of the isolation structures 31, 32 can also be curved in a circular arc shape toward the second main surface 4 side.

[0173] In this way, the width of the isolation structures 31, 32 is smaller than the width of the connection structures 21, 22. The width of the isolation structures 31, 32 can also be substantially equal to the width of the connection structures 21, 22. The width of the isolation structures 31, 32 can also be larger than the width of the connection structures 21, 22. The width of the isolation structures 31, 32 can also be substantially equal to the width of the gate structures 12. The width of the isolation structures 31, 32 can also be larger than the width of the gate structures 12. The width of the isolation structures 31, 32 can also be smaller than the width of the gate structures 12.

[0174] The width of the isolation structure 31, 32 can also be 0.1 μm or more and 5 μm or less. The width of the isolation structure 31, 32 can also have a value belonging to at least one range of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0175] In this mode, the depth of the isolation structure 31, 32 is smaller than the depth of the connection structure 21, 22. The depth of the isolation structure 31, 32 can also be substantially equal to the depth of the connection structure 21, 22. The depth of the isolation structure 31, 32 can also be larger than the depth of the connection structure 21, 22. The depth of the isolation structure 31, 32 can also be substantially equal to the depth of the gate structure 12. The depth of the isolation structure 31, 32 can be larger than the depth of the gate structure 12. The depth of the isolation structure 31, 32 can also be smaller than the depth of the gate structure 12. For example, the isolation structure 31, 32 can also be formed at the first main surface 3 side at intervals from the depth position of the middle portion of the gate structure 12.

[0176] The depth of the isolation structure 31, 32 can also be 0.1 μm or more and 10 μm or less. The depth of the isolation structure 31, 32 can also have a value belonging to at least one range of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less.

[0177] Hereinafter, the structure of one isolation structure 31, 32 will be described. The isolation structure 31, 32 includes an isolation trench 33, an isolation insulating film 34, an isolation electrode 35, and an isolation buried insulator 36. The isolation trench 33 is dug from the first main surface 3 toward the second main surface 4, and divides the side wall and the bottom wall of the isolation structure 31, 32. The isolation trench 33 is connected to a plurality of trenches 13 adjacent in the second direction Y.

[0178] The isolation insulating film 34 covers the wall surface of the isolation trench 33 in a film shape. The isolation insulating film 34 is connected to the insulating film 14 and the buried insulator 16 at the communication portion of the trench 13 and the isolation trench 33. The isolation insulating film 34 can be regarded as a portion of the insulating film 14 that is drawn into the isolation trench 33. The connection portion of the insulating film 14 and the isolation insulating film 34 can be regarded as one constituent element of the gate structure 12, and can also be regarded as one constituent element of the isolation structure 31, 32.

[0179] The isolation insulating film 34 can include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The isolation insulating film 34 preferably has a single layer structure. The isolation insulating film 34 preferably contains a silicon oxide film composed of an oxide of the chip 2. The isolation insulating film 34 is preferably formed of the same insulating material as the insulating film 14.

[0180] The isolation electrode 35 is buried in the isolation trench 33 through the isolation insulating film 34. The isolation electrode 35 can also contain conductive polysilicon. The isolation electrode 35 is buried in the bottom wall side of the trench 13 at intervals from the first main surface 3 to the bottom wall side of the isolation trench 33. The isolation electrode 35 is preferably buried in the bottom wall side of the isolation trench 33 at intervals from the middle portion of the isolation trench 33, and has an electrode surface located more on the bottom wall side than the middle portion of the isolation trench 33.

[0181] The isolation electrode 35 is connected to the buried portion 15a at the communication portion of the trench 13 and the isolation trench 33. The isolation electrode 35 can be regarded as a portion of the buried electrode 15 (buried portion 15a) that is drawn into the isolation trench 33. The connection portion of the buried electrode 15 and the isolation electrode 35 can be regarded as one constituent element of the gate structure 12, and can also be regarded as one constituent element of the isolation structure 31, 32.

[0182] The electrode surface of the isolation electrode 35 is located on the bottom wall side of the isolation trench 33 with respect to the electrode surface of the drawn-out portion 15b of the buried electrode 15. The electrode surface of the isolation electrode 35 is preferably located at a depth position substantially equal to the electrode surface of the buried portion 15a.

[0183] The isolation buried insulator 36 is buried in the opening side of the isolation trench 33. The isolation buried insulator 36 can also be buried in the isolation trench 33 through the isolation insulating film 34. The isolation buried insulator 36 can also be buried in the isolation trench 33 without the isolation insulating film 34 in a manner of directly covering the side wall of the isolation trench 33.

[0184] The isolation buried insulator 36 extends in a band shape in the second direction Y in plan view. The isolation buried insulator 36 is connected to the buried insulator 16 at the communication portion of the trench 13 and the isolation trench 33. The isolation buried insulator 36 is provided as a field insulator that relaxes an electric field to the isolation trench 33. The cross-sectional area of the isolation buried insulator 36 is preferably larger than the cross-sectional area of the isolation electrode 35.

[0185] The buried isolation insulator 36 has an insulating surface in the vicinity of the first main surface 3. The insulating surface can also be formed in the same plane as the first main surface 3. The insulating surface can also be located on the side of the bottom wall of the isolation trench 33 with respect to the first main surface 3. The insulating surface can also protrude upward more than the first main surface 3.

[0186] The buried isolation insulator 36 can also contain at least one of silicon oxide, silicon nitride, and silicon oxynitride. The buried isolation insulator 36 can also have a single-layer configuration. The buried isolation insulator 36 can also be formed of the same insulating material as the isolation insulating film 34. The buried isolation insulator 36 is preferably composed of a deposit accumulated by a CVD method or the like, and preferably has a different density of compaction from that of the isolation insulating film 34. The buried isolation insulator 36 is preferably formed of the same insulating material as the buried insulator 16.

[0187] The isolation structures 31, 32 can also be configured of a trench insulating type instead of a trench electrode type. In this case, an insulator (silicon oxide, silicon nitride, silicon oxynitride, or the like) is buried in the isolation trench 33 with the isolation insulating film 34 interposed instead of the isolation electrode 35. In this case, the isolation insulating film 34 can also be removed.

[0188] The semiconductor device 1A includes a plurality of floating regions 37 of n-type formed in the region between the end portions (connection structures 21, 22) of the plurality of gate structures 12 and the plurality of isolation structures 31, 32 in the outer side region 7. The plurality of floating regions 37 each include a portion of the drift layer 9 in the region between the end portions (connection structures 21, 22) of the plurality of gate structures 12 and the plurality of isolation structures 31, 32, and are formed in an electrically floating state.

[0189] Although specific illustrations are omitted, the plurality of floating regions 37 can also include a high-concentration region having a higher n-type impurity concentration than that of the drift layer 9 in the surface layer portion of the drift layer 9. In this case, the n-type impurity concentration of the high-concentration region can also be approximately equal to that of the drain source regions 28, 29. In addition, the high-concentration region can also have a depth approximately equal to that of the drain source regions 28, 29.

[0190] The semiconductor device 1A includes a field structure 42 of one or more trench electrode types formed in the first main surface 3 in the outer side region 7. The field structure 42 can also be referred to as a "trench field structure". The number of the field structure 42 is arbitrary, and is adjusted according to the electric field to be mitigated or the like.

[0191] The number of the field structures 42 can also be one, two, three, four, five, six, seven, eight, nine, or ten. The number of the field structures 42 is preferably five or less. In this case, the semiconductor device 1A includes three field structures 42. The base potential, the second drain-source potential (low potential) can also be applied to the plurality of field structures 42. The plurality of field structures 42 can also be formed in an electrically floating state.

[0192] The plurality of field structures 42 are formed at the periphery side of the first main surface 3 and at the first main surface 3 of the outer peripheral region 7b, spaced apart from the plurality of gate structures 12 (the plurality of connection structures 21, 22). The spacing between the plurality of gate structures 12 (the plurality of connection structures 21, 22) and the innermost (the active region 6 side) field structure 42 is preferably larger than the spacing between the plurality of gate structures 12. Of course, the spacing between the gate structure 12 and the field structure 42 can also be equal to or smaller (less) than the spacing between the plurality of gate structures 12.

[0193] The plurality of field structures 42 are arranged spaced apart from each other and extend in a band shape along the periphery of the first main surface 3, respectively. In this case, the plurality of field structures 42 collectively surround the plurality of active regions 6 (the plurality of gate structures 12) in plan view and are formed in a polygonal ring shape (in this case, a quadrilateral ring shape) having four sides parallel to the periphery of the chip 2.

[0194] In this case, the plurality of field structures 42 are located inside the drift layer 9 in cross-sectional view. Specifically, the plurality of field structures 42 are formed at the first main surface 3 side spaced apart from each other with respect to the depth position of the bottom of the drift layer 9, have a side wall and a bottom wall located inside the drift layer 9. The plurality of field structures 42 can also be formed in a tapered shape in which the opening width toward the bottom wall is narrowed in cross-sectional view.

[0195] The plurality of field structures 42 can also reach the base layer 8 through the bottom of the drift layer 9. That is, the plurality of field structures 42 can have a portion (side wall) located inside the drift layer 9 and a portion (bottom wall) located inside the base layer 8. The bottom wall of the plurality of field structures 42 preferably has a flat portion extending substantially parallel to the first main surface 3. Of course, the bottom wall of the plurality of field structures 42 can also be curved in a circular arc shape toward the second main surface 4 side.

[0196] The spacing between the plurality of field structures 42 can also be substantially equal to the spacing between the plurality of gate structures 12. The spacing between the plurality of field structures 42 can also be smaller than the spacing between the plurality of gate structures 12. The spacing between the plurality of field structures 42 can also be larger than the spacing between the plurality of gate structures 12.

[0197] The interval of the plurality of field structures 42 can also be 0.1 μm or more and 5 μm or less. The interval of the field structures 42 can have a value belonging to at least one range of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0198] In this mode, the width of the field structure 42 is larger than the width of the gate structure 12. The width of the field structure 42 can also be smaller than the width of the gate structure 12. The width of the field structure 42 can also be substantially equal to the width of the gate structure 12. The width of the field structure 42 can also be substantially equal to the width of the connection structures 21, 22. The width of the field structure 42 can also be larger than the width of the connection structures 21, 22. The width of the field structure 42 can also be smaller than the width of the connection structures 21, 22.

[0199] The width of the field structure 42 can also be 0.1 μm or more and 5 μm or less. The width of the field structure 42 can have a value belonging to at least one range of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0200] In this mode, the depth of the field structure 42 is larger than the depth of the gate structure 12. The depth of the field structure 42 can also be smaller than the depth of the gate structure 12. The depth of the field structure 42 can also be substantially equal to the depth of the gate structure 12. The depth of the field structure 42 can also be substantially equal to the depth of the connection structures 21, 22. The depth of the field structure 42 can also be larger than the depth of the connection structures 21, 22. The depth of the field structure 42 can also be smaller than the depth of the connection structures 21, 22.

[0201] The depth of the field structure 42 can also be 0.1 μm or more and 10 μm or less. The depth of the field structure 42 can also have a value in at least one range of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less.

[0202] The structure of one field structure 42 will be described below. The field structure 42 includes a field trench 43, a field insulating film 44, and a field electrode 45. The field trench 43 is dug from the first main surface 3 toward the second main surface 4, dividing a side wall and a bottom wall of the field structure 42.

[0203] The field insulating film 44 covers the wall surface of the field trench 43 in a film shape. The field insulating film 44 can include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The field insulating film 44 preferably has a single-layer structure. The field insulating film 44 preferably includes a silicon oxide film composed of an oxide of the chip 2. The field insulating film 44 is preferably formed of the same insulating material as the insulating film 14.

[0204] The field electrode 45 is embedded in the field trench 43 through the field insulating film 44. The field electrode 45 can also include conductive polysilicon. The field electrode 45 has an electrode surface on the first main surface 3 side with respect to an electrode surface of the embedded portion 15a. The electrode surface of the field electrode 45 is located in the vicinity of the first main surface 3.

[0205] The electrode surface of the field electrode 45 can also be formed in the same plane as the first main surface 3. The electrode surface of the field electrode 45 can also be located on the bottom wall side of the field trench 43 with respect to the first main surface 3. The electrode surface of the field electrode 45 can also protrude more upward than the first main surface 3.

[0206] The field structure 42 can also be configured of a trench insulating type instead of a trench electrode type. In this case, an insulator (silicon oxide, silicon nitride, silicon oxynitride, or the like) is embedded in the field trench 43 through the field insulating film 44 instead of the field electrode 45. In this case, the field insulating film 44 can also be removed.

[0207] The semiconductor device 1A includes a plurality of first impurity regions 51 of p type formed in the inner portion of the chip 2 in regions along the lower end portions of the plurality of gate structures 12, respectively. The first impurity regions 51 have a p-type impurity concentration higher than the p-type impurity concentration of the base layer 8. The p-type impurity concentration of the first impurity regions 51 can be 1 x 1018 cm-3 or more and 1 x 1020 cm-3 or less, for example. 16 cm -3 The p-type impurity concentration of the first impurity regions 51 can be 1 x 1018 cm-3 or more and 1 x 1020 cm-3 or less, for example. 19 cm -3 The p-type impurity concentration of the first impurity regions 51 can be 1 x 1018 cm-3 or more and 1 x 1020 cm-3 or less, for example.

[0208] The plurality of first impurity regions 51 are formed in a one-to-one corresponding relationship with the lower end portions of the corresponding gate structures 12 at intervals with respect to the gate structures 12 adjacent in the second direction Y. The plurality of first impurity regions 51 have portions covering the bottom walls and portions covering the side walls at the lower end portions of the corresponding gate structures 12. The plurality of first impurity regions 51 extend in a band shape along the corresponding gate structures 12 in the first direction X in plan view.

[0209] The plurality of first impurity regions 51 oppose the buried electrodes 15 through the insulating films 14 at the lower end portions of the corresponding gate structures 12. The plurality of first impurity regions 51 are electrically connected to the drift layer 9 on the first main surface 3 side and to the base layer 8 on the second main surface 4 side. In this manner, the plurality of first impurity regions 51 have portions that change the conductivity type of the drift layer 9 from n-type to p-type on the first main surface 3 side.

[0210] In a case where the bottom walls of the plurality of gate structures 12 are located inside the base layer 8, the plurality of first impurity regions 51 can also be formed at intervals on the second main surface 4 side from the bottom of the drift layer 9. In this case, the plurality of first impurity regions 51 can also oppose the drift layer 9 through a portion of the base layer 8.

[0211] The plurality of first impurity regions 51 are each formed wider than the corresponding gate structure 12. Specifically, the plurality of first impurity regions 51 each include a bulging portion that protrudes in an arc shape (circular arc shape) from the lower side of the gate structure 12 in the horizontal direction (both sides) in cross section. In a case where the gate structure 12 is formed in a tapered shape, the bulging portion opposes the side wall of the gate structure 12 in the thickness direction of the chip 2.

[0212] With respect to the plurality of first impurity regions 51 adjacent in the second direction Y, the bulging portion of one first impurity region 51 is connected to the bulging portion of another first impurity region 51. That is, the plurality of first impurity regions 51 are connected to each other in the second direction Y. Thus, the plurality of first impurity regions 51 isolate the base layer 8 and the drift layer 9 in the up-down direction in the corresponding active region 6. The connection portions of the plurality of bulging portions can also oppose the plurality of drain-source regions 28, 29 through the drift layer 9.

[0213] Portions of the plurality of first impurity regions 51 along the lower end portions of the plurality of gate structures 12 each form a channel (current path) of a transistor structure Tr. Inversion and non-inversion of the channel are controlled by the plurality of gate structures 12.

[0214] When a gate potential is given to the plurality of gate structures 12, a first drain-source potential is given to the first drain-source region 28, and a second drain-source potential is given to the second drain-source region 29, the plurality of channels become in an on state, and a drain-source current Ids is generated (refer to FIG. 6).Figure 6 ).

[0215] The drain-source current Ids flows from the first drain-source region 28 to the second drain-source region 29 via the drift layer 9 and the plurality of first impurity regions 51. That is, the drain-source current Ids passes through the region present below the plurality of (in this mode, 2) gate structures 12 between the first drain-source region 28 and the second drain-source region 29 in the second direction Y.

[0216] The first impurity region 51 is formed by introducing a p-type impurity to the inside of the chip 2 via the bottom wall portion of the trench 13. In the case of the trench 13 having a flat bottom wall, the p-type impurity can be appropriately introduced to the inside of the chip 2. Therefore, the first impurity region 51 (channel) is appropriately formed in the region along the lower end portion of the gate structure 12.

[0217] The semiconductor device 1A includes a plurality of second impurity regions 52 of p-type formed in the inside of the chip 2 in the regions along the lower end portions of the plurality of connection structures 21, 22, respectively. The second impurity region 52 has a p-type impurity concentration higher than the p-type impurity concentration of the base layer 8. The p-type impurity concentration of the second impurity region 52 is preferably substantially equal to the p-type impurity concentration of the first impurity region 51. The p-type impurity concentration of the second impurity region 52 can be 1 x 1018cm-3 or more and 1 x 1020cm-3 or less. 16 cm -3 The above and 1 x 1018cm-3 or more and 1 x 1020cm-3 or less. 19 cm -3 The above and 1 x 1018cm-3 or more and 1 x 1020cm-3 or less.

[0218] The plurality of second impurity regions 52 are formed in one-to-one correspondence with respect to the lower end portions of the corresponding connection structures 21, 22, respectively. The plurality of second impurity regions 52 have portions covering the bottom walls and portions covering the side walls at the lower end portions of the corresponding connection structures 21, 22. The plurality of second impurity regions 52 extend in a band shape along the corresponding connection structures 21, 22 in the second direction Y in plan view, and are connected to the first impurity region 51 at both end portions of the corresponding connection structures 21, 22.

[0219] The plurality of second impurity regions 52 oppose the connection electrode 25 across the connection insulating film 24 at the lower end portions of the corresponding connection structures 21, 22. The plurality of second impurity regions 52 are electrically connected to the drift layer 9 at the first main surface 3 side and electrically connected to the base layer 8 at the second main surface 4 side. In this mode, the plurality of second impurity regions 52 have portions that replace the conduction type of the drift layer 9 from n-type to p-type at the first main surface 3 side.

[0220] In a case where the bottom walls of the plurality of connection formations 21, 22 are located in the base layer 8, the plurality of second impurity regions 52 can also be formed in the region of the second main face 4 side spaced apart from the bottom of the drift layer 9. In this case, the plurality of second impurity regions 52 can also be opposed to the drift layer 9 through a portion of the base layer 8.

[0221] In this mode, the plurality of connection formations 21, 22 are formed deeper than the plurality of gate formations 12, and the plurality of second impurity regions 52 are formed deeper than the plurality of first impurity regions 51. That is, the bottoms of the plurality of second impurity regions 52 are located on the second main face 4 side with respect to the bottoms of the plurality of first impurity regions 51. Of course, it can also be that the plurality of connection formations 21, 22 are formed to a depth approximately equal to the plurality of gate formations 12, and the plurality of second impurity regions 52 are formed to a depth approximately equal to the plurality of first impurity regions 51.

[0222] The plurality of second impurity regions 52 are each formed wider than the corresponding connection formation 21, 22. Specifically, the plurality of second impurity regions 52, like the plurality of first impurity regions 51, each include a bulging portion protruding in an arc shape (circular arc shape) in the horizontal direction (both sides) from the region below the connection formation 21, 22 when viewed in cross section. In a case where the connection formation 21, 22 is formed in a tapered shape, the bulging portion is opposed to the side wall of the connection formation 21, 22 in the thickness direction of the chip 2.

[0223] The second impurity region 52 is formed by introducing a p-type impurity into the interior of the chip 2 via the bottom wall portion of the connection trench 23. In a case of the connection trench 23 having a flat bottom wall, the p-type impurity can be appropriately introduced into the interior of the chip 2. Thus, the second impurity region 52 is appropriately formed in the region along the lower end portion of the connection formation 21, 22.

[0224] The semiconductor device 1A includes, in the interior of the chip 2, a plurality of third impurity regions 53 of p-type formed in the region along the lower end portion of the plurality of isolation formations 31, 32. The third impurity region 53 has a p-type impurity concentration higher than the p-type impurity concentration of the base layer 8. The p-type impurity concentration of the third impurity region 53 is preferably approximately equal to the p-type impurity concentration of the first impurity region 51. The p-type impurity concentration of the third impurity region 53 can be 1 x 1018cm-3or more. 16 cm -3 The p-type impurity concentration of the third impurity region 53 can be 1 x 1018cm-3or more. 19 cm -3 The p-type impurity concentration of the third impurity region 53 can be 1 x 1018cm-3or more.

[0225] The plurality of third impurity regions 53 are formed in one-to-one correspondence with the lower ends of the corresponding isolation structures 31, 32, respectively. The plurality of third impurity regions 53 have portions covering the bottom walls and portions covering the side walls at the lower ends of the corresponding isolation structures 31, 32. The plurality of third impurity regions 53 extend in a strip shape along the corresponding isolation structures 31, 32 in the second direction Y in plan view, and are connected to the first impurity regions 51 at both ends of the corresponding isolation structures 31, 32.

[0226] The plurality of third impurity regions 53 are opposed to the isolation electrodes 35 through the isolation insulating films 34 at the lower ends of the corresponding isolation structures 31, 32. The plurality of third impurity regions 53 are electrically connected to the drift layer 9 on the first main surface 3 side and electrically connected to the base layer 8 on the second main surface 4 side. In this way, the plurality of third impurity regions 53 have portions that replace the conduction type of the drift layer 9 from n-type to p-type on the first main surface 3 side.

[0227] In a case where the bottom walls of the plurality of isolation structures 31, 32 are located inside the base layer 8, the plurality of third impurity regions 53 can also be formed apart from the bottom of the drift layer 9 on the second main surface 4 side. In this case, the plurality of third impurity regions 53 can also be opposed to the drift layer 9 through a portion of the base layer 8.

[0228] In this way, the plurality of isolation structures 31, 32 are formed to substantially the same depth as the plurality of gate structures 12, and the plurality of third impurity regions 53 are formed to substantially the same depth as the plurality of first impurity regions 51. Of course, it is also possible that the plurality of isolation structures 31, 32 are formed deeper than the plurality of gate structures 12, and the plurality of third impurity regions 53 are formed deeper than the plurality of first impurity regions 51.

[0229] The plurality of third impurity regions 53 are each formed wider than the corresponding isolation structures 31, 32. Specifically, the plurality of third impurity regions 53 each include a bulging portion that protrudes in an arc shape (circular arc shape) from a region below the isolation structure 31, 32 in a horizontal direction (both sides) in cross section, similarly to the plurality of first impurity regions 51. In a case where the isolation structures 31, 32 are formed in a tapered shape, the bulging portion is opposed to the side wall of the isolation structure 31, 32 in the thickness direction of the chip 2.

[0230] The third impurity region 53 is formed by introducing p-type impurities into the inside of the chip 2 through the bottom wall portion of the isolation trench 33. In a case of the isolation trench 33 having a flat bottom wall, the p-type impurities can be appropriately introduced into the inside of the chip 2. Thus, the third impurity region 53 is appropriately formed in a region along the lower end of the isolation structure 31, 32.

[0231] The semiconductor device 1A includes a plurality of fourth impurity regions 54 of p type formed in the inner portion of the chip 2 at regions along the lower end portions of the plurality of field structures 42, respectively. The fourth impurity regions 54 have a p type impurity concentration higher than the p type impurity concentration of the base layer 8. It is preferable that the p type impurity concentration of the fourth impurity regions 54 be approximately equal to the p type impurity concentration of the first impurity regions 51. The p type impurity concentration of the fourth impurity regions 54 can be 1 x 1018cm-3or more. 16 cm -3 -3or more. 19 cm -3 -3or more.

[0232] The plurality of fourth impurity regions 54 are formed in a one-to-one corresponding relationship with respect to the lower end portions of the corresponding field structures 42 at intervals from the first impurity regions 51, the second impurity regions 52, and the third impurity regions 53, respectively. The plurality of fourth impurity regions 54 have portions covering the bottom walls and portions covering the side walls at the lower end portions of the corresponding field structures 42. The plurality of fourth impurity regions 54 extend in a band shape along the corresponding field structures 42 in plan view. Specifically, the plurality of fourth impurity regions 54 extend in a ring shape along the corresponding field structures 42 in plan view.

[0233] The plurality of fourth impurity regions 54 are opposed to the field electrodes 45 across the field insulating films 44 at the lower end portions of the corresponding field structures 42. The plurality of fourth impurity regions 54 are electrically connected to the drift layer 9 on the first main surface 3 side and electrically connected to the base layer 8 on the second main surface 4 side. In this manner, the plurality of fourth impurity regions 54 have portions that replace the conduction type of the drift layer 9 from n type to p type on the first main surface 3 side.

[0234] In a case where the bottom walls of the plurality of field structures 42 are located inside the base layer 8, the plurality of fourth impurity regions 54 can also be formed at intervals from the bottom portion of the drift layer 9 on the second main surface 4 side. In this case, the plurality of fourth impurity regions 54 can also be opposed to the drift layer 9 across a portion of the base layer 8.

[0235] In this manner, the plurality of field structures 42 are formed deeper than the plurality of gate structures 12, and the plurality of fourth impurity regions 54 are formed deeper than the plurality of first impurity regions 51. That is, the bottom portions of the plurality of fourth impurity regions 54 are located on the second main surface 4 side with respect to the bottom portions of the plurality of first impurity regions 51. Of course, it is also possible that the plurality of field structures 42 are formed to approximately the same depth as the plurality of gate structures 12, and the plurality of fourth impurity regions 54 are formed to approximately the same depth as the plurality of first impurity regions 51.

[0236] The plurality of fourth impurity regions 54 are each formed wider than the corresponding field configuration 42. Specifically, the plurality of fourth impurity regions 54 each contain, in a cross section, a bulging portion protruding in an arc shape (circular arc shape) from a region below the field configuration 42 toward the horizontal direction (both sides), similarly to the plurality of first impurity regions 51. In a case where the field configuration 42 is formed in a tapered shape, the bulging portion is opposed to the side wall of the field configuration 42 in the thickness direction of the chip 2.

[0237] With respect to the plurality of fourth impurity regions 54 adjacent to each other, the bulging portion of one fourth impurity region 54 is connected to the bulging portion of another fourth impurity region 54. Thereby, the plurality of fourth impurity regions 54 isolate the base layer 8 and the drift layer 9 in the up-and-down direction in the outer side region 7.

[0238] The fourth impurity region 54 is formed by introducing a p-type impurity into the inside of the chip 2 through the bottom wall portion of the field trench 43. In a case where the field trench 43 has a flat bottom wall, the p-type impurity can be appropriately introduced into the inside of the chip 2. Therefore, the fourth impurity region 54 is appropriately formed in a region along the lower end portion of the field configuration 42.

[0239] The semiconductor device 1A includes one or a plurality (one in this mode) of trench electrode type base configurations 55 formed in the outer side region 7 in the first main face 3. The base configuration 55 can also be referred to as a "trench base configuration". The base configuration 55 is given a base potential. The base configuration 55 includes a plurality of first base configurations 55a and at least one (one in this mode) second base configuration 55b.

[0240] The plurality of first base configurations 55a are each disposed in the plurality of boundary regions 7a. The plurality of first base configurations 55a each extend in a band shape in the second direction Y in the corresponding boundary region 7a. The plurality of first base configurations 55a each have a first end portion on one side of the second direction Y and a second end portion on the other side of the second direction Y. Of course, the plurality of first base configurations 55a can each be arranged in the corresponding one boundary region 7a in the second direction Y at intervals.

[0241] Each first base configuration 55a is disposed at an inner side from the plurality of gate configurations 12 adjacent in the first direction X, and is opposed to the plurality of gate configurations 12 on both sides in the first direction X. That is, each first base configuration 55a is disposed in a region between the plurality of first connection configurations 21 and the plurality of second connection configurations 22 in the corresponding boundary region 7a, and is opposed to the plurality of connection configurations 21, 22 on both sides in the first direction X. Thereby, the plurality of first base configurations 55a isolate the plurality of active regions 6 (the plurality of gate configurations 12) on both sides in the first direction X.

[0242] The second base structure 55b is arranged in the outer peripheral region 7b. The second base structure 55b is arranged in a region between the plurality of active regions 6 (the plurality of gate structures 12) and the innermost field structure 42, extending in a band shape along the plurality of active regions 6. In this way, the second base structure 55b has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in plan view, dividing the plurality of active regions 6 from a plurality of directions.

[0243] In this way, the second base structure 55b collectively surrounds the plurality of active regions 6 (the plurality of gate structures 12) in plan view, formed in a polygonal ring shape (in this way, a quadrilateral ring shape) having four sides parallel to the periphery of the chip 2. The second base structure 55b opposes the plurality of active regions 6 (the plurality of gate structures 12) in the first direction X and the second direction Y. Of course, a plurality of second base structures 55b can also be arranged in a manner surrounding the plurality of active regions 6 (the plurality of gate structures 12) at intervals in the first direction X and the second direction Y along the plurality of active regions 6.

[0244] The second base structure 55b is formed at an interval from the first end portion of the plurality of first base structures 55a on one side in the second direction Y on the periphery side (the innermost field structure 42 side) of the chip 2. That is, the first end portion of the plurality of first base structures 55a is formed as an open end.

[0245] The second base structure 55b is connected to the second end portion of the plurality of first base structures 55a on the other side in the second direction Y. That is, the second base structure 55b connects the plurality of first base structures 55a in a comb shape toward the plurality of boundary regions 7a. In addition, the second base structure 55b is formed as an extraction portion extracted from the plurality of first base structures 55a to the outer peripheral region 7b.

[0246] The base structure 55 is located within the drift layer 9 in cross section. Specifically, the base structure 55 is formed at an interval from the depth position of the bottom of the drift layer 9 on the first main surface 3 side, having a side wall and a bottom wall located within the drift layer 9. The base structure 55 can also be formed in a tapered shape in which the opening width narrows toward the bottom wall in cross section. The bottom wall of the base structure 55 can also have a flat portion extending substantially parallel to the first main surface 3. Of course, the bottom wall of the base structure 55 can also be curved in a circular arc shape toward the second main surface 4.

[0247] The width of the base structure 55 is preferably smaller than the width of the field structure 42. The width of the base structure 55 can also be larger than the width of the field structure 42. The width of the base structure 55 can also be substantially equal to the width of the field structure 42. In this way, the width of the base structure 55 is smaller than the width of the gate structure 12. The width of the base structure 55 can also be larger than the width of the gate structure 12. The width of the base structure 55 can also be substantially equal to the width of the gate structure 12.

[0248] The width of the base structure 55 can also be 0.1 μm or more and 5 μm or less. The width of the base structure 55 can also have a value belonging to at least one range of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0249] The depth of the base structure 55 is smaller than the depth of the field structure 42. In this way, the depth of the base structure 55 is smaller than the depth of the gate structure 12. The base structure 55 is preferably formed apart from the depth position of the electrode face of the buried portion 15a of the gate structure 12 on the first main face 3 side by an interval. The base structure 55 is preferably formed apart from the depth position of the intermediate portion of the gate structure 12 on the first main face 3 side by an interval. That is, the bottom wall of the base structure 55 is preferably formed at a depth position opposite to the buried insulator 16 in the horizontal direction.

[0250] The depth of the base structure 55 can also be 0.1 μm or more and 10 μm or less. The depth of the base structure 55 can also have a value belonging to at least one range of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less.

[0251] The base structure 55 includes a base trench 56 and a base electrode 57. The base trench 56 is excavated from the first main face 3 toward the second main face 4, dividing the side wall and the bottom wall of the base structure 55. The base electrode 57 is buried in the base trench 56, electrically connected to the chip 2 inside the base trench 56.

[0252] In this way, the base electrode 57 includes a first electrode 58 and a second electrode 59. The first electrode 58 covers the wall face of the base trench 56 in a film shape. The first electrode 58 can also have a single layer structure composed of a Ti film or a Ti alloy film. The first electrode 58 can also have a laminated structure sequentially laminating a layer containing a Ti film and a Ti alloy film from the chip 2 side. The Ti alloy film can also be a TiN film.

[0253] The second electrode 59 is embedded in the base trench 56 via the first electrode 58 and is electrically connected to the chip 2 via the first electrode 58. The second electrode 59 can include at least one of W, Al, an Al alloy, Cu, and a Cu alloy. The Al alloy can include at least one of an AlSi alloy, an AlCu alloy, and an AlSiCu alloy.

[0254] The semiconductor device 1A includes a silicide layer 60 formed in a region inside the chip 2 along the base structure 55. The silicide layer 60 is formed in a region along each of the plurality of first base structures 55a and a region along the second base structure 55b inside the chip 2. The silicide layer 60 is formed in a film shape along the wall surfaces (side walls and a bottom wall) of the base structure 55, and is mechanically and electrically connected to the base electrode 57.

[0255] The silicide layer 60 is formed in the inner side at intervals from the plurality of gate structures 12 (the plurality of connection structures 21, 22) adjacent in the first direction X in the plurality of boundary regions 7a. The silicide layer 60 is formed at intervals from the plurality of gate structures 12 (the plurality of connection structures 21, 22) and the innermost field structure 42 in the outer peripheral region 7b.

[0256] The silicide layer 60 can also include at least one of a Ti silicide layer, a Ni silicide layer, a Co silicide layer, a Mo silicide layer, and a W silicide layer. In this way, the silicide layer 60 includes a Ti silicide layer.

[0257] The thickness of the silicide layer 60 can be 1 nm or more and 500 nm or less. The thickness of the silicide layer 60 can have a value in at least one range of 1 nm or more and 50 nm or less, 50 nm or more and 100 nm or less, 100 nm or more and 200 nm or less, 200 nm or more and 300 nm or less, 300 nm or more and 400 nm or less, and 400 nm or more and 500 nm or less.

[0258] The semiconductor device 1A includes a contact region 61 of p type formed in a region below the base structure 55 inside the chip 2. In this way, the contact region 61 is formed by introducing a p type impurity into the drift layer 9. The contact region 61 has a p type impurity concentration higher than an n type impurity concentration of the drift layer 9, and changes the conduction type of the drift layer 9 from n type to p type.

[0259] The p type impurity concentration of the contact region 61 is higher than the p type impurity concentration of the base layer 8. Of course, the contact region 61 can also be formed by introducing a p type impurity into the base layer 8. The p type impurity concentration of the contact region 61 can be 1 x 1019 cm-3 or more and 1 x 1021 cm-3 or less. 16 cm -3 and 1 x 1021 cm-3 or less. 21 cm -3 The following.

[0260] The contact region 61 extends in a band shape along the base structure 55. Specifically, the contact region 61 is formed in a region below the plurality of first base structures 55a and a region below the second base structure 55b in the chip 2, respectively. The contact region 61 extends in a band shape along the corresponding first base structure 55a in the second direction Y in each boundary region 7a.

[0261] The contact region 61 extends in a band shape along the second base structure 55b in the outer peripheral region 7b. The contact region 61 has a portion extending in a band shape in the first direction X along the second base structure 55b and a portion extending in a band shape in the second direction Y. In this way, the contact region 61 is formed as a polygonal ring (in this case, a quadrilateral ring) extending along the base structure 55.

[0262] The contact region 61 protrudes in the horizontal direction from the region directly below the base structure 55, and is connected to the plurality of gate structures 12, the plurality of connection structures 21, 22, and the innermost field structure 42. The contact region 61 extends in the thickness direction of the chip 2 in the thickness range between the base layer 8 and the base structure 55, and reaches the base layer 8 through the bottom of the drift layer 9.

[0263] The contact region 61 has a lower end portion connected to the base layer 8 and an upper end portion connected to the base structure 55, and electrically connects the base structure 55 and the base layer 8. In this way, the lower end portion of the contact region 61 is formed at the first main surface 3 side at intervals from the depth position of the bottom of the first impurity region 51 and the fourth impurity region 54.

[0264] Of course, the lower end portion of the contact region 61 can also be located below (on the second main surface 4 side) compared to the depth position of the bottom of the first impurity region 51 and the fourth impurity region 54. The lower end portion of the contact region 61 can also be curved in an arc shape (circular arc shape) toward the second main surface 4.

[0265] The lower end portion of the contact region 61 can also be connected to the first impurity region 51 at a portion along the gate structure 12. The lower end portion of the contact region 61 can also be connected to the second impurity region 52 at a portion along the connection structure 21, 22. The lower end portion of the contact region 61 can also be connected to the innermost fourth impurity region 54 at a portion along the innermost field structure 42.

[0266] For example, in the boundary region 7a, the lower end portion of the contact region 61 can also be connected to the plurality of first impurity regions 51 at a portion along the plurality of gate structures 12 adjacent in the first direction X. For example, in the boundary region 7a, the lower end portion of the contact region 61 can also be connected to the plurality of second impurity regions 52 at a portion along the first connection structure 21 and the second connection structure 22 adjacent in the first direction X.

[0267] For example, in the outer peripheral region 7b, the lower end portion of the contact region 61 can also be connected with the first impurity region 51 and the fourth impurity region 54 along a portion of the gate structure 12 and the innermost field structure 42. For example, in the outer peripheral region 7b, the lower end portion of the contact region 61 can also be connected with the second impurity region 52 and the fourth impurity region 54 along a portion of the connection structure 21, 22 and the innermost field structure 42.

[0268] The upper end portion of the contact region 61 is formed apart from the first main face 3 on the bottom wall side of the base structure 55, has a portion along the side wall and the bottom wall of the base structure 55. The upper end portion of the contact region 61 is electrically connected with the side wall and the bottom wall of the base structure 55 via the silicide layer 60. The upper end portion of the contact region 61 can also be curved in an arc shape (circular arc shape) toward the first main face 3. That is, the upper end portion of the contact region 61 can also be formed in a manner that gradually separates from the first main face 3 as it moves away from the base structure 55.

[0269] The semiconductor device 1A includes a surface layer region 62 of n-type formed around the base structure 55 in the surface layer portion of the first main face 3. The surface layer region 62 has a higher n-type impurity concentration than the n-type impurity concentration of the drift layer 9. The n-type impurity concentration of the surface layer region 62 can also be higher than the n-type impurity concentration of the drain source region 28, 29. The n-type impurity concentration of the surface layer region 62 can be lower than the n-type impurity concentration of the drain source region 28, 29. The n-type impurity concentration of the surface layer region 62 can be 1 x 1018cm-3or more, and 1 x 1020cm-3or less. 15 cm -3 The n-type impurity concentration of the surface layer region 62 can be 1 x 1018cm-3or more, and 1 x 1020cm-3or less. 20 cm -3 The n-type impurity concentration of the surface layer region 62 can be 1 x 1018cm-3or more, and 1 x 1020cm-3or less.

[0270] The surface layer region 62 extends in a band shape along the base structure 55. Specifically, in this mode, the surface layer region 62 is formed in the surface layer portion of the first main face 3 in regions along the plurality of first base structures 55a and in regions along the second base structure 55b. The surface layer region 62 extends in a band shape in the second direction Y along the corresponding first base structure 55a in each boundary region 7a.

[0271] The surface layer region 62 extends in a band shape along the second base structure 55b in the outer peripheral region 7b. The surface layer region 62 has a portion extending in a band shape in the first direction X along the second base structure 55b and a portion extending in a band shape in the second direction Y. In this mode, the surface layer region 62 is formed in a multi-sided ring shape (in this mode, a four-sided ring shape) extending along the second base structure 55b.

[0272] The surface layer region 62 is formed in a thickness range between the first main face 3 and the contact region 61. The surface layer region 62 is electrically connected to the base structure 55 via the silicide layer 60 at the upper end portion, and is electrically connected to the contact region 61 at the lower end portion. In this way, the surface layer region 62 has a bottom portion that is curved in an arc shape toward the first main face 3.

[0273] That is, the surface layer region 62 is formed in a manner that gradually deepens as it moves away from the base structure 55, has a shallow portion formed in the vicinity of the base structure 55, and a deep portion formed away from the base structure 55. The shallow portion of the surface layer region 62 is formed apart from the bottom wall of the base structure 55 on the first main face 3 side, and is electrically connected to the side wall of the base structure 55 via the silicide layer 60.

[0274] The deep portion of the surface layer region 62 is located in a region on the second main face 4 side with respect to the depth position of the bottom wall of the base structure 55. The deep portion of the surface layer region 62 is located in a region on the first main face 3 side with respect to the depth position of the bottom wall of the plurality of gate structures 12 and the bottom wall of the plurality of field structures 42. It is preferable that the deep portion of the surface layer region 62 be located in a region on the first main face 3 side with respect to the depth position of the electrode face of the buried electrode 15.

[0275] It is particularly preferable that the deep portion of the surface layer region 62 be located in a region on the first main face 3 side with respect to the depth position of the intermediate portion of the gate structure 12. The deep portion of the surface layer region 62 is connected to the plurality of gate structures 12, the plurality of connection structures 21, 22, and the innermost field structure 42. Of course, the surface layer region 62 can also have a substantially constant depth.

[0276] The surface layer region 62 can also have a concentration gradient in which the n-type impurity concentration gradually decreases in the thickness direction. That is, the n-type impurity concentration of the surface layer region 62 can also gradually decrease from the shallow portion to the deep portion. In this case, the n-type impurity concentration of the deep portion is smaller than the n-type impurity concentration of the shallow portion. The n-type impurity concentration of the shallow portion can also be substantially equal to the n-type impurity concentration of the plurality of drain source regions 28, 29.

[0277] Referring to Figures 7-10 , the semiconductor device 1A includes an insulating interlayer film 70 that covers the first main face 3. The interlayer film 70 can also be referred to as an "interlayer insulating film", an "intermediate film", an "intermediate insulating film", or the like. The interlayer film 70 has a laminated structure that includes a first interlayer film 71 and a second interlayer film 72 that are sequentially laminated from the chip 2 (first main face 3) side.

[0278] The first interlayer film 71 is an insulating film in which wiring is arranged, and has a single layer structure in which a single insulating film is formed, or a laminated structure in which a plurality of insulating films are included. The first interlayer film 71 can include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first interlayer film 71 covers the plurality of active regions 6 and the outer side region 7 together in a film shape (layer shape) on the first main face 3.

[0279] That is, the first interlayer film 71 covers the plurality of gate structures 12, the plurality of connection structures 21, 22, the plurality of isolation structures 31, 32, the plurality of drain source regions 28, 29, the plurality of field structures 42, and the like all together. The first interlayer film 71 can also cover the outer side insulating films 10, 11 on the periphery side of the first main surface 3. The first interlayer film 71 can also cover the first main surface 3 from the outer side insulating films 10, 11 inwardly with a space therebetween, leaving the outer side insulating films 10, 11 exposed.

[0280] The second interlayer film 72 is an insulating film for configuring a wiring on an upper side than the first interlayer film 71, and has a single layer structure composed of a single insulating film or a stacked layer structure including a plurality of insulating films. The second interlayer film 72 can include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second interlayer film 72 covers the first interlayer film 71 in a film shape (layer shape).

[0281] Referring to Figure 14 and Figure 15 The semiconductor device 1A includes a multilayer wiring structure 73 configured on the chip 2 (the first main surface 3). The multilayer wiring structure 73 is formed using the interlayer film 70. Specifically, the multilayer wiring structure 73 includes a first layer wiring 74 configured on a lower layer side of the interlayer film 70 and a second layer wiring 75 configured on an upper layer side of the interlayer film 70. The first layer wiring 74 is configured on the first interlayer film 71 and is covered by the second interlayer film 72. The second layer wiring 75 is configured on the second interlayer film 72 and is stereoscopically crossed with the first layer wiring 74.

[0282] In this mode, the multilayer wiring structure 73 is composed of a 2-layer structure including the first layer wiring 74 and the second layer wiring 75. That is, the first layer wiring 74 is formed as a lowermost layer wiring of the multilayer wiring structure 73, and the second layer wiring 75 is formed as an uppermost layer wiring of the multilayer wiring structure 73. The second layer wiring 75 is exposed from the interlayer film 70.

[0283] The multilayer wiring structure 73 can include the first layer wiring 74 and the second layer wiring 75 which are opposed in the up-down direction with a portion (the second interlayer film 72) of the interlayer film 70 therebetween, and the number of layers of the multilayer wiring structure 73 is not limited to two layers. That is, the multilayer wiring structure 73 can have a stacked structure of three or more layers. For example, in a case where the interlayer film 70 has one or more lower interlayer films on a lower layer than the first interlayer film 71, the multilayer wiring structure 73 can include one or more lower layer wirings configured on a lower layer than the first layer wiring 74.

[0284] The first layer wiring 74 has a stacked structure including a first electrode 76 and a second electrode 77 stacked in this order from the first interlayer film 71 side. The first electrode 76 covers the first interlayer film 71 in a film shape. The first electrode 76 can include either or both of a Ti film and a Ti alloy film. The Ti alloy film can also be a TiN film.

[0285] The second electrode 77 covers the first electrode 76 in a film shape. The second electrode 77 can include at least one of a W film, an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film can also include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0286] The second layer wiring 75 has a stacked structure including a first electrode 78 and a second electrode 79 stacked in this order from the second interlayer film 72 side. The first electrode 78 covers the second interlayer film 72 in a film shape. The first electrode 78 can include either or both of a Ti film and a Ti alloy film. The Ti alloy film can also be a TiN film.

[0287] The second electrode 79 covers the first electrode 78 in a film shape. The second electrode 79 can include at least one of a W film, an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film can also include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0288] Referring to Figure 14 The first layer wiring 74 includes a plurality of wiring groups 80. The plurality of wiring groups 80 are respectively arranged on the plurality of active regions 6 at intervals in the first direction X. The plurality of wiring groups 80 are arranged in a one-to-one correspondence with respect to the first to sixth active regions 6A to 6F, and are arranged in the first to sixth wiring groups 80A to 80F in this order from the third side surface 5C side.

[0289] The first wiring group 80A is arranged on the first active region 6A. The second wiring group 80B is arranged on the second active region 6B at an interval in the first direction X from the first wiring group 80A, and is opposite the first wiring group 80A in the first direction X. The third wiring group 80C is arranged on the third active region 6C at an interval in the first direction X from the second wiring group 80B, and is opposite the second wiring group 80B in the first direction X.

[0290] The fourth wiring group 80D is arranged on the fourth active region 6D at intervals in the first direction X from the third wiring group 80C opposite to the third wiring group 80C in the first direction X. The fifth wiring group 80E is arranged on the fifth active region 6E at intervals in the first direction X from the fourth wiring group 80D opposite to the fourth wiring group 80D in the first direction X. The sixth wiring group 80F is arranged on the sixth active region 6F at intervals in the first direction X from the fifth wiring group 80E opposite to the fifth wiring group 80E in the first direction X.

[0291] The plurality of wiring groups 80 respectively include a plurality of first lower wiring lines 81 and a plurality of second lower wiring lines 82. The first lower wiring lines 81 transmit the first drain-source potential to the first drain-source regions 28. The second lower wiring lines 82 transmit the second drain-source potential to the second drain-source regions 29. The first lower wiring lines 81 can also be referred to as "first drain-source wiring lines". The second lower wiring lines 82 can also be referred to as "second drain-source wiring lines".

[0292] The plurality of first lower wiring lines 81 respectively extend in a strip shape in the first direction X on the corresponding active regions 6 arranged at intervals in the second direction Y. That is, the plurality of first lower wiring lines 81 are arranged in a strip shape extending in the first direction X. The plurality of first lower wiring lines 81 are respectively arranged on the plurality of first drain-source regions 28 (the plurality of first mesa portions 26) in a one-to-one corresponding relationship in the stacking direction. The plurality of first lower wiring lines 81 are respectively electrically connected to the corresponding first drain-source regions 28.

[0293] With respect to the plurality of wiring groups 80, the plurality of first lower wiring lines 81 are opposite to each other in the first direction X. That is, with respect to one and the other wiring group 80, the plurality of first lower wiring lines 81 belonging to the other wiring group 80 are opposite to the plurality of first lower wiring lines 81 belonging to the one wiring group 80 in a one-to-one corresponding relationship.

[0294] Hereinafter, the layout of one first lower wiring line 81 will be described. The first lower wiring line 81 preferably has both end portions located inward of both end portions (the first end portion and the second end portion) of the corresponding gate structure 12 (the inward side of the corresponding active region 6) in the first direction X. The both end portions of the first lower wiring line 81 are preferably located inward of the plurality of connection structures 21, 22.

[0295] The both end portions of the first lower wiring 81 can also be located in regions between the corresponding connection structures 21, 22 and the isolation structures 31, 32, opposite to the floating regions 37 in the stacking direction. The both end portions of the first lower wiring 81 can also be located above the corresponding isolation structures 31, 32. The both end portions of the first lower wiring 81 can also be located inward of the corresponding isolation structures 31, 32, and above the corresponding first drain source regions 28 (first mesa portions 26).

[0296] The first lower wiring 81 can also have a width larger than a width of the corresponding first mesa portion 26 with respect to the second direction Y, respectively. That is, the first lower wiring 81 can also overlap with a plurality of (in this mode, 2) gate structures 12 located directly below. In this case, it is preferable that the first lower wiring 81 has a width smaller than a width of the corresponding first gate unit GU1. Of course, the first lower wiring 81 can also have a width smaller than the width of the first mesa portion 26. Of course, the first lower wiring 81 can also have a width larger than the width of the first gate unit GU1.

[0297] The width of the first lower wiring 81 can also be 0.1 μm or more and 15 μm or less. The width of the first lower wiring 81 can have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, 9 μm or more and 10 μm or less, 10 μm or more and 11 μm or less, 11 μm or more and 12 μm or less, 12 μm or more and 13 μm or less, 13 μm or more and 14 μm or less, and 14 μm or more and 15 μm or less.

[0298] The plurality of second lower wirings 82 are respectively arranged in regions between the plurality of first lower wirings 81 in the second direction Y on the corresponding active regions 6, spaced apart. The plurality of second lower wirings 82 respectively extend in a strip shape in the first direction X, and are arranged in the second direction Y, spaced apart. That is, the plurality of second lower wirings 82 are arranged in a strip shape extending in the first direction X. The plurality of second lower wirings 82 are respectively mixed in regions between the plurality of first lower wirings 81. Specifically, the plurality of second lower wirings 82 are arranged alternately with the plurality of first lower wirings 81 in the second direction Y.

[0299] The plurality of second lower wirings 82 are respectively arranged on the plurality of second drain-source regions 29 (the plurality of second mesa portions 27) so as to face the plurality of second drain-source regions 29 (the plurality of second mesa portions 27) in one-to-one correspondence in the stacking direction. The plurality of second lower wirings 82 are respectively electrically connected to the corresponding second drain-source regions 29.

[0300] With respect to the plurality of wiring groups 80, the plurality of second lower wirings 82 face each other in the first direction X. That is, with respect to one and the other wiring groups 80, the plurality of second lower wirings 82 belonging to the other wiring group 80 face the plurality of second lower wirings 82 belonging to the one wiring group 80 in one-to-one correspondence. The plurality of second lower wirings 82 can also be arranged so as to be spaced apart from the plurality of first lower wirings 81 by a wiring interval of 0.1 μm or more and 15 μm or less with respect to the second direction Y, respectively.

[0301] The wiring interval can have a value in at least one range of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, 9 μm or more and 10 μm or less, 10 μm or more and 11 μm or less, 11 μm or more and 12 μm or less, 12 μm or more and 13 μm or less, 13 μm or more and 14 μm or less, and 14 μm or more and 15 μm or less.

[0302] Hereinafter, the layout of one second lower wiring 82 will be described. The second lower wiring 82 preferably has both end portions located inward of both end portions (first end portion and second end portion) of the corresponding gate structure 12 (inner side of the corresponding active region 6) with respect to the first direction X. The both end portions of the second lower wiring 82 are preferably located at positions inward of the corresponding connection structures 21, 22.

[0303] The both end portions of the second lower wiring 82 can also be located in regions between the corresponding connection structures 21, 22 and the corresponding isolation structures 31, 32, facing the floating region 37 in the stacking direction. The both end portions of the second lower wiring 82 can also be located on the corresponding isolation structures 31, 32. The both end portions of the second lower wiring 82 can also be located inward of the corresponding isolation structures 31, 32 and on the corresponding second drain-source region 29 (second mesa portion 27).

[0304] The second lower wiring 82 can also have a width larger than the width of the corresponding second mesa portion 27 with respect to the second direction Y. That is, the second lower wiring 82 can also overlap with a plurality of (in this mode, 2) gate structures 12 located directly below. In this case, it is preferable that the second lower wiring 82 have a width smaller than the width of the corresponding second gate unit GU2. Of course, the second lower wiring 82 can also have a width smaller than the width of the second mesa portion 27. Of course, the second lower wiring 82 can also have a width larger than the width of the second gate unit GU2.

[0305] The width of the second lower wiring 82 can also be 0.1 μm or more and 15 μm or less. The width of the second lower wiring 82 can have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, 9 μm or more and 10 μm or less, 10 μm or more and 11 μm or less, 11 μm or more and 12 μm or less, 12 μm or more and 13 μm or less, 13 μm or more and 14 μm or less, and 14 μm or more and 15 μm or less.

[0306] The second lower wiring 82 preferably has a length approximately equal to the length of the first lower wiring 81 with respect to the first direction X. According to this structure, it is possible to suppress variations in wiring resistance between the first lower wiring 81 and the second lower wiring 82. The second lower wiring 82 preferably has a width approximately equal to the width of the first lower wiring 81 with respect to the second direction Y. According to this structure, it is possible to suppress variations in wiring resistance between the first lower wiring 81 and the second lower wiring 82.

[0307] Thus, in each wiring group 80, the first drain-source potential is imparted to the plurality of first drain-source regions 28 via the plurality of first lower wirings 81, and the second drain-source potential is imparted to the second drain-source region 29 via the plurality of second lower wirings 82. That is, the first drain-source potential and the second drain-source potential are alternately imparted in the second direction Y in correspondence with the layout of the plurality of first lower wirings 81 and the plurality of second lower wirings 82. Therefore, the drain-source current Ids is correspondingly alternately input and output in the second direction Y.

[0308] The semiconductor device 1A (the first layer wiring 74) includes a plurality of inter-wiring regions IWR partitioned in regions between the plurality of wiring groups 80. The plurality of inter-wiring regions IWR are respectively partitioned in regions between the end portion of one of the wiring groups 80 and the end portion of the other of the wiring groups 80. The end portion of each of the wiring groups 80 is formed by the end portion of the plurality of first lower wirings 81 and the end portion of the plurality of second lower wirings 82. The inter-wiring regions IWR do not have the first lower wirings 81 and the second lower wirings 82.

[0309] The plurality of inter-wiring regions IWR are respectively partitioned in a strip shape extending in the second direction Y so as to expose the first interlayer film 71. The plurality of inter-wiring regions IWR correspond to the plurality of boundary regions 7a in a one-to-one relationship in the stacking direction and extend in a strip shape along the corresponding boundary regions 7a. Each of the inter-wiring regions IWR preferably exposes the first end portions (the plurality of first connection formations 21) of the plurality of gate formations 12 and the second end portions (the plurality of second connection formations 22) of the plurality of gate formations 12 adjacent in the first direction X in plan view.

[0310] The semiconductor device 1A (the first layer wiring 74) includes one or more (one in this mode) third lower wirings 83 and one or more (one in this mode) fourth lower wirings 84. The third lower wirings 83 transmit gate potentials to the gate formations 12. The fourth lower wirings 84 transmit base potentials to the base formations 55. The third lower wirings 83 can also be referred to as "gate wirings". The fourth lower wirings 84 can also be referred to as "base wirings".

[0311] The third lower wirings 83 are arranged on the outer region 7 at intervals from the plurality of wiring groups 80. The third lower wirings 83 are led around the inside and outside of the plurality of inter-wiring regions IWR. Specifically, the third lower wirings 83 include a plurality of first gate wirings 85, a plurality of second gate wirings 86, and at least one (one in this mode) third gate wiring 87.

[0312] The plurality of first gate wirings 85 are respectively arranged on one side in the first direction X with respect to the plurality of active regions 6. The plurality of first gate wirings 85 extend in a strip shape in the second direction Y so as to cross (orthogonally in this mode) the first end portions of the plurality of gate formations 12 and electrically connect to the first end portions of the plurality of gate formations 12.

[0313] That is, the first gate wirings 85 for the first active region 6A extend in a strip shape in the second direction Y in the outer peripheral region 7b so as to cross the first end portions of the plurality of gate formations 12. The first gate wirings 85 for the first active region 6A oppose the plurality of wiring groups 80 (both the plurality of first lower wirings 81 and the plurality of second lower wirings 82) in the first direction X.

[0314] The plurality of first gate lines 85 for the second to sixth active regions 6B to 6F extend in the second direction Y in the corresponding boundary regions 7a (inter-wiring regions IWR) in a strip shape, respectively, crossing (in this embodiment, orthogonally) the first end portions of the plurality of gate structures 12. The first gate lines 85 for the second to sixth active regions 6B to 6F are opposed to the plurality of wiring groups 80 (both the plurality of first lower lines 81 and the plurality of second lower lines 82) on both sides in the first direction X.

[0315] In this embodiment, the plurality of first gate lines 85 extend in a strip shape along the plurality of first connection structures 21, covering the plurality of first connection structures 21. The plurality of first gate lines 85 are electrically connected to the plurality of first connection structures 21, and apply a gate potential to the plurality of gate structures 12 via the plurality of first connection structures 21. The plurality of first gate lines 85 have first end portions on one side in the second direction Y and second end portions on the other side in the second direction Y.

[0316] In this embodiment, the plurality of first gate lines 85 are provided only in the corresponding inter-wiring regions IWR, and do not have portions located in the wiring groups 80 (regions between the first lower lines 81 and the second lower lines 82). That is, the plurality of first gate lines 85 do not have portions that cross the adjacent wiring groups 80 in the first direction X. In this embodiment, the plurality of first gate lines 85 do not have portions that extend in the first direction X in the inter-wiring regions IWR. Of course, the plurality of first gate lines 85 can have portions that meander toward one side and the other side in the first direction X in the inter-wiring regions IWR.

[0317] The plurality of second gate lines 86 are provided on the other side in the first direction X with respect to the plurality of active regions 6, and are opposed to the plurality of first gate lines 85 across the active regions 6 corresponding to the first direction X. The plurality of second gate lines 86 extend in the second direction Y in a strip shape crossing (in this embodiment, orthogonally) the second end portions of the plurality of gate structures 12, and are electrically connected to the second end portions of the plurality of gate structures 12.

[0318] That is, the second gate lines 86 for the first to fifth active regions 6B to 6E extend in the second direction Y in the corresponding boundary regions 7a (inter-wiring regions IWR) in a strip shape, respectively, crossing the second end portions of the plurality of gate structures 12. The second gate lines 86 for the first to fifth active regions 6B to 6E are opposed to the plurality of wiring groups 80 (both the plurality of first lower lines 81 and the plurality of second lower lines 82) on both sides in the first direction X.

[0319] The second gate wiring 86 for the sixth active region 6F extends in a strip shape in the second direction Y in the outer peripheral region 7b so as to cross (specifically, orthogonally cross) the second end portions of the plurality of gate structures 12. The second gate wiring 86 for the sixth active region 6F opposes the plurality of wiring groups 80 (both the plurality of first lower wirings 81 and the plurality of second lower wirings 82) in the first direction X.

[0320] In this manner, the plurality of second gate wirings 86 extend in a strip shape along the plurality of second connection structures 22 so as to cover the plurality of second connection structures 22. The plurality of second gate wirings 86 are electrically connected to the plurality of second connection structures 22, and the gate potential is applied to the plurality of gate structures 12 via the plurality of second connection structures 22.

[0321] The plurality of second gate wirings 86 are respectively arranged in the first direction X at intervals from the first gate wiring 85 in the corresponding inter-wiring region IWR so as to extend substantially in parallel with respect to the first gate wiring 85. The plurality of second gate wirings 86 have first end portions on one side in the second direction Y and second end portions on the other side in the second direction Y.

[0322] The third gate wiring 87 is arranged on the outer peripheral region 7b in a region on one side in the second direction Y with respect to the plurality of wiring groups 80 so as to oppose the plurality of wiring groups 80 in the second direction Y. The third gate wiring 87 extends in a strip shape in the first direction X so as to connect the first end portions of the plurality of first gate wirings 85 and the first end portions of the plurality of second gate wirings 86.

[0323] That is, the third gate wiring 87 connects the plurality of first gate wirings 85 and the plurality of second gate wirings 86 in a comb shape toward the plurality of inter-wiring regions IWR (the boundary region 7a). The third gate wiring 87 is formed as an extraction portion extracted from the plurality of first gate wirings 85 and the plurality of second gate wirings 86 to the outer peripheral region 7b. The second end portions of the plurality of first gate wirings 85 and the second end portions of the plurality of second gate wirings 86 are formed as open ends.

[0324] The third gate wiring 87 is arranged in a region between the plurality of active regions 6 (the plurality of gate structures 12) and the innermost field structure 42. The third gate wiring 87 is arranged at intervals from the first end portions (open ends) of the plurality of first base structures 55a toward one side in the second direction Y (the field structure 42 side) so as to oppose the first end portions (open ends) of the plurality of first base structures 55a in the second direction Y. That is, a region between the first end portions of the plurality of first base structures 55a and the second base structure 55b is formed as a wiring path of the third gate wiring 87 (the third lower wiring 83).

[0325] The fourth lower wiring 84 is arranged on the outer side region 7 at intervals from the plurality of wiring groups 80. The fourth lower wiring 84 is arranged in the outer side region 7 at a position overlapping the base structure 55, and is led out to the inner and outer sides of the inter-wiring region IWR. Specifically, the fourth lower wiring 84 includes a plurality of first base wirings 88 and at least one (in this mode, one) second base wiring 89.

[0326] The plurality of first base wirings 88 are respectively arranged on the corresponding first base structure 55a in the inter-wiring region IWR (the boundary region 7a) so as to be electrically connected to the corresponding first base structure 55a. The plurality of first base wirings 88 are respectively arranged in the corresponding inter-wiring region IWR in a region between the first gate wiring 85 and the second gate wiring 86 on both sides in the first direction X opposite to the first gate wiring 85 and the second gate wiring 86.

[0327] The plurality of first base wirings 88 respectively extend the region between the corresponding first gate wiring 85 and the second gate wiring 86 in the second direction Y in a strip shape along the first base structure 55a. The plurality of first base wirings 88 respectively have a first end portion on one side in the second direction Y and a second end portion on the other side in the second direction Y. The first end portions of the plurality of first base wirings 88 are formed at intervals from the third lower wiring 83 (the third gate wiring 87) on the other side in the second direction Y opposite to the third lower wiring 83 (the third gate wiring 87) in the second direction Y.

[0328] In this mode, the plurality of first base wirings 88 are arranged only in the corresponding inter-wiring region IWR, and do not have a portion located in the wiring group 80 (a region between the first lower wiring 81 and the second lower wiring 82). That is, the plurality of first base wirings 88 do not have a portion that crosses the adjacent wiring group 80 in the first direction X. In this mode, the plurality of first base wirings 88 do not have a portion that extends in the first direction X in the inter-wiring region IWR. Of course, the plurality of first base wirings 88 can also have a portion that meanders to one side and the other side in the first direction X in the inter-wiring region IWR.

[0329] The second base wiring 89 is arranged on the second base structure 55b in the outer peripheral region 7b so as to be electrically connected to the second base structure 55b. The second base structure 55b is arranged in a region between the plurality of active regions 6 (the plurality of gate structures 12) and the innermost field structure 42, and extends in a strip shape along the second base structure 55b. Specifically, the second base structure 55b is arranged in a region between the third lower wiring 83 and the innermost field structure 42.

[0330] In this mode, the second base configuration 55b has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y along the second base configuration 55b. In this mode, the second base configuration 55b encloses the plurality of active regions 6 (the plurality of gate configurations 12) altogether along the second base configuration 55b, and is divided into a polygonal ring shape (in this mode, a quadrilateral ring shape) having four sides parallel to the periphery of the chip 2. The second base configuration 55b opposes the plurality of wiring groups 80 in the first direction X and the second direction Y.

[0331] The second base wiring 89 is connected to the second end portions of the plurality of first base wirings 88 on the other side in the second direction Y. That is, the second base wiring 89 connects the plurality of first base wirings 88 into a comb shape toward the plurality of inter-wiring regions IWR. The plurality of first base wirings 88 are connected into a comb shape engaged with the plurality of first gate wirings 85 and the plurality of second gate wirings 86. The second base wiring 89 is formed as an extraction portion extracted from the plurality of first base wirings 88 to the outer peripheral region 7b.

[0332] The second base wiring 89 is formed at intervals in the second direction Y from the second end portions (open end portions) of the plurality of first gate wirings 85 and the plurality of second gate wirings 86, and opposes the second end portions (open end portions) of the plurality of first gate wirings 85 and the plurality of second gate wirings 86 in the second direction Y.

[0333] For example, in a case where the plurality of field configurations 42 are given a base potential, the second base wiring 89 (the fourth lower wiring 84) covers the plurality of field configurations 42 altogether, and is electrically connected to the plurality of field configurations 42. In a case where the plurality of field configurations 42 are formed in an electrically floating state, an electrical connection portion of the second base wiring 89 (the fourth lower wiring 84) with respect to the plurality of field configurations 42 is not formed.

[0334] In this case, the second base wiring 89 (the fourth lower wiring 84) can also be disposed in a region directly above the plurality of field configurations 42, and oppose the plurality of field configurations 42 with the first interlayer film 71 interposed therebetween. Of course, the second base wiring 89 (the fourth lower wiring 84) can also be disposed at intervals inward from the plurality of field configurations 42.

[0335] The multilayer wiring configuration 73 (the semiconductor device 1A) includes a plurality of via electrodes 91 to 94 embedded in the first interlayer film 71. The plurality of via electrodes 91 to 94 includes a plurality of first via electrodes 91, a plurality of second via electrodes 92, a plurality of third via electrodes 93, and at least one (in this mode, one) fourth via electrode 94.

[0336] The first via electrode 91 is a plug electrode that transmits a first drain-source potential to the first drain-source region 28. The second via electrode 92 is a plug electrode that transmits a second drain-source potential to the second drain-source region 29. The third via electrode 93 is a plug electrode that transmits a gate potential to the gate structure 12 (connection structure 21, 22). The fourth via electrode 94 is a plug electrode that transmits a base potential to the base structure 55.

[0337] The first via electrode 91 can also be called a "first drain-source via electrode". The second via electrode 92 can also be called a "second drain-source via electrode". The third via electrode 93 can also be called a "gate via electrode". The fourth via electrode 94 can also be called a "base via electrode".

[0338] In this way, the plurality of via electrodes 91 to 94 each include a first electrode 95 and a second electrode 96. The first electrode 95 covers the wall surface of the via formed in the first interlayer film 71 in a film shape. The first electrode 95 can include either or both of a Ti film and a Ti alloy film. The Ti alloy film can also be a TiN film.

[0339] The second electrode 96 is embedded in the via via the first electrode 95. The second electrode 96 can include at least one of W, Al, an Al alloy, Cu, and a Cu alloy. The Al alloy can include at least one of an AlSi alloy, an AlCu alloy, and an AlSiCu alloy.

[0340] The plurality of first via electrodes 91 exist in the region between the plurality of first drain-source regions 28 and the plurality of first lower wiring lines 81 in the first interlayer film 71, and electrically connect the plurality of first lower wiring lines 81 to the corresponding first drain-source regions 28, respectively. The multilayer wiring structure 73 can have at least one first via electrode 91 in the region between one first lower wiring line 81 and one first drain-source region 28.

[0341] In this way, the plurality of first via electrodes 91 exist in the region between the corresponding first lower wiring line 81 and the first drain-source region 28, and are arranged at intervals in the first direction X. The first via electrode 91 can also be formed in a triangular shape, a quadrangular shape, a rectangular shape, a polygonal shape, a circular shape, or an elliptical shape when viewed from above. Of course, the first via electrode 91 can also be formed in a band shape (for example, a rectangular shape) extending in the first direction X.

[0342] The first via electrode 91 can also be formed using the first lower wiring 81. In this case, the first electrode 95 of the first via electrode 91 is formed integrally with the first electrode 76 of the first lower wiring 81, forming one electrode film with the first electrode 76. Similarly, the second electrode 96 of the first via electrode 91 is formed integrally with the second electrode 77 of the first lower wiring 81, forming one electrode with the second electrode 77.

[0343] The plurality of second via electrodes 92 are present in the first interlayer film 71 in regions between the plurality of second drain-source regions 29 and the plurality of second lower wirings 82, electrically connecting the plurality of second lower wirings 82 to the corresponding second drain-source regions 29. The multilayer wiring structure 73 can have at least one second via electrode 92 in a region between one second lower wiring 82 and one second drain-source region 29.

[0344] In this mode, the plurality of second via electrodes 92 are present in regions between the corresponding first lower wirings 81 and the first drain-source regions 28, arranged at intervals in the first direction X. The second via electrodes 92 can also be formed in a triangular shape, a quadrangular shape, a rectangular shape, a polygonal shape, a circular shape, or an elliptical shape when viewed from above. Of course, the second via electrodes 92 can also be formed in a strip shape (e.g., a rectangular shape) extending in the first direction X.

[0345] The second via electrode 92 can also be formed using the second lower wiring 82. In this case, the first electrode 95 of the second via electrode 92 is formed integrally with the first electrode 76 of the second lower wiring 82, forming one electrode film with the first electrode 76. Similarly, the second electrode 96 of the second via electrode 92 is formed integrally with the second electrode 77 of the second lower wiring 82, forming one electrode with the second electrode 77.

[0346] The plurality of third via electrodes 93 are present in the first interlayer film 71 in regions between the plurality of gate structures 12 (the plurality of connection structures 21, 22) and the third lower wirings 83, electrically connecting the third lower wirings 83 to the plurality of gate structures 12 (the plurality of connection structures 21, 22). The multilayer wiring structure 73 can have at least one third via electrode 93 with respect to one gate structure 12 (connection structure 21, 22).

[0347] In this mode, the plurality of third via electrodes 93 are present in regions between one connection structure 21, 22 and the third lower wiring 83, arranged at intervals in the second direction Y. The third via electrodes 93 can also be formed in a triangular shape, a quadrangular shape, a rectangular shape, a polygonal shape, a circular shape, or an elliptical shape when viewed from above. Of course, the third via electrodes 93 can also be formed in a strip shape (e.g., a rectangular shape) extending in the second direction Y.

[0348] In this mode, the connection formation 21, 22 having a width wider than the gate formation 12 is formed. Therefore, since the alignment margin of the third via electrode 93 with respect to the connection formation 21, 22 can be ensured, the third via electrode 93 can be properly connected to the connection formation 21, 22.

[0349] The third via electrode 93 can also be formed using the third lower wiring 83. In this case, the first electrode 95 of the third via electrode 93 is integrally formed with the first electrode 76 of the third lower wiring 83, forming one electrode film with the first electrode 76. Similarly, the second electrode 96 of the third via electrode 93 is integrally formed with the second electrode 77 of the third lower wiring 83, forming one electrode with the second electrode 77.

[0350] The fourth via electrode 94 is present in the first interlayer film 71 in a region between the base formation 55 and the fourth lower wiring 84, electrically connecting the fourth lower wiring 84 and the base formation 55. The fourth via electrode 94 is formed in a strip shape extending along the base formation 55 in plan view. In this mode, the fourth via electrode 94 has a planar shape matching the planar shape of the base formation 55 in plan view. That is, the fourth via electrode 94 has a plurality of portions extending in a strip shape along the plurality of first base formations 55a, and a portion extending in a strip shape along the second base formation 55b.

[0351] Of course, the multilayer wiring formation 73 can also include a plurality of fourth via electrodes 94. In this case, the plurality of fourth via electrodes 94 are arranged at intervals along the base formation 55 (the fourth lower wiring 84). In this case, the fourth via electrode 94 can also be formed in a triangular shape, a quadrangular shape, a rectangular shape, a polygonal shape, a circular shape, or an elliptical shape in plan view. Of course, the fourth via electrode 94 can also be formed in an end strip shape extending along the base formation 55 (the base wiring).

[0352] The fourth via electrode 94 is mechanically and electrically connected to the base electrode 57. In this mode, the fourth via electrode 94 is integrally formed with the base electrode 57. Specifically, the first electrode 95 of the fourth via electrode 94 is integrally formed with the first electrode 58 of the base electrode 57, forming one electrode film with the first electrode 58. Similarly, the second electrode 96 of the fourth via electrode 94 is integrally formed with the second electrode 59 of the base electrode 57, forming one electrode with the second electrode 59.

[0353] The fourth via electrode 94 can also be formed using the fourth lower wiring 84. In this case, the first electrode 95 of the fourth via electrode 94 is integrally formed with the first electrode 76 of the fourth lower wiring 84, forming one electrode film with the first electrode 76. Similarly, the second electrode 96 of the fourth via electrode 94 is integrally formed with the second electrode 77 of the fourth lower wiring 84, forming one electrode with the second electrode 77.

[0354] In the case where the base potential is imparted to the plurality of field structures 42, a plurality of fourth via electrodes 94 is present between the second base wiring 89 (fourth lower wiring 84) and the plurality of field structures 42, and the second base wiring 89 (fourth lower wiring 84) is electrically connected to the plurality of field structures 42.

[0355] Referring to Figure 15 and the like, the second layer wiring 75 includes a plurality of pad wirings 101 to 104. The plurality of pad wirings 101 to 104 includes one or more (in this mode, a plurality) of first pad wirings 101, one or more (in this mode, a plurality) of second pad wirings 102, one or more (in this mode, one) of third pad wirings 103, and one or more (in this mode, one) of fourth pad wirings 104.

[0356] The first pad wiring 101 imparts the first drain source potential to the first lower wiring 81. The second pad wiring 102 imparts the second drain source potential to the second lower wiring 82. The third pad wiring 103 imparts the gate potential to the third lower wiring 83. The fourth pad wiring 104 imparts the base potential to the fourth lower wiring 84.

[0357] The first pad wiring 101 can also be referred to as a "first drain source pad wiring". The second pad wiring 102 can also be referred to as a "second drain source pad wiring". The third pad wiring 103 can also be referred to as a "gate pad wiring". The fourth pad wiring 104 can also be referred to as a "base pad wiring".

[0358] The number of the first pad wirings 101, the number of the second pad wirings 102, the number of the third pad wirings 103, and the number of the fourth pad wirings 104 are all arbitrary. In this mode, the multilayer wiring structure 73 (semiconductor device 1A) includes ten first pad wirings 101, ten second pad wirings 102, one third pad wiring 103, and one fourth pad wiring 104. That is, the total number of the first to fourth pad wirings 101 to 104 is 22.

[0359] The plurality of pad wirings 101 to 104 is respectively arranged in a plurality of arrangement regions 105 (also refer to Figure 1 ) set in the interlayer film 70. The arrangement region 105 can also be referred to as a "pad arrangement region". The plurality of arrangement regions 105 is a quadrangular imaginary region set in a matrix shape (in this mode, 5 rows by 5 columns) along the first direction X and the second direction Y in plan view. The plurality of arrangement regions 105 is respectively set on the corresponding one boundary region 7a, straddling two active regions 6 adjacent in the first direction X. The planar area of the plurality of arrangement regions 105 can be appropriately adjusted in accordance with the planar area of the chip 2, the wiring layout of the mounting substrate, and the like.

[0360] The 10 first pad wirings 101 are arranged at intervals in the first direction X in the 5 arrangement regions 105 of the first row and the 5 arrangement regions 105 of the fourth row. Each first pad wiring 101 is arranged on the boundary region 7a in the corresponding arrangement region 105, straddling two active regions 6 adjacent in the first direction X.

[0361] The 10 second pad wirings 102 are arranged at intervals in the first direction X in the 5 arrangement regions 105 of the second row and the 5 arrangement regions 105 of the fifth row. Each second pad wiring 102 is arranged on the boundary region 7a in the corresponding arrangement region 105, straddling two active regions 6 adjacent in the first direction X.

[0362] The plurality of second pad wirings 102 arranged in the second row and the plurality of first pad wirings 101 arranged in the first row respectively oppose each other in the second direction Y in a one-to-one correspondence. Similarly, the plurality of second pad wirings 102 arranged in the fifth row and the plurality of first pad wirings 101 arranged in the fourth row respectively oppose each other in the second direction Y in a one-to-one correspondence.

[0363] The third pad wiring 103 is arranged in the arrangement region 105 of the fifth column of the third row. The third pad wiring 103 is disposed on the boundary region 7a in the corresponding arrangement region 105, straddling two active regions 6 adjacent in the first direction X. The third pad wiring 103 opposes the second pad wiring 102 on one side in the second direction Y and opposes the first pad wiring 101 on the other side in the second direction Y.

[0364] The fourth pad wiring 104 is arranged in the arrangement region 105 of the first column of the third row. The fourth pad wiring 104 is disposed on the boundary region 7a in the corresponding arrangement region 105, straddling two active regions 6 adjacent in the first direction X. The fourth pad wiring 104 opposes the second pad wiring 102 on one side in the second direction Y and opposes the first pad wiring 101 on the other side in the second direction Y.

[0365] The remaining arrangement regions 105 not having the pad wirings 101 to 104 are disposed as space regions 106. In this way, three arrangement regions 105 of the second to fourth columns of the third row are disposed as space regions 106. That is, the three second pad wirings 102 arranged in the second row and the three first pad wirings 101 arranged in the fourth row in alignment with the three space regions 106 respectively oppose each other in the second direction Y in a one-to-one correspondence. The fourth pad wiring 104 opposes the third pad wiring 103 in the first direction X with the three space regions 106 interposed therebetween.

[0366] The second layer wiring 75 includes a plurality of first wiring units U1, a plurality of second wiring units U2, a third wiring unit U3, and a fourth wiring unit U4. The first to fourth wiring units U1 to U4 are respectively grouped (classified) according to the layout of the first to fourth pad wirings 101 to 104.

[0367] The plurality of first wiring units U1 respectively include the first pad wiring 101 and the second pad wiring 102 that are opposed (proximally opposed) in the second direction Y. That is, the second layer wiring 75 includes ten first wiring units U1. In each first wiring unit U1, the first pad wiring 101 and the second pad wiring 102 are selectively electrically connected to the first lower wiring 81 and the second lower wiring 82 of the plurality of wiring groups 80 located directly below. The plurality of first wiring units U1 respectively have the same layout except for the first lower wiring 81 and the second lower wiring 82 that are the connection targets.

[0368] The plurality of second wiring units U2 respectively include the first pad wiring 101 and the second pad wiring 102 that are opposed across the space region 106 in the second direction Y. That is, the second layer wiring 75 includes three second wiring units U2. In each second wiring unit U2, the first pad wiring 101 and the second pad wiring 102 are selectively electrically connected to the first lower wiring 81 and the second lower wiring 82 of the plurality of wiring groups 80 located directly below.

[0369] The third wiring unit U3 includes the first pad wiring 101, the second pad wiring 102, and the third pad wiring 103 that are opposed (proximally opposed) in the second direction Y. In the third wiring unit U3, the first pad wiring 101 and the second pad wiring 102 are selectively electrically connected to the first lower wiring 81 and the second lower wiring 82 of the plurality of wiring groups 80 located directly below. In addition, the third pad wiring 103 is electrically connected to the third lower wiring 83.

[0370] The fourth wiring unit U4 includes the first pad wiring 101, the second pad wiring 102, and the fourth pad wiring 104 that are opposed (proximally opposed) in the second direction Y. In the fourth wiring unit U4, the first pad wiring 101 and the second pad wiring 102 are selectively electrically connected to the first lower wiring 81 and the second lower wiring 82 of the plurality of wiring groups 80 located directly below. In addition, the fourth pad wiring 104 is electrically connected to the fourth lower wiring 84.

[0371] Hereinafter, after the structure of the first wiring unit U1 is described, the structures of the second to fourth wiring units U2 to U4 are sequentially described. Figures 16A-16J is an enlarged plan view of the first wiring unit U1 indicating the first to tenth layout examples.

[0372] In Figures 16A-16JIn the present embodiment, a first wiring unit U1 disposed on the first side 5A side of the chip 2 is exemplified. Hereinafter, the structure of the first wiring unit U1 will be described as a basic mode example. Figure 16A The first wiring unit U1 shown in FIG. 1 is described as a basic mode example. The first wiring unit U1 shown in FIG. 2 is described as a modification example of the basic mode example. Figures 16B-16J The first wiring unit U1 shown in FIG. 1 is described as a basic mode example. The first wiring unit U1 shown in FIG. 2 is described as a modification example of the basic mode example.

[0373] In addition, hereinafter, the structure within one first wiring unit U1 is described unless specifically indicated. In addition, hereinafter, as two wiring groups 80 on one side and the other side of the first direction X, a first wiring group 80A and a second wiring group 80B are applied, and the layout of the first wiring unit U1 with respect to these wiring groups 80 is exemplified.

[0374] Of course, the following description also applies to other first wiring unit U1 layouts with respect to two wiring groups 80 adjacent on one side and the other side of the first direction X among the second to sixth wiring groups 80B to 80F. The specific structure in this case is obtained by replacing the first wiring group 80A and the second wiring group 80B with two wiring groups 80 adjacent on one side and the other side of the first direction X among the second to sixth wiring groups 80B to 80F in the following description.

[0375] Referring to Figure 16A A first wiring unit U1 includes a disposition region 105 for a first pad wiring 101 and a disposition region 105 for a second pad wiring 102 (first layout example). Hereinafter, the disposition region 105 for the first pad wiring 101 will be referred to as a "first disposition region 105A", and the disposition region 105 for the second pad wiring 102 will be referred to as a "second disposition region 105B".

[0376] The first disposition region 105A is disposed on one side of the second direction Y in plan view. The first disposition region 105A is disposed in a quadrangular shape (preferably a square shape) in plan view. The first disposition region 105A includes the first wiring group 80A and the second wiring group 80B adjacent in the first direction X with the inter-wiring region IWR therebetween.

[0377] In other words, the first disposition region 105A overlaps the first active region 6A and the second active region 6B adjacent in the first direction X with the boundary region 7a therebetween. The first disposition region 105A includes at least one first lower wiring 81 belonging to the first wiring group 80A and at least one first lower wiring 81 belonging to the second wiring group 80B.

[0378] Specifically, the first arrangement region 105A includes at least one (in this mode, a plurality) of the first lower wiring 81 and at least one (in this mode, a plurality) of the second lower wiring 82 belonging to the first wiring group 80A, and at least one (in this mode, a plurality) of the first lower wiring 81 and at least one (in this mode, a plurality) of the second lower wiring 82 belonging to the second wiring group 80B.

[0379] In the first arrangement region 105A, the number of the first lower wiring 81 of the first wiring group 80A, the number of the second lower wiring 82 of the first wiring group 80A, the number of the first lower wiring 81 of the second wiring group 80B, and the number of the second lower wiring 82 of the second wiring group 80B are arbitrary.

[0380] For example, in the first wiring group 80A (the second wiring group 80B) of the first arrangement region 105A, the number of the first lower wiring 81 (the second lower wiring 82) can also be 1 or more and 1000 or less. For example, in the first wiring group 80A (the second wiring group 80B) of the first arrangement region 105A, the number of the first lower wiring 81 (the second lower wiring 82) can also have a value belonging to at least one range of 1 or more and 50 or less, 50 or more and 100 or less, 100 or more and 250 or less, 250 or more and 500 or less, 500 or more and 750 or less, and 750 or more and 1000 or less.

[0381] In the first wiring group 80A of the first arrangement region 105A, it is preferable that the number of the second lower wiring 82 is approximately equal to the number of the first lower wiring 81. In the second wiring group 80B of the first arrangement region 105A, it is preferable that the number of the second lower wiring 82 is approximately equal to the number of the first lower wiring 81. In the first arrangement region 105A, it is preferable that the number of the first lower wiring 81 of the second wiring group 80B is approximately equal to the number of the first lower wiring 81 of the first wiring group 80A. In addition, it is preferable that the number of the second lower wiring 82 of the second wiring group 80B is approximately equal to the number of the second lower wiring 82 of the first wiring group 80A.

[0382] In this mode, in both the first wiring group 80A and the second wiring group 80B, the plurality of the second lower wiring 82 is arranged alternately with the plurality of the first lower wiring 81. In addition, the first lower wiring 81 and the second lower wiring 82 of the second wiring group 80B are respectively opposite to the first lower wiring 81 and the second lower wiring 82 of the first wiring group 80A in the first direction X.

[0383] Therefore, in the first wiring group 80A of the first arrangement region 105A, the difference between the number of the first lower wiring 81 and the number of the second lower wiring 82 is 0 to 1. Also, in the second wiring group 80B of the first arrangement region 105A, the difference between the number of the first lower wiring 81 and the number of the second lower wiring 82 is 0 to 1.

[0384] Also, in the first arrangement region 105A, the difference between the number of the first lower wiring 81 of the first wiring group 80A and the number of the first lower wiring 81 of the second wiring group 80B is 0 to 1. Also, the difference between the number of the second lower wiring 82 of the first wiring group 80A and the number of the second lower wiring 82 of the second wiring group 80B is 0 to 1.

[0385] The second arrangement region 105B is provided on the other side in the second direction Y with respect to the first arrangement region 105A when viewed in plan, and is adjacent to the first arrangement region 105A. The second arrangement region 105B divides the boundary portion 107 from the first arrangement region 105A. The second arrangement region 105B is provided in a quadrangular shape (preferably, a square shape) when viewed in plan, and divides the boundary portion 107 extending in the first direction X. The planar area of the second arrangement region 105B is substantially equal to the planar area of the first arrangement region 105A.

[0386] The second arrangement region 105B includes the first wiring group 80A and the second wiring group 80B adjacent in the first direction X with the wiring interval region IWR interposed therebetween. In other words, the second arrangement region 105B overlaps the first active region 6A and the second active region 6B adjacent in the first direction X with the boundary region 7a interposed therebetween. The second arrangement region 105B includes at least one second lower wiring 82 belonging to the first wiring group 80A and at least one second lower wiring 82 belonging to the second wiring group 80B.

[0387] Specifically, the second arrangement region 105B includes at least one (in this mode, a plurality) of the first lower wiring 81 and at least one (in this mode, a plurality) of the second lower wiring 82 belonging to the first wiring group 80A, and at least one (in this mode, a plurality) of the first lower wiring 81 and at least one (in this mode, a plurality) of the second lower wiring 82 belonging to the second wiring group 80B.

[0388] In the second arrangement region 105B, the number of the first lower wiring 81 of the first wiring group 80A, the number of the second lower wiring 82 of the first wiring group 80A, the number of the first lower wiring 81 of the second wiring group 80B, and the number of the second lower wiring 82 of the second wiring group 80B are all arbitrary.

[0389] For example, in the first wiring group 80A (second wiring group 80B) of the second arrangement region 105B, the number of the first lower wiring 81 (second lower wiring 82) can also be 1 or more and 1000 or less. For example, in the first wiring group 80A (second wiring group 80B) of the second arrangement region 105B, the number of the first lower wiring 81 (second lower wiring 82) can also have a value belonging to at least one range of 1 or more and 50 or less, 50 or more and 100 or less, 100 or more and 250 or less, 250 or more and 500 or less, 500 or more and 750 or less, and 750 or more and 1000 or less.

[0390] In the first wiring group 80A of the second arrangement region 105B, it is preferable that the number of the second lower wiring 82 is approximately equal to the number of the first lower wiring 81. In the second wiring group 80B of the second arrangement region 105B, it is preferable that the number of the second lower wiring 82 is approximately equal to the number of the first lower wiring 81. In the second arrangement region 105B, it is preferable that the number of the first lower wiring 81 of the second wiring group 80B is approximately equal to the number of the first lower wiring 81 of the first wiring group 80A. In addition, it is preferable that the number of the second lower wiring 82 of the second wiring group 80B is approximately equal to the number of the second lower wiring 82 of the first wiring group 80A.

[0391] In this manner, in both the first wiring group 80A and the second wiring group 80B, the plurality of second lower wirings 82 and the plurality of first lower wirings 81 are alternately arranged. In addition, the first lower wiring 81 and the second lower wiring 82 of the second wiring group 80B are respectively opposite to the first lower wiring 81 and the second lower wiring 82 of the first wiring group 80A in the first direction X.

[0392] Therefore, in the first wiring group 80A of the second arrangement region 105B, the difference between the number of the first lower wiring 81 and the number of the second lower wiring 82 is 0 or more and 1 or less. In addition, in the second wiring group 80B of the second arrangement region 105B, the difference between the number of the first lower wiring 81 and the number of the second lower wiring 82 is 0 or more and 1 or less.

[0393] In addition, in the second arrangement region 105B, the difference between the number of the first lower wiring 81 of the first wiring group 80A and the number of the first lower wiring 81 of the second wiring group 80B is 0 or more and 1 or less. In addition, the difference between the number of the second lower wiring 82 of the first wiring group 80A and the number of the second lower wiring 82 of the second wiring group 80B is 0 or more and 1 or less.

[0394] As for the first wiring group 80A of the first arrangement region 105A and the first wiring group 80A of the second arrangement region 105B, the number of the first lower wiring 81 is preferably equal to each other, and the number of the second lower wiring 82 is preferably equal to each other. That is, the wiring resistance of the first wiring group 80A of the second arrangement region 105B is preferably substantially equal to the wiring resistance of the first wiring group 80A of the first arrangement region 105A.

[0395] In addition, as for the second wiring group 80B of the first arrangement region 105A and the second wiring group 80B of the second arrangement region 105B, the number of the first lower wiring 81 is preferably equal to each other, and the number of the second lower wiring 82 is preferably equal to each other. That is, the wiring resistance of the second wiring group 80B of the second arrangement region 105B is preferably substantially equal to the wiring resistance of the second wiring group 80B of the first arrangement region 105A.

[0396] The first pad wiring 101 is arranged in the first arrangement region 105A. The first pad wiring 101 has a planar area smaller than that of the first arrangement region 105A. The first pad wiring 101 is arranged inward from the periphery of the first arrangement region 105A at an interval in plan view, and is formed in a polygonal shape having four sides parallel to the periphery of the chip 2 (the periphery of the first arrangement region 105A). The first pad wiring 101 is biased to one side in the first direction X with respect to the central portion of the boundary portion 107, and is biased to one side in the second direction Y with respect to the boundary portion 107.

[0397] The first pad wiring 101 is arranged on the first wiring group 80A and the second wiring group 80B adjacent in the first direction X with the wiring interval region IWR therebetween. That is, the first pad wiring 101 is arranged on the wiring interval region IWR, and is drawn out to the first wiring group 80A and the second wiring group 80B adjacent in the first direction X. In other words, the first pad wiring 101 is arranged on the first active region 6A and the second active region 6B adjacent in the first direction X with the interface region 7a therebetween.

[0398] The first pad wiring 101 is opposed to the first wiring group 80A, the second wiring group 80B, and the wiring interval region IWR with the second interlayer film 72 therebetween. The first pad wiring 101 is electrically connected to at least one first lower wiring 81 of the first wiring group 80A and at least one first lower wiring 81 of the second wiring group 80B.

[0399] Specifically, the first pad wiring 101 has a first end portion on one side of the first direction X and a second end portion on the other side of the first direction X. The first end portion of the first pad wiring 101 is disposed on the first wiring group 80A. The first end portion of the first pad wiring 101 is disposed on at least one (in this case, a plurality of) first lower wiring 81 of the first wiring group 80A, and is electrically connected to the at least one (in this case, a plurality of) first lower wiring 81 of the first wiring group 80A.

[0400] In this case, the first end portion of the first pad wiring 101 overlaps the at least one (in this case, a plurality of) first lower wiring 81 and the at least one (in this case, a plurality of) second lower wiring 82 of the first wiring group 80A. The first end portion of the first pad wiring 101 is electrically isolated from all the second lower wiring 82 of the first wiring group 80A.

[0401] The second end portion of the first pad wiring 101 is disposed on the second wiring group 80B. The second end portion of the first pad wiring 101 is disposed on at least one (in this case, a plurality of) first lower wiring 81 of the second wiring group 80B, and is electrically connected to the at least one (in this case, a plurality of) first lower wiring 81 of the second wiring group 80B.

[0402] In this case, the second end portion of the first pad wiring 101 overlaps the at least one (in this case, a plurality of) first lower wiring 81 and the at least one (in this case, a plurality of) second lower wiring 82 of the second wiring group 80B. The second end portion of the first pad wiring 101 is electrically isolated from all the second lower wiring 82 of the second wiring group 80B.

[0403] The first pad wiring 101 is electrically connected to both the first lower wiring 81 of the first wiring group 80A and the first lower wiring 81 of the second wiring group 80B across the inter-wiring region IWR. Therefore, the current path connecting the first lower wiring 81 of the first wiring group 80A to the first pad wiring 101 is shortened, and the current path connecting the first lower wiring 81 of the second wiring group 80B to the first pad wiring 101 is shortened. As a result, the wiring resistance between the first pad wiring 101 and the first lower wiring 81 of the first wiring group 80A is reduced, and the wiring resistance between the first pad wiring 101 and the first lower wiring 81 of the second wiring group 80B is reduced.

[0404] The number of the first lower wiring 81 of the first wiring group 80A, the number of the second lower wiring 82 of the first wiring group 80A, the number of the first lower wiring 81 of the second wiring group 80B, and the number of the second lower wiring 82 of the second wiring group 80B are arbitrary below the first pad wiring 101.

[0405] For example, in the first wiring group 80A (second wiring group 80B) directly below the first pad wiring 101, the number of the first lower wiring 81 (second lower wiring 82) can also be 1 or more and 1000 or less. For example, in the first wiring group 80A (second wiring group 80B) directly below the first pad wiring 101, the number of the first lower wiring 81 (second lower wiring 82) can also have a value in at least one range of 1 or more and 50 or less, 50 or more and 100 or less, 100 or more and 250 or less, 250 or more and 500 or less, 500 or more and 750 or less, and 750 or more and 1000 or less.

[0406] In the first wiring group 80A directly below the first pad wiring 101, it is preferable that the number of the second lower wiring 82 be approximately equal to the number of the first lower wiring 81. In the second wiring group 80B directly below the first pad wiring 101, it is preferable that the number of the second lower wiring 82 be approximately equal to the number of the first lower wiring 81. Directly below the first pad wiring 101, it is preferable that the number of the first lower wiring 81 of the second wiring group 80B be approximately equal to the number of the first lower wiring 81 of the first wiring group 80A. In addition, it is preferable that the number of the second lower wiring 82 of the second wiring group 80B be approximately equal to the number of the second lower wiring 82 of the first wiring group 80A.

[0407] In this manner, in both the first wiring group 80A and the second wiring group 80B, the plurality of second lower wirings 82 are arranged alternately with the plurality of first lower wirings 81. In addition, the first lower wiring 81 and the second lower wiring 82 of the second wiring group 80B are respectively opposite to the first lower wiring 81 and the second lower wiring 82 of the first wiring group 80A in the first direction X.

[0408] Therefore, in the first wiring group 80A directly below the first pad wiring 101, the difference between the number of the first lower wiring 81 and the number of the second lower wiring 82 is 0 or more and 1 or less. In addition, in the second wiring group 80B directly below the first pad wiring 101, the difference between the number of the first lower wiring 81 and the number of the second lower wiring 82 is 0 or more and 1 or less.

[0409] In addition, in the first pad wiring 101, the difference between the number of the first lower wiring 81 of the first wiring group 80A and the number of the first lower wiring 81 of the second wiring group 80B is 0 or more and 1 or less. In addition, the difference between the number of the second lower wiring 82 of the first wiring group 80A and the number of the second lower wiring 82 of the second wiring group 80B is 0 or more and 1 or less.

[0410] That is, in the first wiring group 80A (second wiring group 80B) directly below the first pad wiring 101, the variation in wiring resistance between the first lower wiring 81 and the second lower wiring 82 is suppressed. In addition, directly below the first pad wiring 101, the variation in wiring resistance between the first wiring group 80A and the second wiring group 80B is suppressed. With respect to the first wiring group 80A directly below the first end portion of the first pad wiring 101 and the second wiring group 80B directly below the second end portion of the first pad wiring 101, the number of the first lower wiring 81 is preferably equal to each other, and the number of the second lower wiring 82 is preferably equal to each other.

[0411] The first pad wiring 101 overlaps the third lower wiring 83 in the portion covering the inter-wiring region IWR. In this manner, the first pad wiring 101 overlaps both the first gate wiring 85 and the second gate wiring 86. The first pad wiring 101 is opposed to the third lower wiring 83 (the first gate wiring 85 and the second gate wiring 86) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the third lower wiring 83.

[0412] The first pad wiring 101 overlaps the fourth lower wiring 84 in the portion covering the inter-wiring region IWR. In this manner, the first pad wiring 101 overlaps the first base wiring 88. The first pad wiring 101 is opposed to the fourth lower wiring 84 (the first base wiring 88) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the fourth lower wiring 84.

[0413] The first wiring unit U1 includes the second pad wiring 102 that is disposed at an interval from the first pad wiring 101 (the first arrangement region 105A) toward the other side in the second direction Y in the second arrangement region 105B. The second pad wiring 102 has a planar area smaller than the planar area of the second arrangement region 105B. The second pad wiring 102 is disposed at an interval from the periphery of the second arrangement region 105B inward in plan view, and is formed in a polygonal shape having four sides parallel to the periphery of the chip 2 (the periphery of the second arrangement region 105B).

[0414] The second pad wiring 102 is biased on the other side in the first direction X with respect to the central portion of the first pad wiring 101 (the central portion of the boundary portion 107), and is biased on the other side in the second direction Y with respect to the boundary portion 107. The distance between the second pad wiring 102 and the boundary portion 107 is preferably substantially equal to the distance between the first pad wiring 101 and the boundary portion 107. That is, the boundary portion 107 is preferably located substantially in the middle between the first pad wiring 101 and the second pad wiring 102.

[0415] The second pad wiring 102 preferably has a planar layout that is substantially congruent with the planar layout of the first pad wiring 101. That is, the planar shape of the second pad wiring 102 is preferably substantially equal to the planar shape of the first pad wiring 101, and the planar area of the second pad wiring 102 is preferably substantially equal to the planar area of the first pad wiring 101. The second pad wiring 102 is preferably configured to be point-symmetrical with respect to the first pad wiring 101 with the center portion of the boundary portion 107 as the center.

[0416] The second pad wiring 102 is configured on the first wiring group 80A and the second wiring group 80B that are adjacent in the first direction X with the inter-wiring region IWR therebetween. That is, the second pad wiring 102 is configured on the inter-wiring region IWR and is drawn out to the first wiring group 80A and the second wiring group 80B that are adjacent in the first direction X. In other words, the second pad wiring 102 is configured on the first active region 6A and the second active region 6B that are adjacent in the first direction X with the boundary region 7a therebetween.

[0417] The second pad wiring 102 is opposite to the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR with the second interlayer film 72 therebetween. The second pad wiring 102 is electrically connected to at least one second lower wiring 82 of the first wiring group 80A and at least one second lower wiring 82 of the second wiring group 80B.

[0418] Specifically, the second pad wiring 102 has a first end portion on one side in the first direction X and a second end portion on the other side in the first direction X. The first end portion of the second pad wiring 102 is configured on the first wiring group 80A. The first end portion of the second pad wiring 102 is configured on at least one (in this case, a plurality of) second lower wiring 82 of the first wiring group 80A and is electrically connected to the at least one (in this case, a plurality of) second lower wiring 82 of the first wiring group 80A.

[0419] In this case, the first end portion of the second pad wiring 102 overlaps at least one (in this case, a plurality of) first lower wiring 81 and at least one (in this case, a plurality of) second lower wiring 82 of the first wiring group 80A. The first end portion of the second pad wiring 102 is electrically isolated from all the first lower wiring 81 of the first wiring group 80A.

[0420] The second end portion of the second pad wiring 102 is configured on the second wiring group 80B. The second end portion of the second pad wiring 102 is configured on at least one (in this case, a plurality of) second lower wiring 82 of the second wiring group 80B and is electrically connected to the at least one (in this case, a plurality of) second lower wiring 82 of the second wiring group 80B.

[0421] In this mode, the second end portion of the second pad wiring 102 overlaps at least one (in this mode, a plurality) of the first lower wirings 81 and at least one (in this mode, a plurality) of the second lower wirings 82 of the second wiring group 80B. The second end portion of the second pad wiring 102 is electrically isolated from all of the first lower wirings 81 of the second wiring group 80B.

[0422] The second pad wiring 102 is electrically connected to both the second lower wiring 82 of the first wiring group 80A and the second lower wiring 82 of the second wiring group 80B across the inter-wiring region IWR. Therefore, it is possible to shorten the current path connecting the second lower wiring 82 of the first wiring group 80A and the second pad wiring 102, and it is possible to shorten the current path connecting the second lower wiring 82 of the second wiring group 80B and the second pad wiring 102. Thereby, it is possible to reduce the wiring resistance between the second pad wiring 102 and the second lower wiring 82 of the first wiring group 80A, and it is possible to reduce the wiring resistance between the second pad wiring 102 and the second lower wiring 82 of the second wiring group 80B.

[0423] The number of the first lower wirings 81 of the first wiring group 80A, the number of the second lower wirings 82 of the first wiring group 80A, the number of the first lower wirings 81 of the second wiring group 80B, and the number of the second lower wirings 82 of the second wiring group 80B are arbitrary directly below the second pad wiring 102.

[0424] For example, the number of the first lower wirings 81 (second lower wirings 82) in the first wiring group 80A (second wiring group 80B) directly below the second pad wiring 102 can also be 1 or more and 1000 or less. For example, the number of the first lower wirings 81 (second lower wirings 82) in the first wiring group 80A (second wiring group 80B) directly below the second pad wiring 102 can also have a value belonging to at least one range of 1 or more and 50 or less, 50 or more and 100 or less, 100 or more and 250 or less, 250 or more and 500 or less, 500 or more and 750 or less, and 750 or more and 1000 or less.

[0425] It is preferable that the number of the second lower wirings 82 be approximately equal to the number of the first lower wirings 81 in the first wiring group 80A directly below the second pad wiring 102. It is preferable that the number of the second lower wirings 82 be approximately equal to the number of the first lower wirings 81 in the second wiring group 80B directly below the second pad wiring 102. It is preferable that the number of the first lower wirings 81 of the second wiring group 80B be approximately equal to the number of the first lower wirings 81 of the first wiring group 80A directly below the second pad wiring 102. In addition, it is preferable that the number of the second lower wirings 82 of the second wiring group 80B be approximately equal to the number of the second lower wirings 82 of the first wiring group 80A.

[0426] In this mode, in both the first wiring group 80A and the second wiring group 80B, the plurality of second lower wiring lines 82 are arranged alternately with the plurality of first lower wiring lines 81. Further, the first lower wiring line 81 and the second lower wiring line 82 of the second wiring group 80B respectively oppose the first lower wiring line 81 and the second lower wiring line 82 of the first wiring group 80A in the first direction X.

[0427] Therefore, in the first wiring group 80A directly below the second pad wiring line 102, the difference between the number of the first lower wiring lines 81 and the number of the second lower wiring lines 82 is 0 to 1. Further, in the second wiring group 80B directly below the second pad wiring line 102, the difference between the number of the first lower wiring lines 81 and the number of the second lower wiring lines 82 is 0 to 1.

[0428] Further, directly below the second pad wiring line 102, the difference between the number of the first lower wiring lines 81 of the first wiring group 80A and the number of the first lower wiring lines 81 of the second wiring group 80B is 0 to 1. Further, directly below the second pad wiring line 102, the difference between the number of the second lower wiring lines 82 of the first wiring group 80A and the number of the second lower wiring lines 82 of the second wiring group 80B is 0 to 1.

[0429] That is, in the first wiring group 80A (the second wiring group 80B) directly below the second pad wiring line 102, the variation in the wiring resistance between the first lower wiring line 81 and the second lower wiring line 82 is suppressed. Further, directly below the second pad wiring line 102, the variation in the wiring resistance between the first wiring group 80A and the second wiring group 80B is suppressed. With respect to the first wiring group 80A directly below the first end portion of the second pad wiring line 102 and the second wiring group 80B directly below the second end portion of the second pad wiring line 102, it is preferable that the number of the first lower wiring lines 81 be equal to each other and the number of the second lower wiring lines 82 be equal to each other.

[0430] With respect to the first wiring group 80A directly below the first pad wiring line 101 and the first wiring group 80A directly below the second pad wiring line 102, it is preferable that the number of the first lower wiring lines 81 be equal to each other and the number of the second lower wiring lines 82 be equal to each other. That is, it is preferable that the wiring resistance of the first wiring group 80A directly below the second pad wiring line 102 be substantially equal to the wiring resistance of the first wiring group 80A directly below the first pad wiring line 101.

[0431] With respect to the second wiring group 80B directly below the first pad wiring line 101 and the second wiring group 80B directly below the second pad wiring line 102, it is preferable that the number of the first lower wiring lines 81 be equal to each other and the number of the second lower wiring lines 82 be equal to each other. That is, it is preferable that the wiring resistance of the second wiring group 80B directly below the second pad wiring line 102 be substantially equal to the wiring resistance of the second wiring group 80B directly below the first pad wiring line 101.

[0432] The second pad wiring 102 overlaps the third lower wiring 83 at a portion covering the inter-wiring region IWR. In this way, the second pad wiring 102 overlaps both the first gate wiring 85 and the second gate wiring 86. The second pad wiring 102 faces the third lower wiring 83 (the first gate wiring 85 and the second gate wiring 86) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the third lower wiring 83.

[0433] The second pad wiring 102 overlaps the fourth lower wiring 84 at a portion covering the inter-wiring region IWR. In this way, the second pad wiring 102 overlaps the first base wiring 88. The second pad wiring 102 faces the fourth lower wiring 84 (the first base wiring 88) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the fourth lower wiring 84.

[0434] The first wiring unit U1 includes a first interconnection wiring configuration 108 formed in a region between the first pad wiring 101 and the second pad wiring 102. The first interconnection wiring configuration 108 forms a current path of a drain-source current Ids between the first pad wiring 101 and the second pad wiring 102.

[0435] The first interconnection wiring configuration 108 includes at least one (in this way, a plurality) of first lead-out wirings 109 led out from the first pad wiring 101 toward the second pad wiring 102 in the second direction Y. The plurality of first lead-out wirings 109 are electrically connected to either one or both of at least one first lower wiring 81 of the first wiring group 80A and at least one first lower wiring 81 of the second wiring group 80B in a region between the first pad wiring 101 and the second pad wiring 102.

[0436] The plurality of first lead-out wirings 109 include at least one (in this way, one) first long wiring 110 that is longer, and at least one (in this way, a plurality) first short wiring 111 that is shorter than the first long wiring 110. The first long wiring 110 can also be referred to as a "first long lead-out wiring", a "first main lead-out wiring", or the like. The first short wiring 111 can also be referred to as a "first short lead-out wiring", a "first sub lead-out wiring", or the like.

[0437] The number of the first short wirings 111 is arbitrary and is appropriately adjusted in accordance with the size of the first pad wiring 101 or the like. The number of the first short wirings 111 can also be one or more and 50 or less. The number of the first short wirings 111 can also have a value in at least one range of one or more and five or less, five or more and ten or less, ten or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, 40 or more and 50 or less. In this way, two first short wirings 111 are provided.

[0438] The first long wiring 110 has a width smaller than that of the first pad wiring 101 (the second pad wiring 102) in the first direction X, and is drawn out in a band shape from the first end portion of the first pad wiring 101 to the first wiring group 80A (the first active region 6A) in the second direction Y. The width of the first long wiring 110 is larger than that of the first lower wiring 81 (the second lower wiring 82). In this way, the first long wiring 110 crosses (is orthogonal to) at least one (in this way, a plurality of) first lower wirings 81 and at least one (in this way, a plurality of) second lower wirings 82 of the first wiring group 80A in the first arrangement region 105A.

[0439] The first long wiring 110 is drawn out from the first arrangement region 105A to the second arrangement region 105B in the second direction Y across the boundary portion 107. In this way, the first long wiring 110 crosses (is orthogonal to) at least one (in this way, a plurality of) first lower wirings 81 and at least one (in this way, a plurality of) second lower wirings 82 in both the first arrangement region 105A and the second arrangement region 105B.

[0440] The first long wiring 110 is electrically connected to at least one (in this way, a plurality of) first lower wirings 81 of the first wiring group 80A in the first arrangement region 105A. In addition, the first long wiring 110 is electrically connected to at least one (in this way, a plurality of) first lower wirings 81 of the first wiring group 80A in the second arrangement region 105B.

[0441] The first long wiring 110 has a first opposite portion 112 drawn out to a region opposite to the second pad wiring 102 in the first direction X in the second direction Y. The first opposite portion 112 is opposite to the entire region of the first end portion of the second pad wiring 102 in the first direction X. The first opposite portion 112 (the first long wiring 110) crosses (is orthogonal to) one or a plurality of (preferably all) first lower wirings 81 and one or a plurality of (preferably all) second lower wirings 82 passing directly below the second pad wiring 102 in the first direction X with respect to the first wiring group 80A.

[0442] The first opposite portion 112 is electrically connected to a portion of one or a plurality of (preferably all) first lower wirings 81 covered by the second pad wiring 102 and exposed from the second pad wiring 102. On the other hand, the first opposite portion 112 is electrically isolated from one or a plurality of (preferably all) second lower wirings 82 passing directly below the second pad wiring 102.

[0443] The first long wiring line 110 forms a current path of the drain-source current Ids together with the second pad wiring line 102 which is opposite (close opposite) in the first direction X. Specifically, the current path of the drain-source current Ids is formed between the second pad wiring line 102 and the first long wiring line 110 via the first lower wiring line 81 and the second lower wiring line 82 which pass directly below both the second pad wiring line 102 and the first long wiring line 110 in the first direction X. Such a layout is effective in reducing the wiring resistance between the first pad wiring line 101 and the second pad wiring line 102.

[0444] The plurality of first short wiring lines 111 each have a width smaller than the width of the first pad wiring line 101 (the second pad wiring line 102) in the first direction X, and are arranged in the region on the second end portion side with respect to the first long wiring line 110. The width of the first short wiring line 111 can also be substantially equal to the width of the first long wiring line 110. The width of the first short wiring line 111 can also be greater than the width of the first long wiring line 110. The width of the first short wiring line 111 can also be smaller than the width of the first long wiring line 110. The width of the first short wiring line 111 is greater than the width of the first lower wiring line 81 (the second lower wiring line 82).

[0445] The plurality of first short wiring lines 111 are arranged in a strip shape (in this case, an oblong shape) in the second direction Y from the first pad wiring line 101 to the second pad wiring line 102 with intervals in the first direction X. The plurality of first short wiring lines 111 can also be led out in a trapezoidal shape (preferably, an isosceles trapezoidal shape) or a triangular shape (preferably, an isosceles triangular shape).

[0446] The plurality of first short wiring lines 111 are arranged in a comb-tooth shape extending in the second direction Y, and are opposite to each other in the first direction X. The plurality of first short wiring lines 111 are opposite to the first long wiring line 110 in the first direction X. The plurality of first short wiring lines 111 are formed with intervals from the second pad wiring line 102 on the first pad wiring line 101 side, and are opposite to the second pad wiring line 102 in the second direction Y.

[0447] The plurality of first short wiring lines 111 are electrically connected to at least one (in this case, a plurality) of the first lower wiring lines 81 in the region between the first pad wiring line 101 and the second pad wiring line 102. Specifically, the plurality of first short wiring lines 111 include one or more (in this case, one) first short wiring lines 111 on one side, and one or more (in this case, one) first short wiring lines 111 on the other side. It is preferable that the number of the first short wiring lines 111 on the other side be equal to the number of the first short wiring lines 111 on one side.

[0448] The one-side first short wiring 111 is drawn out from the first pad wiring 101 onto the first wiring group 80A (the first active region 6A) in a region on the first wiring group 80A opposite the second pad wiring 102 in the second direction Y. The one-side first short wiring 111 is electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the first wiring group 80A. In this case, the one-side first short wiring 111 crosses (orthogonally intersects) at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in the first arrangement region 105A.

[0449] The one-side first short wiring 111 crosses (orthogonally intersects) at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in the second direction Y across the boundary portion 107 from the first arrangement region 105A to the second arrangement region 105B. In this case, the one-side first short wiring 111 crosses (orthogonally intersects) at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in both the first arrangement region 105A and the second arrangement region 105B.

[0450] The one-side first short wiring 111 is electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the first wiring group 80A in the first arrangement region 105A. In addition, the one-side first short wiring 111 is electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the first wiring group 80A in the second arrangement region 105B.

[0451] The one-side first short wiring 111 crosses (orthogonally intersects) at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in the first direction X directly below the first long wiring 110. That is, the one-side first short wiring 111 is electrically connected to a portion of at least one (in this case, a plurality) of the first lower wirings 81 exposed from the first long wiring 110 covered by the first long wiring 110.

[0452] In the case where the plurality of first short wirings 111 include a plurality of one-side first short wirings 111, the plurality of one-side first short wirings 111 are arranged at intervals in the first direction X in the region on the first wiring group 80A. That is, the plurality of one-side first short wirings 111 are arranged in a comb shape extending in the second direction Y in the region on the first wiring group 80A.

[0453] The other-side first short wiring 111 is drawn out from the first pad wiring 101 onto the second wiring group 80B (second active region 6B) in a region on the second wiring group 80B opposite the second pad wiring 102 in the second direction Y. The other-side first short wiring 111 is electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the second wiring group 80B. In this case, the other-side first short wiring 111 crosses (is orthogonal to) at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the second wiring group 80B in the first arrangement region 105A.

[0454] The other-side first short wiring 111 is drawn out from the first arrangement region 105A to the second arrangement region 105B in the second direction Y across the boundary portion 107. In this case, the other-side first short wiring 111 crosses (is orthogonal to) at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the second wiring group 80B in both the first arrangement region 105A and the second arrangement region 105B.

[0455] The other-side first short wiring 111 is electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the second wiring group 80B in the first arrangement region 105A. Also, the other-side first short wiring 111 is electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the second wiring group 80B in the second arrangement region 105B.

[0456] In the case where the plurality of first short wirings 111 include a plurality of other-side first short wirings 111, the plurality of other-side first short wirings 111 are arranged at intervals in the first direction X in the region on the second wiring group 80B. That is, the plurality of other-side first short wirings 111 are arranged in a comb shape extending in the second direction Y in the region on the second wiring group 80B.

[0457] Either one or both of the one-side and other-side first short wirings 111 can also overlap the inter-wiring region IWR. In this case, either one or both of the one-side and other-side first short wirings 111 overlap either one or both of the third lower wiring 83 and the fourth lower wiring 84, and are electrically isolated from both the third lower wiring 83 and the fourth lower wiring 84 by the second interlayer film 72.

[0458] Of course, the plurality of first draw-out wirings 109 can also include an intermediate first short wiring 111 overlapping the inter-wiring region IWR. In this case, the intermediate first short wiring 111 can also be drawn out from a region on the inter-wiring region IWR onto both the first wiring group 80A and the second wiring group 80B adjacent in the first direction X.

[0459] The intermediate first short wiring 111 can also be electrically connected to at least one (e.g., a plurality of) first lower wiring 81 of the first wiring group 80A and at least one (e.g., a plurality of) first lower wiring 81 of the second wiring group 80B in the first layout region 105A.

[0460] The intermediate first short wiring 111 can also cross (orthogonally) at least one (e.g., a plurality of) first lower wiring 81 and at least one (e.g., a plurality of) second lower wiring 82 of the first wiring group 80A in the first layout region 105A. In addition, the intermediate first short wiring 111 can also cross (orthogonally) at least one (e.g., a plurality of) first lower wiring 81 and at least one (e.g., a plurality of) second lower wiring 82 of the second wiring group 80B in the first layout region 105A.

[0461] The intermediate first short wiring 111 can also extend from the first layout region 105A to the second layout region 105B in the second direction Y across the boundary portion 107. The intermediate first short wiring 111 can also cross (orthogonally) at least one (e.g., a plurality of) first lower wiring 81 and at least one (e.g., a plurality of) second lower wiring 82 of the first wiring group 80A in both the first layout region 105A and the second layout region 105B.

[0462] In addition, the intermediate first short wiring 111 can also cross (orthogonally) at least one (e.g., a plurality of) first lower wiring 81 and at least one (e.g., a plurality of) second lower wiring 82 of the second wiring group 80B in both the first layout region 105A and the second layout region 105B.

[0463] The intermediate first short wiring 111 can also be electrically connected to at least one (e.g., a plurality of) first lower wiring 81 of the first wiring group 80A and at least one (e.g., a plurality of) first lower wiring 81 of the second wiring group 80B in the first layout region 105A. In addition, the intermediate first short wiring 111 can also be electrically connected to at least one (e.g., a plurality of) first lower wiring 81 of the first wiring group 80A and at least one (e.g., a plurality of) first lower wiring 81 of the second wiring group 80B in the second layout region 105B.

[0464] The intermediate first short wiring 111 can also overlap the third lower wiring 83 (the first gate wiring 85 and / or the second gate wiring 86) in a portion covering the inter-wiring region IWR. In this case, the intermediate first short wiring 111 opposes the third lower wiring 83 (the first gate wiring 85 and / or the second gate wiring 86) through the second interlayer film 72 and is electrically isolated from the third lower wiring 83.

[0465] The intermediate first short wiring line 111 can also overlap the fourth lower wiring line 84 (first base wiring line 88) at a portion covering the inter-wiring region IWR. In this case, the intermediate first short wiring line 111 faces the fourth lower wiring line 84 (first base wiring line 88) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the fourth lower wiring line 84.

[0466] The first interconnection wiring structure 108 includes at least one (in this embodiment, a plurality of) second lead-out wiring line 113 led out from the second pad wiring line 102 toward the first pad wiring line 101 in the second direction Y. The plurality of second lead-out wiring lines 113 are electrically connected to either or both of at least one second lower wiring line 82 of the first wiring group 80A and at least one second lower wiring line 82 of the second wiring group 80B in a region between the first pad wiring line 101 and the second pad wiring line 102.

[0467] The plurality of second lead-out wiring lines 113 include at least one (in this embodiment, one) second long wiring line 114 that is relatively long, and at least one (in this embodiment, a plurality of) second short wiring line 115 that is shorter than the second long wiring line 114. The second long wiring line 114 can also be referred to as a "second long lead-out wiring line", a "second main lead-out wiring line", or the like. The second short wiring line 115 can also be referred to as a "second short lead-out wiring line", a "second sub lead-out wiring line", or the like.

[0468] The number of second short wiring lines 115 is arbitrary and is appropriately adjusted in accordance with the size of the second pad wiring line 102 or the like. The number of second short wiring lines 115 can also be one or more and 50 or less. The number of second short wiring lines 115 can also have a value in a range of one or more and five or less, five or more and ten or less, ten or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, 40 or more and 50 or less, or at least one of these ranges.

[0469] The number of second short wiring lines 115 is preferably equal to the number of first short wiring lines 111. According to this structure, the variation in wiring resistance between the first short wiring lines 111 and the second short wiring lines 115 can be suppressed. In this embodiment, two second short wiring lines 115 are provided.

[0470] The second long wiring line 114 has a width in the first direction X that is smaller than the width of the second pad wiring line 102 (first pad wiring line 101), and is led out in a band shape from the second end portion of the second pad wiring line 102 toward the second wiring group 80B (second active region 6B) in the second direction Y. The width of the second long wiring line 114 is greater than the width of the second lower wiring line 82 (first lower wiring line 81). The second long wiring line 114 preferably has a width in the first direction X that is substantially equal to the width of the first long wiring line 110. According to this structure, the variation in wiring resistance between the first long wiring line 110 and the second long wiring line 114 can be suppressed.

[0471] The second long wiring line 114 is provided at intervals in the first direction X from the plurality of first lead-out wiring lines 109 (the first long wiring line 110 and the plurality of first short wiring lines 111) opposite to the plurality of first lead-out wiring lines 109 in the first direction X. In this way, the second long wiring line 114 crosses (orthogonally) at least one (in this way, a plurality) of the first lower wiring lines 81 and at least one (in this way, a plurality) of the second lower wiring lines 82 of the second wiring group 80B in the second arrangement region 105B.

[0472] The second long wiring line 114 is drawn out from the second arrangement region 105B to the first arrangement region 105A in the second direction Y across the boundary portion 107. In this way, the second long wiring line 114 crosses (orthogonally) at least one (in this way, a plurality) of the first lower wiring lines 81 and at least one (in this way, a plurality) of the second lower wiring lines 82 in both the first arrangement region 105A and the second arrangement region 105B.

[0473] The second long wiring line 114 is electrically connected to at least one (in this way, a plurality) of the second lower wiring lines 82 of the second wiring group 80B in the second arrangement region 105B. In addition, the second long wiring line 114 is electrically connected to at least one (in this way, a plurality) of the second lower wiring lines 82 of the second wiring group 80B in the first arrangement region 105A.

[0474] The second long wiring line 114 crosses (orthogonally) one or a plurality (preferably all) of the first lower wiring lines 81 and one or a plurality (preferably all) of the second lower wiring lines 82 directly below at least one (in this way, one) of the first lead-out wiring lines 109 (the other-side first short wiring line 111) in the first direction X in a region between the first pad wiring line 101 and the second pad wiring line 102.

[0475] The second long wiring line 114 is electrically connected to a portion of one or a plurality (preferably all) of the second lower wiring lines 82 exposed from the other-side first short wiring line 111 covered by the other-side first short wiring line 111. On the other hand, the second long wiring line 114 is electrically isolated from one or a plurality (preferably all) of the first lower wiring lines 81 directly below the other-side first short wiring line 111.

[0476] The second long wiring line 114 forms, together with the first short wiring line 111 on the other side in the first direction X, a current path of the drain-source current Ids. Specifically, the current path of the drain-source current Ids is formed between the first short wiring line 111 and the second long wiring line 114 on the other side via the first lower wiring line 81 and the second lower wiring line 82 passing directly below both the first short wiring line 111 and the second long wiring line 114 on the other side in the first direction X. Such a layout is effective in reducing the wiring resistance between the first pad wiring line 101 and the second pad wiring line 102.

[0477] The second long wiring line 114 has a second opposing portion 116 drawn out to a region opposite the first pad wiring line 101 in the first direction X. The second opposing portion 116 is opposite the entire region of the second end portion of the first pad wiring line 101 in the first direction X. The second opposing portion 116 (second long wiring line 114) crosses (orthogonally) the one or more (preferably all) first lower wiring lines 81 and the one or more (preferably all) second lower wiring lines 82 passing directly below the first pad wiring line 101 in the first direction X with respect to the second wiring group 80B.

[0478] The second opposing portion 116 is electrically connected to the portion of the one or more (preferably all) second lower wiring lines 82 exposed from the first pad wiring line 101 covered by the first pad wiring line 101. On the other hand, the second opposing portion 116 is electrically isolated from the one or more (preferably all) first lower wiring lines 81 passing directly below the first pad wiring line 101.

[0479] The second opposing portion 116 (second long wiring line 114) forms, together with the first pad wiring line 101 on the other side in the first direction X, a current path of the drain-source current Ids. Specifically, the current path of the drain-source current Ids is formed between the first pad wiring line 101 and the second long wiring line 114 via the first lower wiring line 81 and the second lower wiring line 82 passing directly below both the first pad wiring line 101 and the second long wiring line 114 in the first direction X. Such a layout is effective in reducing the wiring resistance between the first pad wiring line 101 and the second pad wiring line 102.

[0480] The plurality of second short wiring lines 115 each have a width smaller than the width of the second pad wiring line 102 (first pad wiring line 101) in the first direction X with respect to the region on the first end portion side of the second long wiring line 114. The width of the second short wiring line 115 can also be substantially equal to the width of the second long wiring line 114. The width of the second short wiring line 115 can also be greater than the width of the second long wiring line 114. The width of the second short wiring line 115 can also be smaller than the width of the second long wiring line 114.

[0481] The width of the second short wiring 115 is larger than the width of the second lower wiring 82 (the first lower wiring 81). The width of the second short wiring 115 is preferably substantially equal to the width of the first short wiring 111. According to this structure, the variation in the wiring resistance between the first short wiring 111 and the second short wiring 115 can be suppressed.

[0482] The plurality of second short wirings 115 are arranged at intervals in the first direction X and are led out in a band shape (in this case, a long rectangular shape) from the second pad wiring 102 toward the first pad wiring 101 in the second direction Y. The plurality of second short wirings 115 can also be led out in a trapezoidal shape (preferably, an isosceles trapezoidal shape) or a triangular shape (preferably, an isosceles triangular shape).

[0483] The plurality of second short wirings 115 are arranged in a comb-tooth shape extending in the second direction Y and facing each other in the first direction X. The plurality of second short wirings 115 face the plurality of first lead-out wirings 109 in the first direction X. Specifically, the plurality of second short wirings 115 respectively enter the regions between the plurality of first lead-out wirings 109 and extend in the second direction Y in the regions between the plurality of first lead-out wirings 109.

[0484] That is, the plurality of second lead-out wirings 113 include one second short wiring 115 disposed in the region between the first long wiring 110 and the first short wiring 111 and the second short wirings 115 disposed in the regions between the plurality of first short wirings 111. Thus, the plurality of second short wirings 115 are arranged alternately with the plurality of first short wirings 111 in the first direction X. That is, the plurality of second short wirings 115 are arranged in a comb-tooth shape engaged with the plurality of first short wirings 111.

[0485] The second short wiring 115 preferably has a length in the second direction Y substantially equal to the length of the first short wiring 111. According to this structure, the variation in the wiring resistance between the first short wiring 111 and the second short wiring 115 can be suppressed. The plurality of second short wirings 115 are formed at intervals from the first pad wiring 101 on the side of the second pad wiring 102 and face the first pad wiring 101 in the second direction Y.

[0486] The second short wiring 115 is electrically connected to at least one (in this case, a plurality) of the second lower wirings 82 in the region between the first pad wiring 101 and the second pad wiring 102. Specifically, in this case, the plurality of second short wirings 115 include one or more (in this case, one) first-side second short wirings 115 and one or more (in this case, one) second-side second short wirings 115. The number of the second-side second short wirings 115 is preferably equal to the number of the first-side second short wirings 115.

[0487] The one-side second short wiring 115 is drawn out from the second pad wiring 102 onto the first wiring group 80A (the first active region 6A) in a region on the first wiring group 80A opposite the first pad wiring 101 in the second direction Y. The one-side second short wiring 115 is electrically connected to at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A. In this case, the one-side second short wiring 115 crosses (orthogonally) at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in the second arrangement region 105B.

[0488] The one-side second short wiring 115 crosses the boundary portion 107 in the second direction Y, and is drawn out from the second arrangement region 105B to the first arrangement region 105A. In this case, the one-side second short wiring 115 crosses (orthogonally) at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in both the first arrangement region 105A and the second arrangement region 105B.

[0489] The one-side second short wiring 115 is electrically connected to at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in the second arrangement region 105B. In addition, the one-side second short wiring 115 is electrically connected to at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in the first arrangement region 105A.

[0490] The one-side second short wiring 115 crosses (orthogonally) one or more of the first lower wirings 81 and one or more of the second lower wirings 82 directly below at least one (in this case, a plurality) of the first draw wirings 109 (the first long wiring 110 and the first short wiring 111) in the first direction X with respect to the first wiring group 80A.

[0491] The one-side second short wiring 115 is electrically connected to a portion of one or more (in this case, a plurality) of the second lower wirings 82 exposed from the plurality of first draw wirings 109 covered by the plurality of first draw wirings 109. On the other hand, the one-side second short wiring 115 is electrically isolated from one or more (in this case, a plurality) of the first lower wirings 81 directly below the plurality of first draw wirings 109.

[0492] The second short wiring 115 on one side forms a current path of the drain-source current Ids together with the plurality of first lead-out wirings 109 which are opposed (close to be opposed) in the first direction X. Specifically, the current path of the drain-source current Ids is formed between the plurality of first lead-out wirings 109 and the second short wiring 115 on one side via the first lower wiring 81 and the second lower wiring 82 which pass directly below both of the plurality of first lead-out wirings 109 and the second short wiring 115 on one side in the first direction X. Such a layout is effective in reducing the wiring resistance between the first pad wiring 101 and the second pad wiring 102.

[0493] In a case where the plurality of second short wirings 115 include the plurality of second short wirings 115 on one side, the plurality of second short wirings 115 on one side are arranged at intervals in the first direction X in the region on the first wiring group 80A. That is, the plurality of second short wirings 115 on one side are arranged in a comb shape extending in the second direction Y in the region on the first wiring group 80A. For example, the plurality of second short wirings 115 on one side are arranged in a comb shape engaged with the plurality of first short wirings 111 on one side in the region on the first wiring group 80A.

[0494] The second short wiring 115 on the other side is drawn out from the second pad wiring 102 onto the second wiring group 80B (the second active region 6B) which is opposed to the first pad wiring 101 in the second direction Y in the region on the second wiring group 80B. The second short wiring 115 on the other side is electrically connected to at least one (in this mode, a plurality) of the second lower wirings 82 of the second wiring group 80B. In this mode, the second short wiring 115 on the other side crosses (is orthogonal to) at least one (in this mode, a plurality) of the first lower wirings 81 and at least one (in this mode, a plurality) of the second lower wirings 82 of the second wiring group 80B in the second arrangement region 105B.

[0495] The second short wiring 115 on the other side crosses the boundary portion 107 in the second direction Y and is drawn out from the second arrangement region 105B to the first arrangement region 105A. In this mode, the second short wiring 115 on the other side crosses (is orthogonal to) at least one (in this mode, a plurality) of the first lower wirings 81 and at least one (in this mode, a plurality) of the second lower wirings 82 of the second wiring group 80B in both the first arrangement region 105A and the second arrangement region 105B.

[0496] The second short wiring 115 on the other side is electrically connected to at least one (in this mode, a plurality) of the second lower wirings 82 of the second wiring group 80B in the second arrangement region 105B. In addition, the second short wiring 115 on the other side is electrically connected to at least one (in this mode, a plurality) of the second lower wirings 82 of the second wiring group 80B in the first arrangement region 105A.

[0497] The second short wiring 115 on the other side crosses (is orthogonal to) at least one (in this mode, a plurality) of the first lower wirings 81 and at least one (in this mode, a plurality) of the second lower wirings 82 directly below the second long wiring 114 in the first direction X. That is, the second short wiring 115 on the other side is electrically connected to a portion of the at least one (in this mode, a plurality) of the second lower wirings 82 covered by the second long wiring 114 that is exposed from the second long wiring 114.

[0498] The second short wiring 115 on the other side crosses (is orthogonal to) one or more of the first lower wirings 81 and one or more of the second lower wirings 82 directly below the at least one (in this mode, one) of the first lead wirings 109 (the first short wiring 111 on the other side) in the first direction X with respect to the second wiring group 80B.

[0499] The second short wiring 115 on the other side is electrically connected to a portion of the one or more (in this mode, a plurality) of the second lower wirings 82 covered by the first lead wiring 109 that is exposed from the first short wiring 111 on the other side. On the other hand, the second short wiring 115 on the other side is electrically isolated from the one or more (in this mode, a plurality) of the first lower wirings 81 directly below the first lead wiring 109.

[0500] The second short wiring 115 on the other side forms a current path of the drain-source current Ids together with the first lead wiring 109 opposite (proximally opposite) in the first direction X. Specifically, the current path of the drain-source current Ids is formed between the first lead wiring 109 and the second short wiring 115 on the other side via the first lower wirings 81 and the second lower wirings 82 directly below both the first lead wiring 109 and the second short wiring 115 on the other side in the first direction X. Such a layout is effective in reducing the wiring resistance between the first pad wiring 101 and the second pad wiring 102.

[0501] In a case where the plurality of second short wirings 115 includes the plurality of second short wirings 115 on the other side, the plurality of second short wirings 115 on the other side are arranged at intervals in the first direction X in the region on the second wiring group 80B. That is, the plurality of second short wirings 115 on the other side are arranged in a comb shape extending in the second direction Y in the region on the second wiring group 80B. For example, the plurality of second short wirings 115 on the other side are arranged in a comb shape engaged with the plurality of first short wirings 111 on the other side in the region on the second wiring group 80B.

[0502] Either or both of the one-side and the other-side second short wiring 115 can also overlap the inter-wiring region IWR. In this case, either or both of the one-side and the other-side second short wiring 115 overlap either or both of the third lower wiring 83 and the fourth lower wiring 84, and are electrically isolated from both the third lower wiring 83 and the fourth lower wiring 84 by the second interlayer film 72.

[0503] Of course, the plurality of second lead-out wirings 113 can also include the intermediate second short wiring 115 overlapping the inter-wiring region IWR, depending on the layout of the first lead-out wiring 109. In this case, the intermediate second short wiring 115 can also be lead out from the region on the inter-wiring region IWR to both the first wiring group 80A and the second wiring group 80B adjacent in the first direction X.

[0504] The intermediate second short wiring 115 can also be electrically connected to at least one (e.g., a plurality of) second lower wiring 82 of the first wiring group 80A and at least one (e.g., a plurality of) second lower wiring 82 of the second wiring group 80B.

[0505] The intermediate second short wiring 115 can also cross (orthogonally) at least one (e.g., a plurality of) first lower wiring 81 and at least one (e.g., a plurality of) second lower wiring 82 of the first wiring group 80A in the second arrangement region 105B. In addition, the intermediate second short wiring 115 can also cross (orthogonally) at least one (e.g., a plurality of) first lower wiring 81 and at least one (e.g., a plurality of) second lower wiring 82 of the second wiring group 80B in the second arrangement region 105B.

[0506] The intermediate second short wiring 115 can also cross (orthogonally) at least one (e.g., a plurality of) first lower wiring 81 and at least one (e.g., a plurality of) second lower wiring 82 of the first wiring group 80A in the second arrangement region 105B. In addition, the intermediate second short wiring 115 can also cross (orthogonally) at least one (e.g., a plurality of) first lower wiring 81 and at least one (e.g., a plurality of) second lower wiring 82 of the second wiring group 80B in the second arrangement region 105B.

[0507] In addition, the intermediate second short wiring 115 can also cross (orthogonally) at least one (e.g., a plurality of) first lower wiring 81 and at least one (e.g., a plurality of) second lower wiring 82 of the second wiring group 80B in both the first arrangement region 105A and the second arrangement region 105B.

[0508] The intermediate second short wiring 115 can also be electrically connected to at least one (e.g., a plurality) of the second lower wirings 82 of the first wiring group 80A and at least one (e.g., a plurality) of the second lower wirings 82 of the second wiring group 80B in the first configuration region 105A. In addition, the intermediate second short wiring 115 can also be electrically connected to at least one (e.g., a plurality) of the second lower wirings 82 of the first wiring group 80A and at least one (e.g., a plurality) of the second lower wirings 82 of the second wiring group 80B in the second configuration region 105B.

[0509] The intermediate second short wiring 115 can also be opposed to one side first short wiring 111 and the other side first short wiring 111 on both sides of the first direction X. In this case, the intermediate second short wiring 115 forms a current path of the drain-source current Ids together with the one side first short wiring 111 and the other side first short wiring 111 which are opposed (proximally opposed) on both sides of the first direction X.

[0510] The intermediate second short wiring 115 can also overlap the third lower wiring 83 (the first gate wiring 85 and / or the second gate wiring 86) in a portion covering the wiring interval region IWR. In this case, the intermediate second short wiring 115 is opposed to the third lower wiring 83 (the first gate wiring 85 and / or the second gate wiring 86) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the third lower wiring 83.

[0511] The intermediate second short wiring 115 can also overlap the fourth lower wiring 84 (the first base wiring 88) in a portion covering the wiring interval region IWR. In this case, the intermediate second short wiring 115 is opposed to the fourth lower wiring 84 (the first base wiring 88) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the fourth lower wiring 84.

[0512] In this way, the first wiring unit U1 includes the first upper wiring and the second upper wiring. The first upper wiring includes the first pad wiring 101 and the plurality of first lead-out wirings 109, and the second upper wiring includes the second pad wiring 102 and the plurality of second lead-out wirings 113. In this structure, it is preferable that the second upper wiring have a planar layout which is substantially congruent to the planar layout of the first upper wiring.

[0513] That is, it is preferable that the planar shape of the second upper wiring be substantially congruent to the planar shape of the first upper wiring, and the planar area of the second upper wiring be substantially congruent to the planar area of the first upper wiring. It is preferable that the second upper wiring be arranged in point symmetry with respect to the first upper wiring, with the central portion of the boundary portion 107 as the center.

[0514] The first wiring unit U1 includes a wiring gap which electrically isolates the first upper wiring and the second upper wiring. The wiring gap is a portion in which a portion of the interlayer film 70 (the second interlayer film 72) is exposed, and is divided into regions between the first upper wiring and the second upper wiring.

[0515] The width of the wiring gap can also be 0.1 μm or more and 50 μm or less. The width of the wiring gap can also have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or less and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, and 25 μm or more and 30 μm or less.

[0516] The first wiring unit U1 includes multiple first upper via electrodes 117 and multiple second upper via electrodes 118 respectively embedded in the second interlayer film 72. The first upper via electrode 117 is a plug electrode that transmits the first drain-source potential to the first lower wiring 81. The second upper via electrode 118 is a plug electrode that transmits the second drain-source potential to the second lower wiring 82. The first upper via electrode 117 can also be referred to as the "first drain-source upper via electrode". The second upper via electrode 118 can also be referred to as the "second drain-source upper via electrode".

[0517] The plurality of first upper via electrodes 117 are arranged in a matrix with spacing between them relative to the plurality of first lower wirings 81 in the first direction X and the second direction Y. Alternatively, the plurality of first upper via electrodes 117 may be arranged in a staggered pattern with spacing between them relative to the plurality of first lower wirings 81 in the first direction X and the second direction Y. In this case, the regions of the plurality of first upper via electrodes 117 connected to one first lower wiring 81 in the second direction Y are opposite to the regions of the plurality of first upper via electrodes 117 connected to another first lower wiring 81.

[0518] The plurality of second upper via electrodes 118 are arranged in a matrix with spacing between them relative to the plurality of second lower wirings 82 in the first direction X and the second direction Y. Alternatively, the plurality of second upper via electrodes 118 may be arranged in a staggered pattern with spacing between them relative to the plurality of second lower wirings 82 in the first direction X and the second direction Y. In this case, the regions in the second direction Y between the plurality of second upper via electrodes 118 connected to one second lower wiring 82 and the plurality of second upper via electrodes 118 connected to another second lower wiring 82 are opposite.

[0519] In this mode, the first to second upper via electrodes 117, 118 each include a first electrode 119 and a second electrode 120. The first electrode 119 covers the wall surface of the via formed in the second interlayer film 72 in a film shape. The first electrode 119 can include one or both of a Ti film and a Ti alloy film. The Ti alloy film can also be a TiN film.

[0520] The second electrode 120 is embedded in the via via the first electrode 119. The second electrode 120 can include at least one of W, Al, an Al alloy, Cu, and a Cu alloy. The Al alloy can include at least one of an AlSi alloy, an AlCu alloy, and an AlSiCu alloy.

[0521] The first to second upper via electrodes 117, 118 can also be formed in a triangular shape, a quadrangular shape, a rectangular shape, a polygonal shape, a circular shape, or an elliptical shape in plan view. Of course, the first to second upper via electrodes 117, 118 can also be formed in a band shape (for example, a rectangular shape) extending in the first direction X.

[0522] The plurality of first upper via electrodes 117 exist in the second interlayer film 72 in a region between the plurality of first lower wirings 81 and the first pad wiring 101, and electrically connect the first pad wiring 101 and the plurality of first lower wirings 81. The first wiring unit U1 can have at least one first upper via electrode 117 between one first lower wiring 81 and the first pad wiring 101. In this mode, the plurality of first upper via electrodes 117 exist between 1 first lower wiring 81 and the first pad wiring 101.

[0523] In addition, the plurality of first upper via electrodes 117 exist in the second interlayer film 72 in a region between the plurality of first lower wirings 81 and the plurality of first lead-out wirings 109, and electrically connect the plurality of first lead-out wirings 109 and the plurality of first lower wirings 81. The first wiring unit U1 can have at least one first upper via electrode 117 between one first lower wiring 81 and one first lead-out wiring 109. In this mode, the plurality of first upper via electrodes 117 exist between one first lower wiring 81 and one first lead-out wiring 109.

[0524] The number of first upper via electrodes 117 existing between 1 first lower wiring 81 and 1 first lead-out wiring 109 is arbitrary. For example, the number of first upper via electrodes 117 can also be 1 or more and 50 or less. For example, the number of first upper via electrodes 117 can have a value in at least one range of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, and 40 or more and 50 or less.

[0525] The first upper via electrode 117 can also be formed using the first pad wiring 101 (the first lead-out wiring 109). In this case, the first electrode 119 of the first upper via electrode 117 is integrally formed with the first electrode 78 of the first pad wiring 101 (the first lead-out wiring 109), forming one electrode film with the first electrode 78. Similarly, the second electrode 120 of the first upper via electrode 117 is integrally formed with the second electrode 79 of the first pad wiring 101 (the first lead-out wiring 109), forming one electrode with the second electrode 79.

[0526] The plurality of second upper via electrodes 118 exist in the second interlayer film 72 in regions between the plurality of second lower wirings 82 and the second pad wiring 102, electrically connecting the second pad wiring 102 with the plurality of second lower wirings 82. The first wiring unit U1 can have at least one second upper via electrode 118 between one second lower wiring 82 and the second pad wiring 102. In this mode, the plurality of second upper via electrodes 118 exist between one second lower wiring 82 and the second pad wiring 102.

[0527] In addition, the plurality of second upper via electrodes 118 exist in the second interlayer film 72 in regions between the plurality of second lower wirings 82 and the plurality of second lead-out wirings 113, electrically connecting the plurality of second lead-out wirings 113 with the plurality of second lower wirings 82. The first wiring unit U1 can have at least one second upper via electrode 118 between one second lower wiring 82 and one second lead-out wiring 113. In this mode, the plurality of second upper via electrodes 118 exist between one second lower wiring 82 and one second lead-out wiring 113.

[0528] The number of second upper via electrodes 118 existing between one second lower wiring 82 and one second lead-out wiring 113 is arbitrary. For example, the number of second upper via electrodes 118 can also be one or more and 50 or less. For example, the number of second upper via electrodes 118 can also have a value in a range belonging to at least one of one or more and 5 or less, 5 or more and 10 or less, 10 or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, and 40 or more and 50 or less.

[0529] The number of second upper via electrodes 118 connected to one second lead-out wiring 113 is preferably approximately equal to the number of first upper via electrodes 117 connected to one first lead-out wiring 109. The number of second upper via electrodes 118 connected to the second pad wiring 102 is preferably approximately equal to the number of first upper via electrodes 117 connected to the first pad wiring 101.

[0530] The number of the second upper via electrodes 118 connected to the second pad wiring 102 and the plurality of second lead-out wirings 113 is preferably substantially equal to the number of the first upper via electrodes 117 connected to the first pad wiring 101 and the plurality of first lead-out wirings 109. According to these configurations, the variation in wiring resistance can be suppressed.

[0531] The second upper via electrode 118 can also be formed using the second pad wiring 102 (the second lead-out wiring 113). In this case, the first electrode 119 of the second upper via electrode 118 is integrally formed with the first electrode 78 of the second pad wiring 102 (the second lead-out wiring 113), forming one electrode film with the first electrode 78. Similarly, the second electrode 120 of the second upper via electrode 118 is integrally formed with the second electrode 79 of the second pad wiring 102 (the second lead-out wiring 113), forming one electrode with the second electrode 79.

[0532] The first interconnection wiring structure 108 can have various layouts. Hereinafter, the first layout example will be described with reference to FIG. 1. Figures 16B-16J The second to tenth layout examples will be described. The first layout example will be described with reference to FIG. 1. Figure 16B (Second Layout Example), the first interconnection wiring structure 108 includes a plurality of first lead-out wirings 109. The plurality of first lead-out wirings 109 includes a first long wiring 110 and a single first short wiring 111. The layout of the first long wiring 110 is the same as in the case of the first layout example.

[0533] In this manner, the first short wiring 111 is drawn out from the region on the second end portion side of the first pad wiring 101 with respect to the first end portion (the first long wiring 110) of the first pad wiring 101 in a triangular shape. The first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0534] The first short wiring 111 covers at least one (in this manner, a plurality) of the first lower wirings 81 and at least one (in this manner, a plurality) of the second lower wirings 82 of the first wiring group 80A in the first arrangement region 105A. In addition, the first short wiring 111 covers at least one (in this manner, a plurality) of the first lower wirings 81 and at least one (in this manner, a plurality) of the second lower wirings 82 of the second wiring group 80B in the first arrangement region 105A.

[0535] The first short wiring 111 is drawn out from the first arrangement region 105A to the second arrangement region 105B in the second direction Y across the boundary portion 107. In this manner, the first short wiring 111 covers at least one (in this manner, a plurality) of the first lower wirings 81 and at least one (in this manner, a plurality) of the second lower wirings 82 of the first wiring group 80A in the second arrangement region 105B.

[0536] The first short wiring 111 is electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the first wiring group 80A and at least one (in this case, a plurality) of the first lower wirings 81 of the second wiring group 80B in the first layout region 105A. In addition, the first short wiring 111 is electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the first wiring group 80A in the second layout region 105B. The first short wiring 111 is electrically connected to the corresponding first lower wiring 81 via a plurality of first upper via electrodes 117, as in the case of the first layout example.

[0537] The first short wiring 111 can also cover at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the second wiring group 80B in the second layout region 105B. In this case, the first short wiring 111 can also be electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the second wiring group 80B in the second layout region 105B.

[0538] The first short wiring 111 has a first inclined portion that is inclined from the second end portion of the first pad wiring 101 toward the first end portion side of the second pad wiring 102. The extension direction (inclined direction) of the first inclined portion is a direction that intersects both the first direction X and the second direction Y. The first inclined portion crosses the inter-wiring region IWR in the inclined direction. In this case, the intersection (point of intersection) of the first inclined portion and the inter-wiring region IWR is located on the boundary portion 107.

[0539] The first inclined portion also has a front end portion that crosses the boundary portion 107 in the inclined direction and is connected to the first long wiring 110 in the second layout region 105B. The first inclined portion is formed apart from the second pad wiring 102 in the second direction Y on the first pad wiring 101 side in the second layout region 105B.

[0540] The first short wiring 111 overlaps the third lower wiring 83 in the portion that covers the inter-wiring region IWR. In this case, the first short wiring 111 overlaps both the first gate wiring 85 and the second gate wiring 86. The first short wiring 111 opposes the third lower wiring 83 (the first gate wiring 85 and the second gate wiring 86) with the second interlayer film 72 interposed therebetween and is electrically isolated from the third lower wiring 83.

[0541] The first short wiring 111 overlaps the fourth lower wiring 84 in the portion that covers the inter-wiring region IWR. In this case, the first short wiring 111 overlaps the first source wiring 88. The first short wiring 111 opposes the fourth lower wiring 84 (the first source wiring 88) with the second interlayer film 72 interposed therebetween and is electrically isolated from the fourth lower wiring 84.

[0542] The first interconnection wiring structure 108 includes a plurality of second lead lines 113. The plurality of second lead lines 113 includes a second long lead line 114 and a single second short lead line 115. The layout of the second long lead line 114 is the same as in the case of the first layout example.

[0543] In this manner, the second short lead line 115 is led out from the region of the first end portion side of the second land wiring 102 as a triangular shape with respect to the second end portion (second long lead line 114) of the second land wiring 102. The second short lead line 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first land wiring 101 and the second land wiring 102.

[0544] The second short lead line 115 covers at least one (in this manner, a plurality) of the first lower lead lines 81 and at least one (in this manner, a plurality) of the second lower lead lines 82 of the first wiring group 80A in the second arrangement region 105B. In addition, the second short lead line 115 covers at least one (in this manner, a plurality) of the first lower lead lines 81 and at least one (in this manner, a plurality) of the second lower lead lines 82 of the second wiring group 80B in the second arrangement region 105B.

[0545] The second short lead line 115 is led out from the second arrangement region 105B to the first arrangement region 105A in the second direction Y across the boundary portion 107. In this manner, the second short lead line 115 covers at least one (in this manner, a plurality) of the first lower lead lines 81 and at least one (in this manner, a plurality) of the second lower lead lines 82 of the second wiring group 80B in the first arrangement region 105A.

[0546] The second short lead line 115 is electrically connected to at least one (in this manner, a plurality) of the second lower lead lines 82 of the first wiring group 80A and at least one (in this manner, a plurality) of the second lower lead lines 82 of the second wiring group 80B in the second arrangement region 105B. In addition, the second short lead line 115 is electrically connected to at least one (in this manner, a plurality) of the second lower lead lines 82 of the second wiring group 80B in the first arrangement region 105A. The second short lead line 115 is electrically connected to the corresponding second lower lead line 82 via the plurality of second upper via electrodes 118 as in the case of the first layout example.

[0547] The second short lead line 115 can also cover at least one (in this manner, a plurality) of the first lower lead lines 81 and at least one (in this manner, a plurality) of the second lower lead lines 82 of the first wiring group 80A in the first arrangement region 105A. In this case, the second short lead line 115 can also be electrically connected to at least one (in this manner, a plurality) of the second lower lead lines 82 of the first wiring group 80A in the first arrangement region 105A.

[0548] The second short wiring 115 has a second inclined portion which is inclined from the first end portion of the second pad wiring 102 toward the second end portion side of the first pad wiring 101. The extending direction (inclined direction) of the second inclined portion is a direction which intersects both the first direction X and the second direction Y. The second inclined portion crosses the inter-wiring region IWR in the inclined direction. In this way, the intersection (point of intersection) of the second inclined portion and the inter-wiring region IWR is located on the boundary portion 107.

[0549] The second inclined portion also has a front end portion which crosses the boundary portion 107 in the inclined direction and is connected to the second long wiring 114 in the first arrangement region 105A. The second inclined portion is formed apart from the first pad wiring 101 on the second pad wiring 102 side in the first arrangement region 105A, opposite the first pad wiring 101 in the second direction Y.

[0550] The second inclined portion extends apart from the first inclined portion along the first inclined portion. Preferably, the second inclined portion extends substantially in parallel with respect to the first inclined portion apart from the first inclined portion in the perpendicular direction of the first inclined portion. That is, it is preferable that the inclination angle of the second inclined portion is substantially equal to the inclination angle of the first inclined portion. The second short wiring 115 preferably has a planar layout which is substantially congruent with the planar layout of the first short wiring 111.

[0551] The second short wiring 115 covers, with respect to the first wiring group 80A, one or more (preferably all) of the first lower wirings 81 and one or more (preferably all) of the second lower wirings 82 which pass directly below the first short wiring 111 in the first direction X.

[0552] The second short wiring 115 is electrically connected, on the first wiring group 80A side, to the portion of one or more (preferably all) of the second lower wirings 82 which is exposed from the first short wiring 111, which is covered by the first short wiring 111. On the other hand, the second short wiring 115 is electrically isolated from one or more (preferably all) of the first lower wirings 81 which pass directly below the first short wiring 111.

[0553] Likewise, the second short wiring 115 covers, with respect to the second wiring group 80B, one or more (preferably all) of the first lower wirings 81 and one or more (preferably all) of the second lower wirings 82 which pass directly below the first short wiring 111 in the first direction X.

[0554] The second short wiring 115 is electrically connected, on the second wiring group 80B side, to the portion of one or more (preferably all) of the second lower wirings 82 which is exposed from the first short wiring 111, which is covered by the first short wiring 111. On the other hand, the second short wiring 115 is electrically isolated from one or more (preferably all) of the first lower wirings 81 which pass directly below the first short wiring 111.

[0555] Thus, the second short wiring 115 forms a current path of the drain-source current Ids together with the first short wiring 111 opposing (close opposing) in the first direction X in both the first wiring group 80A and the second wiring group 80B.

[0556] The second short wiring 115 overlaps the third lower wiring 83 in a portion covering the inter-wiring region IWR. In this mode, the second short wiring 115 overlaps both the first gate wiring 85 and the second gate wiring 86. The second short wiring 115 opposes the third lower wiring 83 (the first gate wiring 85 and the second gate wiring 86) through the second interlayer film 72 and is electrically isolated from the third lower wiring 83.

[0557] The second short wiring 115 overlaps the fourth lower wiring 84 in a portion covering the inter-wiring region IWR. In this mode, the second short wiring 115 overlaps the first base wiring 88. The second short wiring 115 opposes the fourth lower wiring 84 (the first base wiring 88) through the second interlayer film 72 and is electrically isolated from the fourth lower wiring 84.

[0558] Referring to Figure 16C The first interconnection wiring structure 108 includes a plurality of first lead-out wirings 109 in the third layout example. The plurality of first lead-out wirings 109 includes the first long wiring 110 and a single first short wiring 111. The layout of the first long wiring 110 is the same as in the case of the first layout example.

[0559] The first short wiring 111 is led out from a region of the second end portion side of the first pad wiring 101 in a triangular shape with respect to the first end portion (the first long wiring 110) of the first pad wiring 101. The first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in a region between the first pad wiring 101 and the second pad wiring 102.

[0560] The first short wiring 111 covers at least one (in this mode, a plurality) of the first lower wirings 81 and at least one (in this mode, a plurality) of the second lower wirings 82 of the first wiring group 80A in the first layout region 105A. In addition, the first short wiring 111 covers at least one (in this mode, a plurality) of the first lower wirings 81 and at least one (in this mode, a plurality) of the second lower wirings 82 of the second wiring group 80B in the first layout region 105A.

[0561] The first short wiring 111 is led out from the first layout region 105A to the second layout region 105B in the second direction Y across the boundary portion 107. In this mode, the first short wiring 111 covers at least one (in this mode, a plurality) of the first lower wirings 81 and at least one (in this mode, a plurality) of the second lower wirings 82 of the second wiring group 80B in the second layout region 105B.

[0562] The first short wiring 111 is electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the first wiring group 80A and at least one (in this case, a plurality) of the first lower wirings 81 of the second wiring group 80B in the first layout region 105A. In addition, the first short wiring 111 is electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the second wiring group 80B in the second layout region 105B.

[0563] The first short wiring 111 is electrically connected to the corresponding first lower wiring 81 via the plurality of first upper via electrodes 117, as in the case of the first layout example. The first short wiring 111 can also cover at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in the second layout region 105B. In this case, the first short wiring 111 can also be electrically connected to at least one (in this case, a plurality) of the first lower wirings 81 of the first wiring group 80A in the second layout region 105B.

[0564] In this case, the first short wiring 111 has a first edge portion that is drawn out from the second end portion of the first pad wiring 101 toward the second wiring group 80B in the second direction Y. The first edge portion forms one side extending in the second direction Y with the second end portion of the first pad wiring 101. The first edge portion crosses the boundary portion 107 in the second direction Y and is located in the second layout region 105B. The first edge portion is formed on the first pad wiring 101 side spaced apart from the second pad wiring 102 in the second layout region 105B and is opposite the second pad wiring 102 in the second direction Y.

[0565] In this case, the first inclined portion of the first short wiring 111 is inclined from the first end portion of the first pad wiring 101 toward the second end portion of the second pad wiring 102 and is opposite the first long wiring 110 in the first direction X. The first inclined portion crosses the inter-wiring region IWR in the inclined direction. In this case, the intersection (point of intersection) of the first inclined portion and the inter-wiring region IWR is located on the boundary portion 107.

[0566] The first inclined portion also crosses the boundary portion 107 along the inclined direction and is connected to the first edge portion in the second layout region 105B. That is, the leading end portion of the first inclined portion is located on the same line as the second end portion of the first pad wiring 101.

[0567] The first interconnection wiring structure 108 includes a plurality of second lead lines 113. The plurality of second lead lines 113 includes a second long wiring 114 and a single second short wiring 115. The layout of the second long wiring 114 is the same as in the case of the first layout example.

[0568] The second short wiring 115 is drawn out in a triangular shape from a region of the first end portion side of the second pad wiring 102, and is arranged in a region between the first long wiring 110 and the first short wiring 111. The second short wiring 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in a region between the first pad wiring 101 and the second pad wiring 102.

[0569] The second short wiring 115 covers at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in the second arrangement region 105B. In addition, the second short wiring 115 covers at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the second wiring group 80B in the second arrangement region 105B.

[0570] The second short wiring 115 is drawn out from the second arrangement region 105B to the first arrangement region 105A in the second direction Y across the boundary portion 107. In this case, the second short wiring 115 covers at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in the first arrangement region 105A.

[0571] The second short wiring 115 is electrically connected to at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A and at least one (in this case, a plurality) of the second lower wirings 82 of the second wiring group 80B in the second arrangement region 105B. In addition, the second short wiring 115 is electrically connected to at least one (in this case, a plurality) of the second lower wirings 82 of the first wiring group 80A in the first arrangement region 105A.

[0572] The second short wiring 115 is electrically connected to the corresponding second lower wiring 82 via the plurality of second upper via electrodes 118, as in the case of the first layout example. The second short wiring 115 can also cover at least one (in this case, a plurality) of the first lower wirings 81 and at least one (in this case, a plurality) of the second lower wirings 82 of the second wiring group 80B in the first arrangement region 105A. In this case, the second short wiring 115 can also be electrically connected to at least one (in this case, a plurality) of the second lower wirings 82 of the second wiring group 80B in the first arrangement region 105A.

[0573] In this mode, the second short wiring 115 has a second edge portion that is drawn out from the first end portion of the second pad wiring 102 in the second direction Y. The second edge portion forms an edge that extends in the second direction Y with the first end portion of the second pad wiring 102. The second edge portion is drawn out in the second direction Y across the boundary portion 107 in the first arrangement region 105A. The second edge portion is drawn out in the first arrangement region 105A from the first pad wiring 101 toward the first wiring group 80A at a spacing on the second pad wiring 102 side opposite the first pad wiring 101 in the second direction Y.

[0574] In this mode, the second inclined portion of the second short wiring 115 is inclined from the second end portion of the second pad wiring 102 toward the first end portion of the first pad wiring 101 opposite the second long wiring 114 in the first direction X. The second inclined portion crosses the inter-wiring region IWR in the inclined direction. In this mode, the intersection (point of intersection) of the second inclined portion and the inter-wiring region IWR is located on the boundary portion 107.

[0575] The second inclined portion also crosses the boundary portion 107 along the inclined direction to connect with the second edge portion in the first arrangement region 105A. That is, the leading end portion of the second inclined portion is located on the same line as the first end portion of the second pad wiring 102.

[0576] The second inclined portion extends along the first inclined portion at a spacing from the first inclined portion. Preferably, the second inclined portion extends substantially parallel to the first inclined portion at a spacing in the perpendicular direction to the first inclined portion from the first inclined portion. That is, it is preferable that the angle of inclination of the second inclined portion be substantially equal to the angle of inclination of the first inclined portion. The second short wiring 115 preferably has a planar layout that is substantially congruent to the planar layout of the first short wiring 111.

[0577] As with the case of the second layout example, the second short wiring 115 forms a current path of the drain-source current Ids together with the first short wiring 111 opposite (proximally opposite) in the first direction X in both the first wiring group 80A and the second wiring group 80B.

[0578] Referring to Figure 16D The fourth layout example, the first interconnect wiring structure 108 includes a plurality of first lead-out wirings 109. The plurality of first lead-out wirings 109 includes the first long wiring 110 and a single first short wiring 111. The layout of the first long wiring 110 is the same as in the case of the first layout example.

[0579] The first short wiring 111 is led out in a trapezoidal shape (a quadrangular shape) from a region of the second end portion side of the first pad wiring 101 with respect to the first end portion (the first long wiring 110) of the first pad wiring 101. The first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in a region between the first pad wiring 101 and the second pad wiring 102.

[0580] The first short wiring 111 is electrically connected to at least one (in this mode, a plurality) of the first lower wirings 81 of the first wiring group 80A and at least one (in this mode, a plurality) of the first lower wirings 81 of the second wiring group 80B in the first arrangement region 105A. In addition, the first short wiring 111 is electrically connected to at least one (in this mode, a plurality) of the first lower wirings 81 of the first wiring group 80A in the second arrangement region 105B.

[0581] The first short wiring 111 can also cover at least one (in this mode, a plurality) of the first lower wirings 81 and at least one (in this mode, a plurality) of the second lower wirings 82 of the second wiring group 80B in the second arrangement region 105B. In this case, the first short wiring 111 can also be electrically connected to at least one (in this mode, a plurality) of the first lower wirings 81 of the second wiring group 80B in the second arrangement region 105B.

[0582] The first short wiring 111 has a first front end portion and a first inclined portion. The first front end portion has a width smaller than a width of the first pad wiring 101 in the first direction X and is located on the second pad wiring 102 side with respect to the first pad wiring 101. The first front end portion extends in the first direction X at least on the first wiring group 80A side and is connected to the first long wiring 110.

[0583] In this mode, the first front end portion is located in the second arrangement region 105B. The first front end portion is formed apart from the second pad wiring 102 in the second arrangement region 105B on the first pad wiring 101 side and opposes the first end portion of the second pad wiring 102 in the second direction Y. The first front end portion extends substantially in parallel with respect to the first end portion of the second pad wiring 102.

[0584] The first inclined portion is formed apart from the second end portion of the first pad wiring 101 on the first end portion side of the first pad wiring 101 and exposes the second end portion of the first pad wiring 101. The first inclined portion is inclined from the inner side portion of the first pad wiring 101 toward the first end portion side of the second pad wiring 102. An extension direction (inclination direction) of the first inclined portion is a direction that intersects both the first direction X and the second direction Y.

[0585] The first inclined portion crosses the inter-wiring region IWR in the inclined direction. In this way, the intersection (point of intersection) of the first inclined portion and the inter-wiring region IWR is located on the boundary portion 107. The first inclined portion also crosses the boundary portion 107 in the inclined direction and is connected to the first front end portion in the second arrangement region 105B. Of course, the extension direction (inclined direction) of the first inclined portion can also be the second direction Y. In this case, it is preferable that the first inclined portion extend in the second direction Y on the first wiring group 80A or the inter-wiring region IWR.

[0586] The first interconnection wiring structure 108 includes a plurality of second lead lines 113. The plurality of second lead lines 113 includes a second long lead line 114 and a single second short lead line 115. The layout of the second long lead line 114 is the same as in the case of the first layout example.

[0587] The second short lead line 115 is drawn out from the region on the first end portion side of the second pad wiring 102 to the second end portion (second long lead line 114) of the second pad wiring 102 in a trapezoidal shape (quadrilateral shape). The second short lead line 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0588] The second short lead line 115 is electrically connected to at least one (in this case, a plurality) of the second lower wiring 82 of the first wiring group 80A and at least one (in this case, a plurality) of the second lower wiring 82 of the second wiring group 80B in the second arrangement region 105B. In addition, the second short lead line 115 is electrically connected to at least one (in this case, a plurality) of the second lower wiring 82 of the second wiring group 80B in the first arrangement region 105A.

[0589] The second short lead line 115 can also cover at least one (in this case, a plurality) of the first lower wiring 81 and at least one (in this case, a plurality) of the second lower wiring 82 of the first wiring group 80A in the first arrangement region 105A. In this case, the second short lead line 115 can also be electrically connected to at least one (in this case, a plurality) of the second lower wiring 82 of the first wiring group 80A in the first arrangement region 105A.

[0590] The second short lead line 115 has a second front end portion and a second inclined portion. The second front end portion has a width smaller than the width of the second pad wiring 102 in the first direction X and is located on the first pad wiring 101 side with respect to the second pad wiring 102. The second front end portion extends in the first direction X at least on the second wiring group 80B side and is connected to the second long lead line 114. It is preferable that the width of the second front end portion be substantially equal to the width of the first front end portion.

[0591] In this mode, the second front end portion is located in the first arrangement region 105A. The second front end portion is formed apart from the first pad wiring 101 in the first arrangement region 105A on the second pad wiring 102 side opposite the second end portion of the first pad wiring 101 in the second direction Y. The second front end portion extends substantially in parallel with the second end portion of the first pad wiring 101.

[0592] The second inclined portion is formed apart from the first end portion of the second pad wiring 102 on the second end portion side of the second pad wiring 102 so as to expose the first end portion of the second pad wiring 102. The second inclined portion is inclined from the inner side portion of the second pad wiring 102 toward the second end portion side of the first pad wiring 101. The extending direction (inclined direction) of the second inclined portion is a direction intersecting both the first direction X and the second direction Y.

[0593] The second inclined portion traverses the inter-wiring region IWR in the inclined direction. In this mode, the intersection (point of intersection) of the second inclined portion and the inter-wiring region IWR is located on the boundary portion 107. The second inclined portion also traverses the boundary portion 107 in the inclined direction, connecting with the second front end portion in the first arrangement region 105A. Of course, the extending direction (inclined direction) of the second inclined portion can also be the second direction Y. In this case, it is preferable for the second inclined portion to extend in the second direction Y on the second wiring group 80B or the inter-wiring region IWR.

[0594] The second inclined portion extends along the first inclined portion apart from the first inclined portion. It is preferable for the second inclined portion to extend substantially in parallel with the first inclined portion in the perpendicular direction of the first inclined portion apart from the first inclined portion. That is, it is preferable for the angle of inclination of the second inclined portion to be substantially equal to the angle of inclination of the first inclined portion. The second short wiring 115 preferably has a planar layout substantially congruent with the planar layout of the first short wiring 111.

[0595] As with the case of the second layout example, the second short wiring 115 forms a current path of the drain-source current Ids together with the first short wiring 111 in opposition (proximity opposition) in the first direction X in both the first wiring group 80A and the second wiring group 80B.

[0596] Referring to Figure 16E (Fifth layout example), the first interconnect wiring structure 108 includes a plurality of first lead-out wirings 109. The plurality of first lead-out wirings 109 includes the first long wiring 110 and a single first short wiring 111. The layout of the first long wiring 110 is the same as in the case of the first layout example.

[0597] The first short wiring 111 is led out in a trapezoidal shape (a quadrangular shape) from a region of the second end portion side of the first pad wiring 101 with respect to the first end portion (the first long wiring 110) of the first pad wiring 101. The first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in a region between the first pad wiring 101 and the second pad wiring 102.

[0598] The first short wiring 111 is electrically connected to at least one (in this mode, a plurality) of the first lower wirings 81 of the first wiring group 80A and at least one (in this mode, a plurality) of the first lower wirings 81 of the second wiring group 80B in the first arrangement region 105A. In addition, the first short wiring 111 is electrically connected to at least one (in this mode, a plurality) of the first lower wirings 81 of the second wiring group 80B in the second arrangement region 105B.

[0599] The first short wiring 111 can also cover at least one (in this mode, a plurality) of the first lower wirings 81 and at least one (in this mode, a plurality) of the second lower wirings 82 of the first wiring group 80A in the second arrangement region 105B. In this case, the first short wiring 111 can also be electrically connected to at least one (in this mode, a plurality) of the first lower wirings 81 of the first wiring group 80A in the second arrangement region 105B.

[0600] The first short wiring 111 has a first side portion led out from the second end portion of the first pad wiring 101 toward the second wiring group 80B in the second direction Y. The first side portion forms one side extending in the second direction Y with the second end portion of the first pad wiring 101. The first side portion is formed apart from the second pad wiring 102 in the first pad wiring 101 side in the second arrangement region 105B, opposite to the second pad wiring 102 in the second direction Y. The first side portion traverses the boundary portion 107 in the second direction Y.

[0601] The first front end portion of the first short wiring 111 has a width smaller than that of the first pad wiring 101 in the first direction X, located on the second pad wiring 102 side with respect to the first pad wiring 101. The first front end portion extends in the first direction X at least on the second wiring group 80B side, connected to the first side portion. In this mode, the first front end portion is formed apart from the second pad wiring 102 in the first pad wiring 101 side in the second arrangement region 105B, opposite to the second end portion of the second pad wiring 102 in the second direction Y. The first front end portion extends substantially in parallel with respect to the second end portion of the second pad wiring 102.

[0602] In this mode, the first inclined portion of the first short wiring line 111 is formed apart from the first end portion (the first long wiring line 110) of the first pad wiring line 101 on the second end portion side of the first pad wiring line 101, so that the first end portion of the first pad wiring line 101 is exposed. The first inclined portion is inclined from the inner portion of the first pad wiring line 101 toward the second end portion side of the second pad wiring line 102. The extension direction (inclined direction) of the first inclined portion is a direction intersecting both the first direction X and the second direction Y.

[0603] The first inclined portion crosses the inter-wiring region IWR in the inclined direction. In this mode, the intersection (point of intersection) of the first inclined portion and the inter-wiring region IWR is located on the boundary portion 107. The first inclined portion also crosses the boundary portion 107 in the inclined direction and is connected to the first front end portion in the second arrangement region 105B. Of course, the extension direction (inclined direction) of the first inclined portion can also be the second direction Y. In this case, it is preferable that the first inclined portion extend in the second direction Y on the second wiring group 80B or on the inter-wiring region IWR.

[0604] The first interconnection wiring structure 108 includes a plurality of second lead lines 113. The plurality of second lead lines 113 include a second long wiring line 114 and a single second short wiring line 115. The layout of the second long wiring line 114 is the same as in the case of the first layout example.

[0605] The second short wiring line 115 is drawn out in a trapezoidal shape (quadrilateral shape) from a region on the first end portion side of the second pad wiring line 102 with respect to the second end portion (the second long wiring line 114) of the second pad wiring line 102 and is arranged in a region between the first long wiring line 110 and the first short wiring line 111. The second short wiring line 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in a region between the first pad wiring line 101 and the second pad wiring line 102.

[0606] The second short wiring line 115 is electrically connected to at least one (in this mode, a plurality) of the second lower wiring lines 82 of the first wiring group 80A and at least one (in this mode, a plurality) of the second lower wiring lines 82 of the second wiring group 80B in the second arrangement region 105B. In addition, the second short wiring line 115 is electrically connected to at least one (in this mode, a plurality) of the second lower wiring lines 82 of the first wiring group 80A in the first arrangement region 105A.

[0607] The second short wiring line 115 can also cover at least one (in this mode, a plurality) of the first lower wiring lines 81 and at least one (in this mode, a plurality) of the second lower wiring lines 82 of the second wiring group 80B in the first arrangement region 105A. In this case, the second short wiring line 115 can also be electrically connected to at least one (in this mode, a plurality) of the second lower wiring lines 82 of the second wiring group 80B in the first arrangement region 105A.

[0608] In this mode, the second short wiring 115 has a second edge portion that is drawn out from the first end portion of the second pad wiring 102 toward the first wiring group 80A in the second direction Y. The second edge portion forms one side that extends in the second direction Y with the first end portion of the first pad wiring 101. The second edge portion is formed apart from the first pad wiring 101 on the second pad wiring 102 side in the first arrangement region 105A in the second direction Y.

[0609] The second front end portion has a width smaller than the width of the second pad wiring 102 in the first direction X, and is located on the first pad wiring 101 side with respect to the second pad wiring 102. The second front end portion extends at least on the first wiring group 80A side in the first direction X, and is connected to the second edge portion. In this mode, the second front end portion is formed apart from the first pad wiring 101 on the second pad wiring 102 side in the first arrangement region 105A in the second direction Y opposite the first end portion of the first pad wiring 101. The second front end portion extends substantially in parallel with respect to the first end portion of the first pad wiring 101.

[0610] In this mode, the second inclined portion is formed apart from the second end portion of the second pad wiring 102 (the second long wiring 114) on the first end portion side of the second pad wiring 102, so that the second end portion of the second pad wiring 102 is exposed. The second inclined portion is inclined from the inner portion of the second pad wiring 102 toward the first end portion side of the first pad wiring 101. The extension direction (inclination direction) of the second inclined portion is a direction that intersects both the first direction X and the second direction Y.

[0611] The second inclined portion crosses the inter-wiring region IWR in the inclination direction. In this mode, the intersection (intersection point) of the second inclined portion and the inter-wiring region IWR is located on the boundary portion 107. The second inclined portion crosses the boundary portion 107 in the inclination direction, and is connected to the second front end portion in the first arrangement region 105A. Of course, the extension direction (inclination direction) of the second inclined portion can also be the second direction Y. In this case, it is preferable that the second inclined portion extend in the second direction Y on the first wiring group 80A or the inter-wiring region IWR.

[0612] The second short wiring 115, like the case of the third layout example, forms a current path of the drain-source current Ids together with the first short wiring 111 that opposes (proximally opposes) in the first direction X in both the first wiring group 80A and the second wiring group 80B.

[0613] Reference Signs List Figure 16F(6th Layout Example), the first interconnect wiring structure 108 includes a plurality of first lead-out wirings 109. The plurality of first lead-out wirings 109 includes a first long wiring 110 and a single first short wiring 111. The layout of the first long wiring 110 is the same as in the case of the first layout example.

[0614] The first short wiring 111 is led out from the region of the second end portion side of the first pad wiring 101 in a stepped manner with one step or a plurality of steps (in this case, a plurality of steps) with respect to the first end portion (first long wiring 110) of the first pad wiring 101. The first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0615] The first short wiring 111 is electrically connected to at least one (in this case, a plurality of) first lower wirings 81 of the first wiring group 80A and at least one (in this case, a plurality of) first lower wirings 81 of the second wiring group 80B in the first arrangement region 105A. In addition, the first short wiring 111 is electrically connected to at least one (in this case, a plurality of) first lower wirings 81 of the first wiring group 80A in the second arrangement region 105B.

[0616] The first short wiring 111 can also cover at least one (in this case, a plurality of) first lower wirings 81 and at least one (in this case, a plurality of) second lower wirings 82 of the second wiring group 80B in the second arrangement region 105B. In this case, the first short wiring 111 can also be electrically connected to at least one (in this case, a plurality of) first lower wirings 81 of the second wiring group 80B in the second arrangement region 105B.

[0617] The first short wiring 111 has a first step portion extending in a stepped manner. In this case, the first step portion is led out in a stepped manner from the second end portion side of the first pad wiring 101 to the first end portion side of the second pad wiring 102, and is connected to the first long wiring 110. The first step portion crosses the inter-wiring region IWR and the boundary portion 107 in a stepped manner, and is connected to the first long wiring 110 in the second arrangement region 105B. The first step portion is formed apart from the second pad wiring 102 on the first pad wiring 101 side in the second arrangement region 105B, and is opposite to the second pad wiring 102 in the second direction Y.

[0618] The first interconnect wiring structure 108 includes a plurality of second lead-out wirings 113. The plurality of second lead-out wirings 113 includes a second long wiring 114 and a single second short wiring 115. The layout of the second long wiring 114 is the same as in the case of the first layout example.

[0619] The second short wiring 115 is led out in a stepped manner from the region of the first end portion side of the second pad wiring 102 with a step or steps (in this case, multiple steps) with respect to the second end portion (second long wiring 114) of the second pad wiring 102. The second short wiring 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0620] The second short wiring 115 is electrically connected to at least one (in this case, multiple) second lower wiring 82 of the first wiring group 80A and at least one (in this case, multiple) second lower wiring 82 of the second wiring group 80B in the second arrangement region 105B. In addition, the second short wiring 115 is electrically connected to at least one (in this case, multiple) second lower wiring 82 of the second wiring group 80B in the first arrangement region 105A.

[0621] The second short wiring 115 can also cover at least one (in this case, multiple) first lower wiring 81 and at least one (in this case, multiple) second lower wiring 82 of the first wiring group 80A in the first arrangement region 105A. In this case, the second short wiring 115 can also be electrically connected to at least one (in this case, multiple) second lower wiring 82 of the first wiring group 80A in the first arrangement region 105A.

[0622] The second short wiring 115 has a second step portion that extends in a stepped manner. In this case, the second step portion is led out in a stepped manner from the first end portion side of the second pad wiring 102 to the second end portion side of the first pad wiring 101, and is connected to the second long wiring 114. The second step portion crosses the inter-wiring region IWR and the boundary portion 107 in a stepped manner, and is connected to the second long wiring 114 in the first arrangement region 105A. The second step portion is formed apart from the first pad wiring 101 on the second pad wiring 102 side in the first arrangement region 105A, and is opposite the first pad wiring 101 in the second direction Y.

[0623] The second step portion extends along the first step portion apart from the first step portion. The second step portion preferably extends substantially in parallel to the first step portion with respect to both the first direction X and the second direction Y. The second short wiring 115 preferably has substantially the same planar layout as the first short wiring 111.

[0624] The second short wiring 115, as in the case of the third layout example, forms a current path of the drain-source current Ids together with the first short wiring 111 that is opposite (proximally opposite) in the first direction X in both the first wiring group 80A and the second wiring group 80B.

[0625] Reference Signs List Figure 16G(Seventh Layout Example), the first short wiring 111 ...

Claims

1. A semiconductor device, characterized in that, include: Wiring groups of one side and another side are arranged at intervals in a first direction X, and the wiring groups of one side and the other side respectively include a plurality of first lower wirings and a plurality of second lower wirings arranged in a stripe pattern extending in the first direction X. A first pad wiring, disposed on one and the other wiring groups, and electrically connected to at least one of the first lower wirings in each wiring group; and The second pad wiring is arranged at a distance from the first pad wiring in a second direction Y intersecting the first direction X on one of the wiring groups and the other, and is electrically connected to at least one of the second lower wirings in each wiring group.

2. The semiconductor device according to claim 1, characterized in that: The wiring groups of one party and the other party respectively include a plurality of first underwires and a plurality of second underwires arranged alternately in the second direction Y.

3. The semiconductor device according to claim 1 or 2, characterized in that: The first pad wiring overlaps with both the first lower wiring and the second lower wiring of each of the wiring groups. The second pad wiring overlaps with both the first lower wiring and the second lower wiring of each of the wiring groups.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, Also includes: At least one first lead-out wiring extends from the first pad wiring in the second direction Y and is electrically connected to the first lower wiring in the region between the first pad wiring and the second pad wiring; and At least one second lead-out wiring extends from the second pad wiring in the second direction Y and is electrically connected to the second lower wiring in the region between the first pad wiring and the second pad wiring.

5. The semiconductor device according to claim 4, characterized in that: At least one of the second lead wires is opposite to the first lead wire in the first direction X.

6. The semiconductor device according to claim 4 or 5, characterized in that: At least one of the first lead-out wirings is electrically connected to the first lower wiring of one of the wiring groups.

7. The semiconductor device according to any one of claims 4 to 6, characterized in that: At least one of the first lead-out wirings is electrically connected to the first lower wiring of the wiring group of the other party.

8. The semiconductor device according to any one of claims 4 to 7, characterized in that: At least one of the first lead-out wirings is opposite to the second pad wiring in the first direction X.

9. The semiconductor device according to any one of claims 4 to 8, characterized in that: At least one of the first lead-out wirings is opposite to the second pad wiring in the second direction Y.

10. The semiconductor device according to any one of claims 4 to 9, characterized in that: At least one of the second lead-out wirings is electrically connected to the second lower wiring of one of the wiring groups.

11. The semiconductor device according to any one of claims 4 to 10, characterized in that: At least one of the second lead-out wirings is electrically connected to the second lower wiring of the wiring group of the other party.

12. The semiconductor device according to any one of claims 4 to 11, characterized in that: At least one of the second lead-out wirings is opposite to the first pad wiring in the first direction X.

13. The semiconductor device according to any one of claims 4 to 12, characterized in that: At least one of the second lead-out wirings is opposite to the first pad wiring in the second direction Y.

14. The semiconductor device according to any one of claims 4 to 13, characterized in that: It also includes the wiring closet area defined between the wiring groups of one and the other. The first pad wiring overlaps with the area between the wirings. The second pad wiring overlaps with the area between the wirings. At least one of the first lead-out wirings extends to an area outside the wiring closet area. At least one of the second lead wires extends to a region outside the wiring closet area, and is opposite to the first lead wire in the first direction X, across the wiring closet area.

15. The semiconductor device according to claim 14, characterized in that: At least one of the first lead-out wirings extends in a strip along the inter-wiring area. At least one of the second lead wires extends in a strip along the inter-wire region.

16. The semiconductor device according to any one of claims 4 to 15, characterized in that: Multiple first lead-out wires are led out from the first pad wires. Multiple second lead-out wires are led out from the second pad wires.

17. The semiconductor device according to any one of claims 1 to 16, characterized in that, Also includes: The first pad electrode is configured on the first pad wiring; and The second pad electrode is configured on the second pad wiring.

18. The semiconductor device according to any one of claims 1 to 17, characterized in that: It also includes intermediate wiring in the area configured between the wiring groups on one and the other. The first pad wiring overlaps with the intermediate wiring. The second pad wiring overlaps with the intermediate wiring.

19. The semiconductor device according to any one of claims 1 to 18, characterized in that, Also includes: chip; and The device structure formed in the chip includes a first application terminal that is given a first potential and a second application terminal that is given a second potential different from the first potential. Multiple first lower wirings are electrically connected to the first application terminal on the chip. Multiple second lower wirings are electrically connected to the second application terminal on the chip.

20. A semiconductor device, characterized in that, include: Wiring groups of one party and another party are arranged at intervals from each other, and the wiring groups of one party and the other party respectively include a plurality of first lower wirings and a plurality of second lower wirings; The wiring closet area is divided between the wiring groups on one side and the other side; First pad wiring configured above the wiring closet area; A second pad wiring is disposed at a distance from the first pad wiring above the wiring inter-area area; A first lead-out wiring extends from the first pad wiring to an area outside the wiring closet region and is electrically connected to the first lower wiring of one of the wiring groups; and The second lead-out wiring is led out from the second pad wiring to a region outside the wiring interlock area, opposite to the first lead-out wiring across the wiring interlock area, and is electrically connected to the second lower wiring of the other wiring group.

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