Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention suppresses the generation of a high surge voltage. The semiconductor device of the present invention includes: a trench provided from an upper surface of a base layer to a first impurity layer and further to an inside of a first pillar layer; a first gate electrode provided within the trench and surrounded by a first insulating film; and a second gate electrode provided so as to be in contact with the collector layer sandwiched between the buffer layer and the second impurity layer via a second insulating film and not to reach the first pillar layers, the first pillar layers and the second pillar layers being alternately arranged in a direction intersecting the depth direction of the first pillar layers.

Description

TECHNICAL FIELD

[0001] The technology disclosed in the present application specification relates to semiconductor technology. BACKGROUND

[0002] In a conventional semiconductor device, there is a semiconductor device including a superlattice structure (a structure in which p-type columnar layers and n-type columnar layers are alternately arranged) in a drift region (for example, refer to Patent Document 1). PRIOR ART DOCUMENT PATENT DOCUMENT

[0003] Patent Document 1: Japanese Patent Laid-Open No. 2002-26320 SUMMARY PROBLEMS TO BE SOLVED BY THE INVENTION

[0004] In the conventional structure, because of the superlattice structure (a pressure holding portion) which is thinned, when the recovery current is large, the pressure holding portion is sometimes completely depleted, and a high surge voltage is generated.

[0005] The technology disclosed in the present application specification is completed in view of the above-described problems, and is technology for suppressing generation of a high surge voltage in a semiconductor device having a superlattice structure. SOLUTION TO PROBLEM

[0006] The semiconductor device as a first aspect of the technology disclosed in the present application specification includes: a first pillar layer of a first conductivity type; a plurality of second pillar layers of a second conductivity type, which are provided at a depth reaching inside the first pillar layer from an upper surface of the first pillar layer; a first impurity layer of the first conductivity type, which is provided on the upper surface of the first pillar layer; a base layer of the second conductivity type, which is provided on a surface layer of an upper surface of the first impurity layer; a trench provided to reach the first impurity layer from an upper surface of the base layer and further to reach inside the first pillar layer; a first gate electrode provided inside the trench and surrounded by a first insulating film; a source layer of the first conductivity type, which is provided on a part of the surface layer of the upper surface of the base layer and in contact with the first insulating film; a first interlayer film provided to cover a part of the source layer and the first gate electrode; an emitter electrode covering the base layer, the source layer, and the first interlayer film; a buffer layer of the first conductivity type, which is provided on a lower surface of the first pillar layer; a collector layer of the second conductivity type, which is provided on a surface layer of a lower surface of the buffer layer; a second impurity layer of the first conductivity type, which is provided on a part of the surface layer of the lower surface of the collector layer; a second gate electrode provided in contact with the collector layer sandwiched between the buffer layer and the second impurity layer via a second insulating film and not reaching the first pillar layer; a second interlayer film provided to cover the second gate electrode; and a collector electrode provided to cover the collector layer and the second interlayer film, the first pillar layer and the second pillar layer being alternately arranged in a direction intersecting a depth direction of the first pillar layer. Effects of the Invention

[0007] According to at least the first aspect of the technology disclosed in the present application specification, it is possible to suppress generation of a higher surge voltage in a semiconductor device having a superstructure.

[0008] Furthermore, objects, features, aspects and advantages of the technology disclosed in the present application specification will become clearer with the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a plan view showing an example of a structure of a semiconductor device according to an embodiment. Figure 2 is a plan view showing an example of a structure of a semiconductor device according to an embodiment. Figure 1 is a sectional view showing a structure of an A-B section in an element region in the structure shown in is a sectional view showing a structure of an A-B section in an element region in the structure shown inFigure 3 is a sectional view showing another example of a structure of an A-B section in an element region in the structure shown in Figure 1 Figure 4 is a diagram schematically showing an example of a structure of a semiconductor device to which the embodiment is applied. Figure 5 is a sectional view showing an example of a structure of an A-B section in the structure shown in Figure 4 Figure 6 is a diagram showing a state in which the semiconductor devices shown in Figure 4 Figure 7 is a diagram showing another example of a gate signal of a current mode of a collector current. Figure 8 is a diagram showing an example of a determination method of a large current region and a small current region in a case where a polarity of a collector current is positive. Figure 9 is a diagram schematically showing an example of a structure of a semiconductor device to which the embodiment is applied. Figure 10 Figure 9 Figure 11 is a diagram showing an example of a determination method of a large voltage region and a small voltage region in a case where a polarity of a collector-emitter voltage is positive. Figure 12 is a top view showing an example of a structure of a semiconductor device to which the embodiment is applied. Figure 13 is a sectional view showing an example of a structure of an A-B section in the structure shown in Figure 12 Figure 14 is a sectional view showing a modification example of the structure shown in Figure 13 Figure 15 is a sectional view showing another modification example of the structure shown in Figure 13 DETAILED DESCRIPTION

[0010] Hereinafter, the embodiments will be described with reference to the drawings. In the following embodiments, although detailed features and the like are shown in order to explain the present technology, these features are exemplary, and not all of the features are necessary to achieve the embodiments.

[0011] ​​​​​​​​In addition, the drawings are schematically shown, and for the convenience of explanation, the structures are appropriately omitted or simplified in the drawings. In addition, the mutual relationship of the size and the position of the structures and the like shown in different drawings is not necessarily correctly recorded, and can be appropriately changed. In addition, for the convenience of understanding the contents of the embodiments, sometimes a shadow is added to the plan view and the like which is not a sectional view.

[0012] In addition, in the explanation shown below, the same structural elements are illustrated by annotating the same reference numerals, and their names and functions are also set to be the same. Therefore, in order to avoid repetition, sometimes the detailed explanation thereof is omitted.

[0013] Furthermore, in the explanation described in the present application, when a certain structural element is described as "including", "comprising", or "having" and the like, unless otherwise specified, it is not an exclusive expression that excludes the existence of other structural elements.

[0014] Furthermore, even in the case where a serial number such as "1st" or "2nd" is used in the explanation described in the present application, these terms are used for the convenience of understanding the contents of the embodiments, and the contents of the embodiments are not limited to the order and the like generated by these serial numbers.

[0015] Furthermore, even in the case where a term indicating a specific position or direction such as "upper", "lower", "left", "right", "side", "bottom", "surface", or "back" and the like is used in the explanation described in the present application, these terms are used for the convenience of understanding the contents of the embodiments, regardless of the position or direction at the time of actually implementing the embodiments.

[0016] Furthermore, in the explanation described in the present application, when "… upper surface" or "… lower surface" and the like are described, in addition to the upper surface itself or the lower surface itself of the structural element as an object, a state in which another constituent element is formed on the upper surface or the lower surface of the structural element as an object is also included. That is, for example, when it is described as "B provided on the upper surface of A", this does not hinder another structural element "C" from being interposed between A and B.

[0017] <Embodiment 1> Hereinafter, a semiconductor device and a manufacturing method of a semiconductor device according to the present embodiment will be described.

[0018] <Structure of Semiconductor Device> Figure 1 is a plan view showing an example of the structure of a semiconductor device according to the present embodiment. As shown in the example in Figure 1 As shown in the example in

[0019] Figure 2 It is shown Figure 1 A cross-sectional view of an example structure of section AB in element region 12 of the structure shown.

[0020] like Figure 2 As shown in the example, the component region 12 includes an n-type pillar layer 22 and a plurality of p-type pillar layers 24 extending from the upper surface of the n-type pillar layer 22 to a predetermined depth within the n-type pillar layer 22. Here, the structure in which the n-type pillar layers 22 and the p-type pillar layers 24 are alternately arranged in a direction orthogonal to the depth direction is also referred to as a pressure-resistant retaining section.

[0021] In addition, the component region 12 includes an n-type buffer layer 26 disposed on the lower surface of the n-type pillar layer 22 and an emitter-side n-type layer 28 disposed on the upper surface of the n-type pillar layer 22. In addition, the element region 12 includes a p-type collector layer 30 disposed on the surface layer on the lower surface side of the n-type buffer layer 26, and a p-type base layer 32 disposed on the surface layer on the upper surface side of the n-type layer 28 on the emitter side.

[0022] Furthermore, the component region 12 includes a trench 50 extending from the lower surface of the p-type collector layer 30 into the interior of the n-type buffer layer 26, and a trench 52 extending from the upper surface of the p-type base layer 32 into the emitter-side n-type layer 28 and further into the interior of the n-type pillar layer 22. The trench 50 includes an insulating film 54 disposed along its bottom and side surfaces, and a collector-side gate electrode 58 disposed within the trench 50 and surrounded by the insulating film 54. The trench 52 includes an insulating film 56 disposed along its bottom and side surfaces, and an emitter-side gate electrode 60 disposed within the trench 52 and surrounded by the insulating film 56. The collector-side gate electrode 58 contacts the p-type collector layer 30 sandwiched between the n-type buffer layer 26 and the collector-side n-type layer 34 via the insulating film 54. Moreover, the collector-side gate electrode 58 is configured not to reach the n-type pillar layer 22.

[0023] Furthermore, the device region 12 includes a collector-side n-type layer 34 disposed on a portion of the surface layer on the lower surface side of the p-type collector layer 30 and in contact with the insulating film 54; and an n-type source layer 36 disposed on a portion of the surface layer on the upper surface side of the p-type base layer 32 and in contact with the insulating film 56. Here, the n-type source layer 36, the p-type base layer 32, the insulating film 56, and the emitter-side gate electrode 60 are collectively referred to as the emitter-side channel. Furthermore, the collector-side n-type layer 34, the p-type collector layer 30, the insulating film 54, and the collector-side gate electrode 58 are collectively referred to as the collector-side channel.

[0024] In addition, the device region 12 includes: an interlayer film 38 configured to cover a portion of the collector-side n-type layer 34 and the collector-side gate electrode 58; a collector electrode 42 configured to cover the p-type collector layer 30, the collector-side n-type layer 34 and the interlayer film 38; an interlayer film 40 configured to cover a portion of the n-type source layer 36 and the emitter-side gate electrode 60; and an emitter electrode 44 configured to cover the p-type base layer 32, the n-type source layer 36 and the interlayer film 40.

[0025] The emitter-side n-type layer 28 is shallower than the bottom of the emitter-side gate electrode 60 and is formed between the p-type base layer 32 and the voltage holding portion. The voltage holding portion composed of the n-type pillar layer 22 and the p-type pillar layer 24 is also called a superstructure.

[0026] The peak impurity concentration of the n-type source layer 36 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 The following is an example. Furthermore, the peak impurity concentration of the p-type base layer 32 is, for example, 1 × 10⁻⁶. 17 cm -3 .

[0027] The peak impurity concentration of the emitter-side n-type layer 28 is, for example, 1 × 10⁻⁶. 15 cm -3 Above and 1×10 17 cm -3 The following. Furthermore, the peak impurity concentration of the n-type buffer layer 26 is, for example, 1 × 10⁻⁶. 15 cm -3 Above and 1×10 18 cm -3 the following.

[0028] The peak impurity concentration of the p-type collector layer 30 is, for example, 1 × 10⁻⁶. 17 cm -3 Above and 1×10 19 cm -3 Below. Furthermore, the peak impurity concentration of the collector-side n-type layer 34 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 the following.

[0029] If the pressure-resistant retaining section is composed of an n-type drift layer, the impurity concentration is approximately 1 × 10⁻⁶. 14 cm -3 In the case of the aforementioned superstructure, the impurity concentrations of the n-type column layer 22 and the p-type column layer 24 are approximately 1 × 10⁻⁶. 15 cm -3 .

[0030] The interval of the repetitive arrangement of the emitter-side gate electrodes 60 (emitter-side gate pitch) and the interval of the repetitive arrangement of the collector-side gate electrodes 58 (collector-side gate pitch) can be different.

[0031] Figure 3 is a cross-sectional view showing another example of the structure of the A-B cross section in the element region 12 in the structure shown in Figure 1 is a cross-sectional view showing another example of the structure of the A-B cross section in the element region 12 in the structure shown in

[0032] As shown in the example in Figure 3 As shown in the example in

[0033] Further, the element region 12 includes a p-type collector layer 30A provided on a part of a surface layer on the lower surface side of the n-type buffer layer 26A, a p-type base layer 32, and a trench 52. The trench 52 includes the insulating film 56 and the emitter-side gate electrode 60.

[0034] Further, the element region 12 includes a collector-side n-type layer 34A provided on a part of a surface layer on the lower surface side of the p-type collector layer 30A, and an n-type source layer 36.

[0035] Further, the element region 12 includes an insulating film 54A covering a part of the p-type collector layer 30A, the collector-side n-type layer 34A, and the exposed n-type buffer layer 26A, a collector-side gate electrode 58A covering the insulating film 54A, an interlayer film 38A covering the collector-side gate electrode 58A, a collector electrode 42 provided to cover the p-type collector layer 30A and the interlayer film 38A, an interlayer film 40, and an emitter electrode 44. The collector-side gate electrode 58A contacts the p-type collector layer 30A sandwiched between the n-type buffer layer 26A and the collector-side n-type layer 34A via the insulating film 54A. Also, the collector-side gate electrode 58A is provided so as not to reach the n-type pillar layer 22.

[0036] In the reverse conduction state, a positive voltage is applied to the collector-side gate electrode 58, and at the collector-side channel portion, the collector-side n-type layer 34 and the voltage holding portion are electrically connected.

[0037] In this case, if the emitter-side gate electrode 60 is made to be in an on state (a state in which a positive voltage is applied), single-pole operation is performed, and if the emitter-side gate electrode 60 is made to be in an off state (a state in which a positive voltage is not applied), bipolar operation is performed. Here, single-pole operation refers to operation in which electrons flow from the collector-side n-type layer 34 through the channel, flow through the withstand voltage holding portion, and reach the n-type source layer 36. In addition, bipolar operation refers to operation in which, if electrons flow from the collector-side n-type layer 34 through the channel and flow through the withstand voltage holding portion and reach the p-type base layer 32, holes are injected from the p-type base layer 32.

[0038] In the transition from the reverse conduction state to the off state, that is, in the reverse recovery (hereinafter also referred to as recovery), electrons are discharged to the collector-side n-type layer 34, and holes are discharged to the p-type base layer 32, and the depletion layer expands from both sides of the withstand voltage holding portion.

[0039] If the withstand voltage holding portion is made thin by the superstructure, the withstand voltage holding portion is easily completely depleted at the time of recovery of the bipolar. If the withstand voltage holding portion is completely depleted, the recovery current is suddenly cut off, and thus, when a larger recovery current flows, complete depletion occurs, and a large surge voltage is generated.

[0040] If the emitter-side n-type layer 28 is provided, when the bipolar is in reverse conduction, injection of holes from the p-type base layer 32 is reduced, and thus, accumulation of carriers on the emitter side can be reduced. Thus, at the time of recovery of the bipolar, depletion from the emitter side is promoted. Thus, depletion from the collector side can be suppressed, and a larger surge voltage generated due to complete depletion can be suppressed.

[0041] As described above, according to the semiconductor device according to the present embodiment, a larger surge voltage at the time of recovery of the bipolar can be avoided. Thus, electromagnetic noise or damage due to a larger surge voltage can be suppressed, and at the same time, current can flow in both directions.

[0042] <Embodiment 2> Hereinafter, a semiconductor device and a method of manufacturing a semiconductor device according to the present embodiment will be described. In the following description, the same reference numerals are assigned to the same structural elements as those described in the above-described embodiment, and detailed description thereof is appropriately omitted.

[0043] <Structure of Semiconductor Device> Figure 4 is a diagram schematically showing an example of a structure of a semiconductor device according to the present embodiment. As shown in the example, the semiconductor device includes a collector-side gate drive unit 102 that drives a collector-side gate electrode 58, an emitter-side gate drive unit 104 that drives an emitter-side gate electrode 60, and a control unit 106 that controls the collector-side gate drive unit 102 and the emitter-side gate drive unit 104. Figure 4 As shown in the example, the semiconductor device includes a collector-side gate drive unit 102 that drives a collector-side gate electrode 58, an emitter-side gate drive unit 104 that drives an emitter-side gate electrode 60, and a control unit 106 that controls the collector-side gate drive unit 102 and the emitter-side gate drive unit 104. Figure 1 Figure 1 ​an emitter side gate electrode 60; a PWM (pulse width modulation) control unit 106 that outputs a control signal to the collector side gate drive unit 102 and the emitter side gate drive unit 104; a current detection unit 108 that detects a collector current (load current); and a current mode determination unit 110 that determines a current mode based on a current value detected by the current detection unit 108.

[0044] Figure 5 is a view that shows Figure 4 the semiconductor device shown in FIG. 1 is in a state in which it is connected in series.

[0045] Figure 6 is a view that shows Figure 4 the current mode when the current detected by the current detection unit 108 in the semiconductor device shown in FIG. 1 is divided into examples.

[0046] As shown in Figure 6 when the collector current whose polarity is positive is detected by the current detection unit 108, the current mode determination unit 110 sets the emitter side gate signal to the PWM control signal (i.e., the PWM control signal is output from the PWM control unit 106 to the emitter side gate drive unit 104 based on the determination result of the current mode determination unit 110). Further, in this case, when the collector current value is greater than a threshold value specified in advance, the current mode determination unit 110 sets the collector side gate signal (i.e., a signal that drives the collector side gate electrode 58) to be off, and when the collector current value is less than the threshold value specified in advance, the current mode determination unit 110 sets the collector side gate signal to be on.

[0047] Further, as shown in the example in Figure 6 when the collector current whose polarity is negative is detected by the current detection unit 108, the current mode determination unit 110 sets the collector side gate signal to be on. Further, in this case, when the collector current value is less than a threshold value specified in advance, the current mode determination unit 110 sets the emitter side gate signal to the PWM control signal, and when the collector current value is greater than the threshold value specified in advance, the current mode determination unit 110 cuts off the PWM control signal and does not output the emitter side gate signal.

[0048] Figure 7 is a view that shows another example of a gate signal of a current mode of a collector current. As shown in the example in Figure 7 when the polarity of the collector current is positive and the collector current value is large (i.e., when it is in a large current region), it is set to be a bipolar operation by setting the collector side gate signal to be off.

[0049] Further, as shown in the example in Figure 7As shown in the example in FIG. 6, when the polarity of the collector current is positive and the collector current is small (i.e., when in the small current region), the single mode of operation is set by setting the collector-side gate signal to ON.

[0050] Further, as shown in the example in FIG. 6, when the polarity of the collector current is negative and the collector current is small, the single mode of operation is set by setting the collector-side gate signal to ON. Figure 7

[0051] Further, as shown in the example in FIG. 6, when the polarity of the collector current is negative and the collector current is small, the single mode of operation is set by setting the collector-side gate signal to ON. Figure 7

[0052] Figure 8 FIG. 7 is a graph showing an example of a method of determining the large current region and the small current region in the case where the polarity of the collector current is positive. Figure 8 In FIG. 7, the collector current X1 when the collector-side gate signal is set to ON and the collector current X2 when the collector-side gate signal is set to OFF are shown. In addition, in FIG. 7, the vertical axis represents the magnitude of the collector current, and the horizontal axis represents the magnitude of the voltage between the collector electrode and the emitter electrode. Figure 8

[0053] As shown in the example in FIG. 7, as the voltage between the collector electrode and the emitter electrode becomes larger, both the collector current X1 and the collector current X2 become larger. Further, in a range where the voltage between the collector electrode and the emitter electrode is small, the collector current X2 is smaller than the collector current X1, and in a range where the voltage between the collector electrode and the emitter electrode is large, the collector current X2 is larger than the collector current X1. Figure 8

[0054] The collector current value at the timing at which the magnitude relationship between the collector current X1 and the collector current X2 is reversed can be specified as the boundary value between the large current region and the small current region.

[0055] The collector current (polarity and magnitude) during inverter operation shifts in the order of (positive and large), (positive and small), (negative and small), (negative and large), (negative and small), (positive and small), (positive and large), (positive and small), ···, and the operation mode (current mode) before and after the polarity of the collector current is reversed is the same. Therefore, current detection (detection of 0 A current) is not required at the timing at which the polarity of the collector current is reversed.

[0056] As described above, according to the semiconductor device according to the present embodiment, detection of 0 A current, which is difficult to detect due to noise, is not required.

[0057] ​​​​Therefore, current can flow in both directions of the semiconductor device while preventing damage to the semiconductor device due to false detection of 0A.

[0058] <Embodiment 3> A semiconductor device and a manufacturing method of a semiconductor device according to the present embodiment will be described. In the following description, the same reference numerals are used to designate the same structural elements as those described in the above-described embodiments, and detailed description thereof is appropriately omitted.

[0059] <Structure of Semiconductor Device> Figure 9 is a diagram schematically showing an example of a structure of a semiconductor device according to the present embodiment. As shown in the example, the semiconductor device includes a collector-side gate drive unit 102 that drives a collector-side gate electrode 58, an emitter-side gate drive unit 104 that drives an emitter-side gate electrode 60, a PWM control unit 106 that outputs a control signal to the collector-side gate drive unit 102 and the emitter-side gate drive unit 104, a voltage detection unit 112 that detects a collector-emitter voltage, and a voltage mode determination unit 114 that determines a voltage mode based on a voltage value detected by the voltage detection unit 112. Figure 9 Figure 1 Figure 1

[0060] As shown in the example, when the collector-emitter voltage is detected by the voltage detection unit 112, the voltage mode determination unit 114 determines the voltage mode. Figure 5

[0061] Figure 10 is a diagram showing an example of a division of the voltage mode when the voltage detected by the voltage detection unit 112 in the above-described semiconductor device is determined by the voltage mode determination unit 114. Figure 9

[0062] As shown in the example in FIG. 24, when the collector-emitter voltage having a positive polarity is detected by the voltage detection unit 112, the voltage mode determination unit 114 sets the emitter-side gate signal as the PWM control signal (i.e., the PWM control signal is output from the PWM control unit 106 to the emitter-side gate drive unit 104 based on the determination result of the voltage mode determination unit 114). Further, in this case, when the collector-emitter voltage is greater than a threshold value specified in advance, the voltage mode determination unit 114 sets the collector-side gate signal (i.e., a signal that drives the collector-side gate electrode 58) to be off, and when the collector current value is less than a threshold value specified in advance, the current mode determination unit 110 sets the collector-side gate signal to be on. Figure 10

[0063] Further, as shown in the example in FIG. 24, when the collector-emitter voltage having a negative polarity is detected by the voltage detection unit 112, the voltage mode determination unit 114 sets the collector-side gate signal as the PWM control signal (i.e., the PWM control signal is output from the PWM control unit 106 to the collector-side gate drive unit 102 based on the determination result of the voltage mode determination unit 114). Further, in this case, when the collector-emitter voltage is greater than a threshold value specified in advance, the voltage mode determination unit 114 sets the emitter-side gate signal (i.e., a signal that drives the emitter-side gate electrode 60) to be off, and when the collector current value is less than a threshold value specified in advance, the current mode determination unit 110 sets the emitter-side gate signal to be on. Figure 10 ​​​​​​As shown in the example, when the voltage detection unit 112 detects a negative collector current, the voltage mode determination unit 114 sets the collector-side gate signal to ON. Furthermore, in this case, when the collector-emitter voltage is less than a predetermined threshold, the voltage mode determination unit 114 sets the emitter-side gate signal to a PWM control signal; when the collector-emitter voltage is greater than the predetermined threshold, the voltage mode determination unit 114 cuts off the PWM control signal and does not output the emitter-side gate signal.

[0064] When the polarity of the collector-emitter voltage is positive and the collector-emitter voltage is large, bipolar operation is achieved by turning off the gate on the collector side.

[0065] When the collector-emitter voltage is positive and the collector-emitter voltage is small, it is set to unipolar operation by turning off the gate on the collector side.

[0066] When the collector-emitter voltage is negative and the collector-emitter voltage is small, it is set to unipolar operation by turning on the collector-side gate.

[0067] When the collector-emitter voltage is negative and the collector-emitter voltage is large, bipolar operation is achieved by cutting off the PWM control signal of the emitter-side gate and turning on the collector-side gate.

[0068] Figure 11 This is a diagram illustrating an example of a method for determining the high-voltage and low-voltage regions when the collector-emitter voltage polarity is positive. Figure 11 The diagram shows the collector current Y1 when the collector-side gate signal is set to on and the collector current X2 when the collector-side gate signal is set to off. Additionally, in... Figure 11 In the diagram, the vertical axis represents the magnitude of the collector current, and the horizontal axis represents the magnitude of the voltage between the collector electrode and the emitter electrode.

[0069] like Figure 11 As shown in the example, as the voltage between the collector and emitter electrodes increases, both the collector current Y1 and the collector current Y2 increase. Furthermore, within a smaller range of voltage between the collector and emitter electrodes, the collector current Y2 is less than the collector current Y1; conversely, within a larger range of voltage between the collector and emitter electrodes, the collector current Y2 is greater than the collector current Y1.

[0070] The collector-emitter voltage value at which the relationship between collector current Y1 and collector current Y2 is reversed can be defined as the boundary value between the high voltage region and the low voltage region.

[0071] The collector-emitter voltage (polarity and magnitude) during inverter operation shifts in the following sequence: (positive and large), (positive and small), (negative and small), (negative and large), (negative and small), (positive and small), (positive and large), (positive and small), ... The operating mode (voltage mode) is the same before and after the collector-emitter voltage polarity reversal. Therefore, it is not necessary to perform voltage detection (detection when the voltage is 0V) at the timing of the collector-emitter voltage polarity reversal.

[0072] As described above, the semiconductor device according to this embodiment does not require detection of 0V, which is difficult to detect due to noise.

[0073] Therefore, it is possible to prevent damage to the semiconductor device due to false detection of 0V while allowing current to flow in both directions of the semiconductor device.

[0074] <Implementation Method 4> The semiconductor device and its manufacturing method according to this embodiment will be described. Furthermore, in the following description, structural elements identical to those described in the above embodiments will be illustrated using the same reference numerals, and their detailed descriptions will be omitted where appropriate.

[0075] <On the structure of semiconductor devices> Figure 12 This is a top view illustrating an example of the structure of the semiconductor device according to this embodiment. (Example) Figure 12 As shown in the example, the semiconductor device includes a component region 12 and a terminal region 14A that surrounds the component region 12 when viewed from above.

[0076] Figure 13 It is shown Figure 12 A cross-sectional view of an example structure spanning section AB of element region 12 and terminal region 14A in the structure shown.

[0077] like Figure 13 As shown in the example, component region 12 and terminal region 14A include n-type column layers 22 and multiple p-type column layers 24.

[0078] Furthermore, component region 12 and terminal region 14A include an n-type buffer layer 26. Additionally, component region 12 includes an emitter-side n-type layer 28 disposed on the upper surface of the n-type pillar layer 22.

[0079] In addition, the element region 12 includes a p-type collector layer 30 disposed on the surface layer on the lower surface side of the n-type buffer layer 26, and a p-type base layer 32 disposed on the surface layer on the upper surface side of the n-type layer 28 on the emitter side.

[0080] Further, the terminal region 14A includes an n-type cathode layer 62 provided on a surface layer on the lower surface side of the n-type buffer layer 26, and a plurality of p-type well layers 64 provided on a surface layer on the upper surface side of the n-type pillar layer 22 across the p-type pillar layer 24. Here, the peak impurity concentration of the n-type cathode layer 62 is, for example, 1 x 1018cm-3. 18 cm -3 The above and 1 x 1018cm-3 21 cm -3 The following.

[0081] Further, the element region 12 includes the trench 50 and the trench 52. The trench 50 includes the insulating film 54 and the collector-side gate electrode 58. The trench 52 includes the insulating film 56 and the emitter-side gate electrode 60.

[0082] Further, the element region 12 includes the collector-side n-type layer 34 and the n-type source layer 36.

[0083] Further, the element region 12 includes the interlayer film 38, the collector electrode 42, the interlayer film 40, and the emitter electrode 44.

[0084] Further, the terminal region 14A includes an interlayer film 66 provided to cover a part of the p-type well layer 64, an interlayer film 68 provided to cover a part of the p-type well layer 64 and the p-type pillar layer 24, an interlayer film 70 provided to cover a part of the p-type well layer 64 and the n-type pillar layer 22, an electrode 72 provided to cover a part of the interlayer film 66, a part of the interlayer film 68, and the exposed p-type well layer 64, and an electrode 74 provided to cover a part of the interlayer film 68, a part of the interlayer film 70, and the exposed p-type well layer 64. In addition, a part of the interlayer film 66 is covered by the emitter electrode 44. Further, the collector electrode 42 is provided to cover the n-type cathode layer 62.

[0085] Although the terminal region 14A shown in Figure 12 and Figure 13 The terminal region 14A shown in FIG. 1 has an FLR (Field Limiting Ring) structure, but the terminal region 14A can also have a RESURF (Reduced Surface Field) structure or a VLD (Variation of Lateral Doping) structure.

[0086] In the terminal region 14A, a pn diode composed of the p-type layer (the p-type pillar layer 24, the p-type well layer 64) on the surface side of the n-type pillar layer 22 and the n-type cathode layer 62 on the back surface side of the n-type pillar layer 22 is formed. Therefore, even in the case where the collector-side gate signal is stopped due to a malfunction, reverse conduction can be achieved, and thus damage to the semiconductor device can be suppressed.

[0087] <Regarding Modification Example 1> Figure 14 is a cross-sectional view showing a modification example of the structure shown in Figure 13 FIG. 1.

[0088] As Figure 14 As shown in the example, the element region 12B and the termination region 14B include the n-type pillar layer 22 and the plurality of p-type pillar layers 24.

[0089] Further, the element region 12B and the termination region 14B include the n-type buffer layer 26. Further, the element region 12B includes the emitter-side n-type layer 28 provided on the upper surface of the n-type pillar layer 22.

[0090] Further, the element region 12B includes the p-type collector layer 30B provided on a portion of the surface on the lower surface side of the n-type buffer layer 26; and the p-type base layer 32 provided on the surface on the upper surface side of the emitter-side n-type layer 28.

[0091] Further, the termination region 14B includes the n-type cathode layer 62B provided on the surface on the lower surface side of the n-type buffer layer 26; and the plurality of p-type well layers 64 provided on the surface on the upper surface side of the n-type pillar layer 22 across the p-type pillar layers 24. In addition, the n-type cathode layer 62B is also provided on a portion of the surface on the lower surface side of the n-type buffer layer 26 of the element region 12B. The n-type cathode layer 62B provided in the element region 12B and the n-type cathode layer 62B provided in the termination region 14B can be continuous or discontinuous. That is, the n-type cathode layer 62B provided in the element region 12B can be discretely provided in the element region 12B.

[0092] Further, the element region 12B includes the trench 50 and the trench 52. The trench 50 includes the insulating film 54 and the collector-side gate electrode 58. The trench 52 includes the insulating film 56 and the emitter-side gate electrode 60.

[0093] Further, the element region 12 includes the collector-side n-type layer 34 and the n-type source layer 36.

[0094] Further, the element region 12B includes the interlayer film 38, the collector electrode 42, the interlayer film 40, and the emitter electrode 44. Further, the collector electrode 42 is provided so as to cover the p-type collector layer 30B and the n-type cathode layer 62B.

[0095] Further, the termination region 14B includes the interlayer film 66, the interlayer film 68, the interlayer film 70, the electrode 72, and the electrode 74. In addition, a portion of the interlayer film 66 is covered by the emitter electrode 44.

[0096] In the terminal region 14B, a pn diode composed of the p-type layer (p-type pillar layer 24, p-type well layer 64) of the surface side of the n-type pillar layer 22 and the n-type cathode layer 62B of the back surface side of the n-type pillar layer 22 is formed. Therefore, even in the case where the collector-side gate signal is stopped due to a malfunction, reverse conduction is achieved, and thus damage to the semiconductor device can be suppressed.

[0097] <Regarding Modification 2> Figure 15 is a cross-sectional view showing Figure 13 another modification of the structure shown in

[0098] As Figure 15 As shown in the example, the element region 12C and the terminal region 14C include the n-type pillar layer 22 and a plurality of p-type pillar layers 24.

[0099] Further, the element region 12C and the terminal region 14C include the n-type buffer layer 26. Further, the element region 12C includes the emitter-side n-type layer 28 provided on the upper surface of the n-type pillar layer 22.

[0100] Further, the element region 12C includes the p-type collector layer 30B provided on a part of the surface layer of the lower surface side of the n-type buffer layer 26 and the p-type base layer 32 provided on the surface layer of the upper surface side of the emitter-side n-type layer 28.

[0101] Further, the terminal region 14C includes the n-type cathode layer 62 provided on the surface layer of the lower surface side of the n-type buffer layer 26 and a plurality of p-type well layers 64 provided on the surface layer of the upper surface side of the n-type pillar layer 22 across the p-type pillar layers 24. In addition, the n-type cathode layer 62C is also provided on a part of the surface layer of the lower surface side of the n-type buffer layer 26 of the element region 12C. The n-type cathode layer 62C provided in the element region 12C and the n-type cathode layer 62C provided in the terminal region 14C can be continuous or discontinuous. That is, the n-type cathode layer 62C provided in the element region 12C can be discretely provided in the element region 12C. Further, the n-type cathode layer 62C is a layer in which at least one of the impurity concentration and the depth is formed to be the same as the collector-side n-type layer 34. In addition, the same of the impurity concentration or the same of the depth includes a case where there is a deviation of, for example, about several percent within a measurement error range.

[0102] Further, the element region 12 includes the trench 50 and the trench 52. The trench 50 includes the insulating film 54 and the collector-side gate electrode 58. The trench 52 includes the insulating film 56 and the emitter-side gate electrode 60.

[0103] Further, the element region 12C includes the collector-side n-type layer 34 and the n-type source layer 36.

[0104] In addition, the element region 12C includes an interlayer film 38, a collector electrode 42, an interlayer film 40, and an emitter electrode 44.

[0105] Furthermore, the terminal region 14C includes interlayer membrane 66, interlayer membrane 68, interlayer membrane 70, electrode 72, and electrode 74. Additionally, a portion of the interlayer membrane 66 is covered by the emitter electrode 44.

[0106] As manufacturing Figure 15 The method of the structure shown first involves providing an n-type pillar layer 22 and a p-type pillar layer 24 in the component region 12C and the terminal region 14C. Here, the p-type pillar layer 24 is provided at a depth extending from the upper surface of the n-type pillar layer 22 into the n-type pillar layer 22. The n-type pillar layer 22 and the p-type pillar layer 24 are formed alternately in a direction orthogonal to the depth direction of the n-type pillar layer 22.

[0107] Next, in device region 12C, an emitter-side n-type layer 28 is formed on the upper surface of the n-type pillar layer 22, and a p-type base layer 32 is formed on the surface layer of the upper surface of the emitter-side n-type layer 28. Next, in device region 12C, an n-type source layer 36 is formed on a portion of the surface layer of the upper surface of the p-type base layer 32.

[0108] Next, in the element region 12C, a trench 52 is formed from the upper surface of the p-type base layer 32 to the emitter side n-type layer 28 and further to the interior of the n-type pillar layer 22 in a manner that contacts the n-type source layer 36. An emitter side gate electrode 60 surrounded by an insulating film 56 is formed in the trench 52.

[0109] Next, in the element region 12C, an interlayer film 40 is disposed covering a portion of the n-type source layer 36 and the emitter-side gate electrode 60, and an emitter electrode 44 is disposed covering the p-type base layer 32, the n-type source layer 36 and the interlayer film 40.

[0110] On the other hand, in the component region 12C and the terminal region 14C, an n-type buffer layer 26 is provided on the lower surface of the n-type pillar layer 22.

[0111] Next, in the component region 12C, a p-type collector layer 30B is disposed on a portion of the surface layer of the lower surface of the n-type buffer layer 26.

[0112] Next, in the element region 12C, an n-type cathode layer 62C is provided on another part of the surface layer of the lower surface of the n-type buffer layer 26, and a collector-side n-type layer 34 is provided on a part of the surface layer of the lower surface of the p-type collector layer 30B. At the same time, in the terminal region 14C, an n-type cathode layer 62C is provided on the surface layer of the lower surface of the n-type buffer layer 26.

[0113] Next, in the element region 12C, the collector-side gate electrode 58 is provided in contact with the p-type collector layer 30B interposed between the n-type buffer layer 26 and the collector-side n-type layer 34 via the insulating film 54 and does not reach the n-type pillar layer 22. In the terminal region 14C, the p-type collector layer 30B is provided in contact with the n-type cathode layer 62. Figure 15 In the element region 12C, the trench 50 reaching the inside of the n-type buffer layer 26 from the lower surface of the p-type collector layer 30B and not reaching the n-type pillar layer 22 is provided in contact with the collector-side n-type layer 34, and the collector-side gate electrode 58 surrounded by the insulating film 54 is provided in the trench 50.

[0114] Next, in the element region 12C, the collector-side gate electrode 58 is provided in contact with the p-type collector layer 30B interposed between the n-type buffer layer 26 and the collector-side n-type layer 34 via the insulating film 54 and does not reach the n-type pillar layer 22. In the terminal region 14C, the p-type collector layer 30B is provided in contact with the n-type cathode layer 62.

[0115] In the terminal region 14C, the pn diode composed of the p-type layer (p-type pillar layer 24, p-type well layer 64) of the surface side of the n-type pillar layer 22 and the n-type cathode layer 62 of the back surface side of the n-type pillar layer 22 is formed. Therefore, even in the case where the collector-side gate signal is stopped due to a malfunction, reverse conduction can be achieved, and thus damage to the semiconductor device can be suppressed.

[0116] <Effects produced by the above-described embodiments> Next, examples of effects produced by the above-described embodiments are shown. In the following description, the effects are described based on the specific structures shown in the examples of the above-described embodiments, but other specific structures shown in the examples in the present specification can be substituted within a range where the same effects are produced. That is, hereinafter, for convenience, only one of the corresponding specific structures is described representatively, but other specific structures corresponding to the representatively described specific structure can be substituted.

[0117] In addition, the substitution can also span multiple embodiments. That is, the same effects can be produced by combining each structure exemplified in different embodiments.

[0118] According to the above-described embodiment, the semiconductor device includes a first pillar layer of a first conductivity type (n-type), a plurality of second pillar layers of a second conductivity type (p-type), an n-type first impurity layer, a p-type base layer, a trench 52, a first gate electrode, an n-type source layer, a first interlayer film, an emitter electrode 44, an n-type buffer layer, a p-type collector layer, a second impurity layer, a second gate electrode, a second interlayer film, and a collector electrode 42. Here, the first pillar layer corresponds to, for example, the n-type pillar layer 22 or the like. Further, the second pillar layer corresponds to, for example, the p-type pillar layer 24 or the like. Further, the first impurity layer corresponds to, for example, the emitter-side n-type layer 28 or the like. Further, the base layer corresponds to, for example, the p-type base layer 32 or the like. Further, the first gate electrode corresponds to, for example, the emitter-side gate electrode 60 or the like. Further, the source layer corresponds to, for example, the n-type source layer 36 or the like. Further, the first interlayer film corresponds to, for example, the interlayer film 40 or the like. Further, the buffer layer corresponds to, for example, the n-type buffer layer 26, the n-type buffer layer 26A, or the like. Further, the collector layer corresponds to, for example, the p-type collector layer 30, the p-type collector layer 30A, the p-type collector layer 30B, or the like. Further, the second impurity layer corresponds to, for example, the collector-side n-type layer 34, the collector-side n-type layer 34A, or the like. Further, the second gate electrode corresponds to, for example, the collector-side gate electrode 58, the collector-side gate electrode 58A, or the like. Further, the second interlayer film corresponds to, for example, the interlayer film 38, the interlayer film 38A, or the like. The p-type pillar layer 24 is provided at a depth reaching inside the n-type pillar layer 22 from an upper surface of the n-type pillar layer 22. The emitter-side n-type layer 28 is provided on the upper surface of the n-type pillar layer 22. The p-type base layer 32 is provided on a surface layer of an upper surface of the emitter-side n-type layer 28. The trench 52 is provided to reach the emitter-side n-type layer 28 from an upper surface of the p-type base layer 32 and further to reach inside the n-type pillar layer 22. The emitter-side gate electrode 60 is provided inside the trench 52 and is surrounded by a first insulating film. Here, the first insulating film corresponds to, for example, the insulating film 56 or the like. The n-type source layer 36 is provided on a part of a surface layer of the upper surface of the p-type base layer 32 and is in contact with the insulating film 56. The interlayer film 40 is provided to cover a part of the n-type source layer 36 and the emitter-side gate electrode 60. The emitter electrode 44 is provided to cover the p-type base layer 32, the n-type source layer 36, and the interlayer film 40. The n-type buffer layer 26 is provided on a lower surface of the n-type pillar layer 22. The p-type collector layer 30 is provided on a surface layer of a lower surface of the n-type buffer layer 26. The collector-side n-type layer 34 is provided on a part of a surface layer of a lower surface of the p-type collector layer 30. The collector-side gate electrode 58 is provided in contact with the p-type collector layer 30 sandwiched between the n-type buffer layer 26 and the collector-side n-type layer 34 via a second insulating film and does not reach the n-type pillar layer 22. Here, the second insulating film corresponds to, for example, the insulating film 54, the insulating film 54A, or the like. The interlayer film 38 is provided to cover the collector-side gate electrode 58. The collector electrode 42 is provided to cover the p-type collector layer 30 and the interlayer film 38.Further, the n-type pillar layer 22 and the p-type pillar layer 24 are alternately arranged in a direction intersecting with the depth direction of the n-type pillar layer 22.

[0119] According to such a structure, in the semiconductor device having the superstructure, generation of a large surge voltage can be suppressed. Specifically, since the emitter-side n-type layer 28 is provided, when the bipolar is turned off, injection of holes from the p-type base layer 32 is reduced. Thus, accumulation of carriers at the emitter side can be reduced. Thereby, at the time of recovery of the bipolar, depletion from the emitter side is promoted. Further, depletion from the collector side can be suppressed, and a large surge voltage generated due to complete depletion can be suppressed.

[0120] Further, in the above structure, the same effect can be obtained when other structures exemplified in the present specification are appropriately added to the above structure, i.e., when other structures not mentioned in the present specification are appropriately added to the above structure.

[0121] Further, according to the above-described embodiment, the semiconductor device includes a current detection section and a control section. Here, the current detection section corresponds to, for example, the current detection unit 108 or the like. Further, the control section corresponds to, for example, the current mode determination unit 110 and the PWM control unit 106 or the like. The current detection unit 108 detects the collector current output via the collector electrode 42. The control section controls the voltage applied to the emitter-side gate electrode 60 and the collector-side gate electrode 58 based on the polarity and the current value of the collector current detected by the current detection unit 108. According to such a structure, by switching the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 according to the detected collector current, and separately using the bipolar operation and the unipolar operation of the semiconductor device, generation of a large surge voltage can be suppressed.

[0122] Further, according to the above-described embodiment, when the polarity of the collector current is positive and the current value of the collector current is greater than the predetermined threshold value, the control section sets the emitter-side gate electrode 60 to the on state and sets the collector-side gate electrode 58 to the off state. Further, when the polarity of the collector current is positive and the current value of the collector current is less than the predetermined threshold value, the control section sets the emitter-side gate electrode 60 to the on state and sets the collector-side gate electrode 58 to the on state. Further, when the polarity of the collector current is negative and the current value of the collector current is less than the predetermined threshold value, the control section sets the emitter-side gate electrode 60 to the on state and sets the collector-side gate electrode 58 to the on state. Further, when the polarity of the collector current is negative and the current value of the collector current is greater than the predetermined threshold value, the control section sets the emitter-side gate electrode 60 to the off state and sets the collector-side gate electrode 58 to the on state. According to such a structure, by switching the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 according to the detected collector current, and separately using the bipolar operation and the unipolar operation of the semiconductor device, it is possible to suppress the generation of a large surge voltage.

[0123] Further, according to the above-described embodiment, the semiconductor device includes a voltage detection section and a control section. Here, the voltage detection section corresponds to, for example, the voltage detection unit 112 or the like. Further, the control section corresponds to, for example, the voltage mode determination unit 114 and the PWM control unit 106 or the like. The voltage detection unit 112 detects an inter-electrode voltage that is a voltage applied between the collector electrode 42 and the emitter electrode. The control section controls the voltage applied to the emitter-side gate electrode 60 and the collector-side gate electrode 58 based on the polarity and the voltage value of the inter-electrode voltage detected by the voltage detection unit 112. According to such a structure, by switching the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 according to the detected collector-emitter voltage, and separately using the bipolar operation and the unipolar operation of the semiconductor device, it is possible to suppress the generation of a large surge voltage.

[0124] Further, according to the above-described embodiment, when the polarity of the inter-electrode voltage is positive and the voltage value of the inter-electrode voltage is greater than the predetermined threshold value, the control section sets the emitter-side gate electrode 60 to the on state and sets the collector-side gate electrode 58 to the off state. Further, when the polarity of the inter-electrode voltage is positive and the voltage value of the inter-electrode voltage is less than the predetermined threshold value, the control section sets the emitter-side gate electrode 60 to the on state and sets the collector-side gate electrode 58 to the on state. Further, when the polarity of the inter-electrode voltage is negative and the voltage value of the inter-electrode voltage is less than the predetermined threshold value, the control section sets the emitter-side gate electrode 60 to the on state and sets the collector-side gate electrode 58 to the on state. Further, when the polarity of the inter-electrode voltage is negative and the voltage value of the inter-electrode voltage is greater than the predetermined threshold value, the control section sets the emitter-side gate electrode 60 to the off state and sets the collector-side gate electrode 58 to the on state. According to such a structure, by switching the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 according to the detected collector-emitter voltage, and separately using the bipolar operation and the unipolar operation of the semiconductor device, it is possible to suppress the generation of a large surge voltage.

[0125] Further, according to the above-described embodiment, the semiconductor device includes the element region 12 (or the element region 12B, the element region 12C) and the termination region 14A (or the termination region 14B, the termination region 14C) that surrounds the element region 12 in plan view. The n-type pillar layer 22, the p-type pillar layer 24, and the n-type buffer layer 26 are provided in the element region 12 and the termination region 14A. Here, in the termination region 14A, the semiconductor device includes an n-type cathode layer provided on a surface layer of a lower surface of the n-type buffer layer 26. Note that the cathode layer corresponds to, for example, the n-type cathode layer 62, the n-type cathode layer 62B, the n-type cathode layer 62C, and the like. Also, in the termination region 14A, the collector electrode 42 is provided so as to cover the n-type cathode layer 62. According to such a structure, in the termination region 14A, a pn diode composed of the p-type layer (the p-type pillar layer 24, the p-type well layer 64) of the surface side of the n-type pillar layer 22 and the n-type cathode layer 62 of the back surface side of the n-type pillar layer 22 is formed. Therefore, even in a case where the collector-side gate signal is stopped due to a malfunction, reverse conduction is achieved, and thus it is possible to suppress damage to the semiconductor device.

[0126] Further, according to the above-described embodiment, the n-type cathode layer 62B (or the n-type cathode layer 62C) is provided on a part of the surface layer of the lower surface of the n-type buffer layer 26 in the element region 12B (or the element region 12C). The p-type collector layer 30B is provided on another part of the surface layer of the lower surface of the n-type buffer layer 26. In the element region 12B and the termination region 14B (or the termination region 14C), the collector electrode 42 is provided so as to cover the p-type collector layer 30B and the n-type cathode layer 62B (or the n-type cathode layer 62C). According to such a structure, in the termination region 14B, a pn diode composed of the p-type layer (the p-type column layer 24, the p-type well layer 64) of the surface side of the n-type column layer 22 and the n-type cathode layer 62B of the back surface side of the n-type column layer 22 is formed. Therefore, even in the case where the collector-side gate signal is stopped due to a malfunction, reverse conduction can be achieved, and thus damage to the semiconductor device can be suppressed.

[0127] Further, according to the above-described embodiment, by forming the n-type cathode layer 62C and the collector-side n-type layer 34 in the same process, the impurity concentration or depth thereof is made the same. According to such a structure, since the collector-side n-type layer 34 in the element region 12C and the n-type cathode layer 62C in the element region 12C and the termination region 14C are formed in the same process, compared to the case where they are formed separately in different processes, the manufacturing process can be reduced.

[0128] According to the above-described embodiment, in the method of manufacturing the semiconductor device, the semiconductor device includes the element region 12C and the termination region 14C that surrounds the element region 12C in plan view. Also, in the element region 12C and the termination region 14C, the n-type pillar layer 22 and the plurality of p-type pillar layers 24 provided at depths inside the n-type pillar layer 22 from the upper surface of the n-type pillar layer 22 are alternately arranged in a direction intersecting the depth direction of the n-type pillar layer 22. Also, in the element region 12C, the emitter-side n-type layer 28 is provided on the upper surface of the n-type pillar layer 22, and the p-type base layer 32 is provided on the surface layer of the upper surface of the emitter-side n-type layer 28. Also, in the element region 12C, the n-type source layer 36 is provided on a portion of the surface layer of the upper surface of the p-type base layer 32. Also, in the element region 12C, the trench 52 reaching the emitter-side n-type layer 28 from the upper surface of the p-type base layer 32 and further reaching inside the n-type pillar layer 22 is provided in contact with the n-type source layer 36, and the emitter-side gate electrode 60 surrounded by the insulating film 56 is provided inside the trench 52. Also, in the element region 12C, the interlayer film 40 is provided covering a portion of the n-type source layer 36 and the emitter-side gate electrode 60, and the emitter electrode 44 is provided covering the p-type base layer 32, the n-type source layer 36, and the interlayer film 40. Also, in the element region 12C and the termination region 14C, the n-type buffer layer 26 is provided on the lower surface of the n-type pillar layer 22. Also, in the element region 12C, the p-type collector layer 30B is provided on a portion of the surface layer of the lower surface of the n-type buffer layer 26. Also, in the element region 12C, the n-type cathode layer 62C is provided on another portion of the surface layer of the lower surface of the n-type buffer layer 26, and the collector-side n-type layer 34 is provided on a portion of the surface layer of the lower surface of the p-type collector layer 30B, while in the termination region 14C, the n-type cathode layer 62C is provided on the surface layer of the lower surface of the n-type buffer layer 26. Also, in the element region 12C, the collector-side gate electrode 58 is provided in contact with the p-type collector layer 30B interposed between the n-type buffer layer 26 and the collector-side n-type layer 34 via the insulating film 54 (or the insulating film 54A) and does not reach the n-type pillar layer 22. Also, in the element region 12C, the interlayer film 38 is provided covering the collector-side gate electrode 58. Also, in the element region 12C and the termination region 14C, the collector electrode 42 is provided covering the p-type collector layer 30B, the interlayer film 38, and the n-type cathode layer 62C.

[0129] According to such a structure, in the semiconductor device having the superlattice structure, generation of a high surge voltage can be suppressed. Also, since the collector-side n-type layer 34 in the element region 12C and the n-type cathode layer 62C in the element region 12C and the termination region 14C are formed in the same process, the manufacturing process can be reduced compared to a case where they are formed in different processes, respectively.

[0130] In addition, the order of executing each process can be changed without particular limitation.

[0131] In addition, the same effects can be obtained even when other structures exemplified in the present specification are appropriately added to the above-described structure, i.e., when other structures not mentioned in the present specification are appropriately added to the above-described structure.

[0132] <Modifications of the above-described embodiments> In the above-described embodiments, the material, the material, the size, the shape, the relative positional relationship, or the implementation conditions of each structural element, and the like are sometimes described, but these are merely one example and are not limiting in all aspects.

[0133] Therefore, it can be considered that countless modifications and equivalents not described in the present example are assumed within the technical scope disclosed in the present specification. For example, cases where at least one structural element is modified, added, or omitted, and cases where at least one structural element in at least one embodiment is extracted and combined with a structural element of another embodiment are assumed.

[0134] In addition, in at least one embodiment described above, when a material name or the like is described without being specified, unless there is a contradiction, it is assumed that the material includes other additives, for example, includes an alloy or the like.

[0135] In addition, unless there is a contradiction, when a structural element is described as being provided with "one" in the above-described embodiments, the structural element can be provided with "one or more".

[0136] In addition, each structural element in the above-described embodiments is a conceptual unit, and includes a case where one structural element is composed of a plurality of configurations, a case where one structural element corresponds to a part of a certain configuration, and a case where a plurality of structural elements are included in one configuration within the technical scope disclosed in the present specification.

[0137] In addition, each structural element in the above-described embodiments includes a configuration having other structures or shapes as long as the same function is exerted.

[0138] In addition, the description in the present specification is referred to for all purposes related to the present technology, and is not considered to be a content of the prior art. Explanation of Reference Numerals

[0139] 12-element region, 12B-element region, 12C-element region, 14-terminal region, 14A-terminal region, 14B-terminal region, 14C-terminal region, 22 n-type column layer, 24 p-type column layer, 26 n-type buffer layer, 26A n-type buffer layer, 28 emitter-side n-type layer, 30 p-type collector layer, 30A p-type collector layer, 30B p-type collector layer, 32 p-type base layer, 34 collector-side n-type layer, 34A collector-side n-type layer, 36 n-type source layer, 38 interlayer film, 38A interlayer film, 40 interlayer film, 42 collector electrode, 44 emitter electrode, 50 trench, 52 trench, 54 insulating film, 54A insulating film, 56 insulating film, 58 collector-side gate electrode, 58A collector-side gate electrode, 60 emitter-side gate electrode, 62 n-type cathode layer, 62B n-type cathode layer, 62C n-type cathode layer, 64 p-type well layer, 66 interlayer film, 68 interlayer film, 70 interlayer film, 72 electrode, 74 electrode, 102 collector-side gate drive unit, 104 emitter-side gate drive unit, 106 PWM control unit, 108 current detection unit, 110 current mode determination unit, 112 voltage detection unit, 114 voltage mode determination unit, X1 collector current, X2 collector current, Y1 collector current, Y2 collector current.

Claims

1. A semiconductor device, characterized in that, include: First column layer of first conductivity type; A plurality of second pillar layers of a second conductivity type are disposed at a depth extending from the upper surface of the first pillar layer into the first pillar layer. A first impurity layer of a first conductivity type is disposed on the upper surface of the first pillar layer; A base layer of a second conductivity type is disposed on the surface layer of the upper surface of the first impurity layer; A trench configured to extend from the upper surface of the base layer to the first impurity layer and further into the interior of the first pillar layer; A first gate electrode is disposed within the trench and surrounded by a first insulating film; A source layer of a first conductivity type is disposed on a portion of the surface layer of the upper surface of the base layer and is in contact with the first insulating film. A first interlayer film is configured to cover a portion of the source layer and the first gate electrode; An emitter electrode, wherein the emitter electrode is configured to cover the base layer, the source layer and the first interlayer film; A first conductivity type buffer layer is disposed on the lower surface of the first pillar layer; A second conductivity type collector layer is disposed on the surface layer of the lower surface of the buffer layer. A second impurity layer of a first conductivity type is disposed on a portion of the surface layer of the lower surface of the current collector layer; The second gate electrode is configured to contact the collector layer sandwiched between the buffer layer and the second impurity layer via a second insulating film, and not to reach the first pillar layer; A second interlayer film is configured to cover the second gate electrode; as well as A current collector electrode, configured to cover the current collector layer and the second interlayer film. The first column layer and the second column layer are arranged alternately in a direction that intersects the depth direction of the first column layer.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A current detection unit that detects the collector current output via the collector electrode; as well as The control unit controls the voltage applied to the first gate electrode and the second gate electrode based on the polarity and current value of the collector current detected by the current detection unit.

3. The semiconductor device as claimed in claim 2, characterized in that, In the control unit When the polarity of the collector current is positive and the current value of the collector current is greater than a predetermined threshold, the first gate electrode is set to the on state and the second gate electrode is set to the off state. When the polarity of the collector current is positive and the current value of the collector current is less than a predetermined threshold, the first gate electrode is set to the on state, and the second gate electrode is set to the on state. When the polarity of the collector current is negative and the current value of the collector current is less than a predetermined threshold, the first gate electrode is set to the on state, and the second gate electrode is set to the on state. When the polarity of the collector current is negative and the current value of the collector current is greater than a predetermined threshold, the first gate electrode is set to the off state and the second gate electrode is set to the on state.

4. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A voltage detection unit that detects the voltage applied between the collector electrode and the emitter electrode, i.e., the inter-electrode voltage. as well as The control unit controls the voltage applied to the first gate electrode and the second gate electrode based on the polarity and voltage value of the inter-electrode voltage detected by the voltage detection unit.

5. The semiconductor device as claimed in claim 4, characterized in that, In the control unit When the polarity of the voltage between the electrodes is positive and the voltage value between the electrodes is greater than a predetermined threshold, the first gate electrode is set to the on state and the second gate electrode is set to the off state. When the polarity of the voltage between the electrodes is positive and the voltage value between the electrodes is less than a predetermined threshold, the first gate electrode is set to the on state, and the second gate electrode is set to the on state. When the polarity of the voltage between the electrodes is negative and the voltage value between the electrodes is less than a predetermined threshold, the first gate electrode is set to the on state, and the second gate electrode is set to the on state. When the polarity of the voltage between the electrodes is negative and the voltage value between the electrodes is greater than a predetermined threshold, the first gate electrode is set to the off state and the second gate electrode is set to the on state.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, This includes the component area and the terminal area surrounding the component area when viewed from above. The component region and the terminal region are provided with the first pillar layer, the second pillar layer, and the buffer layer. The semiconductor device further includes a first conductivity type cathode layer in the terminal region, the first conductivity type cathode layer being disposed on the surface layer of the lower surface of the buffer layer. In the terminal region, the collector electrode is configured to cover the cathode layer.

7. The semiconductor device as claimed in claim 6, characterized in that, The cathode layer is disposed on a portion of the surface layer of the lower surface of the buffer layer in the element region. The current collector layer is disposed on another portion of the surface layer of the lower surface of the buffer layer. In the element region and the terminal region, the collector electrode is configured to cover the collector layer and the cathode layer.

8. The semiconductor device as claimed in claim 6 or 7, characterized in that, The cathode layer and the second impurity layer are formed in the same process.

9. The semiconductor device as claimed in claim 8, characterized in that, The cathode layer and the second impurity layer have at least one of the same impurity concentration and depth.

10. A method of manufacturing a semiconductor device, the semiconductor device comprising a component region and a terminal region surrounding the component region in a top view, characterized in that, In the component region and the terminal region, a first pillar layer of a first conductivity type and a plurality of second pillar layers of a second conductivity type are alternately arranged in a direction intersecting the depth direction of the first pillar layer. The plurality of second pillar layers of the second conductivity type are disposed at a depth extending from the upper surface of the first pillar layer to within the first pillar layer. In the component region, a first impurity layer of a first conductivity type is disposed on the upper surface of the first pillar layer, and a base layer of a second conductivity type is disposed on the surface layer of the upper surface of the first impurity layer. In the component region, a source layer of a first conductivity type is disposed on a portion of the surface layer on the upper surface of the base layer. In the device region, a trench is provided in such a manner as to contact the source layer, extending from the upper surface of the base layer to the first impurity layer and further to the interior of the first pillar layer. A first gate electrode surrounded by a first insulating film is provided within the trench. In the device region, a first interlayer film is configured to cover a portion of the source layer and the first gate electrode, and an emitter electrode is configured to cover the base layer, the source layer, and the first interlayer film. In the component region and the terminal region, a buffer layer of the first conductivity type is disposed on the lower surface of the first pillar layer. In the component region, a collector layer of a second conductivity type is disposed on a portion of the surface layer of the lower surface of the buffer layer. In the component region, a cathode layer of the first conductivity type is disposed on another portion of the surface layer of the lower surface of the buffer layer, and a second impurity layer of the first conductivity type is disposed on a portion of the surface layer of the lower surface of the collector layer. Meanwhile, in the terminal region, the cathode layer is disposed on the surface layer of the lower surface of the buffer layer. In the device region, the second gate electrode is configured to contact the collector layer sandwiched between the buffer layer and the second impurity layer via the second insulating film, and not to reach the first pillar layer; In the device region, a second interlayer film is configured to cover the second gate electrode. In the element region and the terminal region, the collector electrode is configured to cover the collector layer, the second interlayer film, and the cathode layer.

Images