Semiconductor device, power conversion device, and method for manufacturing semiconductor device

Abstract

A semiconductor device is provided with: a semiconductor layer (3) of a first conductivity type; a back gate region (4), which is a diffusion layer of the second conductivity type, provided in a surface layer portion of the semiconductor layer (3); a trench (6) provided in the semiconductor layer (3) and penetrating the back gate region (4); a gate insulating film (10) provided on the inner surface of the trench (6); a gate electrode (11) provided on the gate insulating film (10) and embedded in the trench (6); and an electric field relaxation layer (7) which is a diffusion layer of the second conductivity type, is provided on the semiconductor layer (3) below the trench (6), and covers the bottom of the trench (6). The width of the bottom of the electric field relaxation layer (7) is smaller than the width of the entire electric field relaxation layer (7) and smaller than the width of the bottom of the trench (6).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, and particularly to a semiconductor device of trench gate type. BACKGROUND

[0002] A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) of trench gate type in which a gate electrode is arranged in a trench formed in a semiconductor layer (hereinafter referred to as "trench MOSFET") is known. The trench MOSFET can increase the current per unit area flowing therethrough because a channel region is formed in the depth direction of the semiconductor substrate.

[0003] In addition, a MOSFET formed using a silicon carbide (SiC) substrate (hereinafter referred to as "SiC trench MOSFET") has a high critical electric field because the band gap of SiC is larger than that of Si, and thus a high off-state voltage can be obtained. However, the critical electric field of the SiC trench MOSFET becomes high at the bottom surface of the trench in which the gate electrode is buried. Therefore, there is a concern that a high electric field is applied to the gate insulating film at the bottom surface of the trench, and the gate insulating film is destroyed at the bottom surface of the trench.

[0004] For example, a technique is disclosed in Patent Literature 1 in which a P-type electric field relaxation region is provided so as to cover the bottom of the trench in which the gate electrode is buried, and a P-type diffusion layer that electrically connects the electric field relaxation region and the P-type well is provided at the side surface of the trench, thereby relaxing the electric field applied to the gate insulating film at the bottom surface of the trench.

[0005] PRIOR ART DOCUMENTS

[0006] PATENT LITERATURE

[0007] Patent Literature 1: International Publication No. 2018 / 225600 SUMMARY

[0008] PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] If a P-type electric field relaxation region that covers the bottom of the trench is provided, and a P-type diffusion layer that electrically connects the electric field relaxation region and the P-type well is provided at the side surface of the trench as in the technique of Patent Literature 1, the resistance of the region between the trenches, that is, the JFET region (hereinafter referred to as "JFET resistance") becomes high, and thus there is a problem in that the on-state resistance of the MOSFET becomes high.

[0010] The present disclosure was made in order to solve the above problem, and aims to provide a semiconductor device that can suppress an increase in on-state resistance and prevent destruction of the gate insulating film at the bottom surface of the trench.

[0011] Means for solving the problem

[0012] The semiconductor device of the present disclosure includes a semiconductor layer of a first conductivity type; a back gate region that is a diffusion layer of a second conductivity type, provided in a surface layer portion of the semiconductor layer; a trench provided in the semiconductor layer and penetrating the back gate region; a gate insulating film provided on an inner surface of the trench; a gate electrode provided on the gate insulating film and buried in the trench; and an electric field relaxation layer that is a diffusion layer of the second conductivity type, provided in the semiconductor layer below the trench and covering a bottom portion of the trench, a width of a bottom portion of the electric field relaxation layer being smaller than a width of the entire electric field relaxation layer and smaller than a width of the bottom portion of the trench, and an angle formed by a side surface and a bottom surface of the bottom portion of the electric field relaxation layer being 60° or more and less than 90°.

[0013] Effects of the Invention

[0014] According to the semiconductor device of the present disclosure, an increase in on-resistance can be suppressed, and damage to the gate insulating film at the trench bottom surface can be prevented. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a plan view of the semiconductor device of Embodiment 1.

[0016] Figure 2 is a sectional view of the semiconductor device of Embodiment 1.

[0017] Figure 3 is a diagram showing the flow of current when the semiconductor device of Embodiment 1 is turned on.

[0018] Figure 4 is a diagram showing the flow of current when the semiconductor device of the comparative example is turned on.

[0019] Figure 5 is a diagram for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0020] Figure 6 is a diagram for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0021] Figure 7 is a diagram for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0022] Figure 8 is a diagram for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0023] Figure 9 is a diagram for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0024] Figure 10is a view for explaining a manufacturing method of a semiconductor device of Embodiment 1.

[0025] Figure 11 is a view for explaining a manufacturing method of a semiconductor device of Embodiment 1.

[0026] Figure 12 is a sectional view of a semiconductor device of Embodiment 2.

[0027] Figure 13 is a sectional view of a semiconductor device of Embodiment 3.

[0028] Figure 14 is a block diagram showing a structure of a power conversion system to which a power conversion device of Embodiment 4 is applied. DETAILED DESCRIPTION

[0029] In the following embodiments, the first conductivity type is set to N type and the second conductivity type is set to P type, but the first conductivity type can be set to P type and the second conductivity type can be set to N type. In addition, an N type having a relatively high impurity concentration is expressed as "N + ", and a P type having a relatively high impurity concentration is expressed as "P + ". Here, the high and low of the impurity concentration of each region is defined by the peak concentration. That is, a region having a high (or low) impurity concentration means a region having a high (or low) peak concentration of impurities.

[0030] <Embodiment 1>

[0031] Figure 1 and Figure 2 is a view showing a structure of a semiconductor device of Embodiment 1, that is, a SiC trench MOSFET. Figure 1 is a plan view of the semiconductor device, Figure 2 is a sectional view of a region 101 along a line A1-A2 and a region 102 along a line B1-B2 shown in Figure 1 .

[0032] As shown in Figure 2 , the semiconductor device of Embodiment 1 is formed using a semiconductor substrate 1 composed of N type (first conductivity type) SiC. An N type buffer layer 2 having a lower impurity concentration than the semiconductor substrate 1 is formed on the semiconductor substrate 1. An N type semiconductor layer, that is, an epitaxial layer 3 having a lower impurity concentration than the buffer layer 2 is formed on the buffer layer 2.

[0033] A P type diffusion layer, that is, a back gate region 4 in which an ion species (for example, aluminum, boron, or the like) of P type (second conductivity type) is implanted is formed in a surface layer portion of the epitaxial layer 3. A source region 5 as an N + type diffusion layer is formed in a surface layer portion of the back gate region 4.

[0034] A trench 6 with a depth of several μm is formed on the upper surface of the epitaxial layer 3. A P-type diffusion layer, i.e., an electric field mitigation layer 7, is formed at the bottom of the trench 6, which is implanted with P-type ions (such as aluminum, boron, etc.).

[0035] In cross-section, the overall width of the electric field mitigation layer 7 is the same as the width of the bottom of the trench 6, but the width of the bottom of the electric field mitigation layer 7 is smaller than the overall width and also smaller than the width of the bottom of the trench 6. The angle 7a formed by the side surface and bottom surface of the bottom of the electric field mitigation layer 7 is 60° or more and less than 90°. In addition, the width of the bottom of the electric field mitigation layer 7 is more than 40% and less than 90% of the width of the bottom of the trench 6.

[0036] In region 102 along line B1-B2, a connecting layer 8, which serves as a P-type diffusion layer, is formed to connect back gate region 4 to electric field mitigation layer 7.

[0037] P is selectively formed inside the source region 5, where the impurity concentration is higher than that in the back gate region 4. + The diffusion layer is the contact layer 9. The contact layer 9 penetrates the source region 5 and is connected to the back gate region 4 below the source region 5.

[0038] In the epitaxial layer 3, the N-type region that remains after the formation of the back gate region 4, source region 5, electric field mitigation layer 7, connection layer 8, and contact layer 9 becomes the drift layer 31.

[0039] A gate insulating film 10 is formed on the inner surface (bottom and side) of the trench 6. A gate electrode 11 is formed on the gate insulating film 10 in such a way that the trench 6 is filled.

[0040] An interlayer insulating film 12 is formed over the gate electrode 11. The interlayer insulating film 12 has contact holes 13 extending to the source region 5 and the contact layer 9. Specifically, the width of the contact holes 13 is proportional to P. + The contact layer 9 of the diffusion layer is large, and a portion of the contact hole 13 overlaps with the source region 5. In this embodiment, a silicide 14 made of NiSi is formed at the bottom of the contact hole 13 (the source region 5 exposed in the contact hole 13 and the upper surface of the contact layer 9). Furthermore, Figure 1 The top view shows the structure of the upper surface of the epitaxial layer 3. The illustration of the elements formed on the epitaxial layer 3 is omitted, but the location of the contact hole 13 is shown in dashed lines.

[0041] An active electrode 16 is formed on the interlayer insulating film 12. The active electrode 16 is electrically connected to the source region 5 and the contact layer 9 through the contact hole 13. The contact layer 9 provides an ohmic connection between the active electrode 16 and the back gate region 4.

[0042] In the present embodiment, the source electrode 16 is composed of aluminum or AlSi, and the barrier metal 15 composed of Ti or TiN is provided under the source electrode 16. Thus, the source electrode 16 is connected to the source region 5 and the contact layer 9 via the barrier metal 15 and the silicide 14.

[0043] Figure 3 is a sectional view showing the flow of current when the SiC trench MOSFET of Embodiment 1 is turned on. In addition, Figure 4 is a view showing the flow of current when the SiC trench MOSFET of the semiconductor device of Comparative Example is turned on. In Figure 4 , elements identical to or corresponding to those shown in Figure 1 and Figure 2 are denoted by the same reference numerals.

[0044] In the semiconductor device of Comparative Example, the width of the entire electric field relaxation layer 7 is the same as the width of the bottom of the trench 6 when sectioned, and the width of the bottom of the electric field relaxation layer 7 is also the same as the width of the bottom of the trench 6. The other structures are the same as those of the semiconductor device of Embodiment 1.

[0045] Referring to Figure 3 and Figure 4 , the flow of current in the on state of the SiC trench MOSFET is described. If a potential of 0.0 V is applied to the source electrode 16, and a potential of several V is applied to the gate electrode 11 and the back surface of the semiconductor substrate 1, an N-type inversion layer 23 (channel layer) is formed in the portion of the back gate region 4 that is in contact with the trench 6, and an N-type accumulation layer 24 is formed in the portion of the drift layer 31 that is in contact with the trench 6. That is, the inversion layer 23 is formed in the back gate region 4 of the side wall of the trench 6, and the accumulation layer 24 is formed in the drift layer 31 of the side wall of the trench 6.

[0046] If the inversion layer 23 and the accumulation layer 24 are formed on the side wall of the trench 6, the current 201 flows from the back surface of the semiconductor substrate 1 toward the source electrode 16. If the current 201 flows through the drift layer 31 to reach the vicinity of the trench 6, current 203 that collides with the electric field relaxation layer 7 of the bottom of the trench 6 after flowing into the inversion layer 23 and the accumulation layer 24, and current 202 that does not collide with the electric field relaxation layer 7 but directly flows into the inversion layer 23 and the accumulation layer 24 are generated.

[0047] In the region 101 along the A1-A2 line where the connection layer 8 is not present, the current 202 and the current 203 flow toward the source electrode 16 through the drift layer 31 between each other, the accumulation layer 24 and the inversion layer 23 formed on the side wall of the trench 6, and the electric field relaxation layer 7. On the other hand, in the region 102 along the B1-B2 line where the connection layer 8 is present, the current 202 and the current 204 flow toward the source electrode 16 through the drift layer 31 between the electric field relaxation layer 7 and the connection layer 8, the accumulation layer 24 and the inversion layer 23 formed on the side wall of the trench 6, and the connection layer 8.

[0048] Thus, the current 202 and the current 203 generated by the current 201 flowing from the back surface of the semiconductor substrate 1 toward the source electrode 16 flow into the region of the drift layer 31 where the electric field relaxation layer 7 and the connection layer 8 are not formed. Therefore, the amount of the current 202 and the current 203 is limited by the electric field relaxation layer 7 and the connection layer 8. The degree of this limitation is defined as the JFET resistance. In the region 102 where the connection layer 8 is present, the path (current path) through which the current flows is narrowed by the amount of the width of the connection layer 8, and thus the JFET resistance 222 of the region 102 where the connection layer 8 is present is higher than the JFET resistance 221 of the region 101 where the connection layer 8 is not present.

[0049] The on-resistance of the MOSFET is an index indicating the performance of the MOSFET when turned on, and corresponds to the sum of the channel resistance as the resistance of the inversion layer 23, the JFET resistance, and the drain resistance as the resistance of the drift layer 31. Thus, if the region of the electric field relaxation layer 7 and the connection layer 8 becomes larger, the JFET resistance becomes higher, and the on-resistance also becomes higher, and thus the performance of the MOSFET when turned on deteriorates.

[0050] The flow of the current in the semiconductor device of Embodiment 1 shown in Figure 3 is compared with the semiconductor device of the comparative example shown in Figure 4 In the semiconductor device of Embodiment 1, the width of the bottom of the electric field relaxation layer 7 is smaller than the width of the bottom of the trench 6, and thus the width of the entrance of the current path, that is, the region of the drift layer 31 where the electric field relaxation layer 7 and the connection layer 8 are not formed, is wide. Therefore, in the semiconductor device of Embodiment 1, the current 202 that flows without colliding with the electric field relaxation layer 7 increases (the current 203 that collides with the electric field relaxation layer 7 decreases) compared with the semiconductor device of the comparative example, and thus the limitation of the amount of the current, that is, the JFET resistance 221, 222 becomes small. Therefore, the on-resistance of the semiconductor device of Embodiment 1 is small, and the loss is also small.

[0051] In addition, in the semiconductor device of Embodiment 1, since the bottom of the trench 6 is covered with the electric field relaxation layer 7, the following effect is also obtained: the electric field applied to the gate insulating film 10 on the bottom surface of the trench 6 is relaxed, and the destruction of the gate insulating film 10 is prevented.

[0052] Thus, according to the semiconductor device of Embodiment 1, it is possible to suppress an increase in on-resistance of the MOSFET and prevent damage to the gate insulating film 10 at the bottom surface of the trench 6.

[0053] Figures 5 to 11 are diagrams for explaining the manufacturing method of the semiconductor device of Embodiment 1. Hereinafter, the manufacturing method of the semiconductor device of Embodiment 1 will be described with reference to these diagrams.

[0054] First, a semiconductor substrate 1 composed of N-type SiC is prepared, an N-type buffer layer 2 is grown on the semiconductor substrate 1, and an N-type epitaxial layer 3 is grown on the buffer layer 2. Further, a P-type back gate region 4 is formed by injecting P-type ion species (for example, aluminum, boron) into the entire surface of the epitaxial layer 3 multiple times. Furthermore, an N-type source region 5 is formed by selectively injecting N-type ion species (nitrogen, phosphorus) into the surface layer portion of the back gate region 4 using a selective ion implantation using a photolithography technique. Through the procedures up to this point, a structure of Figure 5 is obtained.

[0055] Next, a TEOS oxide film 17 is deposited on the surface of the source region 5 with a thickness of 2.0 μm to 3.0 μm, and the TEOS oxide film 17 is etched by selective dry etching using a photolithography technique, thereby forming openings in the TEOS oxide film 17 corresponding to the formation regions of the trenches 6. Further, the trenches 6 reaching the drift layer 31 below the source region 5 and the back gate region 4 are formed by selective etching with the TEOS oxide film 17 as a mask. Through the procedures up to this point, a structure of Figure 6 is obtained.

[0056] Further, the width of the trench 6 is wider than the width of the opening of the TEOS oxide film 17. In addition, the width of the upper portion of the trench 6 can also be wider than the width of the bottom portion. That is, the width of the upper portion of the mesa-shaped semiconductor layer between the trenches 6 can also be narrower than the width of the bottom portion. In this case, the angle formed by the side wall of the trench 6 and the upper surface of the source region 5 becomes an obtuse angle that is several degrees larger than a right angle.

[0057] Next, P-type ion species (for example, aluminum, boron) are injected multiple times by selective ion implantation with the TEOS oxide film 17 used when the trenches 6 are formed as a mask, thereby forming a P-type electric field relaxation layer 7 at the bottom portion of the trench 6. At this time, since the width of the opening of the TEOS oxide film 17 is narrower than the width of the trench 6, the P-type ion species are mainly injected into the central portion of the trench 6. Therefore, the electric field relaxation layer 7 formed at the bottom portion of the trench 6 is formed deeper in the central portion than in the outer peripheral portion. As a result, the width of the bottom portion of the electric field relaxation layer 7 is smaller than the width of the bottom portion of the trench 6. Through the procedures up to this point, a structure of Figure 7 is obtained.

[0058] Next, the area 101 where the connection layer 8 is not provided is covered with a resist 18 using a photolithography technique. Then, by selective ion implantation with the TEOS oxide film 17 and the resist 18 as masks, P-type ion species (e.g., aluminum, boron) are implanted from a slanting direction several times, whereby a P-type connection layer 8 connecting the electric field relaxation layer 7 and the back gate region 4 is formed on the side wall of the trench 6 of the area 102. The implantation angle in the ion implantation performed from a slanting direction is, for example, in the range of 20 degrees to 40 degrees. Figure 8

[0059] After the resist 18 is removed and the TEOS oxide film 17 is removed by wet etching, a TEOS oxide film 19 is deposited on the epitaxial layer 3 including the inside of the trench 6 at a thickness of 1.0 μm to 2.0 μm. Then, by selective dry etching using a photolithography technique, the TEOS oxide film 19 is etched, whereby an opening corresponding to the formation area of the contact layer 9 is formed on the TEOS oxide film 19. Then, by selective ion implantation with the TEOS oxide film 19 as a mask, P-type ion species (e.g., aluminum, boron, BF2) are implanted once to several times, whereby a P-type contact layer 9 is formed as shown in FIG. 6. Figure 9

[0060] After the TEOS oxide film 19 is removed by wet etching, annealing is performed at a temperature of 1700°C or higher to activate the N-type or P-type diffusion layer formed in the above-described processes. In order to prevent Si sublimation, annealing can also be performed after a carbon-based film (graphite film, etc.) is deposited. The carbon-based film is removed after annealing.

[0061] Next, a TEOS oxide film is deposited on the epitaxial layer 3 at a thickness of about 800 nm to 1500 nm, and the TEOS oxide film is patterned by selective etching using a photolithography technique, whereby a field oxide film (not shown) is formed.

[0062] Next, an oxide film having a thickness of about 30 nm to 70 nm is deposited on the upper surface of the epitaxial layer 3 including the inside of the trench 6, and nitridation at 1100°C is performed, whereby a gate insulating film 10 is formed. Next, polycrystal silicon including N-type impurities is deposited on the epitaxial layer 3 to fill the trench 6, and the polycrystal silicon is etched by selective dry etching using a photolithography technique, whereby a gate electrode 11 is formed in the trench 6. By the processes up to this point, a structure as shown in FIG. 7 is obtained. Figure 10

[0063] ​​​After that, a TEOS oxide film is deposited on the epitaxial layer 3, and then a BPSG film is deposited with a thickness of about 300 nm to 1000 nm, and a TEOS oxide film is again deposited thereon, thereby forming an interlayer insulating film 12. Then, a contact hole 13 is formed in the interlayer insulating film 12 by selective dry etching using a photolithography technique. Etching of the interlayer insulating film 12 composed of the TEOS oxide film, the BPSG film, and the TEOS oxide film can be performed by wet etching alone, or by a combination of dry etching and wet etching (wet etching after dry etching).

[0064] Next, Ni is sputtered on the source region 5 and the contact layer 9 exposed from the contact hole 13, and after heat treatment to remove unreacted Ni, heat treatment is again performed, thereby forming a silicide 14 composed of NiSi. In addition, Ti or TiN is sputtered on the interlayer insulating film 12 including the inside of the contact hole 13 to form a barrier metal 15. Then, aluminum or AlSi is sputtered on the barrier metal 15, and is patterned by selective dry etching or wet etching using a photolithography technique, thereby forming a source electrode 16. After that, a SiN film or a conductive nitride film is deposited, and a polyimide is deposited thereon, thereby forming a protective film (not shown).

[0065] By the above procedure, a structure of Figure 11 is obtained, and the semiconductor device of Embodiment 1 is completed.

[0066] <Embodiment 2>

[0067] Figure 12 is a view showing the structure of the semiconductor device, i.e., SiC trench MOSFET, of Embodiment 2. In Figure 12 , elements identical to or corresponding to the elements shown in Figure 1 and Figure 2 are labeled with the same reference numerals as them.

[0068] The structure of the semiconductor device of Embodiment 2 is such that the cross-sectional shape of the electric field relaxation layer 7 provided at the bottom of the trench 6 is octagonal. The other structure is identical to that of Embodiment 1.

[0069] In a cross section, the width of the entire electric field relaxation layer 7 is identical to the width of the bottom of the trench 6, but since the shape of the electric field relaxation layer 7 is octagonal, the width of the upper portion of the electric field relaxation layer 7 and the width of the bottom are smaller than the width of the bottom of the trench 6. The angle 7b composed of the side surface and the upper surface of the upper portion of the electric field relaxation layer 7 is 30° or more and less than 90°. In addition, the width of the upper portion of the electric field relaxation layer 7 is 4 times or more and 9 times or less of the width of the bottom of the trench 6.

[0070] In the semiconductor device of Embodiment 2, the cross-sectional shape of the electric field relaxation layer 7 is octagonal, and thus the region of the drift layer 31 that is in contact with the trench 6 is larger than in Embodiment 1. Therefore, the accumulation layer 24, which constitutes a part of the current path, is larger, and the JFET resistance can be further reduced.

[0071] <Embodiment 3>

[0072] Figure 13 is a view that shows the structure of the semiconductor device of Embodiment 2, that is, the SiC trench MOSFET. In Figure 13 , elements that are the same as or correspond to the elements shown in Figure 1 and Figure 2 are labeled with the same reference numerals as those elements.

[0073] The structure of the semiconductor device of Embodiment 3 is such that the depth (distance from the upper surface of the epitaxial layer 3) of the bottom of the connection layer 8 that connects the electric field relaxation layer 7 and the back gate region 4 is shallower than the bottom of the electric field relaxation layer 7. The other structures are the same as in Embodiment 1 or 2. Further, in Figure 13 the trench 6 is shown as having an octagonal cross-sectional shape as in Embodiment 2.

[0074] In the semiconductor device of Embodiment 3, the depth of the bottom of the connection layer 8 is shallower than the bottom of the electric field relaxation layer 7, and thus the entrance of the current path (the region of the drift layer 31 that is not formed with the electric field relaxation layer 7 and the connection layer 8) is larger than in Embodiment 1 or 2, and thus the JFET resistance can be further reduced.

[0075] <Embodiment 4>

[0076] This embodiment applies the semiconductor devices of Embodiments 1 to 3 described above to a power conversion device. The application of the semiconductor devices of Embodiments 1 to 3 is not limited to a specific power conversion device, but in the following, as Embodiment 4, a case in which the semiconductor devices of Embodiments 1 to 3 are applied to a three-phase inverter will be described.

[0077] Figure 14 is a block diagram that shows the structure of a power conversion system to which the power conversion device of this embodiment is applied.

[0078] Figure 14 The power conversion system shown in is composed of a power source 1100, a power conversion device 1200, and a load 1300. The power source 1100 is a direct-current power source that supplies direct current to the power conversion device 1200. The power source 1100 can be composed of various power sources, for example, can be composed of a direct-current system, a solar cell, a storage battery, or can be composed of a rectification circuit or an AC / DC converter that is connected to an alternating-current system. In addition, the power source 1100 can be composed of a DC / DC converter that converts direct current output from a direct-current system into prescribed electric power.

[0079] The power conversion device 1200 is a three-phase inverter connected between the power supply 1100 and the load 1300, converts direct current supplied from the power supply 1100 into alternating current, and supplies alternating current to the load 1300. As shown in FIG. 1, the power conversion device 1200 has a main conversion circuit 1201 that converts direct current into alternating current and outputs it, a drive circuit 1202 that outputs a drive signal that drives each switching element of the main conversion circuit 1201, and a control circuit 1203 that outputs a control signal that controls the drive circuit 1202 to the drive circuit 1202. Figure 14

[0080] The load 1300 is a three-phase motor that is driven by alternating current supplied from the power conversion device 1200. Furthermore, the load 1300 is not limited to a specific use, and is used as a motor mounted on various electric appliances, for example, as a motor for a hybrid automobile, an electric automobile, a railway vehicle, an elevator, or an air conditioning device.

[0081] Hereinafter, the details of the power conversion device 1200 will be described. The main conversion circuit 1201 has switching elements and freewheeling diodes (not shown) and converts direct current supplied from the power supply 1100 into alternating current by switching of the switching elements and supplies it to the load 1300. The specific circuit structure of the main conversion circuit 1201 has various structures, but the main conversion circuit 1201 of the present embodiment is a two-level three-phase full-bridge circuit and can be constituted by six switching elements and six freewheeling diodes that are connected in antiparallel to each switching element. The semiconductor device of any one of the above-described Embodiments 1 to 3 is applied to each switching element of the main conversion circuit 1201. The six switching elements are connected in series in two switching elements each to constitute an upper arm and a lower arm, and each upper arm and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper arm and lower arm, that is, three output terminals of the main conversion circuit 1201 are connected to the load 1300.

[0082] The drive circuit 1202 generates a drive signal that drives the switching elements of the main conversion circuit 1201 and supplies it to the control electrode of the switching elements of the main conversion circuit 1201. Specifically, a drive signal that causes the switching elements to be in an on state and a drive signal that causes the switching elements to be in an off state are output to the control electrode of each switching element in accordance with a control signal from the control circuit 1203 described later. In the case where the switching elements are maintained in the on state, the drive signal is a voltage signal (on signal) that is higher than the threshold voltage of the switching elements, and in the case where the switching elements are maintained in the off state, the drive signal becomes a voltage signal (off signal) that is lower than the threshold voltage of the switching elements.

[0083] ​The control circuit 1203 controls the switching elements of the main conversion circuit 1201 to supply desired electric power to the load 1300. Specifically, the time (on time) during which each switching element of the main conversion circuit 1201 should be in the on state is calculated in accordance with the electric power that should be supplied to the load 1300. For example, the main conversion circuit 1201 can be controlled by PWM control that modulates the on time of the switching elements in accordance with the voltage that should be output. Then, the drive circuit 1202 outputs a control command (control signal) so that an on signal is output to the switching element that should be in the on state and an off signal is output to the switching element that should be in the off state at each time. The drive circuit 1202 outputs the on signal or the off signal as a drive signal to the control electrode of each switching element in accordance with the control signal.

[0084] In the power conversion device of the present embodiment, the semiconductor device of Embodiments 1 to 3 is applied as the switching element of the main conversion circuit 1201, and thus the conversion efficiency can be improved.

[0085] In the present embodiment, an example in which the semiconductor device of Embodiments 1 to 3 is applied to a two-level three-phase inverter is described, but the application of the semiconductor device of Embodiments 1 to 3 is not limited to this, and the semiconductor device of Embodiments 1 to 3 can be applied to various power conversion devices. In the present embodiment, the power conversion device is assumed to be a two-level power conversion device, but it can also be a three-level or a multi-level power conversion device, and in the case of supplying electric power to a single-phase load, the semiconductor device of Embodiments 1 to 3 can be applied to a single-phase inverter. In addition, in the case of supplying electric power to a direct-current load or the like, the semiconductor device of Embodiments 1 to 3 can be applied to a DC / DC converter, an AC / DC converter.

[0086] In addition, the power conversion device to which the semiconductor device of Embodiments 1 to 3 is applied is not limited to the case in which the load is a motor described above, and for example, can be used as a power supply device for an electric discharge machine, a laser machine, or an induction heating cooker, a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system, an electricity storage system, or the like.

[0087] In the above description, a MOSFET is shown as the semiconductor device, but the semiconductor device can be a structure of a trench gate type, and for example, can be a structure other than a MOSFET such as an IGBT (Insulated Gate Bipolar Transistor), an RC-IGBT (Reverse Conducting IGBT), or the like. In addition, the material of the semiconductor layer such as the semiconductor substrate 1, the buffer layer 2, and the epitaxial layer 3 is not limited to SiC, and for example, can be silicon (Si), and can also be a wide bandgap semiconductor other than SiC such as gallium nitride (GaN), diamond, or the like.

[0088] Furthermore, each embodiment can be freely combined, or appropriately deformed or omitted.

[0089] <Notes>

[0090] Hereinafter, each embodiment of the present disclosure is described as a note.

[0091] (Note 1)

[0092] A semiconductor device comprising:

[0093] a semiconductor layer of a first conductive type;

[0094] a back gate region that is a diffusion layer of a second conductive type, provided in a surface layer portion of the semiconductor layer;

[0095] a trench provided in the semiconductor layer and penetrating the back gate region;

[0096] a gate insulating film provided on an inner surface of the trench;

[0097] a gate electrode provided on the gate insulating film and buried in the trench; and

[0098] an electric field relaxation layer that is a diffusion layer of the second conductive type, provided in the semiconductor layer below the trench and covering a bottom portion of the trench,

[0099] a width of a bottom portion of the electric field relaxation layer is smaller than a width of the entire electric field relaxation layer and smaller than a width of the bottom portion of the trench.

[0100] (Note 2)

[0101] The semiconductor device according to Note 1, in which

[0102] a width of an upper portion of the electric field relaxation layer is smaller than a width of the entire electric field relaxation layer and smaller than a width of the bottom portion of the trench.

[0103] (Note 3)

[0104] The semiconductor device according to Note 1 or 2, in which

[0105] the semiconductor device further comprises a connection layer that is a diffusion layer of the second conductive type, provided in the semiconductor layer on a side wall of the trench, connecting the electric field relaxation layer and the back gate region,

[0106] a depth of a bottom portion of the connection layer is shallower than a depth of a bottom portion of the electric field relaxation layer.

[0107] (Note 4)

[0108] A power conversion device including:

[0109] a main conversion circuit having the semiconductor device according to any one of Embodiments 1 to 3, which converts input power and outputs;

[0110] a drive circuit which outputs a drive signal for driving the semiconductor device to the semiconductor device; and

[0111] a control circuit which outputs a control signal for controlling the drive circuit to the drive circuit.

[0112] (Embodiment 5)

[0113] A method of manufacturing a semiconductor device, including the following steps:

[0114] (a) forming a back gate region as a diffusion layer of a second conductivity type in a surface layer portion of a semiconductor layer of a first conductivity type;

[0115] (b) forming a trench through the back gate region in the semiconductor layer by selective etching using a mask; and

[0116] (c) forming an electric field relaxation layer as a diffusion layer of the second conductivity type covering a bottom portion of the trench in the semiconductor layer under the trench by selective ion implantation using the mask used in the step (b),

[0117] the trench formed in the step (b) has a width wider than that of an opening of the mask,

[0118] the bottom portion of the electric field relaxation layer formed in the step (c) has a width smaller than that of the entire electric field relaxation layer and smaller than that of the bottom portion of the trench.

[0119] Explanation of Reference Numerals

[0120] 1: semiconductor substrate; 2: buffer layer; 3: epitaxial layer; 4: back gate region; 5: source region; 6: trench; 7: electric field relaxation layer; 8: connection layer; 9: contact layer; 10: gate insulating film; 11: gate electrode; 12: interlayer insulating film; 13: contact hole; 14: silicide; 15: barrier metal; 16: source electrode; 17: TEOS oxide film; 18: resist; 19: TEOS oxide film; 23: inversion layer; 24: accumulation layer; 31: drift layer; 1100: power supply; 1200: power conversion device; 1201: main conversion circuit; 1202: drive circuit; 1203: control circuit; 1300: load.

Claims

1. A semiconductor device comprising: The first conductivity type of semiconductor layer; The back gate region, which serves as the diffusion layer of the second conductivity type, is disposed on the surface portion of the semiconductor layer; A trench is disposed in the semiconductor layer and extends through the back gate region; A gate insulating film is disposed on the inner surface of the trench; A gate electrode is disposed on the gate insulating film and embedded in the trench; as well as As an electric field mitigation layer serving as the diffusion layer for the second conductivity type, it is disposed beneath the semiconductor layer in the trench and covers the bottom of the trench. The width of the bottom of the electric field mitigation layer is smaller than the overall width of the electric field mitigation layer, and also smaller than the width of the bottom of the trench. The angle formed by the side surface and bottom surface of the bottom of the electric field mitigation layer is greater than 60° and less than 90°.

2. The semiconductor device according to claim 1, wherein, The width of the upper part of the electric field mitigation layer is smaller than the overall width of the electric field mitigation layer, and smaller than the width of the bottom of the trench.

3. The semiconductor device according to claim 1 or 2, wherein, The semiconductor device further includes a connection layer serving as a diffusion layer for the second conductivity type. This connection layer is disposed on the semiconductor layer on the sidewall of the trench, connecting the electric field mitigation layer and the back gate region. The bottom of the connecting layer is shallower than the bottom of the electric field mitigation layer.

4. A power conversion device comprising: A main conversion circuit having a semiconductor device as described in any one of claims 1 to 3, which converts and outputs the input power; A driving circuit that outputs a driving signal to the semiconductor device; as well as A control circuit that outputs control signals to the drive circuit.

5. A method for manufacturing a semiconductor device, comprising the following steps: (a) A back gate region serving as a diffusion layer of a second conductivity type is formed on the surface portion of a semiconductor layer of the first conductivity type. (b) A trench penetrating the back gate region is formed in the semiconductor layer by selective etching using a mask; and (c) By using selective ion implantation with the mask used in step (b), an electric field mitigation layer, serving as a diffusion layer of the second conductivity type, is formed in the semiconductor layer beneath the trench, covering the bottom of the trench. The width of the groove formed in step (b) is wider than the width of the opening in the mask. The width of the bottom of the electric field mitigation layer formed in step (c) is smaller than the overall width of the electric field mitigation layer and smaller than the width of the bottom of the trench.

Images