Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device (1) is provided with: an electron traveling layer (103); an electron supply layer (104) provided on the electron traveling layer (103); a gate electrode (303) provided on the electron supply layer (104); a contact layer (212) embedded in a through recess (211) that penetrates the electron supply layer (104) at a position across the gate electrode (303); an electron supply auxiliary layer (401), which is an example of an n-type semiconductor layer comprising an n-type semiconductor containing Si, provided in contact with the electron supply layer (104), in contact with the contact layer (212), and not in contact with the gate electrode (303); a first insulating layer (201) that is provided on the electron supply auxiliary layer (401), is in contact with the Si-containing alloy layer (402) and the gate electrode (303), and is not in contact with the contact layer (212); and a source electrode (301) and / or a drain electrode (302) disposed on the contact layer (212) and the alloy layer (402).

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method thereof, and particularly relates to a Group III nitride semiconductor device using a Group III nitride semiconductor and a manufacturing method thereof. BACKGROUND

[0002] A Group III nitride semiconductor device using a Group III nitride semiconductor, particularly gallium nitride (GaN) or aluminum gallium nitride (AlGaN), has a high insulating breakdown voltage due to the width of the band gap of the material. In addition, in the Group III nitride semiconductor device, a hetero structure such as AlGaN / GaN can be easily formed.

[0003] In the AlGaN / GaN hetero structure, a high concentration of electrons (Two Dimensional Electron Gas) is generated on the GaN layer side at the interface between the AlGaN layer and the GaN layer due to the difference between the piezoelectric polarization due to the difference in the lattice constant between the materials and the spontaneous polarization of the AlGaN and the GaN, and a channel of a two-dimensional electron gas layer is formed. A Group III nitride semiconductor device that utilizes a channel based on the two-dimensional electron gas is applied to high-frequency power devices and the like because the electron saturation velocity is relatively high and the resistance to insulation is relatively high, and the thermal conductivity is also relatively high.

[0004] In these Group III nitride semiconductor devices, in order to improve the characteristics, it is preferable to reduce the contact between the ohmic electrode and the two-dimensional electron gas layer (hereinafter referred to as “ohmic contact”), the resistance of the channel based on the two-dimensional electron gas, and the like, within the Group III nitride semiconductor device as much as possible.

[0005] In the past, in a Group III nitride semiconductor device that utilizes a channel based on a two-dimensional electron gas, a technique for reducing the ohmic contact resistance has been proposed. For example, in Patent Literature 1, a technique is disclosed in which, in order to reduce the ohmic contact resistance, a recess portion (hereinafter referred to as “through recess portion”) that penetrates an electron supply layer composed of AlGaN is formed in a portion of the Group III nitride semiconductor device where the ohmic electrode is formed, and the ohmic electrode is formed.

[0006] PRIOR ART DOCUMENTS PATENT LITERATURE Patent Literature 1: International Publication No. 2021 / 246227 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION However, if a through-hole is formed in the electron supply layer as in the technology disclosed in Patent Document 1, it is inevitable that the two-dimensional electron gas layer and the contact layer buried in the through-hole become point-connected in nature. In addition, if a through-hole is formed in the electron supply layer, at the interface between the two-dimensional electron gas layer (channel layer) composed of GaN and the contact layer, not only do crystal defects occur at the time of formation of the through-hole, but also a region in which the carrier (electron) concentration is reduced occurs at the side surface adjacent portion of the through-hole in the electron supply layer due to contaminant substances in the atmosphere, bonding defects, and there is a problem in that the maximum drain current is reduced.

[0008] The present disclosure was completed in view of such problems, and aims to provide a semiconductor device capable of suppressing reduction in maximum drain current and a manufacturing method thereof.

[0009] Means for solving the problems To achieve the above object, one embodiment of the semiconductor device of the present disclosure has an electron traveling layer, an electron supply layer provided on the electron traveling layer and having a larger band gap than the electron traveling layer, a gate electrode provided on the electron supply layer, a source side contact layer and a drain side contact layer buried in a recess portion that penetrates the electron supply layer at a position apart from the gate electrode, an n-type semiconductor layer composed of an n-type semiconductor containing Si, provided in contact with the electron supply layer and in contact with the source side contact layer and / or the drain side contact layer without being in contact with the gate electrode, an alloy layer provided on the n-type semiconductor layer, containing Si, and having a thickness of 2 nm or less, an insulating layer provided on a portion of the electron supply layer on which the gate electrode is not provided, in contact with the gate electrode and not in contact with the source side contact layer and / or the drain side contact layer, and a source electrode and / or a drain electrode provided on the source side contact layer and / or the drain side contact layer and on the alloy layer, Further, one embodiment of the first manufacturing method of the semiconductor device of the present disclosure includes the following steps: a step of forming an electron supply layer having a larger band gap than an electron travel layer on the electron travel layer; a step of forming an insulating layer containing Si on the electron supply layer without exposure to the atmosphere; a step of thinning a part of the insulating layer to form a thin portion in the insulating layer; a step of leaving a part of the thin portion as an insulating layer remaining portion and forming a through-hole portion that penetrates the thin portion of the insulating layer and the electron supply layer to reach the electron travel layer; a step of embedding and forming a contact layer in the through-hole portion; a step of forming a source electrode and / or a drain electrode across the insulating layer remaining portion and the contact layer; a step of performing heat treatment to form an alloy layer and an electron supply auxiliary layer in the insulating layer remaining portion and the electron supply layer; and a step of removing the insulating layer in which a part is separated from the source electrode and / or the drain electrode to form a gate electrode.

[0010] Further, one embodiment of the second manufacturing method of the semiconductor device of the present disclosure includes the following steps: a step of forming an electron supply layer having a larger band gap than an electron travel layer on the electron travel layer; a step of forming an insulating layer containing Si on the electron supply layer without exposure to the atmosphere; a step of thinning a part of the insulating layer to form a thin portion in the insulating layer; a step of leaving a part of the thin portion as an insulating layer remaining portion and forming a through-hole portion that penetrates the thin portion of the insulating layer and the electron supply layer to reach the electron travel layer; a step of forming a source electrode and / or a drain electrode across the insulating layer remaining portion and the through-hole portion; a step of performing heat treatment to form an alloy layer and an electron supply auxiliary layer in the insulating layer remaining portion and the electron supply layer; and a step of removing the insulating layer in which a part is separated from the source electrode and / or the drain electrode to form a gate electrode.

[0011] Effects of Invention According to the present disclosure, a semiconductor device capable of suppressing reduction in maximum drain current can be obtained. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a cross-sectional view showing a structure of the semiconductor device of Embodiment 1.

[0013] Figure 2 is a schematic view showing a conduction band of a band gap of the semiconductor device of Embodiment 1.

[0014] Figure 3A is a cross-sectional view showing a step of forming a semiconductor layer stack and a first insulating layer and a second insulating layer in the manufacturing method of the semiconductor device of Embodiment 1.

[0015] Figure 3B is a cross-sectional view showing a process of forming a thin portion of the first insulating layer in the method for manufacturing the semiconductor device of Embodiment 1.

[0016] Figure 3C is a cross-sectional view showing a process of forming a through-hole recess in the method for manufacturing the semiconductor device of Embodiment 1.

[0017] Figure 3D is a cross-sectional view showing a process of forming a contact layer in the method for manufacturing the semiconductor device of Embodiment 1.

[0018] Figure 3E is a cross-sectional view showing a process of forming a source electrode and a drain electrode in the method for manufacturing the semiconductor device of Embodiment 1.

[0019] Figure 3F is a cross-sectional view showing a process of performing heat treatment in the method for manufacturing the semiconductor device of Embodiment 1.

[0020] Figure 3G is a cross-sectional view showing a process of forming a gate electrode in the method for manufacturing the semiconductor device of Embodiment 1.

[0021] Figure 4 is a cross-sectional view showing a structure of the semiconductor device of Embodiment 2.

[0022] Figure 5A is a cross-sectional view showing a process of forming a semiconductor layer stack and a first insulating layer and a second insulating layer in the method for manufacturing the semiconductor device of Embodiment 2.

[0023] Figure 5B is a cross-sectional view showing a process of forming a thin portion of the first insulating layer in the method for manufacturing the semiconductor device of Embodiment 2.

[0024] Figure 5C is a cross-sectional view showing a process of forming a through-hole recess in the method for manufacturing the semiconductor device of Embodiment 2.

[0025] Figure 5D is a cross-sectional view showing a process of forming a source electrode and a drain electrode in the method for manufacturing the semiconductor device of Embodiment 2.

[0026] Figure 5E is a cross-sectional view showing a process of performing heat treatment in the method for manufacturing the semiconductor device of Embodiment 2.

[0027] Figure 5F is a cross-sectional view showing a process of forming a gate electrode in the method for manufacturing the semiconductor device of Embodiment 2. DETAILED DESCRIPTION

[0028] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. The embodiments shown herein each represent a specific example of the present disclosure. Therefore, the numerical values, shapes, constituting elements, arrangement and connection of the constituting elements, and steps (procedures) and the order of the steps shown in the following embodiments are examples, and the present disclosure is not intended to be limited thereto. Thus, with respect to the constituting elements in the following embodiments that are not described in the independent claims representing the most generic concept of the present disclosure, the constituting elements are described as arbitrary constituting elements.

[0029] In addition, each drawing is a schematic view and is not necessarily strictly illustrated. Therefore, the scale and the like are not necessarily consistent in each drawing. In each drawing, the same reference numeral is attached to substantially the same structure, and repetitive description is omitted or simplified.

[0030] In addition, in the present specification, the terms "upper", "above", "lower", and "below" in the structure of a semiconductor device are not terms indicating the upper (vertically upward) and lower (vertically downward) in the absolute spatial recognition, but terms defined by the relative positional relationship according to the stacking order in the stacked structure. In addition, the terms "upper" and "lower" are applicable not only to the case where two constituting elements are arranged apart from each other with other constituting elements present between the two constituting elements, but also to the case where two constituting elements are arranged in close contact with each other with the two constituting elements being in contact with each other.

[0031] In addition, in the present specification and the drawings, the x-axis, the y-axis, and the z-axis represent three axes of a three-dimensional orthogonal coordinate system. In each embodiment, two axes parallel to the upper surface included in the substrate possessed by the semiconductor device are taken as the x-axis and the y-axis, and the direction orthogonal to the upper surface is taken as the z-axis direction. In the embodiments described below, the positive direction of the z-axis is sometimes referred to as up, and the negative direction of the z-axis is sometimes referred to as down. Furthermore, in the present specification, "plan view" refers to the case where the substrate possessed by the semiconductor device is observed from the positive direction of the z-axis.

[0032] (Embodiment 1) First, the use of the semiconductor device 1 of Embodiment 1 will be described. Figure 1 The semiconductor device 1 of Embodiment 1 will be described. Figure 1 is a cross-sectional view showing the structure of the semiconductor device 1 of Embodiment 1.

[0033] In the present embodiment, a case where the semiconductor device 1 is a High Electron Mobility Transistor (HEMT) provided with a Schottky junction gate structure will be described.

[0034] As shown in FIG. 1, the semiconductor device 1 of Embodiment 1 includes a substrate 10, a gate electrode 20, a source electrode 30, a drain electrode 40, and a gate insulating layer 50. Figure 1As shown in FIG. 1, the semiconductor device 1 includes a substrate 101, a buffer layer 102, an electron travel layer 103, an electron supply layer 104, a first insulating layer 201, a second insulating layer 202, a source electrode 301, a drain electrode 302, a gate electrode 303, an electron supply auxiliary layer 401, and an alloy layer 402. The substrate 101 is, for example, a silicon substrate composed of Si. In the present embodiment, the substrate 101 is, for example, a silicon substrate composed of a Si single crystal in which a main surface is a (111) surface. Note that the substrate 101 is not limited to a silicon substrate, and can be a substrate composed of sapphire (Sapphire), SiC, GaN, or AlN, or the like, which serves as a base for forming a nitride semiconductor layer. The substrate 101 has, for example, a resistivity of 1 kΩ or more. Note that a substrate having a resistivity of 20 Ω or less can also be used as the substrate 101.

[0035] The buffer layer 102 is provided on the substrate 101. The buffer layer 102 is, for example, a III-V nitride semiconductor layer composed of a plurality of layers of AlN and AlGaN, and has a thickness of 2 μm. In this case, 20 to 100 pairs of AlN and AlGaN can be stacked as one pair. Note that the buffer layer 102 can be a structure in which a plurality of layers of AlN and GaN (0 ≤ α < 0.8) are stacked, and can include a superlattice structure. Further, the buffer layer 102 can be composed of a single layer or a plurality of layers of III-V nitride semiconductors such as InGaN and AlInGaN. Note that the carbon concentration of the buffer layer 102 can be set to 1 x 1018atoms / cm3or more. 1-α Ga α N (0 ≤ α < 0.8) can be stacked, and can include a superlattice structure. Further, the buffer layer 102 can be composed of a single layer or a plurality of layers of III-V nitride semiconductors such as InGaN and AlInGaN. Note that the carbon concentration of the buffer layer 102 can be set to 1 x 1018atoms / cm3or more. 19 atoms / cm 3 The buffer layer 102 is made high-resistive by the above. The electron travel layer 103 is provided on the buffer layer 102. In the present embodiment, the electron travel layer 103 is, for example, a GaN layer composed of GaN having a thickness of 150 nm. Note that the III-V nitride semiconductor that constitutes the electron travel layer 103 is not limited to GaN. The electron travel layer 103 can be composed of III-V nitride semiconductors such as InGaN, AlGaN, and AlInGaN. Further, the electron travel layer 103 can include an n-type impurity.

[0036] The electron supply layer 104 is provided on the electron travel layer 103. The electron supply layer 104 has a larger band gap than the electron travel layer 103. In the present embodiment, the electron supply layer 104 is, for example, an AlGaN layer having a thickness of 13 nm and composed of AlGaN with an Al composition ratio of 30%. On the electron travel layer 103 side of the hetero interface between the electron supply layer 104 and the electron travel layer 103, a high concentration of two-dimensional electron gas is generated, forming a channel of the two-dimensional electron gas layer 105. Thus, the semiconductor device 1 has the two-dimensional electron gas layer 105. The two-dimensional electron gas layer 105 is composed of a first two-dimensional electron gas layer 105A and a second two-dimensional electron gas layer 105B that differ in electron concentration of two-dimensional electron gas, as will be described later in detail.

[0037] Further, the Al composition ratio of the electron supply layer 104 composed of AlGaN is not limited to 30%. The Al composition ratio of the electron supply layer 104 can be 20 to 100%. In addition, the Group III nitride semiconductor that constitutes the electron supply layer 104 is not limited to AlGaN. The electron supply layer 104 can be composed of a Group III nitride semiconductor such as AlInGaN containing In. In addition, the electron supply layer 104 can contain an impurity of n-type.

[0038] A cap layer can be provided on the electron supply layer 104. As the cap layer, for example, a GaN layer having a thickness of about 1 to 2 nm composed of GaN can be used. Further, a spacer layer can be provided between the electron travel layer 103 and the electron supply layer 104. As the spacer layer, for example, an AlN layer having a thickness of about 1 nm composed of AlN can be used.

[0039] The first insulating layer 201 is provided on the electron supply layer 104. The first insulating layer 201 is an insulating layer containing Si (silicon). In the present embodiment, the first insulating layer 201 is a SiN layer composed of SiN. Specifically, the first insulating layer 201 is a SiN layer having a thickness of 2 nm composed of In-situ SiN. In addition, In-situ means formed without exposure to the atmosphere. Thus, the first insulating layer 201 composed of In-situ SiN is a SiN layer formed without exposure to the atmosphere after the formation of the electron supply layer 104.

[0040] By thus composing the first insulating layer 201 of In-situ SiN, it is possible to eliminate the uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104. By eliminating the uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104, the generation of interface states is suppressed. Thus, it is possible to avoid the rise in potential at the interface and suppress the decrease in electron concentration of the two-dimensional electron gas.

[0041] The layer thickness of the first insulating layer 201 is preferably 2 nm or more and 30 nm or less. By making the layer thickness of the first insulating layer 201 2 nm or more, it is possible to suppress a case where oxygen is distributed unevenly at the interface between the first insulating layer 201 and the electron supply layer 104 due to natural oxidation. On the other hand, if the layer thickness of the first insulating layer 201 exceeds 30 nm, the wafer warps when the semiconductor device 1 is manufactured, and the quality of the semiconductor device 1 decreases. Therefore, the layer thickness of the first insulating layer 201 is preferably 30 nm or less. That is, by making the layer thickness of the first insulating layer 201 30 nm or less, it is possible to suppress warping of the wafer.

[0042] In addition, the first insulating layer 201 preferably does not contain oxygen. If the first insulating layer 201 contains oxygen, the interface state at the interface between the first insulating layer 201 and the electron supply layer 104 increases, the potential at the interface between the first insulating layer 201 and the electron supply layer 104 rises, and the electron concentration of the two-dimensional electron gas decreases. By making the first insulating layer 201 not contain oxygen, it is possible to suppress a decrease in the electron concentration of the two-dimensional electron gas.

[0043] The second insulating layer 202 is provided on the first insulating layer 201. In this embodiment, the second insulating layer 202 is in contact with the first insulating layer 201. The layer thickness of the second insulating layer 202 is thicker than that of the first insulating layer 201, but is not limited thereto. That is, the layer thickness of the second insulating layer 202 can also be thinner than that of the first insulating layer 201. The second insulating layer 202 is, for example, a silicon oxide layer having a thickness of 50 nm composed of SiO2. In addition, the second insulating layer 202 is not limited to SiO2, and can be composed of SiN or SiON, or the like.

[0044] The first insulating layer 201 is provided with an opening portion 201a. The opening portion 201a is formed in the first insulating layer 201 in a region where the gate electrode 303 is provided. Therefore, the first insulating layer 201 is provided on a portion of the electron supply layer 104 where the gate electrode 303 is not provided.

[0045] In addition, the second insulating layer 202 is provided with an opening portion 202a. The opening portion 202a is formed in the second insulating layer 202 in a region where the gate electrode 303 is provided. Therefore, the second insulating layer 202 is provided on a portion of the first insulating layer 201 where the gate electrode 303 is not provided.

[0046] The first insulating layer 201 and the second insulating layer 202 are in contact with the gate electrode 303. Further, the first insulating layer 201 and the second insulating layer 202 are not in contact with the contact layer 212. In the present embodiment, the first insulating layer 201 and the second insulating layer 202 are not in contact with either of the source side contact layer 212A and the drain side contact layer 212B, but are not limited thereto. For example, the first insulating layer 201 can be in contact with one of the source side contact layer 212A and the drain side contact layer 212B, but not in contact with the other. Further, the second insulating layer 202 can be in contact with one of the source side contact layer 212A and the drain side contact layer 212B, but not in contact with the other.

[0047] The through-hole recess 211 is provided in the electron supply layer 104. In the present embodiment, the through-hole recess 211 is provided in such a manner as to pass through the first insulating layer 201 and the electron supply layer 104 and reach the electron travel layer 103. The through-hole recess 211 reaches the inside of the electron travel layer 103, and a recess is provided in the electron travel layer 103.

[0048] The distance from the upper surface of the electron travel layer 103 to the deepest part of the bottom surface of the through-hole recess 211 is preferably 10 nm or less. As an example, the distance from the upper surface of the electron travel layer 103 to the deepest part of the bottom surface of the through-hole recess 211 is 5 nm. Further, the angle of elevation of the bottom surface of the through-hole recess 211 from the center portion toward the side portion is preferably 10 degrees or less, and more preferably 5 degrees or less. Thus, when the through-hole recess 211 is formed by dry etching, it is possible to reduce the occurrence of crystal defects on the side surface of the through-hole recess 211, and it is possible to suppress the decrease in the maximum drain current.

[0049] The through-hole recess 211 is provided in correspondence with the region in which the source electrode 301 and the drain electrode 302 are provided. Specifically, the through-hole recess 211 is provided in such a manner as to face each other with the gate electrode 303 interposed therebetween.

[0050] The contact layer 212 is provided in the through-hole recess 211. The contact layer 212 is provided in such a manner as to be buried in the through-hole recess 211. The contact layer 212 provided in one of the pair of through-hole recesses 211 is the source side contact layer 212A, and the contact layer 212 provided in the other of the pair of through-hole recesses 211 is the drain side contact layer 212B. The source side contact layer 212A and the drain side contact layer 212B are provided at positions where the gate electrode 303 is interposed therebetween.

[0051] Further, the through-hole recess 211 is provided separately from the first insulating layer 201 and the second insulating layer 202. Therefore, the contact layer 212 buried in the through-hole recess 211 is also provided separately from the first insulating layer 201 and the second insulating layer 202, and the contact layer 212 is not in contact with the first insulating layer 201 and the second insulating layer 202.

[0052] The contact layer 212 is, for example, an n-GaN layer composed of n-type GaN. In addition, the material composing the contact layer 212 is not limited to n-type GaN, and can be composed of a Group III nitride semiconductor such as InGaN, AlGaN, AlInGaN, and the like containing Si, Ge, or the like as a donor as an n-type impurity, or can be composed of a multilayer electrode film composed of a laminated structure in which Ti, Al, and the like are laminated in order. In addition, the material composing the contact layer 212 can be composed of Ti, Ta, Al, Au, Hf, Ru, and Cu.

[0053] The source electrode 301 or the drain electrode 302 is provided on the contact layer 212. Specifically, the source electrode 301 is provided on the source-side contact layer 212A, and the drain electrode 302 is provided on the drain-side contact layer 212B. The source electrode 301 and the drain electrode 302 are provided so as to face each other with the gate electrode 303 interposed therebetween.

[0054] In addition, the source electrode 301 and the drain electrode 302 are provided on the contact layer 212 and the alloy layer 402. In the present embodiment, the source electrode 301 and the drain electrode 302 also cover a portion of the second insulating layer 202. Specifically, the source electrode 301 is provided so as to cover the source-side contact layer 212A, the alloy layer 402, and a portion of the second insulating layer 202. In addition, the drain electrode 302 is provided so as to cover the drain-side contact layer 212B, the alloy layer 402, and a portion of the second insulating layer 202.

[0055] The source electrode 301 and the drain electrode 302 are composed of, for example, a multilayer electrode film composed of a laminated structure in which a Ti film having a layer thickness of 30 nm and an Al film having a layer thickness of 200 nm are laminated in order, but are not limited thereto. In addition, the source electrode 301 and the drain electrode 302 can be composed of Ti, Ta, W, Al, Au, Hf, Ru, and Cu.

[0056] The gate electrode 303 is provided on the electron supply layer 104. Specifically, the gate electrode 303 is provided on the electron supply layer 104 via the opening portion 201a of the first insulating layer 201 and the opening portion 202a of the second insulating layer 202. In addition, the opening width of the opening portion 201a of the first insulating layer 201 is the same as the opening width of the opening portion 202a of the second insulating layer 202, but is not limited thereto.

[0057] The gate electrode 303 is, for example, a multilayer electrode film composed of a stacked structure in which a TiN film and an Al film are stacked in this order. Note that the gate electrode 303 is not limited to the stacked structure of the TiN film and the Al film, and can be composed of a nitride and a carbide of a transition metal. Specifically, the gate electrode 303 can be composed of TiN, WN, TaN, or HfN. Note that the gate electrode 303 can be composed of Ti, Ta, W, Al, Pd, Pt, Hf, Ru, or Cu, or a compound containing any of these elements, or a multilayer electrode film composed of a plurality of stacked structures. Note that another insulating layer or a p-type nitride semiconductor layer can be provided between the electron supply layer 104 and the gate electrode 303.

[0058] The electron supply auxiliary layer 401 is an n-type semiconductor layer composed of an n-type semiconductor containing Si. The thickness of the electron supply auxiliary layer 401 is preferably less than or equal to 2 nm, but is not limited thereto. In this embodiment, the electron supply auxiliary layer 401 is an n-AlGaN layer composed of n-type AlGaN containing Si with a thickness of 1 nm.

[0059] The electron supply auxiliary layer 401 is in contact with the electron supply layer 104 and the contact layer 212, and is not in contact with the gate electrode 303. In a plan view, the electron supply auxiliary layer 401 is provided between the contact layer 212 and the first insulating layer 201. In a cross-sectional view, the electron supply auxiliary layer 401 is provided so as to be buried in an end portion of the electron supply layer 104 on the side of the contact layer 212. Specifically, in a cross-sectional view, the electron supply auxiliary layer 401 is provided so that an upper surface is coplanar with an upper surface of the electron supply layer 104 and a lower surface is positioned between the upper surface and a lower surface of the electron supply layer 104.

[0060] In this embodiment, the electron supply auxiliary layer 401 is in contact with the source-side contact layer 212A and the drain-side contact layer 212B. Specifically, the electron supply auxiliary layer 401 is buried in an end portion of the electron supply layer 104 on the side of the source-side contact layer 212A and an end portion on the side of the drain-side contact layer 212B. Note that the electron supply auxiliary layer 401 can be in contact with only either of the source-side contact layer 212A and the drain-side contact layer 212B. Further, the electron supply auxiliary layer 401 can be divided into a plurality of layers. In that case, the electron supply auxiliary layer 401 on the side of the source electrode 301 of the plurality of electron supply auxiliary layers 401 can be in contact with the source-side contact layer 212A, and the electron supply auxiliary layer 401 on the side of the drain electrode 302 of the plurality of electron supply auxiliary layers 401 can be in contact with the drain-side contact layer 212B.

[0061] The width of the electron supply auxiliary layer 401 can be smaller than the distance L between the end portion of the electron supply auxiliary layer 401 on the side of the gate electrode 303 and the gate electrode 303. As an example, the width of the electron supply auxiliary layer 401 is 1 μm or less in cross section. Thus, the increase in the off current between the gate electrode 303 and the drain electrode 302 can be effectively suppressed.

[0062] Alternatively, one of the electron supply auxiliary layer 401 on the side of the source electrode 301 and the electron supply auxiliary layer 401 on the side of the drain electrode 302 can not be in contact with the gate electrode 303, and the other can be in contact with the gate electrode 303. For example, in the case where the width of the electron supply auxiliary layer 401 on the side of the drain electrode 302 is within the distance L, the electron supply auxiliary layer 401 on the side of the source electrode 301 can be in contact with the gate electrode 303. Thus, the access resistance between the source electrode 301 and the gate electrode 303 can be reduced, and thus the maximum drain current can be increased.

[0063] The alloy layer 402 is provided on the electron supply auxiliary layer 401 which is an n-type semiconductor layer. Specifically, the alloy layer 402 is provided directly above the electron supply auxiliary layer 401 and in contact with the electron supply auxiliary layer 401.

[0064] The alloy layer 402 is a Si-based alloy layer containing Si. The alloy layer 402 is an alloy layer obtained by reacting the elements constituting the first insulating layer 201 and the elements constituting the source electrode 301 and / or the drain electrode 302. In this case, the Si constituting the alloy layer 402 comes from the Si contained in the first insulating layer 201. In the present embodiment, the first insulating layer 201 is a SiN layer, and the source electrode 301 and the drain electrode 302 are a laminated film of a Ti film and an Al film, and thus the alloy layer 402 is an alloy layer composed of Ti, Al, Si, and N. Specifically, the alloy layer 402 is a TiAlSiN alloy layer composed of a TiAlSiN alloy having a thickness of 1 nm. The thickness of the alloy layer 402 is not limited to 1 nm, and is preferably 2 nm or less. Thus, the Si concentration diffused into the electron supply layer 104 can be increased.

[0065] In addition, the alloy constituting the alloy layer 402 is not limited to the TiAlSiN alloy, and various combinations of alloys can be considered depending on the types of the elements constituting the first insulating layer 201 and the types of the elements constituting the source electrode 301 and the drain electrode 302. Specifically, the alloy layer 402 can be composed of an alloy containing at least one of Ti, Ta, Al, Au, Hf, Ru, and Cu elements and Si.

[0066] Further, the alloy layer 402 does not contact the gate electrode 303, but contacts the contact layer 212. The alloy layer 402 is provided between the contact layer 212 and the first insulating layer 201 when viewed in plan. In this embodiment, the alloy layer 402 contacts not only the contact layer 212 but also the first insulating layer 201.

[0067] In this embodiment, the alloy layer 402 contacts the source-side contact layer 212A and the drain-side contact layer 212B, respectively. Further, the alloy layer 402 can contact only either of the source-side contact layer 212A and the drain-side contact layer 212B. Further, the alloy layer 402 can be divided into a plurality of alloy layers. In this case, the alloy layer 402 on the source electrode 301 side of the plurality of alloy layers 402 can contact the source-side contact layer 212A, and the alloy layer 402 on the drain electrode 302 side of the plurality of alloy layers 402 can contact the drain-side contact layer 212B.

[0068] With the semiconductor device 1 configured in this way, the electron concentration of the two-dimensional electron gas layer 105 can be made different between the portion where the electron supply assisting layer 401 and the alloy layer 402 are present and the portion where the electron supply assisting layer 401 and the alloy layer 402 are not present. Specifically, the two-dimensional electron gas layer 105 has a first two-dimensional electron gas layer 105A in a portion not located below the electron supply assisting layer 401 and the alloy layer 402, and a second two-dimensional electron gas layer 105B in a portion where the electron supply assisting layer 401 and the alloy layer 402 are present, the electron concentration of the second two-dimensional electron gas layer 105B being higher than the electron concentration of the first two-dimensional electron gas layer 105A. Further, the contact layer 212 and the second two-dimensional electron gas layer 105B are ohmic-electrically connected.

[0069] Here, the use of Figure 2 The mechanism in which the electron concentration of the second two-dimensional electron gas layer 105B is higher than the electron concentration of the first two-dimensional electron gas layer 105A is described. Figure 2 is a schematic view of a conduction band indicating the energy band of the semiconductor device 1 of Embodiment 1.

[0070] In Figure 2 , the solid line A is a view of a portion corresponding to the single-dot chain line A of Figure 1 . The broken line B is a view of a portion corresponding to the single-dot chain line B of Figure 1 . That is, Figure 2 the solid line A in Figure 2 is a view of an adjoining portion of the gate electrode 303, i.e., a gate adjoining portion (i.e., a portion where the electron supply assisting layer 401 and the alloy layer 402 are not provided), and the name of the corresponding layer is indicated with the lower double-arrow column (A). Further, Figure 2The broken line B in FIG. 1 is a view of the abutment portion of the contact layer 212, that is, the contact abutment portion (that is, the portion provided with the electron supply assisting layer 401 and the alloy layer 402), and the names of the corresponding layers are indicated with the column (B) of the double-headed arrow on the upper side. Further, the broken line on the upper side (left side in the drawing) of the electron supply assisting layer 401 indicates that the Fermi level of the drain electrode 302 as a metal is in agreement with the conduction band.

[0071] As described above, according to the semiconductor device 1 of the present embodiment, the electron supply assisting layer 401 composed of an n-type semiconductor is provided inside the electron supply layer 104. Due to this, in the portion provided with the electron supply layer 104, the potential of the electron supply layer 104 is relatively lowered, and thus the potential of the interface position between the electron supply layer 104 and the electron travel layer 103 is lowered. As a result, the electron concentration of the second two-dimensional electron gas layer 105B is increased. That is, the electron concentration of the second two-dimensional electron gas layer 105B located below the electron supply assisting layer 401 is relatively larger than the electron concentration of the first two-dimensional electron gas layer 105A not located below the electron supply assisting layer 401.

[0072] In this way, by making the electron concentration of the second two-dimensional electron gas layer 105B higher than the electron concentration of the first two-dimensional electron gas layer 105A, it is possible to alleviate the case where the electron concentration of the side abutment portion of the through-hole 211 in the electron supply layer 104 is lowered. As a result, it is possible to suppress the decrease in the maximum drain current. Further, since the electron concentration of the gate abutment portion corresponding to the first two-dimensional electron gas layer 105A is maintained, it is also possible to decrease the drain current between the gate electrode 303 and the drain electrode 302. That is, with the structure of the semiconductor device 1 of the present embodiment, it is possible to decrease the gate-drain current while suppressing the decrease in the maximum drain current. In addition, the current through not only the contact layer 212 but also the electron supply assisting layer 401 and the alloy layer 402 is increased, and thus it is possible to further suppress the decrease in the maximum drain current.

[0073] Further, in the semiconductor device 1 of the present embodiment, the width of the electron supply assisting layer 401 is preferably 1 μm or less. Due to this, it is possible to effectively decrease the drain current between the gate electrode 303 and the drain electrode 302.

[0074] In the semiconductor device 1 of this embodiment, the band gap of the electron supply auxiliary layer 401 on the side of the electron supply layer 104 can be smaller than the band gap of the electron supply layer 104 on the side of the electron traveling layer 103. Specifically, in the case where the electron supply layer 104 is composed of AlGaN, the Al composition on the side of the electron supply auxiliary layer 401 of the electron supply layer 104 can be smaller than the Al composition on the side of the electron traveling layer 103 of the electron supply layer 104. The larger the Al composition, the lower the electron affinity of AlGaN, and thus the lower the barrier height when the Si-containing alloy layer 402 comes into contact with the electron supply auxiliary layer 401. Therefore, by making the band gap of the electron supply auxiliary layer 401 on the side of the electron supply layer 104 smaller than the band gap of the electron supply layer 104 on the side of the electron traveling layer 103, the ohmic contact resistance can be reduced. Moreover, by reducing the ohmic contact resistance, the variation in the drain current can be reduced.

[0075] In addition, in the semiconductor device 1 of this embodiment, the first insulating layer 201 and the electron supply auxiliary layer 401 can contain halogen such as fluorine (F) or chlorine (Cl), and the halogen concentration of the first insulating layer 201 and the electron supply auxiliary layer 401 is preferably each 1 x 10 18 atoms / cm 3 or more. This is because halogen contained in the semiconductor layer and the insulating layer has a high electronegativity and thus becomes a negative fixed charge. Therefore, by making the halogen concentration of the first insulating layer 201 1 x 10 18 atoms / cm 3 or more, the negative fixed charge in the first insulating layer 201 can be reduced. Thus, the rise in the electric potential at the interface position between the electron supply layer 104 and the electron traveling layer 103 can be eliminated, and the decrease in the electron concentration of the second two-dimensional electron gas layer 105B due to halogen can be eliminated.

[0076] In addition, in the semiconductor device 1 of this embodiment, the thickness of the first insulating layer 201 can be greater than the thickness of the alloy layer 402. Thus, the drain current between the gate electrode 303 and the drain electrode 302 can be further reduced.

[0077] Next, the manufacturing method of the semiconductor device 1 of this embodiment will be described. Figures 3A-3G is a cross-sectional view showing each step in the manufacturing method of the semiconductor device 1 of Embodiment 1. Figures 3A-3G is a cross-sectional view showing each step in the manufacturing method of the semiconductor device 1 of Embodiment 1. Figure 3A A step of forming the semiconductor layer stack 100 and the first insulating layer 201 and the second insulating layer 202 is shown. Figure 3B A step of forming the thin portion 201b in the first insulating layer 201 is shown. Figure 3C A step of forming the through-hole recess portion 211 is shown. Figure 3DA process of forming the contact layer 212 is shown. Figure 3E A process of forming the source electrode 301 and the drain electrode 302 is shown. Figure 3F A process of performing heat treatment is shown. Figure 3G A process of forming the gate electrode 303 is shown.

[0078] First, as shown in Figure 3A A semiconductor layer stack 100 is formed on the substrate 101 by a metal organic chemical vapor deposition (MOCVD) method (semiconductor layer stack formation process). The semiconductor layer stack 100 includes a buffer layer 102, an electron traveling layer 103, and an electron supply layer 104.

[0079] In the present embodiment, the buffer layer 102 having a layer thickness of 2 μm and composed of a stack of AlN and AlGaN, the electron traveling layer 103 having a layer thickness of 200 nm and composed of GaN, and the electron supply layer 104 having a layer thickness of 20 nm and composed of AlGaN with an Al composition ratio of 25% are epitaxially grown in the +c plane direction (<0001> direction) on the substrate 101 composed of Si, thereby forming the semiconductor layer stack 100.

[0080] Next, the first insulating layer 201 is formed on the semiconductor layer stack 100 as an insulating layer containing Si (first insulating layer formation process). Specifically, after the semiconductor layer stack 100 is formed, the first insulating layer 201 composed of SiN having a layer thickness of 2 nm is formed in the same semiconductor crystal growth apparatus (MOCVD furnace). That is, the first insulating layer 201 is formed on the electron supply layer 104 without being exposed to the atmosphere. In this way, by forming the first insulating layer 201 directly above the electron supply layer 104 without being exposed to the atmosphere, oxygen is not unevenly distributed between the electron supply layer 104 and the first insulating layer 201.

[0081] Next, the second insulating layer 202 is formed on the first insulating layer 201 (second insulating layer formation process). Specifically, after the first insulating layer 201 is formed, the substrate 101 on which the semiconductor layer stack 100 and the first insulating layer 201 are formed is transferred to another apparatus, and the second insulating layer 202 composed of SiO2 having a layer thickness of 50 nm is formed. In this configuration, a high concentration of two-dimensional electron gas is generated on the electron traveling layer 103 side of the hetero interface between the electron supply layer 104 and the electron traveling layer 103, and a two-dimensional electron gas layer 105 is formed.

[0082] Further, as film formation conditions at the time of forming the first insulating layer 201 and the second insulating layer 202, for example, the growth temperature is 900 to 1150°C, and the source gas is SiH4and NH3. Further, in order not to mix halogen as an impurity into the first insulating layer 201, it is preferable not to use halogen at the time of performing dry cleaning in the MOCVD furnace. Further, even if halogen is used at the time of dry cleaning, it is possible to remove halogen from the MOCVD furnace after dry cleaning by using N2, NH3, or the like.

[0083] Next, as shown in FIG. 2B, a portion of the first insulating layer 201 is thinned to form a thin portion 201b in the first insulating layer 201 (thin portion formation step). Figure 3B

[0084] Specifically, after applying a resist on the second insulating layer 202, the resist is patterned by photolithography, whereby a mask (resist mask) is formed in a portion of the second insulating layer 202 other than the regions where the contact layer 212 and the electron supply auxiliary layer 401 and the alloy layer 402 are to be formed. That is, an opening portion is formed in the regions of the resist where the contact layer 212 and the electron supply auxiliary layer 401 and the alloy layer 402 are to be formed. Specifically, an opening portion is formed in the regions including the respective regions where the source side contact layer 212A and the drain side contact layer 212B are to be formed.

[0085] Next, etching is performed using the resist having the opening portion as a mask, whereby a portion of the second insulating layer 202 is removed and a portion of the first insulating layer 201 is thinned. In this case, by performing dry etching and wet etching using the resist having the opening portion as a mask, it is possible to selectively remove the second insulating layer 202 with respect to the first insulating layer 201. That is, by performing dry etching and wet etching, the second insulating layer 202 is removed and the first insulating layer 201 is thinned in the regions where the contact layer 212 and the electron supply auxiliary layer 401 and the alloy layer 402 are to be formed. Thus, as shown in FIG. 2C, it is possible to thin a portion of the first insulating layer 201 (the regions where the contact layer 212 and the electron supply auxiliary layer 401 and the alloy layer 402 are to be formed) and form a thin portion 201b in the first insulating layer 201 as a remaining film. Then, the mask (resist) and the polymer generated by dry etching are removed. Figure 3B

[0086] Further, in the case where wet etching is performed on the first insulating layer 201 and the second insulating layer 202, by using DHF or BHF, it is possible to selectively remove the second insulating layer 202 with respect to the first insulating layer 201. Further, in the case where the second insulating layer 202 composed of SiO2is formed, it is also possible to selectively remove only a portion of the first insulating layer 201 by oxidizing the surface of the first insulating layer 201. ​​

[0087] Furthermore, the thickness of the thin portion 201b (residual film) of the first insulating layer 201 is preferably 2 nm or less. In this case, the thickness of the thin portion 201b (residual film) of the first insulating layer 201 is preferably more than half the thickness of the first insulating layer 201 before thinning (i.e., preferably more than half remaining), but is not limited thereto. As an example, when the thickness of the first insulating layer 201 before thinning is 2 nm, the thin portion 201b (residual film) of the first insulating layer 201 is 1.5 nm.

[0088] Next, as Figure 3C As shown, a through recess 211 is formed by removing the end of the thin portion 201b of the first insulating layer 201 and a portion of the semiconductor stacked structure 100 (through recess formation process). Specifically, a portion of the thin portion 201b of the first insulating layer 201 is left as an insulating layer residue 201b1, and a through recess 211 is formed that penetrates the thin portion 201b of the first insulating layer 201 and the electron supply layer 104 to reach the electron travel layer 103.

[0089] In this case, firstly, after applying a photoresist over the second insulating layer 202 and a portion of the thin portion 201b of the first insulating layer 201, the photoresist is patterned using photolithography, thereby forming a mask (photoresist mask) outside the region where the through-recess 211 is formed. That is, the photoresist forms an opening in the region where the through-recess 211 is formed. Specifically, the photoresist has openings in the regions where the source-side contact layer 212A and the drain-side contact layer 212B are formed, respectively.

[0090] Next, dry etching is performed using a resist with the opening as a mask, thereby leaving a portion of the thin portion 201b of the first insulating layer 201 as an insulating layer residue 201b1, and forming a through recess 211 that penetrates the end of the thin portion 201b of the first insulating layer 201 and the electron supply layer 104 to reach the electron travel layer 103. Specifically, as Figure 3C As shown, two through-recesses 211 are formed corresponding to the regions forming the source-side contact layer 212A and the drain-side contact layer 212B. By forming the through-recesses 211, a portion of the electron travel layer 103 is exposed. Then, the mask (resist) and the polymer generated by dry etching are removed.

[0091] Furthermore, in this embodiment, the through-hole recess 211 is formed by dry etching, but it is not limited to this. Specifically, the through-hole recess 211 can also be formed by wet etching.

[0092] In addition, after the first insulating layer 201 is thinned and the through-hollows 211 are formed by dry etching, the side surface of the electron supply layer 104 can be selectively wet-etched using SPM, APM, or KOH. Thus, the side surface of the through-hollows 211 can be made into an inclined surface. Specifically, the side surface of the through-hollows 211 can be made into an inclined surface having an elevation angle of 5 degrees or less in a direction from the center of the bottom surface of the through-hollows 211 toward the side surface.

[0093] Next, as shown in FIG. 2B, the contact layer 212 is formed in the through-hollows 211 (contact layer formation step). Figure 3D

[0094] Specifically, the second insulating layer 202 and the insulating layer remaining portion 201bl of the first insulating layer 201 are used as masks, and n-GaN is grown using MOCVD so as to be embedded in both of the through-hollows 211. Thus, the contact layer 212 composed of n-GaN is selectively formed in both of the through-hollows 211. In addition, the contact layer 212 embedded in one of the through-hollows 211 is the source-side contact layer 212A, and the contact layer 212 embedded in the other of the through-hollows 211 is the drain-side contact layer 212B. + -GaN. Thus, the contact layer 212 composed of n-GaN is selectively formed in both of the through-hollows 211. In addition, the contact layer 212 embedded in one of the through-hollows 211 is the source-side contact layer 212A, and the contact layer 212 embedded in the other of the through-hollows 211 is the drain-side contact layer 212B. + -GaN. Thus, the contact layer 212 composed of n-GaN is selectively formed in both of the through-hollows 211. In addition, the contact layer 212 embedded in one of the through-hollows 211 is the source-side contact layer 212A, and the contact layer 212 embedded in the other of the through-hollows 211 is the drain-side contact layer 212B.

[0095] In the present embodiment, Si is doped as an n-type impurity, and n-GaN is grown so as to form the contact layer 212 with a thickness of 100 nm. The doping concentration of Si in the contact layer 212 is, for example, 2 x 1019 / cm3. + -GaN. Thus, the contact layer 212 composed of n-GaN is selectively formed in both of the through-hollows 211. In addition, the contact layer 212 embedded in one of the through-hollows 211 is the source-side contact layer 212A, and the contact layer 212 embedded in the other of the through-hollows 211 is the drain-side contact layer 212B. 19 / cm 3 In addition, the contact layer 212 is not limited to being formed by regrowth, and can be formed by sputtering. In addition, the contact layer 212 can be formed by ion implantation and plasma treatment, or the like, without forming the through-hollows 211.

[0096] Next, as shown in FIG. 2B, the contact layer 212 is formed in the through-hollows 211 (contact layer formation step). Figure 3E

[0097] Specifically, after a laminated film composed of a Ti film with a layer thickness of 30 nm and an Al film with a layer thickness of 200 nm is formed by vapor deposition or sputtering, the unnecessary laminated film is removed by a lift off method. Thus, the source electrode 301 and the drain electrode 302 composed of the laminated film of the Ti film and the Al film are formed in a predetermined shape on the contact layer 212. In the present embodiment, the source electrode 301 is formed on the source-side contact layer 212A, and the drain electrode 302 is formed on the drain-side contact layer 212B. Then, the resist mask and the polymer are removed.​​

[0098] In addition, in this embodiment, the source electrode 301 and the drain electrode 302 are formed by vapor deposition and stripping, but are not limited thereto. For example, after forming a stacked film by sequentially depositing Ti film and Al film by sputtering, the stacked film can be patterned using photolithography and dry etching to form the source electrode 301 and drain electrode 302 of a predetermined shape.

[0099] Next, as Figure 3F As shown, heat treatment is performed to form an electron supply auxiliary layer 401 and an alloy layer 402 in the insulating layer residue 201b1 of the first insulating layer 201 and the electron supply layer 104 (heat treatment process).

[0100] The heat treatment temperature is, for example, 400~600°C, preferably 500~550°C. Furthermore, the heat treatment is preferably performed in an oxygen-free atmosphere. In this embodiment, the heat treatment was carried out at 540°C in a N2 atmosphere.

[0101] By performing heat treatment in this way, the elements constituting the insulating layer residue 201b1 of the first insulating layer 201 and the electron supply layer 104 diffuse and alloy with the elements constituting the source electrode 301 and the drain electrode 302 due to heat, forming the electron supply auxiliary layer 401 and the alloy layer 402.

[0102] Specifically, in this embodiment, since the first insulating layer 201 is an insulating layer containing Si and the electron supply layer 104 is an AlGaN layer, in the upper portion of the electron supply layer 104 that is connected to the insulating layer residue 201b1 of the first insulating layer 201, nitrogen vacancies are formed due to the diffusion of Si constituting the first insulating layer 201, thus forming an n-type AlGaN layer as an electron supply auxiliary layer 401. That is, an electron supply auxiliary layer 401 as an n-type semiconductor layer is formed.

[0103] Furthermore, in this embodiment, since the source electrode 301 and drain electrode 302 contain Ti, nitrogen vacancies are formed due to the diffusion of Ti, thereby making the upper portion of the electron supply layer 104 n-type. That is, in this embodiment, the upper portion of the electron supply layer 104 is n-type through the diffusion of Si and Ti caused by heat treatment, forming an electron supply auxiliary layer 401 as an n-type semiconductor layer.

[0104] In this way, the upper portion of the electron supply layer 104 is n-type to form an electron supply auxiliary layer 401, which serves as an n-type semiconductor layer, thereby generating a second two-dimensional electron gas layer 105B with a higher electron concentration than the first two-dimensional electron gas layer 105A. As a result, the second two-dimensional electron gas layer 105B is ohmically connected to the source electrode 301 and the drain electrode 302.

[0105] Furthermore, in order to facilitate the diffusion of Si from the first insulating layer 201 to the electron supply layer 104 through heat treatment, the insulating layer residue 201b1, which is part of the thin portion 201b of the first insulating layer 201, is preferably thin. In this case, as described above, the thickness of the thin portion 201b of the first insulating layer 201 is preferably 2 nm or less. This increases the Si content in the upper portion of the electron supply layer 104, allowing for further n-type shaping of the upper portion of the electron supply layer 104.

[0106] Next, as Figure 3G As shown, the first insulating layer 201, the portion of which is separated from the source electrode 301 and the drain electrode 302, is removed to form the gate electrode 303 (gate electrode formation process). In this embodiment, since a second insulating layer 202 is formed on the first insulating layer 201, the portion of the first insulating layer 201 separated from the source electrode 301 and the drain electrode 302 in both the first insulating layer 201 and the second insulating layer 202 is removed to form the gate electrode 303.

[0107] Specifically, after applying a photoresist onto the second insulating layer 202, a mask (photoresist mask) is formed outside the area where the gate electrode 303 is formed (the predetermined area for gate electrode formation) using photolithography. Next, the second insulating layer 202 and the first insulating layer 201 are selectively removed using dry etching, forming an opening 201a in the first insulating layer 201 and an opening 202a in the second insulating layer 202 to expose the electron supply layer 104. Then, the mask (photoresist mask) and the polymer generated by dry etching are removed. Afterward, the gate electrode 303 is formed in the openings 201a and 202a. Specifically, after forming a stacked film consisting of a 50nm thick TiN film and a 450nm thick Al film sequentially deposited by sputtering, the stacked film is patterned using photolithography and dry etching to form... Figure 3F The gate electrode 303 is of the specified shape shown. Then, the mask and the polymer produced by dry etching are removed.

[0108] Thus, after Figures 3A-3G A series of processes to complete Figure 1 The semiconductor device 1 shown has the following structure.

[0109] (Implementation Method 2) Next, use Figure 4 The semiconductor device 2 of Embodiment 2 will be described. Figure 4 This is a cross-sectional view showing the structure of the semiconductor device 2 according to Embodiment 2. Furthermore, the following description focuses on the differences from Embodiment 1, omitting or simplifying the description of commonalities.

[0110] The semiconductor device 2 of this embodiment differs from the semiconductor device 1 of the above-described Embodiment 1 in the structure of the source electrode 301A and the drain electrode 302A. Specifically, the source electrode 301A and the drain electrode 302A in this embodiment are a structure in which the source electrode 301 and the drain electrode 302 and the contact layer 212 are integrated by being composed of the same material in the semiconductor device 1 of the above-described Embodiment 1.

[0111] More specifically, the source electrode 301A in this embodiment is a structure in which the source electrode 301 and the source-side contact layer 212A are integrated by being composed of the same material in the semiconductor device 1 of the above-described Embodiment 1. Further, the drain electrode 302A of this embodiment is a structure in which the drain electrode 302 and the drain-side contact layer 212B are integrated by being composed of the same material in the semiconductor device 1 of the above-described Embodiment 1. That is, the semiconductor device 2 of this embodiment does not have a contact layer composed of a semiconductor material.

[0112] In this embodiment, the source electrode 301A and the drain electrode 302A are provided in a manner of being buried in the through-hole recess 211. In addition, the source electrode 301A and the drain electrode 302A are provided in a manner of covering the alloy layer 402 and a part of the second insulating layer 202. The source electrode 301A and the drain electrode 302A are composed of, for example, a multilayer electrode film composed of a laminated structure in which a Ti film having a layer thickness of 30 nm and an Al film having a layer thickness of 200 nm are sequentially laminated, but are not limited thereto. In addition, the source electrode 301A and the drain electrode 302A do not contain Au, but are not limited thereto. In addition, the material constituting the source electrode 301A and the drain electrode 302A can be composed of Ti, Ta, Al, Hf, Ru, and Cu.

[0113] The source electrode 301A and the drain electrode 302A thus composed are ohmically connected to the second two-dimensional electron gas layer 105B.

[0114] The semiconductor device 2 of this embodiment also achieves the same effects as the above-described Embodiment 1. Specifically, in this embodiment, the electron supply auxiliary layer 401 and the alloy layer 402 as the n-type semiconductor layer are also provided, and thus the electron concentration of the second two-dimensional electron gas layer 105B is larger than the electron concentration of the first two-dimensional electron gas layer 105A. Thereby, it is possible to alleviate the decrease in the electron concentration of the side surface abutment portion of the through-hole recess 211 in the electron supply layer 104, and thus it is possible to suppress the decrease in the maximum drain current.

[0115] Further, according to the semiconductor device 2 of the present embodiment, the source electrode 301A and the drain electrode 302A have a function of a contact layer, and a contact layer composed of a semiconductor material is not provided. Thus, the process of forming the contact layer can be reduced. In addition, according to the semiconductor device 2 of the present embodiment, the source electrode 301A and the drain electrode 302A do not contain Au, and thus the manufacturing cost can be reduced.

[0116] Next, using Figures 5A-5F The manufacturing method of the semiconductor device 2 of the present embodiment will be described. Figures 5A-5F is a cross-sectional view showing each process in the manufacturing method of the semiconductor device 2 of Embodiment 2. Figure 5A A process of forming the semiconductor layer stack 100 and the first insulating layer 201 and the second insulating layer 202 is shown. Figure 5B A process of forming the thin portion 201b in the first insulating layer 201 is shown. Figure 5C A process of forming the through-hole recess 211 is shown. Figure 5D A process of forming the source electrode 301A and the drain electrode 302A is shown. Figure 5E A process of performing heat treatment is shown. Figure 5F A process of forming the gate electrode 303 is shown.

[0117] First, as shown in Figure 5A , a semiconductor layer stack 100 including a buffer layer 102, an electron traveling layer 103, and an electron supply layer 104 is formed over a substrate 101 using MOCVD (semiconductor layer stack forming process). This process is the same as the process of Figure 3A in Embodiment 1 described above.

[0118] Next, as shown in Figure 5B , a thin portion 201b is formed in the first insulating layer 201 by thinning a portion of the first insulating layer 201 (thin portion forming process). This process is the same as the process of Figure 3B in Embodiment 1 described above.

[0119] Next, as shown in Figure 5C , a through-hole recess 211 is formed by removing an end portion of the thin portion 201b of the first insulating layer 201 and a portion of the semiconductor layer stack 100 (through-hole recess forming process). Specifically, a portion of the thin portion 201b of the first insulating layer 201 is left as an insulating layer remaining portion 201b1, and the through-hole recess 211 that reaches the electron traveling layer 103 by penetrating the thin portion 201b of the first insulating layer 201 and the electron supply layer 104 is formed. This process is the same as the process of Figure 3C in Embodiment 1 described above.

[0120] Next, as shown in Figure 5DAs shown, a source electrode 301A and a drain electrode 302A are embedded in the through recess 211 (source electrode / drain electrode formation process). Specifically, the source electrode 301A and the drain electrode 302A are formed across the insulating layer residue 201b1 of the first insulating layer 201 and the through recess 211.

[0121] In this embodiment, using the second insulating layer 202 and the first insulating layer 201 as masks, Ti films and Al films are sequentially deposited by sputtering to form a stacked film embedded in the through-recess 211. Then, a mask is formed in the region where the source electrode 301A and the drain electrode 302A are formed by photolithography. The region where the mask is formed spans the through-recess 211, the insulating layer residue 201b1 of the first insulating layer 201, and the second insulating layer 202 when viewed from above. Next, the Al and Ti films outside the region where the mask is formed are removed by dry etching, thereby forming the source electrode 301A and the drain electrode 302A across the insulating layer residue 201b1 of the first insulating layer 201 and the through-recess 211. Finally, the mask and polymer are removed.

[0122] Next, as Figure 5E As shown, heat treatment is performed to form an electron supply auxiliary layer 401 and an alloy layer 402 on the insulating layer residue 201b1 of the first insulating layer 201 and the electron supply layer 104 (heat treatment process). This process is the same as that in Embodiment 1 described above. Figure 3F The process is the same. That is, by performing heat treatment, the elements constituting the insulating layer residue 201b1 of the first insulating layer 201 and the electron supply layer 104 diffuse and alloy with the elements constituting the source electrode 301A and the drain electrode 302A due to heat, forming the electron supply auxiliary layer 401 and the alloy layer 402.

[0123] Next, as Figure 5F As shown, the first insulating layer 201, the portion of which is separated from the source electrode 301A and the drain electrode 302A is removed to form the gate electrode 303 (gate electrode formation process). In this embodiment, since the second insulating layer 202 is formed on the first insulating layer 201, the gate electrode 303 is formed by removing the portions of the first insulating layer 201 and the second insulating layer 202 that are separated from the source electrode 301A and the drain electrode 302A. This process is the same as in Embodiment 1 described above. Figure 3G The procedures are the same.

[0124] Thus, after Figures 5A-5F A series of processes to complete Figure 4 Semiconductor device 2 with the structure shown.

[0125] (Modified example) The semiconductor device of the present disclosure has been described above based on Embodiment 1 and Embodiment 2, but the present disclosure is not limited to Embodiment 1 and Embodiment 2 described above.

[0126] For example, in Embodiment 1 and Embodiment 2 described above, the electron traveling layer 103 and the electron supply layer 104 are composed of a Group III nitride semiconductor, but are not limited thereto. Specifically, the electron traveling layer 103 and the electron supply layer 104 can be composed of another semiconductor material such as a Group III arsenide semiconductor.

[0127] Further, a mode obtained by applying various modifications to the above-described embodiments, a mode obtained by arbitrarily combining the constituent elements and functions in the embodiments within a range not departing from the gist of the present disclosure, and the like are also included in the present disclosure. In addition, from among the plurality of claims recited in the present application at the time of filing, a combination of two or more claims that is technically not contradictory is also included in the present disclosure. For example, when dependent claims recited in the claims of the present application at the time of filing are set as multiple claims or multiple dependent claims in a manner of referring to all the upper claims within a range not technically contradictory, a combination of all the claims included in the multiple claims or the multiple dependent claims is also included in the present disclosure.

[0128] Industrial applicability The technology of the present disclosure can be used as a semiconductor device such as a transistor for a switch used in a communication device, an inverter, a power supply circuit, and the like that require high-speed operation. Among them, in particular, the technology of the present disclosure has applicability to a high-frequency power device that is greatly affected by heat generation due to an ohmic contact resistance.

[0129] Explanation of reference signs 1, 2 semiconductor device 100 semiconductor layer stack 101 substrate 102 buffer layer 103 electron traveling layer 104 electron supply layer 105 two-dimensional electron gas layer 105A first two-dimensional electron gas layer 105B second two-dimensional electron gas layer 201 first insulating layer 201a opening portion 201b thin portion 201b1 insulating layer remaining portion 202 second insulating layer 202a opening portion 211 through recess 212 contact layer 212A source side contact layer 212B drain side contact layer 301, 301A source electrode 302, 302A drain electrode 303 gate electrode 401 electron supply auxiliary layer 402 alloy layer

Claims

1. A semiconductor device, characterized in that, have: Electronic travel layer; An electron supply layer is disposed on the electron travel layer, and its band gap is larger than that of the electron travel layer; A gate electrode is disposed on the electron supply layer; The source-side contact layer and the drain-side contact layer are buried in the recess that runs through the electron supply layer at a position separated from the gate electrode. An n-type semiconductor layer, composed of an n-type semiconductor containing Si, is connected to the electron supply layer and to the source-side contact layer and / or the drain-side contact layer, but is not grounded to the gate electrode. An alloy layer, containing Si, is disposed on the n-type semiconductor layer and has a thickness of less than 2 nm; An insulating layer is disposed on the portion of the electron supply layer where the gate electrode is not disposed, and is in contact with the gate electrode but not in contact with the source-side contact layer and / or the drain-side contact layer; as well as The source electrode and / or drain electrode are disposed on the source-side contact layer and / or the drain-side contact layer and on the alloy layer.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the n-type semiconductor layer is less than 2 nm.

3. The semiconductor device according to claim 1 or 2, characterized in that, In cross-section, the width of the n-type semiconductor layer is less than 1 μm.

4. The semiconductor device according to claim 1 or 2, characterized in that, In the lower part of the n-type semiconductor layer, the band gap of the portion of the electron supply layer on the n-type semiconductor layer side is smaller than the band gap of the portion of the electron travel layer side in the electron supply layer.

5. The semiconductor device according to claim 1 or 2, characterized in that, The source electrode and the source-side contact layer are made of the same material and do not contain Au. The drain electrode and the drain-side contact layer are made of the same material and do not contain Au.

6. The semiconductor device according to claim 1 or 2, characterized in that, The halogen concentration of the insulating layer is 1×10⁻⁶. 18 atoms / cm 3 the following.

7. The semiconductor device according to claim 1 or 2, characterized in that, The thickness of the insulating layer is greater than the thickness of the alloy layer.

8. The semiconductor device according to claim 7, characterized in that, The thickness of the insulating layer is greater than 2nm and less than 30nm.

9. The semiconductor device according to claim 1 or 2, characterized in that, There is no uneven distribution of oxygen between the insulating layer and the electron supply layer.

10. The semiconductor device according to claim 1 or 2, characterized in that, The electron travel layer and the electron supply layer are made of group III nitride semiconductors.

11. A method for manufacturing a semiconductor device, characterized in that, It includes the following processes: The process of forming an electron supply layer with a larger bandgap than the electron travel layer on the electron travel layer; The process of forming a Si-containing insulating layer on the electron supply layer without exposing it to the atmosphere; The process of thinning a portion of the insulating layer to form a thin section in the insulating layer; A process in which a portion of the thin portion remains as an insulating layer residue, and a through recess is formed that penetrates the thin portion of the insulating layer and the electron supply layer to reach the electron travel layer; The process of embedding and forming a contact layer in the through recess; The process of forming a source electrode and / or a drain electrode across the insulating layer residue and the contact layer; The process of performing heat treatment to form an alloy layer and an electron supply auxiliary layer in the residual portion of the insulating layer and the electron supply layer; as well as The process of removing the portion of the insulating layer that is separated from the source electrode and / or the drain electrode to form a gate electrode.

12. A method for manufacturing a semiconductor device, characterized in that, It includes the following processes: The process of forming an electron supply layer with a larger bandgap than the electron travel layer on the electron travel layer; The process of forming a Si-containing insulating layer on the electron supply layer without exposing it to the atmosphere; The process of thinning a portion of the insulating layer to form a thin section in the insulating layer; A process in which a portion of the thin portion remains as an insulating layer residue, and a through recess is formed that penetrates the thin portion of the insulating layer and the electron supply layer to reach the electron travel layer; The process of forming a source electrode and / or a drain electrode across the insulating layer residue and the through-recess; The process of performing heat treatment to form an alloy layer and an electron supply auxiliary layer in the residual portion of the insulating layer and the electron supply layer; as well as The process of removing the portion of the insulating layer that is separated from the source electrode and / or the drain electrode to form a gate electrode.

13. The method for manufacturing a semiconductor device according to claim 11 or 12, characterized in that, The insulating layer is composed of SiN.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, There is no uneven distribution of oxygen between the insulating layer and the electron supply layer.

15. The method for manufacturing a semiconductor device according to claim 11 or 12, characterized in that, In the process of forming a thin portion on the insulating layer, the thickness of the thin portion is less than 2 nm.

16. The method of manufacturing a semiconductor device according to claim 11 or 12, characterized in that, The electron travel layer and the electron supply layer are made of group III nitride semiconductors.

Images