Printing head and printing device

Abstract

The invention discloses a printing head and a printing device, and the printing head comprises a substrate, and a data conversion module, a gate driving module and a light-emitting module which are located on the substrate, and the data conversion module generates a plurality of gray scale control signals according to a received first control signal and a plurality of input data signals; and the gate driving module generates a plurality of gate control signals according to the second control signal, and the light emitting module emits light according to the plurality of gray scale control signals and the plurality of gate control signals, so that the light emitting control of the printing head can be realized, a driving chip is omitted, and the cost of the printing head is saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of printing equipment, in particular to a print head and a printing device. BACKGROUND

[0002] In the printing technology of scanning and photo imaging by using light emitting diode (LED), the light emitting diode in the print head can convert the electrical signal output by the driving chip, which represents the data information to be printed, into an optical signal, so as to project the optical signal onto the photosensitive drum to form a latent image, then attract toner at the position corresponding to the latent image to realize image development, and then transfer the toner to the paper through transfer to complete printing. However, the application of the electrical signal output by the driving chip to represent the data signal to be printed has high cost, which is not conducive to saving the cost of the print head. SUMMARY

[0003] The embodiments of the present application provide a print head and a printing device, which can save the cost of the print head.

[0004] The embodiments of the present application provide a print head, which comprises a substrate, a data conversion module, a gate drive module and a light emitting module. The data conversion module is located on the substrate, and the data conversion module is configured to generate a plurality of gray scale control signals according to a received first control signal and a plurality of input data signals. The gate drive module is located on the substrate, and the gate drive module is configured to generate a plurality of gate control signals according to a second control signal. The light emitting module is located on the substrate, and the light emitting module is electrically connected with the data conversion module and the gate drive module, and the light emitting module is configured to emit light according to the plurality of gray scale control signals and the plurality of gate control signals.

[0005] The embodiments of the present application also provide a printing device, which comprises any of the above-mentioned print heads and a printing control device. The printing control device is electrically connected with the print head, and the printing control device is configured to output the first control signal, the second control signal and the plurality of input data signals to the print head.

[0006] The print head and the printing device provided by the present application set the print head to comprise a substrate and a data conversion module, a gate drive module and a light emitting module located on the substrate, so as to generate a plurality of gray scale control signals by the data conversion module according to a received first control signal and a plurality of input data signals, generate a plurality of gate control signals by the gate drive module according to a second control signal, so that the light emitting module can emit light according to the plurality of gray scale control signals and the plurality of gate control signals, thereby realizing the light emitting control of the print head, and then omitting to set the driving chip, thereby saving the cost of the print head. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from the structures shown in these drawings without creative labor.

[0008] Figure 1 Structure schematic diagram of a print head of a comparative example of the present application.

[0009] Figure 2 Structure schematic diagram of a print head of an embodiment of the present application.

[0010] Figures 3A-3D Principle block diagram of a print head provided by an embodiment of the present application.

[0011] Figure 4 Principle block diagram of a first conversion unit and a second conversion unit provided by an embodiment of the present application.

[0012] Figure 5 Circuit structure schematic diagram of a shift register and a latch provided by an embodiment of the present application.

[0013] Figure 6 Circuit structure diagram of a level conversion circuit of an embodiment of the present application.

[0014] Figure 7 Circuit structure diagram of a decoder of an embodiment of the present application.

[0015] Figure 8 Circuit structure diagram of a digital-to-analog conversion circuit of an embodiment of the present application.

[0016] Figure 9 Principle block diagram of a gate driving module of an embodiment of the present application.

[0017] Figure 10 Circuit structure diagram of a clock generation unit of an embodiment of the present application.

[0018] Figure 11 Timing diagram of a trigger signal, a second clock signal and a third clock signal of an embodiment of the present application.

[0019] Figure 12 Connection schematic diagram of a pixel driving circuit and a light emitting device of an embodiment of the present application.

[0020] Figure 13 Timing diagram of a pixel driving circuit of an embodiment of the present application.

[0021] Figure 14 Schematic diagram of a light emitting group of an embodiment of the present application.

[0022] Figure 15 Timing diagram corresponding to simultaneous light emission of light emitting devices located in multiple pixel rows for embodiments of the present application.

[0023] Figure 16 Block diagram of a printing device for embodiments of the present application.

[0024] Explanation of reference numerals.

[0025] 10, light emitting device; 20, driving chip; 30, substrate.

[0026] 40, light emitting module; 41, light emitting driving circuit; 401, coupling unit; 402, reset unit; 403, compensation unit; 404, switching unit; 42, light emitting group; 421, light emitting unit.

[0027] 50, data conversion module; 51, first conversion unit; 51A, first sub-conversion unit; 51B, second sub-conversion unit; 511, shift register unit; 512, latch unit; 5121, latch sub-unit; 513, level conversion unit; 52, second conversion unit; 53, decoding unit; 53A, first decoding unit; 53B, second decoding unit.

[0028] 60, gate driving module; 601, first gate driving sub-module; 602, second gate driving sub-module; 603, third gate driving sub-module; 61, clock generation unit; 62, gate driving unit.

[0029] 70, signal input module; 71, connecting electrode; 72, flexible circuit board; 73, wireless communication unit.

[0030] 81, NAND gate; 82, inverter; 821, first inverter; 822, second inverter; 823, third inverter; 83, AND gate; 84, NOT gate; 85, OR gate; 86, level shifter.

[0031] 91, print head; 92, print control module; 93, photosensitive drum; 94, developing module; 95, transfer module; 96, charging module.

[0032] CS1, first control signal; CS11, first clock signal; CS12, latch control signal; CS2, second control signal; CS21, second clock signal; CS22, trigger signal; CS23, start signal; CK, third clock signal.

[0033] S1, input data signal; S2, gray scale control signal; Scn, gate control signal; Scn1, first stage gate control signal; Scn2, second stage gate control signal; Scn3, third stage gate control signal; Scnp, pth stage gate control signal; ScnA, first gate control signal; ScnB, second gate control signal; ScnC, third gate control signal.

[0034] VGHH, first voltage terminal; VGLL, second voltage terminal; VGH, third voltage terminal; VGL, fourth voltage terminal; Vdd, first power terminal; Vss, second power terminal.

[0035] LIN, input terminal of level conversion circuit; LO, output terminal of level conversion circuit; YIN and YIN1-YIN3, input terminals of decoder; YO and YO0-YO7, output terminals of decoder; YO10-YO17, output terminals of first decoder; YO20-YO27, output terminals of second decoder; VO, output terminal of digital-to-analog conversion circuit.

[0036] PL, pixel row; PT, P-type transistor; NT, N-type transistor; Tdr, driving transistor; Ti1, first reset transistor; Ti2, second reset transistor; Tda, data transistor; Tc, compensation transistor; Ts, switching device; Ts1, first switching transistor; Ts2, second switching transistor; Tr, initialization transistor; C, storage capacitor. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0038] In addition, the description such as "first", "second" and the like in the embodiments of the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it, when the combination of technical solutions appears to be contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the scope of protection claimed by the present application.

[0039] As Figure 1A structure schematic diagram of a print head of a comparative example of the present application. In some embodiments, the light emitting device 10 in the print head emits light under the driving of the electric signal output by the driving chip 20, which represents the data information to be printed, to cooperate with the photosensitive drum, developing device, etc. to realize printing. However, the driving chip 20 is high in cost, which is not conducive to saving the cost of the print head. Therefore, the embodiments of the present application provide a print head, so that the driving chip 20 is no longer needed in the print head, thereby saving the cost of the print head.

[0040] As Figure 2 A structure schematic diagram of a print head of an embodiment of the present application, Figures 3A-3D A principle block diagram of the print head provided by the embodiments of the present application. The embodiments of the present application provide a print head, which comprises a substrate 30, a light emitting module 40 and a light emitting driving circuit 41.

[0041] The substrate 30 can comprise at least one of a rigid substrate and a flexible substrate. The rigid substrate can at least comprise a glass substrate. The flexible substrate can at least comprise a polyimide material.

[0042] The light emitting module 40 and the light emitting driving circuit 41 are located on the substrate 30, and the light emitting driving circuit 41 can generate a plurality of gate control signals Scn and a plurality of gray scale control signals S2 to control the light emitting module 40 to emit light.

[0043] Optionally, the light emitting driving circuit 41 can be arranged around the light emitting module 40, so that the light emitting driving circuit 41 can provide the required signals for the light emitting devices 10 located at various places in the light emitting module 40, thereby reducing the light emitting difference of the light emitting devices 10 at various places in the light emitting module 40.

[0044] Please continue to refer to Figures 3A-3D The light emitting driving circuit 41 can comprise a data conversion module 50 and a gate driving module 60.

[0045] The data conversion module 50 is located on the substrate 30, and the data conversion module 50 is configured to generate a plurality of gray scale control signals S2 according to the received first control signal CS1 and a plurality of input data signals S1.

[0046] The gate driving module 60 is located on the substrate 30, and the gate driving module 60 is configured to generate a plurality of gate control signals Scn according to the second control signal CS2.

[0047] The light emitting module 40 is located on the substrate 30, and the light emitting module 40 is electrically connected with the data conversion module 50 and the gate driving module 60, and the light emitting module 40 is configured to emit light according to the plurality of gray scale control signals S2 and the plurality of gate control signals Scn.

[0048] By locating the light-emitting module 40, the data conversion module 50 and the gate driving module 60 on the substrate 30, and by the data conversion module 50 generating the multiple gray-scale control signals S2 according to the first control signal CS1 and the multiple input data signals S1, and by the gate driving module 60 generating the multiple gate control signals Scn according to the second control signal CS2, the light-emitting module 40 emits light according to the multiple gray-scale control signals S2 and the multiple gate control signals Scn, so that the light-emitting control of the light-emitting module 40 is realized without the driving chip 20, and the driving chip 20 is omitted in the print head, which is beneficial to saving the cost of the print head.

[0049] It should be noted that the light-emitting module 40, the data conversion module 50 and the gate driving module 60 on the substrate 30 can mean that the light-emitting module 40, the data conversion module 50 and the gate driving module 60 are prepared on the substrate 30 by processes such as, but not limited to, yellow light process.

[0050] In some embodiments, the light-emitting module 40, the data conversion module 50 and the gate driving module 60 can share part of the process to realize synchronous preparation, thereby saving the preparation process and preparation cost.

[0051] It should be noted that the multiple input data signals S1 can be high-speed parallel data signals, and each high-speed parallel data signal can correspond to a serial data signal. The input data signal S1 can correspond to the content information to be printed.

[0052] In order to enable the first control signal CS1 and the multiple input data signals S1 to be transmitted to the data conversion module 50, the print head can further include a signal input module 70, as shown in Figure 2 and Figures 3A-3D The signal input module 70 is electrically connected with the data conversion module 50, and the signal input module 70 is configured to transmit the first control signal CS1 and the multiple input data signals S1, so as to transmit the first control signal CS1 and the multiple input data signals S1 to the data conversion module 50.

[0053] Optionally, in order to reduce the loss of the first control signal CS1 and the multiple input data signals S1 on the transmission path, and facilitate the signal transmission between the signal input module 70 and the data conversion module 50, the signal input module 70 can be located on the side of the data conversion module 50 away from the light-emitting module 40.

[0054] As shown in Figure 4 a principle block diagram of the first conversion unit and the second conversion unit provided by the embodiments of the present application. Please continue to refer to Figures 3A-3D and Figure 4The data conversion module 50 can include at least a first conversion unit 51 and a second conversion unit 52 to convert a plurality of input data signals S1 received by the data conversion module 50 into a plurality of gray scale control signals S2 for driving the light emitting module 40 to emit light.

[0055] The first conversion unit 51 can be electrically connected with the signal input module 70, and the at least a first conversion unit 51 is configured to generate a plurality of logic control signals according to the first control signal CS1 and the plurality of input data signals S1.

[0056] The second conversion unit 52 is electrically connected with the first conversion unit 51, and the second conversion unit 52 is configured to generate a plurality of gray scale control signals S2 according to the plurality of logic control signals.

[0057] It should be noted that the logic control signal can be a signal with high level and low level jump. That is, the voltage value corresponding to the high level of the logic control signal can be a first voltage value, and the voltage value corresponding to the low level of the logic control signal can be a second voltage value, and the first voltage value is greater than the second voltage value.

[0058] Optionally, in order to facilitate the first control signal CS1 and the plurality of input data signals S1 to be transmitted from the signal input module 70 to the first conversion unit 51, and to reduce the loss of the first control signal CS1 and the plurality of input data signals S1 on the transmission path, so that the gray scale control signal S2 generated by the data conversion module 50 has better quality, the first conversion unit 51 can be located between the second conversion unit 52 and the signal input module 70, as shown in Figure 3A and Figure 3D .

[0059] Optionally, in order to input the plurality of input data signals S1 to the data conversion module 50 as needed, the first control signal CS1 includes a first clock signal CS11 and a latch control signal CS12. In order to enable the first conversion unit 51 to generate a plurality of logic control signals according to the plurality of input data signals S1, the first conversion unit 51 can include a shift register unit 511, a latch unit 512, and a level conversion unit 513.

[0060] As will be described below with reference to Figures 3B-3C , the shift register unit 511 is electrically connected with the signal input module 70, and the shift register unit 511 is configured to output a plurality of parallel data signals according to the first clock signal CS11 and the plurality of input data signals S1.

[0061] The latch unit 512 is electrically connected with the shift register unit 511, and the latch unit 512 is configured to latch or output the plurality of parallel data signals according to the latch control signal CS12.

[0062] The level conversion unit 513 is electrically connected with the latch unit 512, and the level conversion unit 513 is configured to adjust the amplitude of the plurality of parallel data signals to generate a corresponding plurality of logic control signals.

[0063] The input data signal S1 can be a high-speed parallel data signal, and the plurality of parallel data signals output by the shift register unit 511 can be low-speed parallel data signals. The high-speed parallel data signal corresponds to a serial data signal. Therefore, the shift register can be configured to convert the high-speed serial data into low-speed parallel data.

[0064] Optionally, to generate the plurality of parallel data signals according to the plurality of input data signals S1, the shift register unit 511 can include a plurality of shift registers, wherein each shift register is configured to generate one parallel data signal according to the first clock signal CS11 and one input data signal S1.

[0065] In some embodiments, the shift register can be implemented by a plurality of D flip-flops, as shown in FIG. 8. Figure 5 As shown in FIG. 8, the shift register can include a plurality of D flip-flops. Figure 5 The shift register and the latch provided by the embodiments of the present application are shown in the circuit structure diagram. The shift register can include a plurality of D flip-flops, the plurality of D flip-flops receive the first clock signal CS11, the first D flip-flop receives the corresponding input data signal S1, and the D flip-flops electrically connected after the first D flip-flop all take the output signal of the previous D flip-flop as the input signal. At the first rising edge of the first clock signal CS11, the first D flip-flop can output the first input data of the first bit of the input data signal S1 to the shift register, and the output state of each D flip-flop is maintained in the initial state. At the second rising edge of the first clock signal CS11, the first D flip-flop outputs the second input data of the second bit of the input data signal S1 to the shift register, and the second D flip-flop outputs the first bit of data. In this way, the plurality of bits of the input data signal S1 are stored in the output end of the plurality of D flip-flops, so that the signals output by the output end of the plurality of D flip-flops are parallel data signals. It should be noted that any bit of the plurality of bits of the input data signal S1 can have two states of 0 or 1. The output end of the D flip-flop can correspond to the Q output end of the D flip-flop. The S end of the D flip-flop can be the set-1 end, the R end of the D flip-flop can be the set-0 end, and the Q' end of the D flip-flop can be another output end.

[0066] In some embodiments, the D flip-flop can be obtained by combining a plurality of NAND gates 81, as shown in FIG. 9. Figure 5The NAND gate 81 can be implemented by using at least one of P-type transistors and N-type transistors in some embodiments. Optionally, the P-type transistors or the N-type transistors can be thin film transistors, so as to use the existing manufacturing process of the display panel and reduce the manufacturing cost of the printhead.

[0067] It should be noted that, Figure 5 The implementation of the D flip-flop and the shift register shown is only illustrative and is not intended to limit the D flip-flop and the shift register to Figure 5 The design shown.

[0068] Please continue to refer to Figures 3B-3C and Figure 4 The latch unit 512 can include a plurality of latch sub-units 5121, each of which is electrically connected to a shift register, and each of which includes a plurality of latches. Optionally, the plurality of latches can include latch 1, latch 2, …, and latch N. Wherein, N>2, N is a positive integer.

[0069] The plurality of latches of the same latch sub-unit 5121 are configured to receive a parallel data signal output by the corresponding shift register, and latch or output the received parallel data signal according to the latch control signal CS12.

[0070] In some embodiments, the latch can be obtained by combining a plurality of D flip-flops, as Figure 5 The plurality of D flip-flops in the latch are electrically connected to the output ends of the plurality of D flip-flops in the shift register, for receiving the parallel data signal output by the shift register. The plurality of D flip-flops in the latch latch or output the received parallel data signal according to the rising edge of the latch control signal CS12.

[0071] It should be noted that, Figure 5 The implementation of the latch shown is only illustrative and is not intended to limit the latch to Figure 5 The design shown.

[0072] Please continue to refer to Figures 3B-3C and Figure 4 In order to obtain a logic control signal according to the parallel data signal, the plurality of level conversion units 513 can include a plurality of level conversion circuits, each of which is electrically connected to a latch of the plurality of latch sub-units 5121, and each of which is configured to adjust the amplitude of the parallel data signal output by the plurality of latches to obtain a logic control signal.

[0073] Optionally, the level conversion circuit can include a combination of a plurality of P-type transistors and N-type transistors. As Figure 6Fig. 1 is a circuit structure diagram of a level conversion circuit according to an embodiment of the present application. In the figure, PT represents a P-type transistor, NT represents an N-type transistor, VGHH represents a first voltage terminal, VGLL represents a second voltage terminal, VGH represents a third voltage terminal, and VGL represents a fourth voltage terminal. The first voltage terminal VGHH is configured to provide a voltage signal having a first voltage value, and the second voltage terminal VGLL is configured to provide a voltage signal having a second voltage value. The voltage value of the voltage signal provided by the first voltage terminal VGHH is greater than the voltage value of the voltage signal provided by the third voltage terminal VGH, and the voltage value of the voltage signal provided by the second voltage terminal VGLL is less than the voltage value of the voltage signal provided by the fourth voltage terminal VGL.

[0074] When the signal received by the input terminal LIN of the level conversion circuit is at a high level, the signal output by the level conversion circuit from the output terminal LO has a first voltage value, which is greater than the voltage value of the input signal received by the level conversion circuit. When the signal received by the level conversion circuit is at a low level, the signal output by the level conversion circuit has a second voltage value, which is less than the voltage value of the input signal received by the level conversion circuit. The input signal received by the level conversion circuit and the output signal output by the level conversion circuit can have the same frequency and the same phase.

[0075] Please continue to refer to Figures 3A-3D and Figure 4 The second conversion unit 52 is configured to generate the gray scale control signal S2 according to the logic control signal. The second conversion unit 52 includes a plurality of digital-to-analog conversion circuits. Optionally, the plurality of digital-to-analog conversion circuits can include a digital-to-analog conversion circuit 1, a digital-to-analog conversion circuit 2, and a digital-to-analog conversion circuit N.

[0076] Each digital-to-analog conversion circuit is electrically connected to at least one level conversion circuit. Each digital-to-analog conversion circuit is configured to generate one gray scale control signal S2 according to at least one logic control signal. Thus, the plurality of digital-to-analog conversion circuits can generate a plurality of gray scale control signals S2. As shown in Figure 4 The digital-to-analog conversion circuit 1, the digital-to-analog conversion circuit 2, and the digital-to-analog conversion circuit N generate a plurality of gray scale control signals S2, which include a first gray scale control signal S21, a second gray scale control signal S21, and an Nth gray scale control signal S2N.

[0077] Optionally, the digital-to-analog conversion circuit can be implemented by using a resistor string design. The digital-to-analog conversion circuit can control the number of resistors connected between the first power terminal and the second power terminal according to the logic control signal, so as to obtain the gray scale control signal S2 for controlling the light emitting module 40 to implement different display gray scales.

[0078] Optionally, the first clock signal CS11 and the corresponding input data signal S1 are received by the shift register unit 511 to generate a plurality of parallel data signals, the plurality of parallel data signals are latched or output by the latch unit 512, the amplitude of the plurality of parallel data signals is adjusted by the level conversion unit 513 to achieve a plurality of logic control signals, and the logic control signals are received by the digital-to-analog conversion circuit to generate the gray scale control signal S2. Thus, in order to make the signals pass through a shorter transmission path during transmission, reduce the transmission loss of the signals, and reduce the probability of overlap between the signal lines transmitting the signals and the mutual influence between the signals, the shift register unit 511, the latch unit 512, the level conversion unit 513, and the second conversion unit 52 are arranged in sequence from the signal input module 70 to the light-emitting module 40, as shown in Figures 3B-3C Thus, the first clock signal CS11 and the plurality of input data signals S1 output by the signal input module 70 can be received by the shift register unit 511 through a shorter transmission path, the parallel data signals output by the shift register unit 511 can also be received by the latch unit 512 through a shorter transmission path, the signals output by the latch unit 512 can also be received by the level conversion unit 513 through a shorter transmission path, and the logic control signals output by the level conversion unit 513 can also be received by the second conversion unit 52 through a shorter transmission path. Moreover, the probability of overlap between the plurality of signal lines transmitting the first clock signal CS11, the input data signal S1, the parallel data signal, and the logic control signal can be reduced, and the mutual influence between the signals can be reduced.

[0079] The higher the luminous intensity requirement of the light-emitting module 40 is, the more the first conversion unit 51 and the second conversion unit 52 need to be applied. However, with the increase in the number of the first conversion unit 51 and the second conversion unit 52, the layout space occupied by the first conversion unit 51 and the second conversion unit 52 on the substrate 30 becomes larger, thereby causing the size of the print head to also become larger, which is not conducive to the control of the size of the print head. Thus, in order to meet the luminous intensity requirement while reducing the size of the print head, the data conversion module 50 can further include a decoding unit 53, as shown in Figure 3C and Figure 4

[0080] The decoding unit 53 can be electrically connected between the level conversion unit 513 and the second conversion unit 52, and the decoding unit 53 is configured to receive a plurality of logic control signals to generate a plurality of binary signals. The second conversion unit 52 is configured to generate a plurality of gray scale control signals S2 according to the plurality of binary signals.

[0081] ​By setting the decoding unit 53, the m-bit logic control signal can be converted into an n-bit binary signal, and m < n, so that the number of binary signals generated based on the logic control signal is greater than the number of logic control signals, and then the gray scale control signal S2 generated based on the binary signal can be used to make the light intensity of the light emitting module 40 show more levels. Wherein, m > 1.

[0082] Optionally, when the color depth of the light emitting module 40 is greater than or equal to 4 bits, the data conversion module 50 can include the decoding unit 53. When the color depth of the light emitting module 40 is less than 4 bits, the number of devices corresponding to the application when the data conversion module 50 includes the decoding unit 53 and the number of devices corresponding to the application when the data conversion module 50 does not include the decoding unit 53 are not much different. Therefore, when the color depth of the light emitting module 40 is less than 4 bits, the data conversion module 50 does not include the decoding unit 53, which can reduce the cost of the print head. Wherein, the device can be an element corresponding to the implementation of the shift register unit 511, the latch unit 512, the level conversion unit 513 and the second conversion unit 52. The device includes at least one of a transistor, a resistor, a capacitor and an inductor.

[0083] In some embodiments, the decoding unit 53 includes a decoder. The decoder can include a combination of an inverter 82 and a NAND gate 81. As shown in FIG. 8, the decoder includes the inverter 82 and the NAND gate 81. The input of the inverter 82 is connected to the logic control signal, and the output of the inverter 82 is connected to the input of the NAND gate 81. The output of the NAND gate 81 is connected to the binary signal. Figure 7 For the circuit structure diagram of the decoder of the embodiment of the present application, the decoder includes a plurality of inverters 82 and a plurality of NAND gates 81. The plurality of inverters 82 can include a first inverter 821 connected to the input YIN of the decoder, a second inverter 822 connected to the first inverter 821, and a third inverter 823 connected to the plurality of outputs YO of the decoder. The input of the plurality of NAND gates 81 is connected to the corresponding first inverter 821 and / or second inverter 822, and the output of the plurality of NAND gates 81 is connected to the input of the plurality of third inverters 823.

[0084] As shown in FIG. 9, the decoder includes the plurality of inverters 82 and the plurality of NAND gates 81. The input of the first inverter 821 is connected to the logic control signal, and the output of the first inverter 821 is connected to the input of the second inverter 822. The output of the second inverter 822 is connected to the input of the third inverter 823. The input of the NAND gate 81 is connected to the corresponding first inverter 821 and / or second inverter 822, and the output of the NAND gate 81 is connected to the input of the third inverter 823. Figure 7The decoder is shown as an example of a decoder with a 3-bit level. The decoder includes three input terminals YIN and eight output terminals YO. The three input terminals YIN are a first input terminal YIN1 to a third input terminal YIN3, and the eight output terminals YO are a first output terminal YO0 to an eighth output terminal YO7. The decoder includes three first inverters 821, three second inverters 822, eight NAND gates 81, and eight third inverters 823. The three first inverters 821 are connected to the three input terminals YIN of the decoder in a one-to-one manner, and the three second inverters 822 are connected to the three first inverters 821 in a one-to-one manner. The output terminal of the first inverter 821 connected to the first input terminal YIN1 of the decoder is electrically connected to the input terminal of the NAND gate located at an odd position in the eight NAND gates 81 arranged in sequence, and the output terminal of the second inverter 822 connected to the first input terminal YIN1 of the decoder is electrically connected to the input terminal of the NAND gate located at an even position in the eight NAND gates 81 arranged in sequence. The output terminal of the first inverter 821 connected to the second input terminal YIN2 of the decoder is electrically connected to the input terminal of the NAND gate located at the 1st position, the 2nd position, the 5th position, and the 6th position in the eight NAND gates 81 arranged in sequence, and the output terminal of the second inverter 822 connected to the second input terminal YIN2 of the decoder is electrically connected to the input terminal of the NAND gate located at the 3rd position, the 4th position, the 7th position, and the 8th position in the eight NAND gates 81 arranged in sequence. The output terminal of the first inverter 821 connected to the third input terminal YIN3 of the decoder is electrically connected to the input terminal of the NAND gate located at the first four positions in the eight NAND gates 81 arranged in sequence, and the output terminal of the second inverter 822 connected to the third input terminal YIN3 of the decoder is electrically connected to the input terminal of the NAND gate located at the last four positions in the eight NAND gates arranged in sequence. The output terminals of the eight NAND gates 81 arranged in sequence are connected to the input terminals of the eight third inverters 823 in a one-to-one manner, and the output terminals of the eight third inverters 823 are connected to the eight output terminals YO of the decoder in a one-to-one manner.

[0085] The signal received by the input terminal YIN of the decoder can be a binary number. Corresponding Figure 7 The decoder shown in the figure, the binary number received by the three input terminals YIN of the decoder constitutes a three-bit binary number.

[0086] For example, the three inputs of the decoder are all 0, and the three-bit binary number formed by the three inputs is 000. After the three-bit binary number is inputted into the first inverter 821 and the second inverter 822, the first NAND gate in the eight NAND gates receives the three-bit binary number 111, and the output of the first NAND gate is 0. After the output of the first NAND gate is inputted into the third inverter 823, the first output of the decoder is 1. The second NAND gate to the eighth NAND gate in the eight NAND gates receive the three-bit binary number, and the outputs of the second NAND gate to the eighth NAND gate are all 1. After the outputs of the second NAND gate to the eighth NAND gate are inputted into the third inverters 823, the second output to the eighth output of the decoder are all 0. Similarly, when the three-bit binary number is 001, the second output of the decoder is 1. When the three-bit binary number is 010, the third output of the decoder is 1. When the three-bit binary number is 011, the fourth output of the decoder is 1. When the three-bit binary number is 100, the fifth output of the decoder is 1. When the three-bit binary number is 101, the sixth output of the decoder is 1. When the three-bit binary number is 110, the seventh output of the decoder is 1. When the three-bit binary number is 111, the eighth output of the decoder is 1.

[0087] It should be noted that the inverter 82 can be a NAND gate. The inverter 82 and the NAND gate 81 can be composed of at least one of a P-type transistor and an N-type transistor.

[0088] In some embodiments, to make the multiple gray scale control signals S2 outputted by the second conversion unit 52 can make the light emitting module 40 show more brightness levels, the data conversion module 50 includes two first conversion units 51 and two decoding units 53, as shown in Figure 4

[0089] ​The two first conversion units 51 can include a first sub-conversion unit 51A and a second sub-conversion unit 51B. The two decoding units 53 can include a first decoding unit 53A and a second decoding unit 53B. The first decoding unit 53A is located between the first sub-conversion unit 51A and the second conversion unit 52, and the second decoding unit 53B is located between the second sub-conversion unit 51B and the second conversion unit 52. The first decoding unit 53A and the second decoding unit 53B each include a plurality of decoders electrically connected between the plurality of level conversion circuits and a digital-to-analog conversion circuit, and configured to receive a plurality of logic control signals to generate a binary signal. The same digital-to-analog conversion circuit is electrically connected to a decoder of the first decoding unit 53A and a decoder of the second decoding unit 53B. Each digital-to-analog conversion circuit is configured to generate a gray scale control signal S2 according to a binary signal output by a decoder of the first decoding unit 53A and a binary signal output by a decoder of the second decoding unit 53B.

[0090] Optionally, when the data conversion module 50 includes two first conversion units 51 and two decoding units 53, the digital-to-analog converter can use a combination of a plurality of resistors and a plurality of switching devices. As shown in FIG. 4, the data conversion module 50 includes two first conversion units 51 and two decoding units 53. The two first conversion units 51 are electrically connected between the first power supply end Vdd and the second power supply end Vss. The two decoding units 53 are electrically connected between the two first conversion units 51 and the second conversion unit 52. Figure 8 The circuit structure diagram of the digital-to-analog conversion circuit of the embodiment of the present application is shown in FIG. 5, taking the design of the color depth of the light emitting module 40 as an example. The digital-to-analog conversion circuit includes a plurality of switching devices Ts and a plurality of resistors R connected between the first power supply end Vdd and the second power supply end Vss. Two 3-bit level decoders are electrically connected to the digital-to-analog conversion circuit to provide binary signals to the digital-to-analog conversion circuit to control the number of resistors R connected between the first power supply end Vdd and the output end VO of the digital-to-analog conversion circuit, thereby controlling the amplitude of the gray scale control signal S2 output by the digital-to-analog converter.

[0091] For example, when the signal output by the first output end Y010 of a decoder (referred to as a first decoder) in the first decoding unit 53A is 0, and the signals output by the second output end Y011 to the eighth output end Y017 are all 1; the signal output by the first output end Y020 of a decoder (referred to as a second decoder) in the second decoding unit 53B is 0, and the signals output by the second output end Y021 to the eighth output end Y027 are all 1, the switching device Ts controlled by the signal output by the first output end Y010 of the first decoder is turned on, and the switching device controlled by the signal output by the first output end Y020 of the second decoder is turned on. At this time, only one resistor R is connected between the first power supply end Vdd and the output end VO of the digital-to-analog conversion circuit. Similarly, the number of resistors connected between the first power supply end Vdd and the output end VO of the digital-to-analog conversion circuit corresponding to other values of the signals output by the first decoder and the second decoder can also be obtained.

[0092] It should be noted that the switching device Ts can be a P-type transistor or an N-type transistor.

[0093] To facilitate understanding of the data conversion module 50 of this application, Figure 4 The data conversion module 50 shown is illustrated by way of example. Assuming the signal input module 70 inputs A 10MHz parallel input data values ​​to the shift register unit 511, these A 10MHz parallel input data values ​​are input to A shift registers respectively. Each shift register receives one 10MHz parallel input data value. Under the control of the first clock signal CS11, the A shift registers convert the A 10MHz parallel input data values ​​into B 1MHz parallel data values, which are then stored in the latch unit 512. Under the action of the latch control signal CS12, multiple latches in the latch unit 512 output parallel data to the level conversion unit 513. The same level conversion circuit receives data output from one latch in the multiple latch subunits 5121, and uses the level conversion circuit to convert the parallel data to obtain a logic control signal with high and low level transitions. The same decoder simultaneously receives the logic control signals output from multiple level conversion circuits to convert the received logic control signals into multi-bit binary signals. The digital-to-analog converter receives two multi-bit binary signals to generate a grayscale control signal S2. Among them, the first clock signals CS11 corresponding to the A shift registers can have a phase difference. A < B, B > 1.

[0094] Please continue reading. Figures 3A-3D To simplify the signal transmission design on the printhead, the signal input module 70 can be used to provide the required second control signal CS2 to the gate drive module 60. That is, the signal input module 70 is electrically connected to the gate drive module 60, and the signal input module 70 is configured to transmit the second control signal CS2 to the gate drive module 60.

[0095] It should be noted that the signal input module 70 can be connected to the data conversion module 50 and the gate drive module 60 via wires, connecting electrodes, etc.

[0096] Optionally, the gate driving module 60 and the signal input module 70 can be located on different sides of the light-emitting module 40 to optimize the layout of the data conversion module 50 and the gate driving module 60 on the substrate 30 without affecting the signal input module 70 providing the required signal to the data conversion module 50.

[0097] like Figure 9 This is a schematic block diagram of the gate driving module according to an embodiment of this application. Figure 10 This is a circuit diagram of the clock generation unit according to an embodiment of this application. Figure 11 This is a timing diagram of the trigger signal, the second clock signal, and the third clock signal in an embodiment of this application.

[0098] The second control signal CS2 may include a second clock signal CS21, a trigger signal CS22, and a start signal CS23. The gate driving module 60 may include a clock generation unit 61 and a gate driving unit 62. The clock generation unit 61 is configured to generate a plurality of third clock signals CK based on the second clock signal CS21 and the trigger signal CS22. Optionally, the plurality of third clock signals CK may include a first third clock signal CK1, a second third clock signal CK2, ..., an Nth third clock signal CKN.

[0099] Gate driving unit 62 is electrically connected to clock generation unit 61. Gate driving unit 62 is configured to generate multiple gate control signals Scn based on start signal CS23 and multiple third clock signals CK. Optionally, the multiple gate control signals Scn may include a first-level gate control signal Scn1, a second-level gate control signal Scn2, a third-level gate control signal Scn3, ..., a p-th-level gate control signal Scnp. Where p ≠ N. In some embodiments, p > N.

[0100] Optionally, the clock generation unit 61 may include a combination of AND gate 83, NOT gate 84, OR gate 85, NAND gate 81 and level shifter 86, such as Figures 10-11 As shown. The second clock signal CS21 includes a first sub-clock signal HS and a second sub-clock signal DE. The first sub-clock signal HS and the second sub-clock signal DE are transmitted to the same AND gate via the first and second input terminals of the clock generation unit 61. The trigger signal CS22 is transmitted to the NOT gate 84 via the third input terminal of the clock generation unit 61. The first sub-clock signal HS, the second sub-clock signal DE, and the trigger signal CS22 are combined by the AND gate, OR gate, NAND gate, and level converter in the clock generation unit 61 to output multiple third clock signals CK. The frequency of the second clock signal CS21 can be greater than the frequency of the third clock signal CK, and the number of second clock signals CS21 can be less than the number of third clock signals CK.

[0101] It should be noted that the level converter 86 in the clock generation unit 61 can use the same or different circuit topology as the level conversion circuit in the level conversion unit 513.

[0102] In some embodiments, the clock generation unit 61 may be a timing controller.

[0103] Optionally, the gate driving unit 62 can include a plurality of cascaded gate driving circuits, each of which can output a gate control signal Scn. In some embodiments, among the plurality of cascaded gate driving circuits, the first gate driving circuit outputs a gate control signal according to the start signal CS23 and the corresponding third clock signal CK, and each gate driving circuit cascaded after the first gate driving circuit can output the gate control signal of the current stage according to the gate control signal output by the previous stage gate driving circuit and the corresponding third clock signal CK. For example, the Zth gate driving circuit outputs the Zth gate control signal Scn(Z) according to the (Z-1)th gate control signal Scn(Z-1) output by the (Z-1)th gate driving circuit and the corresponding third clock signal CK. Wherein, 1<Z≤p.

[0104] It should be noted that the gate driving circuit can include a combination of transistors, capacitors and other elements. The design of the gate driving circuit can refer to the gate driving circuit in the display panel for generating the scan signal, which will not be described here.

[0105] To realize the light emission of the light emitting module 40, the light emitting module 40 can include a light emitting unit and a pixel driving unit. The light emitting unit can include a plurality of light emitting devices 10. The light emitting device 10 can be at least one of an organic light emitting diode, a sub-millimeter light emitting diode, and a micro light emitting diode. The pixel driving unit can include a plurality of pixel driving circuits.

[0106] As Figure 12 The connection diagram of the pixel driving circuit and the light emitting device of the embodiment of the present application.

[0107] Each pixel driving circuit is electrically connected to at least one light emitting device 10, and each pixel driving circuit is configured to drive the corresponding light emitting device 10 to emit light according to the corresponding gate control signal Scn and the corresponding gray scale control signal S2.

[0108] Optionally, the plurality of gate control signals Scn includes a first gate control signal ScnA, a second gate control signal ScnB, and a third gate control signal ScnC. The pixel driving circuit includes a driving transistor Tdr, a coupling unit 401, a reset unit 402, a compensation unit 403, and a switching unit 404.

[0109] The driving transistor Tdr is configured to generate a driving current to drive the corresponding light emitting device 10 to emit light according to the corresponding gray scale control signal S2.

[0110] Optionally, the control end of the driving transistor Tdr is electrically connected to the first node No1, the first source-drain end of the driving transistor Tdr is electrically connected to the first power supply end Vdd, and the second source-drain end of the driving transistor Tdr is electrically connected to the anode of the corresponding light emitting device 10.

[0111] The coupling unit 401 is electrically connected to the control end of the driving transistor Tdr through the first node No1 and the second node No2, and is configured to couple the gray scale control signal S2 to the first node No1.

[0112] Optionally, the coupling unit 401 includes a storage capacitor C, which is electrically connected between the first node No1 and the second node No2.

[0113] The reset unit 402 is electrically connected to the coupling unit 401, and is configured to reset the potentials of the first node No1 and the second node No2 according to the first gate control signal ScnA.

[0114] Optionally, the reset unit 402 includes a first reset transistor Ti1 and a second reset transistor Ti2, the control ends of the first reset transistor Ti1 and the second reset transistor Ti2 are configured to receive the first gate control signal ScnA, the first source-drain end of the first reset transistor Ti1 is electrically connected to the first power supply end Vdd, and the second source-drain end of the first reset transistor Ti1 and the second node No2 are electrically connected. The first source-drain end of the second reset transistor Ti2 is configured to receive the reset signal VI, and the second source-drain end of the second reset transistor Ti2 and the first node No1 are electrically connected.

[0115] The compensation unit 403 is electrically connected to the first node No1 and the driving transistor Tdr, and is configured to transmit the corresponding gray scale control signal S2 to the second node No2 according to the second gate control signal ScnB, and store the threshold voltage information of the driving transistor Tdr to the first node No1 according to the second gate control signal ScnB.

[0116] Optionally, the compensation unit 403 includes a data transistor Tda and a compensation transistor Tc. The control ends of the data transistor Tda and the compensation transistor Tc are configured to receive the second gate control signal ScnB, the first source-drain end of the data transistor Tda is configured to receive the gray scale control signal S2, and the second source-drain end of the data transistor Tda and the second node No2 are electrically connected. The first source-drain end of the compensation transistor Tc is electrically connected to the second source-drain end of the driving transistor Tdr, and the second source-drain end of the compensation transistor Tc and the first node No1 are electrically connected.

[0117] The switch unit 404 is electrically connected with the second node No2, the driving transistor Tdr and the corresponding light emitting device 10. The switch unit 404 is configured to couple the gray scale control signal S2 to the first node No1 through the coupling unit 401 according to the third gate control signal ScnC, and to connect the current flow path between the driving transistor Tdr and the light emitting device 10 according to the third gate control signal ScnC.

[0118] Optionally, the switch unit 404 includes a first switch transistor Ts1 and a second switch transistor Ts2. The control end of the first switch transistor Ts1 and the control end of the second switch transistor Ts2 are configured to receive the third gate control signal ScnC. The first source-drain end of the first switch transistor Ts1 is configured to receive the reset signal VI. The second source-drain end of the first switch transistor Ts1 and the second node No2 are electrically connected. The first source-drain end of the second switch transistor Ts2 and the second source-drain end of the driving transistor Tdr are electrically connected. The second source-drain end of the second switch transistor Ts2 and the anode of the corresponding light emitting device 10 are electrically connected.

[0119] Optionally, the pixel driving circuit further includes an initialization transistor Tr. The control end of the initialization transistor Tr is configured to receive the second gate control signal ScnB. The first source-drain end of the initialization transistor Tr is electrically connected with the second power supply end Vss. The second source-drain end of the initialization transistor Tr is electrically connected with the anode of the light emitting device 10. The initialization transistor Tr is configured to control the electrical connection between the second power supply end Vss and the anode of the light emitting device 10 according to the second gate control signal ScnB.

[0120] Figure 13 The timing diagram of the pixel driving circuit of the embodiment of the present application is described taking the transistors included in the pixel driving circuit as P-type transistors as an example, and the working principle of the pixel driving circuit is described.

[0121] In the first time period t1, the first gate control signal ScnA has a low level, the first reset transistor Ti1 and the second reset transistor Ti2 are turned on, the first power supply end Vdd and the second node No2 are electrically connected, and the voltage signal provided by the first power supply end Vdd is transmitted to the second node No2 to reset the second node No2. The reset signal VI is transmitted to the first node No1 to reset the first node No1.

[0122] The second period t2: the second gate control signal ScnB has a low level, the data transistor Tda, the compensation transistor Tc and the initialization transistor Tr are turned on, the gray scale control signal S2 is transmitted to the second node No2, and the voltage signal provided by the first power supply end Vdd is transmitted to the first node No1 through the driving transistor Tdr and the compensation transistor Tc, so as to store the threshold voltage information of the driving transistor Tdr to the first node No1. The voltage signal supplied by the second power supply end Vss is transmitted to the anode of the light emitting device 10, so as to reset the anode of the light emitting device 10.

[0123] The third period t3: when the third gate control signal ScnC has a low level, the first switch transistor Ts1 and the second switch transistor Ts2 are turned on, the reset signal VI is transmitted to the corresponding second node No2, and the potential of the second node No2 is changed from the voltage value corresponding to the gray scale control signal S2 to the voltage value corresponding to the reset signal VI. The variation amount generated by the potential variation of the second node No2 is equal to the difference between the voltage value corresponding to the reset signal VI and the voltage value corresponding to the gray scale control signal S2. The variation amount is coupled to the first node No1 through the storage capacitor C, so that the potential of the first node No1 is changed from the sum of the voltage signal corresponding to the first power supply end Vdd and the threshold voltage of the driving transistor Tdr to the sum of the voltage signal corresponding to the first power supply end Vdd, the threshold voltage of the driving transistor Tdr and the variation amount, so that the generated driving current of the driving transistor Tdr is related to the voltage value corresponding to the gray scale control signal S2 and the voltage value corresponding to the reset signal VI, and is independent of the threshold voltage of the driving transistor Tdr, thereby reducing the influence of the threshold voltage of the driving transistor Tdr on the driving current. The driving current flows through the light emitting device 10, so as to make the light emitting device 10 emit light.

[0124] Please continue to refer to Figures 3A-3D In order to provide the required gate control signal Scn to the light emitting module 40, the gate drive module 60 can include a first gate drive submodule 601, a second gate drive submodule 602 and a third gate drive submodule 603. Among them, the first gate drive submodule 601 is configured to generate a plurality of first gate control signals ScnA according to the second control signal CS2, so as to output to the reset unit 402 of the plurality of pixel drive circuits. The second gate drive submodule 602 is configured to generate a plurality of second gate control signals ScnB according to the second control signal CS2, so as to output to the compensation unit 403 of the plurality of pixel drive circuits. The third gate drive submodule 603 is configured to generate a plurality of third gate control signals ScnC according to the second control signal CS2, so as to output to the switch unit 404 of the plurality of pixel drive circuits.

[0125] Optionally, the first gate control signal ScnA outputted by the first gate driving sub-module 601 can be the same as the second gate control signal ScnB outputted by the second gate driving sub-module 602, and the first gate driving sub-module 601 and the second gate driving sub-module 602 can be located at opposite sides of the light emitting module 40 to form double-side driving for the plurality of pixel driving circuits.

[0126] In some embodiments, the reset unit 402 and the compensation unit 403 can share the gate control signal Scn outputted by the gate driving circuit of different stages in the same gate driving module 60, so as to reduce the layout space occupied by the gate driving module 60.

[0127] In some embodiments, the reset unit 402 and the compensation unit 403 in the same pixel driving circuit are controlled by the gate control signal Scn outputted by the gate driving circuit of different stages in the first gate driving sub-module 601. For example, in the same pixel driving circuit, the reset unit 402 is controlled by the (t-1)th gate control signal Scn(t-1) outputted by the gate driving circuit of the (t-1)th stage in the first gate driving sub-module 601, and the compensation unit 403 is controlled by the tth gate control signal Scn(t) outputted by the gate driving circuit of the tth stage in the first gate driving sub-module 601. Wherein, t is greater than 1, and t is less than or equal to the total number of the gate driving circuits included in the first gate driving sub-module 601.

[0128] Please continue to refer to Figures 3A-3D , the first gate driving sub-module 601, the second gate driving sub-module 602 and the third gate driving sub-module 603 and the data conversion module 50 can be arranged around the light emitting module 40, and the data conversion module 50 and the third gate driving sub-module 603 are located at opposite sides of the light emitting module 40, and the first gate driving sub-module 601 and the second gate driving sub-module 602 are located at opposite sides of the light emitting module 40, so as to transmit the first gate control signal ScnA, the second gate control signal ScnB, the third gate control signal ScnC and the gray scale control signal S2 to the light emitting module 40, thereby realizing the light emitting control of the light emitting module 40.

[0129] Optionally, the light emitting module 40 can include at least one light emitting group. As Figure 14 The schematic diagram of the light emitting group of the embodiment of the present application, at least one light emitting group 42 includes a plurality of light emitting units 421, each light emitting unit 421 includes a plurality of light emitting devices 10 located in the same pixel row PL. Wherein, the pixel driving circuit electrically connected with the plurality of light emitting devices 10 of each light emitting group 42 is configured to drive the plurality of light emitting devices 10 to emit light according to the corresponding gray scale control signal S2 and the same third gate control signal ScnC, so that the plurality of light emitting devices 10 of the plurality of pixel rows PL are controlled by the same third gate control signal ScnC, which is beneficial to reduce the power consumption of the print head.

[0130] As Figure 15 A timing diagram corresponding to the simultaneous light emission of the light emitting devices located in the plurality of pixel rows in an embodiment of the present application. Take an example in which the light emitting group 42 includes a plurality of light emitting devices 10 located in 8 pixel rows PL, and the pixel driving circuit includes P-type transistors.

[0131] The first gate control signal ScnA and the second gate control signal ScnB corresponding to the pixel driving circuit electrically connected to the plurality of light emitting devices 10 located in the first pixel row have effective pulses in sequence, so that the pixel driving circuit electrically connected to the plurality of light emitting devices 10 located in the first pixel row experiences the corresponding first period (i.e. the first first period t1 in Figure 15 ) and the second period (i.e. the first second period t2 in Figure 15 ) in sequence. Subsequently, the first gate control signal Scn and the second gate control signal Scn corresponding to the pixel driving circuit electrically connected to the plurality of light emitting devices 10 located in the second pixel row have effective pulses in sequence, so that the pixel driving circuit electrically connected to the plurality of light emitting devices 10 located in the second pixel row experiences the corresponding first period (i.e. the second first period t1 in Figure 15 ) and the second period (i.e. the second second period t2 in Figure 15 ) in sequence. In succession, until the first gate control signal Scn and the second gate control signal Scn corresponding to the pixel driving circuit electrically connected to the plurality of light emitting devices 10 located in the eighth pixel row have effective pulses in sequence, so that the pixel driving circuit electrically connected to the plurality of light emitting devices 10 located in the eighth pixel row experiences the corresponding first period (i.e. the eighth first period t1 in Figure 15 ) and the second period (i.e. the eighth second period t2 in Figure 15 ) in sequence. Subsequently, the pixel driving circuit electrically connected to the plurality of light emitting devices 10 located in the first pixel row and the pixel driving circuit electrically connected to the plurality of light emitting devices 10 located in the eighth pixel row have the same third gate control signal ScnC with an effective level, so that the plurality of light emitting devices 10 located in the first pixel row and the eighth pixel row simultaneously enter the third period t3, and the plurality of light emitting devices 10 located in the first pixel row and the eighth pixel row simultaneously emit light.

[0132] Optionally, the duration of the simultaneous light emission of the plurality of light emitting devices 10 of the same light emitting group can be greater than or equal to 8 microseconds (μs) and less than or equal to 20 microseconds (μs). The time difference of the starting time of the effective pulse of the first gate control signal ScnA corresponding to the plurality of light emitting devices 10 of the adjacent two pixel rows PL can be equal to 20 microseconds.

[0133] It should be understood that, Figure 3A-3CThe effective pulses of the first gate control signal ScnA corresponding to the plurality of light emitting devices 10 in the plurality of pixel rows are drawn in the same signal, and the effective pulses of the second gate control signal ScnB corresponding to the plurality of light emitting devices 10 in the plurality of pixel rows are drawn in the same signal, in order to facilitate the description that the plurality of light emitting devices 10 in the plurality of pixel rows are controlled by the same third gate control signal ScnC. In actual applications, the effective pulses of the first gate control signal ScnA corresponding to the plurality of light emitting devices 10 in the plurality of pixel rows can be dispersed in multiple signals, and the effective pulses of the second gate control signal ScnB corresponding to the plurality of light emitting devices 10 in the plurality of pixel rows can be dispersed in multiple signals.

[0134] In some embodiments, the light emitting devices 10 located in the same light emitting unit 421 can be located on the same light bar. Optionally, each pixel driving circuit can be configured to drive the plurality of light emitting devices 10 located on the same light bar to emit light, so as to reduce the number of pixel driving circuits.

[0135] Please continue to refer to Figures 3A-3C The signal input module 70 can include a plurality of connection electrodes 71, and the plurality of connection electrodes 71 can include a first connection electrode, a second connection electrode, and a plurality of third connection electrodes, which can be respectively used to transmit the first control signal CS1, the second control signal CS2, and the plurality of input data signals S1.

[0136] That is, the first connection electrode is located on the substrate 30, and the first connection electrode is configured to transmit the first control signal CS1 to the data conversion module 50. The second connection electrode is located on the substrate 30, and the second connection electrode is configured to transmit the second control signal CS2 to the gate driving module 60. The plurality of third connection electrodes are located on the substrate 30, and the plurality of third connection electrodes are configured to transmit the plurality of input data signals S1 to the data conversion module 50.

[0137] Optionally, the number of third connection electrodes is greater than or equal to the ratio of the demand rate of the print head to the data rate of the input data signal S1 output by the print control module. In some embodiments, the number of third connection electrodes is greater than the ratio of the demand rate of the print head to the data rate of the input data signal S1 output by the print control module, so that the ability of the print head to receive the input data signal S1 is greater than the application demand.

[0138] For example, if the print head includes 600 light emitting devices 10 per inch, the print head includes 4992 light emitting devices 10 in total, the corresponding line period of the print head is 184 microseconds, the light emitting module 40 needs to have a light emitting intensity of 1 bit, the demand rate is 34 MHz, the data rate of the input data signal S1 is 6 MHz, and the print head applies an input voltage of 5 V, then 6 input data signals S1 can be used, and 6 third connection electrodes need to be set.

[0139] For example, if the print head includes 600 light emitting devices 10 per inch, the print head includes 4992 light emitting devices 10 in total, the corresponding line period of the print head is 184 microseconds, the light emitting module 40 needs to have a light emitting intensity of 4 bits, the demand rate is 136 MHz, the data rate of the input data signal S1 is 6 MHz, and the print head applies an input voltage of 5 V, then 24 input data signals S1 can be used, and 24 third connection electrodes need to be set. If the data rate of the input data signal S1 is 3 MHz, and the print head applies an input voltage of 3.3 V, then 48 input data signals S1 can be used, and 48 third connection electrodes need to be set. If the data rate of the input data signal S1 is 10 MHz, and the print head applies an input voltage of 1.8 V to 3.3 V, then 16 input data signals S1 can be used, and 16 third connection electrodes need to be set. The corresponding line period of the print head of 184 microseconds can include the sum of the first period, the second period, and the third period experienced by the plurality of light emitting devices 10 of the same light emitting group.

[0140] It should be noted that the demand rate refers to the total amount of pixel data that the print head needs to process per second at a specified resolution and color depth. The data rate of the input data signal S1 output by the print control module can refer to the original data rate transmitted by the print control module to the print head. In some embodiments, the data rate of the input data signal S1 output by the print control module can refer to the interface transmission rate of the print control module to the print head.

[0141] After the number of third connection electrodes is determined, the connection electrodes for transmitting the first control signal CS1 and the second control signal CS2 are set correspondingly, so that the drive of the light emitting module 40 in the print head can be realized.

[0142] Please continue to refer to Figure 3DIn some embodiments, the signal input module 70 further comprises a flexible circuit board 72 which is bound to the substrate 30 through a plurality of connection electrodes 71, and the flexible circuit board 72 is configured to transmit the first control signal CS1, the second control signal CS2 and the plurality of input data signals S1 output by the printing control module to the corresponding connection electrodes 71, so as to realize the signal transmission between the printing control module and the gate driving module 60 and the data conversion module 50.

[0143] In addition, the signal input module 70 can also receive the first control signal CS1, the second control signal CS2 and the plurality of input data signals S1 in a wireless communication manner. Please continue to refer to Figure 16 The signal input module 70 comprises a wireless communication unit 73 which is configured to communicate with the printing control module to receive the first control signal CS1, the second control signal CS2 and the plurality of input data signals S1 output by the printing control module.

[0144] By arranging the wireless communication unit 73, the connection electrodes 71 and the flexible circuit board 72 included in the signal input module 70 can be reduced or omitted, which is conducive to realizing efficient and convenient information interaction between the printing control module and the print head.

[0145] It should be understood that the wireless communication unit 73 in the signal input module 70 can serve as a receiving end to receive the plurality of signals output by the printing control module. The printing control module can serve as a sending end to provide the print head with the required signals. The communication manner between the wireless communication unit 73 and the printing control module includes but is not limited to at least one of the following technologies: wireless local area network, mobile communication, infrared communication, etc. The communication manner based on the wireless local area network includes but is not limited to the communication realized in the manner of WiFi or Bluetooth, the communication manner based on the mobile communication includes but is not limited to the communication realized in the manner of Global System for Mobile Communications, 3G, 4G or 5G, etc., and the communication manner based on the infrared communication includes but is not limited to the communication realized in the manner of infrared data transmission, etc.

[0146] Optionally, the signal input module 70 further comprises a signal processing unit which can perform at least one of the following processes on the first control signal CS1, the second control signal CS2 and the input data signals S1 received by the wireless communication unit 73, such as amplification, filtering, etc., to obtain the processed first control signal CS1, the second control signal CS2 and the input data signals S1, and then transmit the processed first control signal CS1, the second control signal CS2 and the input data signals S1 to the data conversion module 50 and the gate driving module 60 correspondingly.

[0147] In some embodiments, the fabrication process of the data conversion module 50, the gate driving module 60, and the light emitting module 40 can introduce a copper process and a side trace process to extend the traces on the substrate 30 toward the light emitting module 40, the data conversion module 50, and the gate driving module 60 to the side of the substrate 30 away from the light emitting module 40. The power manager that provides at least one voltage signal of the input voltage, the first voltage signal, the second voltage signal, and the like to the print head can be fabricated on the side of the substrate 30 away from the light emitting module 40 to improve the integration of the print head.

[0148] ​ For the principle block diagram of the print device of the embodiments of the present application, the present application further provides a print device, the print device comprising any of the print head 91 described above.

[0149] The print device can further comprise a print control module 92, the print control module 92 being electrically connected with the print head 91, and the print control module 92 being configured to output a first control signal CS1, a second control signal CS2, and a plurality of input data signals S1 to the print head 91.

[0150] In some embodiments, the print control module 92 can comprise at least one of a graphic processor, a microprocessor, and the like.

[0151] To realize the printing function of the print device, the print device can further comprise a photosensitive drum 93, a developing module 94, and a transfer module 95. The photosensitive drum 93 can rotate, and the photosensitive drum 93 is configured to receive the light signal projected by the print head 91 to form a latent image on the surface of the photosensitive drum 93. The developing module 94 is configured to develop the latent image on the surface of the photosensitive drum 93. The transfer module 95 is configured to transfer the image developed on the surface of the photosensitive drum 93 to a paper sheet.

[0152] Optionally, the print head 91 and the developing module 94 can be arranged at intervals along the rotation direction of the photosensitive drum 93, and both are arranged toward the surface of the photosensitive drum 93. The photosensitive drum 93 can be driven to rotate by a motor or the like. The developing module 94 can comprise a toner cartridge, and the toner cartridge is provided with toner, and the toner is electrostatically adsorbed on the position of the latent image on the surface of the photosensitive drum 93. The transfer module 95 and the surface of the photosensitive drum 93 are provided with a paper sheet, and the transfer module 95 can comprise a roller or the like mechanical structure.

[0153] When the light emitted by the print head 91 irradiates the surface of the photosensitive drum 93, the area of the surface of the photosensitive drum 93 receiving the light signal corresponds to the change of the electric charge, thereby forming a latent image. When the latent image moves to the position corresponding to the developing module 94 with the rotation of the photosensitive drum 93, the toner included in the developing module 94 is adsorbed to the position of the latent image of the photosensitive drum 93, thereby making the electrostatic latent image become a visible toner image, realizing the development of the latent image. When the developed image moves to the position corresponding to the transfer module 95 with the rotation of the photosensitive drum 93, the transfer module 95 will transfer the developed image to the paper, thereby completing the printing.

[0154] Optionally, the printing device can further include a charging module 96 for charging the surface of the photosensitive drum 93. The charging module 96 can form a uniform electric charge on the entire surface of the photosensitive drum 93, so as to form a latent image on the surface of the photosensitive drum 93 when the surface of the photosensitive drum 93 receives the light signal emitted by the print head 91. In some embodiments, the charging module 96 is a charging roller.

[0155] Since the printing device includes any of the above-mentioned print heads, the printing device at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

[0156] The above-mentioned is only an optional embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation made by using the content of the present application specification and drawings, or directly / indirectly applied in other related technical fields under the inventive concept of the present application is included in the patent protection scope of the present application.

Claims

1. A printhead, characterized by, The application relates to a display device, comprising: a substrate; a data conversion module located on the substrate and configured to generate a plurality of gray scale control signals according to a received first control signal and a plurality of input data signals; a gate drive module located on the substrate and configured to generate a plurality of gate control signals according to a second control signal; a light emitting module located on the substrate and electrically connected to the data conversion module and the gate drive module, and configured to emit light according to the plurality of gray scale control signals and the plurality of gate control signals.

2. The printhead of claim 1, wherein, The application further comprises: a signal input module electrically connected to the data conversion module and configured to transmit the first control signal and the plurality of input data signals; wherein the signal input module is located on a side of the data conversion module away from the light emitting module.

3. The printhead of claim 2, wherein, The data conversion module comprises: at least one first conversion unit electrically connected to the signal input module and configured to generate a plurality of logic control signals according to the first control signal and the plurality of input data signals; a second conversion unit electrically connected to the first conversion unit and configured to generate the plurality of gray scale control signals according to the plurality of logic control signals; wherein the first conversion unit is located between the second conversion unit and the signal input module.

4. The printhead of claim 3, wherein, The first control signal comprises a first clock signal and a latch control signal; and the first conversion unit comprises: a shift register unit electrically connected to the signal input module and configured to output a plurality of parallel data signals according to the first clock signal and the plurality of input data signals; a latch unit electrically connected to the shift register unit and configured to latch or output the plurality of parallel data signals according to the latch control signal; a level conversion unit electrically connected to the latch unit and configured to adjust the amplitude of the plurality of parallel data signals to generate the corresponding plurality of logic control signals.

5. The printhead of claim 4, wherein, From the signal input module to the light emitting module, the shift register unit, the latch unit, the level conversion unit and the second conversion unit are arranged in sequence.

6. The printhead of claim 4, wherein: the shift register unit comprises a plurality of shift registers, each of which is configured to generate one of the plurality of parallel data signals according to the first clock signal and one of the plurality of input data signals; the latch unit comprises a plurality of latch sub-units, each of which is electrically connected to one of the shift registers, and each of which comprises a plurality of latches, the plurality of latches of the same latch sub-unit being configured to receive one of the parallel data signals output by the corresponding shift register and to latch or output the received parallel data signal according to the latch control signal; the level conversion unit comprises a plurality of level conversion circuits, each of which is electrically connected to one of the latches of the plurality of latch sub-units and configured to adjust the amplitude of the parallel data signal to obtain one of the logic control signals. The second conversion unit comprises a plurality of digital-to-analog conversion circuits, each of the digital-to-analog conversion circuits is electrically connected with at least one of the level conversion circuits, and each of the digital-to-analog conversion circuits is configured to generate one of the gray scale control signals according to at least one of the logic control signals.

7. The printhead of claim 6, wherein, The color depth of the light emitting module is greater than or equal to 4 bits, and the data conversion module further comprises: a decoding unit electrically connected between the level conversion unit and the second conversion unit and configured to receive a plurality of the logic control signals to generate a plurality of binary signals; wherein the second conversion unit is configured to generate a plurality of the gray scale control signals according to a plurality of the binary signals.

8. The printhead of claim 7, wherein, The data conversion module comprises: two first conversion units including a first sub-conversion unit and a second sub-conversion unit; two decoding units including a first decoding unit and a second decoding unit, the first decoding unit being located between the first sub-conversion unit and the second conversion unit, and the second decoding unit being located between the second sub-conversion unit and the second conversion unit; the first decoding unit and the second decoding unit each comprise a plurality of decoders, each of the decoders being electrically connected between a plurality of the level conversion circuits and one of the digital-to-analog conversion circuits and configured to receive a plurality of the logic control signals to generate one of the binary signals; wherein the same digital-to-analog conversion circuit is electrically connected with one of the decoders of the first decoding unit and one of the decoders of the second decoding unit, and each of the digital-to-analog conversion circuits is configured to generate one of the gray scale control signals according to one of the binary signals output by one of the decoders of the first decoding unit and one of the binary signals output by one of the decoders of the second decoding unit.

9. The printhead of claim 2, wherein, The signal input module is electrically connected with the gate driving module, and the signal input module is configured to transmit the second control signal; wherein the gate driving module and the signal input module are located at different sides of the light emitting module.

10. The printhead of claim 1, wherein, The second control signal comprises a second clock signal, a trigger signal and a start signal; The gate driving module comprises: a clock generation unit configured to generate a plurality of third clock signals according to the second clock signal and the trigger signal; and a gate driving unit electrically connected with the clock generation unit and configured to generate a plurality of the gate control signals according to the start signal and a plurality of the third clock signals.

11. The printhead of claim 1, wherein, The light emitting module comprises: a plurality of light emitting devices; and a plurality of pixel driving circuits, each of the pixel driving circuits is electrically connected with at least one of the light emitting devices and configured to drive corresponding light emitting device to emit light according to corresponding gate control signal and corresponding gray scale control signal.

12. The printhead of claim 11, wherein, The plurality of gate control signals comprises a first gate control signal, a second gate control signal and a third gate control signal; The pixel driving circuit comprises: a driving transistor configured to generate a driving current according to the corresponding gray scale control signal to drive the corresponding light emitting device to emit light; a coupling unit electrically connected with the control terminal of the driving transistor through a first node and electrically connected with a second node, configured to couple the gray scale control signal to the first node; a reset unit electrically connected with the coupling unit, configured to reset the electric potential of the first node and the electric potential of the second node according to the first gate control signal; a compensation unit electrically connected with the first node and the driving transistor, configured to transmit the corresponding gray scale control signal to the second node according to the second gate control signal, and store the threshold voltage information of the driving transistor to the first node according to the second gate control signal; a switch unit electrically connected with the second node, the driving transistor and the corresponding light emitting device, configured to couple the gray scale control signal to the first node through the coupling unit according to the third gate control signal, and connect the current flow path between the driving transistor and the light emitting device according to the third gate control signal.

13. The printhead of claim 12, wherein, The gate drive module comprises: a first gate drive sub-module configured to generate a plurality of the first gate control signals according to the second control signal, to output to the reset unit of a plurality of the pixel driving circuits; a second gate drive sub-module configured to generate a plurality of the second gate control signals according to the second control signal, to output to the compensation unit of a plurality of the pixel driving circuits; and a third gate drive sub-module configured to generate a plurality of the third gate control signals according to the second control signal, to output to the switch unit of a plurality of the pixel driving circuits.

14. The printhead of claim 13, wherein, The first gate drive sub-module, the second gate drive sub-module, the third gate drive sub-module and the data conversion module are arranged around the light emitting module, and the data conversion module and the third gate drive sub-module are located on opposite sides of the light emitting module, and the first gate drive sub-module and the second gate drive sub-module are located on opposite sides of the light emitting module.

15. The printhead of claim 12, wherein, The light emitting module comprises at least one light emitting group, and at least one light emitting group comprises a plurality of light emitting units, each light emitting unit comprising a plurality of light emitting devices located in the same pixel row; wherein the pixel driving circuit electrically connected with a plurality of light emitting devices of each light emitting group is configured to drive a plurality of light emitting devices to emit light according to the corresponding gray scale control signal and the same third gate control signal.

16. The printhead of claim 2, wherein, The signal input module comprises a plurality of connection electrodes, and the plurality of connection electrodes comprises: a first connection electrode located on the substrate and configured to transmit the first control signal to the data conversion module; a second connection electrode located on the substrate and configured to transmit the second control signal to the gate drive module; a plurality of third connection electrodes located on the substrate and configured to transmit a plurality of input data signals to the data conversion module.

17. The printhead of claim 16, wherein, The number of third connection electrodes is greater than or equal to the ratio of the required rate of the print head to the data rate of the input data signal output by the print control module.

18. The printhead of claim 2, wherein, The signal input module comprises: A wireless communication unit configured to communicate with a print control module to receive the first control signal, the second control signal and a plurality of input data signals output by the print control module.

19. A printing device, characterized by Comprise: The print head according to any one of claims 1-18; And A print control module electrically connected to the print head and configured to output the first control signal, the second control signal and a plurality of input data signals to the print head.

20. The printing device of claim 19, wherein, Further comprise: A photosensitive drum, the photosensitive drum is rotatable, and the photosensitive drum is configured to receive the light signal projected by the print head to form a latent image on the surface of the photosensitive drum; A developing module configured to develop the latent image on the surface of the photosensitive drum; A transfer module configured to transfer the developed image on the surface of the photosensitive drum to a paper.

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