Chip test system, device and method based on AI large model training
By using an AI-based large-scale model-based chip testing system, the problems of high reliance on manual labor, insufficient scenario coverage, and poor reusability in traditional chip mass production testing have been solved, achieving a high-efficiency and low-cost chip testing solution.
Patent Information
- Application Number
- CN202511004504.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-21
- Publication Date
- 2025-11-07
AI Technical Summary
Traditional chip mass production testing solutions rely heavily on manual intervention, resulting in low testing efficiency, insufficient scenario coverage, poor reusability, and high testing costs, making it difficult to meet the rapid testing and iteration needs of complex chips.
The chip testing system based on AI large-scale model training generates test stimulus files through locally deployed AI large-scale models, and designs communication interaction logic in combination with the characteristics of chip testing to improve the efficiency and coverage of test stimulus generation.
Significantly improves chip mass production testing efficiency, reduces manual intervention, shortens testing cycles, increases functional coverage, and reduces testing costs.
Smart Images
Figure CN120908650A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip testing, and in particular to a chip testing system, device and method based on AI large model training. BACKGROUND
[0002] Chip mass production testing is a key link to ensure chip performance, reliability and yield, involving a complete process from wafer testing to post-packaging testing, directly affecting product reliability and cost.
[0003] With the continuous development of very large scale integrated circuits, the requirements for chip parameters are becoming more and more precise, and new demands for chip mass production testing are constantly emerging, especially in terms of testing efficiency and test coverage. The traditional chip testing solution mainly develops relevant mass production testing schemes through ATE (full name Automation Test Equipment) machine to test and screen chips, and the developed testing scheme requires to improve the defect fault test coverage as much as possible to screen unqualified chips, and also needs to adjust and modify some analog modules to different degrees. During the testing process, the test excitation needs to be adjusted manually according to the project, and then the simulation is continuously iterated and confirmed. The above chip mass production testing environment development has the following disadvantages: 1) strong dependence on manual work: usually, senior engineers need to manually write test cases according to the actual testing needs of different projects, and the development cycle accounts for more than 40% of the entire testing process, the testing efficiency is low, and high requirements are put forward for the testing personnel. Moreover, repeated testing requirements are time-consuming and laborious, and cannot meet the rapid testing iteration needs of complex chips. 2) Insufficient scene coverage: the excitation generated by the existing automatic script can only test single chip function, and it is difficult to cover boundary conditions and abnormal scene conditions, especially some complex interface protocol test cases are difficult to enumerate abnormal scenes. 3) Poor reusability: a large amount of adaptation and modification is needed for cross-project excitation transplantation, and the chip port changes need to be re-designed for testing scheme, resulting in a reusability of less than 30%. 4) High testing cost: testing time and testing cost are proportional, with the increasing complexity of chip, the testing content is increasing, and the testing cost is significantly increased.
[0004] It can be seen that the traditional chip mass production testing environment development has been unable to adapt to the needs of chip mass production testing with increasing complexity, and the complexity of batch production and the increasing refinement of chip design require more efficient chip testing schemes.
[0005] On the other hand, artificial intelligence (i.e., AI) is a technology that studies enabling a computer to simulate some thinking processes and intelligent behaviors of a person, mainly including principles of computer-implemented intelligence, manufacturing a computer similar to human brain intelligence, and enabling a computer to achieve higher level applications. In recent years, AI has ushered in a wave of development, and various AI large models have emerged, such as OpenAI GPT, MetaLLaMA, DeepSeek, etc. How to utilize AI large models to provide more application scenarios is also one of the current research hotspots. SUMMARY
[0006] The purpose of the present application is to overcome the shortcomings of the prior art, based on AI large model technology, to construct a collaborative verification system for chip mass production testing, which improves the most important test stimulus problem of chip mass production testing by using locally deployed AI large models, and designs the communication interaction logic of the host computer end and the AI large model end and the to-be-tested chip end according to the chip test characteristics, which well solves the problems of test stimulus generation efficiency and test coverage, thereby improving the chip mass production test efficiency.
[0007] To achieve the above-mentioned goal, the present application provides the following technical solutions: A chip test system based on AI large model training, the system comprising an AI large model end, a host computer end and a to-be-tested chip end, the host computer end being provided with a test stimulus module, the host computer end and the to-be-tested chip end being connected by hardware through standardized fixed connection terminals for communication interaction; The AI large model end is used for stimulus training based on a locally deployed AI large model, and generating a test stimulus file according to chip test requirements; The host computer end is used for acquiring the test stimulus file generated by the AI large model end, and converting the test stimulus file into a configuration signal file acceptable to the to-be-tested chip, the signal output satisfying the communication protocol of the to-be-tested chip; and outputting a stimulus signal to the to-be-tested chip through the test stimulus module according to the configuration signal file; The to-be-tested chip end is used for receiving the stimulus signal output by the host computer end, and feeding back a function verification signal to the host computer end.
[0008] Further, the AI large model end comprises a model training knowledge base, a prompt information input end and a model output end; The locally deployed AI large model is provided with an input port, after collecting a training resource file through the input port, the training resource file is provided to the AI large model for training and analysis to complete the construction of a knowledge base environment, the files that have been trained and analyzed are stored in the knowledge base as knowledge base files, and the knowledge base files record the mapping relationship between chip test requirements and corresponding test stimuli; The prompt information input end is configured to collect a chip test requirement file, a chip design file and a chip port file of a new chip, and send them to the AI large model; The AI large model is configured to update the knowledge base environment after training and analyzing the received chip design file and chip port file of the new chip to be tested, and generate a target test stimulus file meeting the test requirement according to all test stimuli corresponding to the extended chip test requirement after combining the updated new knowledge base environment with the received chip test requirement file. The AI model output end is configured to output the target test stimulus file generated by the AI large model.
[0009] Further, the prompt information input end is also configured to collect a scene keyword prompt file, which is used to expand keywords of test requirement points and test scenes of the new chip test requirement file to cover more test scenes. At this time, the AI large model is configured to expand test requirement points and test scenes of the chip test requirement file according to the test requirement points and test scene information in the scene keyword prompt file, form an expanded chip test requirement file according to the received chip test requirement file and scene keyword prompt file, and generate a target test stimulus file after obtaining all test stimuli corresponding to the expanded chip test requirement.
[0010] Further, the training resource file includes a chip design file, a test stimulus file, a chip port file and a test requirement file of a historical chip project. The AI large model end can batch output corresponding test stimulus files according to multiple test requirements and / or test scenes of a chip to be tested.
[0011] Further, the host computer end is provided with a file conversion module and a human-computer interaction module, The file conversion module is configured to convert the received test stimulus file into a configuration signal file of a corresponding type according to an acceptable configuration signal type of the chip to be tested. The human-computer interaction module is configured to collect a user's inspection operation instruction, and output an output signal of the configuration signal file and a function verification signal fed back by the chip to be tested according to the inspection operation instruction, so as to allow the user to inspect the test stimulus file and the function of the chip to be tested. The test stimulus module is also configured to perform parameter optimization and adjustment according to the test state of the chip.
[0012] Further, at the host computer end, the output signal of the dynamic waveform window output configuration signal file is output, and the function verification signal fed back from the chip under test end is monitored, the signal fed back from the chip under test end is transmitted by physical signal through the standardized slot between the host computer end and the chip under test end, and input / output (IO) and reading and writing operations on the internal register of the chip are supported; The test excitation module in the host computer end is configured to pour excitation signals from the IO port into the chip PAD end of the chip under test according to the configuration signal file meeting the communication protocol of the chip under test, so that the chip under test is in a test state; in the test state, the chip under test will make corresponding feedback signals according to the poured excitation signals, and output the feedback signals to the host computer end through the corresponding PAD port; the host computer end judges whether the function of the chip under test is normal according to the received feedback signals.
[0013] Further, the configuration signal file meets the timing requirements of the chip communication protocol, and the chip under test end reserves a register read / write port; after obtaining the register read / write test operation instruction issued by the host computer end, the chip under test is subjected to register read / write operation through the chip PAD end.
[0014] Further, the chip under test end is a chip test board card that has been pasted, and includes a clock crystal oscillator, an indicator light, different test mode switching switches, and a standardized connector for communication connection with the host computer end. After receiving the excitation signals issued by the configuration signal file of the host computer end, the chip under test end feeds back a state signal to the host computer end, indicating whether the function under test meets the requirements.
[0015] The application further provides a chip testing device based on AI large model training, and the device comprises: An AI model training module is configured to perform excitation training based on a locally deployed AI large model, and generate a test excitation file according to chip testing requirements; An excitation conversion engine is configured to obtain the test excitation file generated by the AI large model end, and convert the test excitation file into a configuration signal file acceptable by the chip under test end, wherein the signal output meets the communication protocol of the chip under test; A test excitation module is configured to output excitation signals to the chip under test according to the configuration signal file; A chip under test platform is a mass production test platform built for a chip under test that has been taped out, wherein the chip under test performs corresponding function tests according to the excitation signals, and feeds back function verification signals.
[0016] The application further provides a chip mass production test method, and the method comprises the following steps: An AI large model is trained based on local deployment, and a test excitation file is generated according to chip testing requirements; The test excitation file is converted into a configuration signal file acceptable to the chip end to be tested, and the signal output meets the communication protocol of the chip to be tested; According to the configuration signal file, the excitation signal is output to the chip to be tested; The chip to be tested receives the excitation signal for corresponding functional testing and feeds back the functional verification signal to the host computer end.
[0017] Compared with the prior art, the present application has the following advantages and positive effects as an example: based on AI large model technology, the present application constructs a collaborative verification system for chip mass production testing, which improves the main test excitation problem of chip mass production testing by using the locally deployed AI large model, and designs the communication interaction logic of the host computer end, the AI large model end and the chip to be tested according to the chip test characteristics, which solves the problems of test excitation generation efficiency and test coverage rate, thereby improving the chip mass production test efficiency.
[0018] Compared with the traditional method mainly relying on engineer's manual intervention and correction of chip mass production testing, the present application constructs a more intelligent and efficient chip mass production testing scheme, combines the test excitation of the existing development project with the design file, port file and test requirement file of the chip, and trains the large model by the locally deployed AI large model training method to output the excitation file meeting the test requirements, reduces the manual intervention and modification, and can adapt to the exhaustive test excitation, realizes the great shortening of the test period, the great improvement of the functional coverage rate, and the significant reduction of the manual intervention and design dependency of different projects, improves the output efficiency and reliability of the test excitation, and thereby improves the efficiency and test quality of the chip test. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 The information transmission schematic diagram of the chip test system based on AI large model training provided by the embodiment of the present application.
[0020] Figure 2 The module structure diagram of the chip test device based on AI large model training provided by the embodiment of the present application.
[0021] Figure 3 The flowchart of the chip mass production testing method provided by the embodiment of the present application. DETAILED DESCRIPTION
[0022] The chip test system, device and method based on AI large model training disclosed in the present application are further described in detail below in combination with the drawings and specific embodiments. It should be noted that the known technologies (including methods and devices) known to those skilled in the related art can not be discussed in detail, but the above known technologies are considered as part of the specification under appropriate circumstances. Meanwhile, other examples of exemplary embodiments can have different values. The structures, proportions, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content disclosed in the specification for understanding and reading by those skilled in the art, and are not used to limit the implementation conditions of the application.
[0023] In the description of the embodiments of the present application, " / " represents the meaning of or, and "and / or" is used to describe the association relationship of the associated objects, indicating that there can be three relationships, such as "A and / or B", indicating that A and B exist alone, B exists alone, and A and B exist simultaneously. In the description of the embodiments of the present application, "multiple" means two or more. Embodiments
[0024] Referring to Figure 1 As shown, the chip test system based on AI large model training provided by the present application includes an AI large model end, a host computer end and a chip under test end. The AI large model end can perform excitation training and excitation file generation based on the locally deployed AI large model, which can generate test excitation files that meet the requirements according to different requirements. The host computer end is configured to convert the excitation files generated by the AI large model into configuration signal files that can be output in real time, and the host computer end and the chip under test end are directly connected through standardized fixed connection terminals, so as to communicate and interact, ensuring the reliability and security of communication and interaction. At the same time, the chip test system supports the excitation module of the host computer end to directly read and write the internal registers of the chip through the input and output IO, wherein the input and output IO signals should be transmitted according to the specified communication protocol (the communication protocol acceptable by the chip under test). Further, the user can view the excitation configuration output signal and the feedback signal of the chip under test in real time through the host computer end to verify the correctness of the excitation file and the effectiveness of the function of the chip under test.
[0025] The locally deployed AI large model end can specifically include a model training knowledge base, a prompt information input end and a model output end.
[0026] The locally deployed AI large model is provided with an input port. After importing the training resource file through the input port, the AI large model is provided for training and analysis, and the construction of the knowledge base environment is completed. The files that have been trained and analyzed are stored as knowledge base files in the knowledge base, and the knowledge base files record the mapping relationship between chip test requirements and corresponding test excitation.
[0027] Specifically, the training resource file can include a chip design file, a test stimulus file, a chip port file and a test requirement file of a historical chip project.
[0028] By importing the complete design file of the historical chip project, model training and parsing are performed, and an environment of the knowledge base is built.
[0029] Further, in addition to the need to import the design file of the historical chip project and sequentially perform parsing, the chip port file can also be imported into the knowledge base and trained, thereby improving the intelligence and practicality level of the AI large model in chip testing. The chip port file is used to describe the input and output (I / O) pin information of the chip top module, including pin name, direction (input / output / bidirectional), electrical characteristics (voltage, driving capability), etc.; and is also used to describe the communication protocol and timing specification of the chip and external system or other modules, including signal grouping, timing parameters (such as setup / hold time), protocol type, etc.
[0030] In order to enable the AI model to recognize and deeply learn the functions realized by the chip test stimulus more quickly, different chip tests need to provide different stimulus files, and therefore the test stimulus file and the test requirement file of the historical chip project also need to be provided to the AI large model and sequentially trained and parsed.
[0031] The files that have been trained and parsed are stored as knowledge base files.
[0032] According to new chip test requirements, the chip design file and the chip port file of the new chip also need to be provided to the large model for training and parsing, as an updated environment of the new knowledge base.
[0033] Accordingly, the application is provided with a prompt information input end, which is used to collect the chip test requirement file, the chip design file and the chip port file of the new chip and send them to the AI large model.
[0034] The AI large model is configured to: after training and parsing the received chip design file and the chip port file of the new chip to be tested, update the environment of the aforementioned knowledge base to complete the preparation work of generating the test stimulus of the new chip to be tested; and after obtaining all test stimuli corresponding to the new chip test requirements according to the received chip test requirement file and combining the updated new knowledge base environment, generate a target test stimulus file that meets the test requirements. The target test stimulus file is the test stimulus file required by the current new chip to be tested.
[0035] The AI model output end is used to output the target test stimulus file generated by the AI large model.
[0036] Thus, the AI large model end combines the provided file with the previously trained new knowledge base environment to output a target test stimulus file that meets the test requirements.
[0037] Preferably, the prompt information input end is also used to collect (such as import) a scene keyword prompt file, which is used to expand the test requirement points and test scenes of the aforementioned new chip test requirement file with keywords to cover more test scenes.
[0038] At this time, the AI large model is configured to: according to the received chip test requirement file and the scene keyword prompt file, expand the test requirement points and test scenes of the chip test requirement file according to the test requirement points and test scene information in the scene keyword prompt file, to form an expanded chip test requirement file; and, according to the expanded chip test requirement file, combined with the aforementioned updated new knowledge base environment, after obtaining all test stimuli corresponding to the expanded chip test requirement, generate a target test stimulus file, which is a test stimulus file that meets multiple test requirements and covers multiple test scenes.
[0039] In this way, the scene keyword prompt file is used to expand the test requirement file of the new chip, supplement new test requirement points and cover test scenes, so as to meet the mass production test requirements of the chip in multiple functions and multiple scenes.
[0040] Next, the chip test stimulus file generated by the AI large model training is provided to the host computer end, and the host computer end converts the stimulus file output by the model into a configuration signal file acceptable to the chip under test.
[0041] The host computer end is used to obtain the test stimulus file generated by the AI large model end, and convert the test stimulus file into a configuration signal file acceptable to the chip under test, and the signal output meets the communication protocol of the chip under test; and according to the configuration signal file, output the stimulus signal, i.e. test signal, to the chip under test through the test stimulus module.
[0042] The chip under test is used to receive the stimulus signal output by the host computer end and feed back the function verification signal to the host computer end.
[0043] In this embodiment, the main function of the host computer end is to realize configuration signal file conversion and test stimulus file checking.
[0044] Specifically, the host computer end can be provided with a file conversion module and a human-computer interaction module.
[0045] The file conversion module is used to convert the received test stimulus file into a configuration signal file of a corresponding type according to the type of configuration signal acceptable to the chip under test.
[0046] The human-computer interaction module is used to collect the user's inspection operation instructions, and output the output signal (i.e., the excitation signal) of the configuration signal file and the function verification signal fed back by the chip under test according to the inspection operation instructions, so that the user can check the test excitation file and the function of the chip under test, thereby verifying the correctness of the excitation file and the effectiveness of the function of the chip under test.
[0047] In this embodiment, the test stimulus module is also used to optimize and adjust parameters according to the test status of the chip.
[0048] Specifically, on the host computer, the output signal of the configuration signal file is output through a dynamic waveform window, and the functional verification signal fed back from the chip under test is monitored. The signal fed back from the chip under test is physically transmitted via a standardized slot between the host computer and the chip under test, supporting input / output I / O and read / write operations on the chip's internal registers.
[0049] The configuration signal file generated by the above conversion needs to meet the communication protocol of the chip under test (DUT). The host computer will use the configuration signal file that meets this communication protocol to inject the excitation signal from the I / O port to the chip PAD of the DUT through the test excitation module. At this time, the chip is in a test-ready state. In the test-ready state, the chip will generate a corresponding feedback signal according to the injected excitation signal and output the feedback signal from the corresponding PAD port to the host computer. The host computer will then determine whether the tested function of the chip is normal based on the received feedback signal.
[0050] In this embodiment, the configuration signal file also meets the timing requirements of the chip communication protocol. The chip under test has a reserved register read / write port. After receiving the register read / write test operation command issued by the host computer, the chip under test performs register read / write operations through the chip's PAD. Thus, the user can issue register read / write test operations through the relevant software on the host computer.
[0051] In this embodiment, the chip under test is actually a chip test board that has been surface-mounted, which mainly includes a clock crystal oscillator, indicator lights, a switch for switching different test modes, and a standardized connector for communication with the host computer. Figure 1 (Standardized slots in the system).
[0052] After receiving the excitation signal (i.e. test signal) from the configuration signal file on the host computer, the chip under test sends a status signal to the host computer to indicate whether the function under test meets the requirements, thus completing the closed loop of the test.
[0053] In this embodiment, the AI large model can also be used to analyze the test function and the test scenario corresponding to the test stimulus file, establish the correspondence between the test function / test scenario and the chip test stimulus, and after naming or numbering the test function / test scenario, the corresponding chip test stimulus information can be obtained through the project name and / or number of the test function / test scenario. In this way, the generation speed of the chip test stimulus file can be improved, and the coverage demand of the chip test multifunctional scene can be met.
[0054] The above scheme provided by the application is based on the demand in the chip test field, uses the current AI large model technology, takes the design file, requirement file and port file of the historical chip project as the training resource file, fully utilizes the advantages of the AI large model, batch outputs the test stimulus file that can be used for the existing development chip, and further improves the functional coverage and application scene coverage of the test stimulus through the extended requirement file, so that the efficiency and test reliability of the chip test can be significantly improved. Through the batch generated stimulus file, the stimulus file can be converted into the configuration signal file acceptable by the chip under test on the host computer end by the existing test software or conversion script, the signal output of the configuration signal file meets the communication protocol of the chip under test. Meanwhile, the feedback system of the chip under test can efficiently complete the chip mass production functional test, forms a complete test system of stimulus generation, signal conversion and test feedback, and accelerates the application of the AI large model in the chip test field.
[0055] Referring to Figure 2 Another embodiment of the application is shown, and a chip test device based on AI large model training is also provided.
[0056] The device comprises an AI model training module, a stimulus conversion engine, a test stimulus module and a chip under test platform.
[0057] The AI model training module is used for performing stimulus training based on the AI large model deployed locally, and generating a test stimulus file according to the chip test demand.
[0058] The stimulus conversion engine is used for obtaining the test stimulus file generated by the AI large model end, and converting the test stimulus file into a configuration signal file acceptable by the chip under test, and the signal output meets the communication protocol of the chip under test.
[0059] The test stimulus module is used for outputting the stimulus signal to the chip under test according to the configuration signal file.
[0060] The chip under test platform is a mass production test platform built for the chip under test that has been taped out, the chip under test performs corresponding functional test according to the stimulus signal, and feeds back the functional verification signal.
[0061] Other technical features can be gleaned from the description of the preceding embodiments, which will not be repeated here.
[0062] Referring to Figure 3 As shown in another embodiment of the application, a chip mass production test method is also provided, which comprises the following steps.
[0063] S100, incentive training based on localized deployment of AI large model, and generating a test incentive file according to chip test requirements.
[0064] S200, converting the test incentive file into a configuration signal file acceptable to the chip under test, and the signal output satisfies the communication protocol of the chip under test.
[0065] S300, outputting the incentive signal to the chip under test according to the configuration signal file.
[0066] S400, the chip under test receives the incentive signal for corresponding functional test, and feeds back the functional verification signal to the host computer end.
[0067] Other technical features can be gleaned from the description of the preceding embodiments, which will not be repeated here.
[0068] In the above description, the disclosure of the application is not intended to limit itself to these aspects. Rather, the components can be selectively and operatively combined in any number of ways within the target protection scope of the disclosure. In addition, terms like "include", "comprise" and "have" should be interpreted as inclusive or open-ended, rather than exclusive or closed, unless explicitly defined as the opposite. All technical, scientific or other terms are consistent with the meaning understood by those skilled in the art, unless defined as the opposite. Common terms found in dictionaries should not be interpreted too idealistically or too unrealistically in the context of relevant technical documents, unless the disclosure explicitly limits it as such. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the claims.
Claims
1. An AI large model training-based chip test system, characterized in that, The AI large model end, the host computer end and the chip under test end are connected through a standardized fixed connection terminal for hardware connection to communicate and interact; The AI large model end is configured to perform excitation training based on the locally deployed AI large model, and generate a test excitation file according to a chip test requirement; The host computer end is configured to acquire the test excitation file generated by the AI large model end, convert the test excitation file into a configuration signal file acceptable to the chip under test, and output an excitation signal to the chip under test through the test excitation module according to the configuration signal file, wherein the signal output satisfies a communication protocol of the chip under test; The chip under test end is configured to receive the excitation signal output by the host computer end and feed back a function verification signal to the host computer end.
2. The system of claim 1, wherein, The AI large model end includes a model training knowledge base, a prompt information input end and a model output end; The locally deployed AI large model is provided with an input port, through which a training resource file is collected and provided to the AI large model for training and analysis to build a knowledge base environment, and the files that have been trained and analyzed are stored in the knowledge base as knowledge base files, which record the mapping relationship between chip test requirements and corresponding test excitations; The prompt information input end is configured to collect chip test requirement files, chip design files and chip port files of a new chip and send them to the AI large model; The AI large model is configured to update the environment of the knowledge base after training and analysis of the received chip design files and chip port files of the new chip under test, and generate a target test excitation file that meets the test requirement after obtaining all test excitations corresponding to the new chip test requirement based on the received chip test requirement file and the updated new knowledge base environment; The AI model output end is configured to output the target test excitation file generated by the AI large model.
3. The system of claim 2, wherein, The prompt information input end is also configured to collect a scene keyword prompt file, which is used to expand keywords of test requirement points and test scenes of the new chip test requirement file to cover more test scenes; At this time, the AI large model is configured to expand test requirement points and test scenes of the chip test requirement file according to the test requirement points and test scene information in the scene keyword prompt file based on the received chip test requirement file and scene keyword prompt file, form an expanded chip test requirement file, and generate a target test excitation file after obtaining all test excitations corresponding to the expanded chip test requirement based on the expanded chip test requirement file and the updated new knowledge base environment.
4. The system of claim 2 or 3, wherein, The training resource file includes chip design files, test excitation files, chip port files and test requirement files of historical chip projects; The AI large model end can batch output corresponding test excitation files according to multiple test requirements and / or test scenes of the new chip under test.
5. The system of any one of claims 1-3, wherein, The host computer end is provided with a file conversion module and a man-machine interaction module, The file conversion module is configured to convert the received test stimulus file into a configuration signal file of a corresponding type according to a type of configuration signal acceptable to the chip under test; The human-computer interaction module is configured to collect an inspection operation instruction of a user, and output an output signal of the configuration signal file and a function verification signal fed back from the chip under test according to the inspection operation instruction, so as to enable the user to inspect the test stimulus file and the function of the chip under test; The test stimulus module is further configured to perform parameter optimization adjustment according to a test state of the chip.
6. The system of claim 5, wherein, On the host computer side, the output signal of the configuration signal file is output through a dynamic waveform window, and the function verification signal fed back from the chip under test is monitored, the signal fed back from the chip under test is transmitted through physical signal transmission between the standardized slots between the host computer side and the chip under test, and input and output IO and read and write operations on internal registers of the chip are supported. The test stimulus module in the host computer side is configured to fill the stimulus signal from the IO port into the chip PAD of the chip under test according to the configuration signal file meeting the communication protocol of the chip under test, at this time, the chip is in a test-ready state; in the test-ready state, the chip will make a corresponding feedback signal according to the filled stimulus signal, and output the feedback signal from the corresponding PAD port to the host computer side; the host computer side judges whether the function of the current chip under test is normal according to the received feedback signal.
7. The system of claim 6, wherein, The configuration signal file meets the timing requirements of the chip communication protocol, and the chip under test side reserves a register read-write port, after obtaining the register read-write test operation instruction issued by the host computer side, performs register read-write operation on the chip under test through the chip PAD.
8. The system of claim 1, wherein: The chip under test side is a chip test board card that has been pasted, including a clock crystal oscillator, an indicator light, different test mode switching switches, and a standardized connector for communication connection with the host computer side. After receiving the stimulus signal issued by the configuration signal file of the host computer side, the chip under test side feeds back a state signal to the host computer side to indicate whether the function under test meets the requirements.
9. An AI large model training-based chip testing device, characterized in that It comprises: An AI model training module is configured to perform stimulus training based on a localized AI large model, and generate a test stimulus file according to chip test requirements; An excitation conversion engine is configured to obtain the test stimulus file generated by the AI large model side, and convert the test stimulus file into a configuration signal file acceptable to the chip under test, and the signal output meets the communication protocol of the chip under test; A test stimulus module is configured to output a stimulus signal to the chip under test according to the configuration signal file; A chip under test platform is a mass production test platform built for a chip under test that has been taped out, the chip under test performs corresponding function test according to the stimulus signal, and feeds back a function verification signal.
10. A method of testing a chip for mass production, characterized by It comprises the following steps: Performing stimulus training based on a localized AI large model, and generating a test stimulus file according to chip test requirements; Converting the test stimulus file into a configuration signal file acceptable to the chip under test, and the signal output meets the communication protocol of the chip under test; Outputting a stimulus signal to the chip under test according to the configuration signal file; The chip under test receives the stimulus signal to perform corresponding function test, and feeds back a function verification signal to the host computer side.