Band-gap reference circuit with low noise and high power supply ripple suppression capability

Abstract

The invention belongs to the technical field of analog integrated circuits, and designs a band-gap reference circuit with low noise and high power supply ripple suppression capability. The invention provides a pre-voltage-stabilizing structure to improve the low-frequency PSR. The amplification factor from the operational amplifier equivalent input noise to the reference voltage output is reduced through the voltage division ratio, and the low-frequency noise output by the reference voltage is effectively reduced through the isolation effect of the amplifier.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of analog integrated circuit power supply, and particularly relates to a low-noise high-power ripple rejection capability bandgap reference circuit. BACKGROUND

[0002] The bandgap reference voltage source provides a reference voltage for various analog circuit systems, such as ADC (Analog-to-Digital Converter, ADC for short), LDO (Low Dropout Regulator, LDO for short) and the like, and has extremely high requirements for the noise drift of the reference voltage and the power stability.

[0003] The conventional bandgap reference is formed by offsetting the positive temperature coefficient voltage difference of a transistor and the negative temperature coefficient voltage of a transistor to form a zero temperature coefficient voltage, and the positive temperature coefficient voltage is clamped through the virtual short characteristic of an amplifier. The amplifier amplifies the input crosstalk noise and couples the amplifier noise to the reference voltage source. The conventional low-noise reference mainly reduces the low-frequency noise through the chopping technology by switching the modulation signal, but the chopping technology will additionally introduce clock ripples and increase the circuit complexity.

[0004] The conventional bandgap reference voltage generally has a low power rejection ratio, and the conventional circuit is mainly limited by the matching of the current mirror, and the power rejection ratio is generally 40dB~80dB, and the power noise and ripple rejection capability is weak.

[0005] Therefore, how to solve the contradiction problem that the noise amplification coefficient increases due to the amplifier clamping reference voltage is the key research object in the field. SUMMARY

[0006] To solve the above background art, the application provides a low-noise high-power ripple rejection capability circuit suitable for BiCMOS process or BCD process.

[0007] The application reduces the noise amplification coefficient and increases the pre-stabilization circuit to realize the following technical scheme: A low-noise high-power ripple rejection circuit, as shown in Figure 1 , includes a pre-stabilization circuit, a bandgap reference core circuit and a high-order compensation circuit; in addition, as shown in Figure 2 , it includes a starting circuit, a biasing circuit and an amplifier module, which Figure 1 supplement the content of the module.

[0008] The pre-stabilization circuit comprises a first error amplifier AE1, a first PMOS transistor M1, a seventh resistor R7, and an eighth resistor R8; the input negative terminal of the first error amplifier AE1 is connected to a first reference voltage VREF1, the input positive terminal is connected between the seventh resistor R7 and the eighth resistor R8, and the output terminal is connected to the gate of the first PMOS transistor M1; the drain of the first PMOS transistor M1 is the output of the pre-stabilization circuit, and the source of the first PMOS transistor M1 is connected to a power supply; and the drain of the first PMOS transistor M1 is connected to the ground through the seventh resistor R7 and the eighth resistor R8.

[0009] The bandgap reference core comprises a third error amplifier AE3, a ninth PMOS transistor M9, a tenth PMOS transistor M10, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a first resistor R1, a second resistor R2_1, a third resistor R2_2, a fourth resistor R3_1, a fifth resistor R3_2, a sixth resistor R3_3, and a seventh resistor R3_4; the sources of the ninth PMOS transistor M9 and the tenth PMOS transistor M10 are connected to the output of the pre-stabilization circuit, the gate of the ninth PMOS transistor M9 is connected to the output of the third error amplifier AE3, and the drain of the ninth PMOS transistor M9 is connected to one end of the first resistor R1 and outputs a second reference voltage VREF2; the gate and the drain of the tenth PMOS transistor M10 are connected to the collector of the third NPN transistor Q3; the other end of the first resistor R1 is connected to the bases of the first NPN transistor Q1 and the third NPN transistor Q3, and one end of the second resistor R2_1 and the third resistor R2_2; the other ends of the second resistor R2_1 and the third resistor R2_2 are respectively connected to the collectors of the second NPN transistor Q2 and the first NPN transistor Q1; the emitters of the first NPN transistor Q1 and the second NPN transistor Q2 are connected to one end of the fourth resistor R3_1 to provide a voltage signal VF; the other end of the fourth resistor R3_1 provides a voltage signal VG, and the other end of the fourth resistor R3_1 is connected to the ground through the fifth resistor R3_2; and the emitter of the third NPN transistor Q3 is connected to the seventh resistor R3_4 through the sixth resistor R3_3 and then connected to the ground.

[0010] The high-order compensation circuit comprises a second error amplifier AE2, a second NMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6; The second error amplifier AE2 inputs a reference voltage VREF1 at a negative terminal, and a positive terminal of the second error amplifier AE2 is connected to a source terminal of a second NMOS transistor, and an output of the second error amplifier AE2 is connected to a gate terminal of the second NMOS transistor; a drain terminal of the second NMOS transistor and a source terminal of a third PMOS transistor and a source terminal of a fourth PMOS transistor are connected to an output of the pre-stabilization circuit; a source terminal of the second NMOS transistor is connected to one end of a sixth resistor R6; the other end of the sixth resistor R6 is connected to one end of a fifth resistor R5 and provides a voltage signal VD; the other end of the fifth resistor R5 is connected to one end of a fourth resistor R4 and provides a voltage signal VE; source terminals of a fifth PMOS transistor M5 and a sixth PMOS transistor M6 are connected; source terminals of a seventh PMOS transistor M7 and an eighth PMOS transistor M8 are connected; gate terminals of the fifth PMOS transistor M5 and the seventh PMOS transistor M7 are connected to a voltage signal VF; a gate terminal of the sixth PMOS transistor M6 is connected to the voltage signal VE; a gate terminal of the eighth PMOS transistor M8 is connected to the voltage signal VD; the other end of the fourth resistor and a drain terminal of the sixth PMOS transistor and a drain terminal of the seventh PMOS transistor are grounded.

[0011] The starting circuit comprises a third PMOS transistor Ms1, a third two PMOS transistor Ms2, a ninth resistor Rs, a first capacitor Cs; a gate terminal of the third PMOS transistor Ms1 is connected to a starting signal Vbp1 of the bias circuit, a source terminal of the third PMOS transistor Ms1 is connected to a power supply, and a drain terminal of the third PMOS transistor Ms1 is connected to ground through the first capacitor Cs. A gate terminal of the third two PMOS transistor Ms2 is connected to a drain terminal of the third PMOS transistor Ms1, a drain terminal of the third two PMOS transistor Ms2 is connected to a feedback signal Vbp2 of the bias circuit through the ninth resistor Rs, and a source terminal of the third two PMOS transistor Ms2 is grounded.

[0012] The bias circuit comprises a second two PMOS transistor M22, a second three PMOS transistor M23, a second four PMOS transistor M24, a second five PMOS transistor M25, a second six NMOS transistor M26, a second seven NMOS transistor M27, a second eight NMOS transistor M28, a second nine NMOS transistor M29, a tenth resistor Rp, an eleventh resistor Rn, a twelfth resistor Rd; The gate of the second two PMOS M22 and the gate of the second three PMOS M23 are connected to the drain of the second four PMOS M24 to provide a voltage signal Vbp1, the drain of the second two PMOS M22 and the second three PMOS M23 are connected to the source of the second four PMOS M24 and the second five PMOS M25 respectively, the source of the second two PMOS M22 and the second three PMOS M23 are both connected to the power supply; the gate of the second four PMOS M24 and the second five PMOS M25 are connected to the drain of the second six NMOS M26 to provide a voltage signal Vbp2, the drain of the second four PMOS M24 and the second five PMOS M25 are connected to the drain of the second six NMOS M26 and the second seven NMOS M27 through the tenth resistance Rp and the eleventh resistance Rn respectively; the gate of the second six NMOS M26 and the second seven NMOS M27 are connected to the drain of the second five PMOS M25 to provide a voltage signal VREF1, the source of the second six NMOS M26 and the second seven NMOS M27 are connected to the drain of the second eight NMOS M28 and the second nine NMOS M29 respectively; the gate of the second eight NMOS M28 and the second nine NMOS M29 are connected to the drain of the second seven NMOS M27 to provide a voltage signal Vbn1, the source of the second eight NMOS M28 is grounded through the twelfth resistance Rd, and the source of the second nine NMOS M29 is also grounded.

[0013] The error amplifier comprises an eleventh PMOS M11, a twelfth PMOS M12, a thirteenth PMOS M13, a fourteenth PMOS M14, a fifteenth PMOS M15, a sixteenth PMOS M16, a seventeenth PMOS M17, an eighteenth NMOS M18, a nineteenth NMOS M19, a twentieth NMOS M20, and a twenty-first NMOS M21. The source of the eleventh PMOS transistor M11, the fourteenth PMOS transistor M14 and the fifteenth PMOS transistor M15 is connected to a power supply; the source of the eleventh PMOS transistor M11 is connected to a voltage signal Vbp1, and the drain thereof is connected to the source of the twelfth PMOS transistor M12 and the thirteenth PMOS transistor M13; the gate of the twelfth PMOS transistor M12 and the thirteenth PMOS transistor M13 is the input positive terminal and the input negative terminal of an error amplifier respectively, and the drain of the twelfth PMOS transistor M12 and the thirteenth PMOS transistor M13 is connected to the drain of the twentieth NMOS transistor M20 and the twenty-first NMOS transistor M21 respectively; the gate of the fourteenth PMOS transistor M14 and the fifteenth PMOS transistor M15 is connected to the drain of the sixteenth PMOS transistor M16, and the drain of the fourteenth PMOS transistor M14 and the fifteenth PMOS transistor M15 is connected to the source of the sixteenth PMOS transistor M16 and the seventeenth PMOS transistor M17 respectively; the gate of the sixteenth PMOS transistor M16 and the seventeenth PMOS transistor M17 is connected to a voltage signal Vbp2, and the drain of the sixteenth PMOS transistor M16 and the seventeenth PMOS transistor M17 is connected to the drain of the eighteenth NMOS transistor M18 and the nineteenth NMOS transistor M19 respectively; the gate of the eighteenth NMOS transistor M18 and the nineteenth NMOS transistor M19 is connected to a voltage signal VREF1, and the source of the eighteenth NMOS transistor M18 and the nineteenth NMOS transistor M19 is connected to the drain of the twentieth NMOS transistor M20 and the twenty-first NMOS transistor M21 respectively; the gate of the twentieth NMOS transistor M20 and the twenty-first NMOS transistor M21 is connected to a voltage signal Vbn1, and the source of the twentieth NMOS transistor M20 and the twenty-first NMOS transistor M21 is grounded.

[0014] The substrate of all the NMOS transistors is grounded, and the substrate of all the PMOS transistors is connected to the power supply.

[0015] The bandgap reference core circuit of the application can realize low noise without external modulation, and the circuit is suitable for ordinary standard BiCMOS process.

[0016] The pre-stabilization circuit of the application can realize voltage limiting in a wide power voltage range, suppress power ripple and greatly improve the power supply rejection ratio.

[0017] The pre-stabilization circuit of the application expands the power voltage bearing range and improves the low-frequency power ripple suppression capability.

[0018] The bandgap reference core circuit of the application can realize low noise without external modulation, and the circuit is suitable for ordinary standard BiCMOS process.

[0019] The bandgap reference core circuit of the application can realize low noise without external modulation, and the circuit is suitable for ordinary standard BiCMOS process. Attached Figure Description

[0020] Figure 1 This is the top-level circuit diagram of the present invention; Figure 2 This invention supplements the bias circuit of the top-level circuit diagram and the bottom-level circuit. Figure 3 The figure shows the simulation results of the reference voltage temperature drift of the circuit of the present invention. Figure 4 The simulation results of the power supply rejection ratio of the circuit of the present invention are shown in the figure. Figure 5 The diagram shows the simulation results of the noise of the circuit of the present invention. Detailed Implementation

[0021] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings: The circuit of this invention can operate at a voltage of 2.7~5.5V. The method to improve the PSR is to use a pre-regulator circuit to generate a stable internal voltage that does not fluctuate with the power supply voltage to power the reference circuit. The PSR of the pre-regulator circuit and the PSR of the reference circuit are combined to become the PSR of the entire reference voltage. The method to reduce noise in this invention is to multiply the equivalent input noise of the error amplifier by an attenuation factor before transmitting it to the reference voltage, thereby suppressing the low-frequency output noise of the reference voltage.

[0022] The low-noise, high-power-ripple-suppression bandgap reference circuit structure proposed in this invention is shown in the figure below. Figure 1 As shown, it consists of three parts: a pre-regulator circuit, a bandgap core, and a high-order compensation circuit. Figure 2 As Figure 1 The additions include a start-up circuit, a bias circuit, and an error amplifier.

[0023] Figure 1 The structure of the three error amplifiers is as follows: Figure 2 The image shows a folded cascode amplifier with a single-ended PMOS input and folded cascode structure. Figure 1 The first reference voltage VREF1 in the middle is determined by Figure 2 The bias circuitry is provided in the middle.

[0024] Figure 2The start-up circuit in the power supply voltage is powered on due to the capacitor Cs charge of 0, the voltage signal Vbp2 is high level, the PMOS tube Ms2 is turned on to pull down Vbp2, and then the PMOS tube M22 is turned on at the same time, and the PMOS tube Ms1 is also turned on to charge the capacitor Cs, and the capacitor Cs is charged to high level to turn off the PMOS tube Ms2; therefore the start-up circuit does not consume static current after the bias circuit works normally. Figure 2 The bias circuit current in the power supply voltage is determined by the resistance Rd, and the current is , the current is a current independent of the power supply voltage, and the first reference voltage VREF1 generated is also a voltage independent of the power supply voltage.

[0025] The key to the design of the error amplifier is a high-gain operational amplifier, and the gain of the amplifier is: ; High gain can reduce the equivalent input error voltage and equivalent input noise, and high-gain operational amplifier can reduce the low-frequency PSR of the bandgap reference core and improve the power supply ripple rejection capability.

[0026] The first reference voltage is provided to the first error amplifier AE1 as an input reference, so that the voltage on the resistor R8 is limited to through the virtual short and virtual open characteristics of the amplifier, thereby generating a pre-regulation output voltage . Therefore is a voltage independent of the provided power supply voltage, and the pre-regulation can stabilize the voltage of 2.7~5.5V to about 2.2V.

[0027] In the bandgap reference core circuit, the emitter area of Q1 is set to A, the emitter area of Q2 is set to N·A, R2_1=R2_2=R2, R3_1=R3_2=R3_3=R3_4=R3; The positive temperature coefficient current is generated by , and the current generates a positive temperature coefficient voltage through R1; is a negative temperature coefficient voltage; therefore a zero-temperature coefficient voltage of first-order compensation is obtained: .

[0028] The high-order compensation circuit mirrors the positive temperature coefficient current through Q3, and then mirrors it to M3 and M4 through M10, and the design key of the mirror current is that the emitter area of Q3 is twice that of Q1, and all resistors are the same type. Set the current , the reference voltage VREF2 is generated by comparing the VD, VE and VF voltages generated by the voltage conversion circuit, and the sub-threshold current is generated from R3_2 compensation. The sub-threshold current formula is ; wherein, is the transistor saturation region current.

[0029] The currents of M5 and M8 are derived to be negative temperature coefficient and positive temperature coefficient currents respectively: ; Both are superimposed at the resistance to compensate for the formation of high-order compensation current . The final reference voltage formula is: ; In the present application, N is 6, and a reference voltage with a temperature drift coefficient below 10ppm / ℃ under the full process angle can be obtained .

[0030] The power supply ripple rejection capability of the overall circuit is obtained by the following formula: ; Therefore, the step-by-step circuit formula is calculated as follows: ; ; wherein, ; is the open-loop gain of the third error amplifier AE3; Therefore, by increasing the gain of the error amplifier, the value of can be reduced to improve the power supply ripple rejection capability of the overall circuit.

[0031] The transconductance of Q1 and Q2 can be obtained by the following formula: ; wherein N is the emitter area ratio of Q2 to Q1.

[0032] The small signal current through R2_2 is , the small signal voltage of node B is , that is ; the small signal current through R2_1 is , that is ; and the small signal voltage of node A is , that is .

[0033] The gain from node C to nodes A and B is: ; The equivalent resistance from node C downward is , that is , so the maximum n is 6, otherwise the equivalent resistance will become negative resistance and thus oscillation will occur.

[0034] The gain from node C to the reference voltage output is: ; The gain from node A, B to the reference voltage is: ; The equivalent output noise of this structure is given by: ; where N is the ratio of the emitter area of Q2 to Q1, N is 6 in this design, N is 6, so the multiplication factor of the equivalent input noise of the error amplifier is 1.008, which realizes the output result of almost no amplification of the equivalent input noise. Therefore, the equivalent input noise voltage of the error amplifier is designed to be very small, and a very small equivalent output noise reference voltage can be obtained.

[0035] Figure 3 The temperature drift of this design is about 7ppm / °C; Figure 4 The simulation of the power supply ripple rejection ability can be seen that the PSR can reach 130dB at DC, and still has 42dB at 100kHz; Figure 5 The noise simulation can be seen that the noise spectral density at 0.1Hz is 8.89 , and the noise spectral density at 1kHz is 290.8n .​

Claims

1. A low-noise high-power-ripple rejection capability bandgap reference circuit, the main body comprising a pre-regulator circuit, a bandgap reference core circuit, and a high-order compensation circuit; the supplementary circuit comprising a start-up circuit, a bias circuit, and an amplifier module; The pre-regulator circuit comprises a first error amplifier AE1, a first PMOS transistor M1, a seventh resistor R7, and an eighth resistor R8. The input negative terminal of the first error amplifier AE1 is connected to a first reference voltage VREF1, the input positive terminal is connected between the seventh resistor R7 and the eighth resistor R8, and the output is connected to the gate of the first PMOS transistor M1; the drain of the first PMOS transistor M1 is the output of the pre-regulator circuit, the source of the first PMOS transistor M1 is connected to the power supply, and the drain of the first PMOS transistor M1 is connected to the ground through the seventh resistor R7 and the eighth resistor R8.

2. The bandgap reference core circuit in a main body circuit according to claim 1, characterized by, The bandgap reference core circuit comprises a third error amplifier AE3, a ninth PMOS transistor M9, a tenth PMOS transistor M10, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a first resistor R1, a second resistor R2_1, a third resistor R2_2, a fourth resistor R3_1, a fifth resistor R3_2, a sixth resistor R3_3, and a seventh resistor R3_4; the sources of the ninth PMOS transistor M9 and the tenth PMOS transistor M10 are connected to the output of the pre-regulator circuit, the gate of the ninth PMOS transistor M9 is connected to the output of the third error amplifier AE3, and the drain of the ninth PMOS transistor M9 is connected to one end of the first resistor R1 and outputs a second reference voltage VREF2; the gate and the drain of the tenth PMOS transistor M10 are connected to the collector of the third NPN transistor Q3. The other end of the first resistor R1 is connected to the bases of the first NPN transistor Q1 and the third NPN transistor Q3, and one end of the second resistor R2_1 and the third resistor R2_2; the other ends of the second resistor R2_1 and the third resistor R2_2 are respectively connected to the collectors of the second NPN transistor Q2 and the first NPN transistor Q1; the emitters of the first NPN transistor Q1 and the second NPN transistor Q2 are connected to one end of the fourth resistor R3_1 to provide a voltage signal VF; the other end of the fourth resistor R3_1 provides a voltage signal VG, and the other end of the fourth resistor R3_1 is connected to the ground through the fifth resistor R3_2; the emitter of the third NPN transistor Q3 is connected to the seventh resistor R3_4 through the sixth resistor R3_3 and then connected to the ground.

3. The high-order compensation circuit in a main body circuit according to claim 1, characterized by, The high-order compensation circuit comprises a second error amplifier AE2, a second NMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The input negative terminal of the second error amplifier AE2 is connected to the reference voltage VREF1, the input positive terminal of the second error amplifier AE2 is connected to the source of the second NMOS transistor, and the output of the second error amplifier AE2 is connected to the gate of the second NMOS transistor. The drain of the second NMOS transistor, the source of the third PMOS transistor, and the source of the fourth PMOS transistor are connected to the output of the pre-regulator circuit. ​ The source of the second NMOS is connected to one end of the sixth resistor R6; the other end of the sixth resistor R6 is connected to one end of the fifth resistor R5 and provides a voltage signal VD; The other end of the fifth resistor R5 is connected to one end of the fourth resistor R4 and provides a voltage signal VE; the sources of the fifth PMOS M5 and the sixth PMOS M6 are connected; the sources of the seventh PMOS M7 and the eighth PMOS M8 are connected; the gates of the fifth PMOS M5 and the seventh PMOS M7 are connected to a voltage signal VF; the gate of the sixth PMOS M6 is connected to a voltage signal VE; the gate of the eighth PMOS M8 is connected to a voltage signal VD; the other end of the fourth resistor and the drain of the sixth PMOS and the drain of the seventh PMOS are grounded.

4. The start-up circuit in a supplemental circuit of claim 1, wherein, The starting circuit comprises a third PMOS Ms1, a fourth PMOS Ms2, a ninth resistor Rs, and a first capacitor Cs; the gate of the third PMOS Ms1 is connected to a bias circuit starting signal Vbp1, the source of the third PMOS Ms1 is connected to a power supply, and the drain of the third PMOS Ms1 is connected to ground through the first capacitor Cs. The gate of the fourth PMOS Ms2 is connected to the drain of the third PMOS Ms1, the drain of the fourth PMOS Ms2 is connected to a feedback signal Vbp2 of the bias circuit through the ninth resistor Rs, and the source of the fourth PMOS Ms2 is connected to ground.

5. The biasing circuit in a supplemental circuit of claim 1, wherein, The bias circuit comprises a second two PMOS M22, a second three PMOS M23, a second four PMOS M24, a second five PMOS M25, a second six NMOS M26, a second seven NMOS M27, a second eight NMOS M28, a second nine NMOS M29, a tenth resistor Rp, an eleventh resistor Rn, a twelfth resistor Rd; the gate of the second two PMOS M22 and the gate of the second three PMOS M23 are connected to the drain of the second four PMOS M24 to provide a voltage signal Vbp1, the drains of the second two PMOS M22 and the second three PMOS M23 are respectively connected to the sources of the second four PMOS M24 and the second five PMOS M25, and the source of the second two PMOS M22 and the source of the second three PMOS M23 are both connected to a power supply; the gates of the second four PMOS M24 and the second five PMOS M25 are connected to the drain of the second six NMOS M26 to provide a voltage signal Vbp2, the drains of the second four PMOS M24 and the second five PMOS M25 are respectively connected to the drains of the second six NMOS M26 and the second seven NMOS M27 through the tenth resistor Rp and the eleventh resistor Rn; the gates of the second six NMOS M26 and the second seven NMOS M27 are connected to the drain of the second five PMOS M25 to provide a voltage signal VREF1, the sources of the second six NMOS M26 and the second seven NMOS M27 are respectively connected to the drains of the second eight NMOS M28 and the second nine NMOS M29; the gates of the second eight NMOS M28 and the second nine NMOS M29 are connected to the drain of the second seven NMOS M27 to provide a voltage signal Vbn1, the source of the second eight NMOS M28 is grounded through the twelfth resistor Rd, and the source of the second nine NMOS M29 is also grounded.

6. The amplifier module in the supplemental circuit of claim 1, wherein, The error amplifier comprises an eleventh PMOS M11, a twelfth PMOS M12, a thirteenth PMOS M13, a fourteenth PMOS M14, a fifteenth PMOS M15, a sixteenth PMOS M16, a seventeenth PMOS M17, an eighteenth NMOS M18, a nineteenth NMOS M19, a twentieth NMOS M20, and a twenty-first NMOS M21; the sources of the eleventh PMOS M11, the fourteenth PMOS M14, and the fifteenth PMOS M15 are all connected to a power supply The source of the eleventh PMOS transistor M11 is connected to a voltage signal Vbp1, and the drain of the eleventh PMOS transistor M11 is connected to the source of a twelfth PMOS transistor M12 and a thirteenth PMOS transistor M13. The gates of the twelfth PMOS transistor M12 and the thirteenth PMOS transistor M13 are connected to the positive input and the negative input of the error amplifier, respectively. The drains of the twelfth PMOS transistor M12 and the thirteenth PMOS transistor M13 are connected to the drains of a twentieth NMOS transistor M20 and a twenty-first NMOS transistor M21, respectively. The gates of a fourteenth PMOS transistor M14 and a fifteenth PMOS transistor M15 are connected to the drain of a sixteenth PMOS transistor M16. The drains of the fourteenth PMOS transistor M14 and the fifteenth PMOS transistor M15 are connected to the sources of the sixteenth PMOS transistor M16 and a seventeenth PMOS transistor M17, respectively. The gates of the sixteenth PMOS transistor M16 and the seventeenth PMOS transistor M17 are connected to a voltage signal Vbp2. The drains of the sixteenth PMOS transistor M16 and the seventeenth PMOS transistor M17 are connected to the drains of an eighteenth NMOS transistor M18 and a nineteenth NMOS transistor M19, respectively. The gates of the eighteenth NMOS transistor M18 and the nineteenth NMOS transistor M19 are connected to a voltage signal VREF1. The sources of the eighteenth NMOS transistor M18 and the nineteenth NMOS transistor M19 are connected to the drains of the twentieth NMOS transistor M20 and the twenty-first NMOS transistor M21, respectively. The gates of the twentieth NMOS transistor M20 and the twenty-first NMOS transistor M21 are connected to a voltage signal Vbn1. The sources of the twentieth NMOS transistor M20 and the twenty-first NMOS transistor M21 are connected to ground.

7. The MOS transistor according to claims 1-6, wherein The substrates of all the NMOS transistors are connected to ground, and the substrates of all the PMOS transistors are connected to the power supply.

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