Instruction scheduling circuit, chip, data processing method and electronic equipment

Abstract

The invention provides an instruction scheduling circuit, a chip, a data processing method and electronic equipment. The instruction scheduling circuit comprises a collector, a first timestamp counter and a data buffer. The collector is used for receiving an instruction state signal from an engine, and the instruction state signal comprises a starting state signal and an ending state signal of an instruction received by the engine; the first timestamp counter is used for receiving a first timestamp signal generated based on the sampling clock counter; the data buffer is used for receiving a data packet formed by the instruction state signal, the first timestamp signal and the second timestamp signal, and writing the data packet into the memory; wherein the second timestamp signal is generated based on a system clock counter. According to the method and the device, the starting timestamp and the ending timestamp of each instruction can be accurately counted in the multi-thread scheduler, so that the running duration of each instruction is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of AI chip design, and in particular to an instruction scheduling circuit, a chip, a data processing method and an electronic device. BACKGROUND

[0002] In an AI chip, an instruction scheduler has a profile function. The profile function of the instruction scheduler is an important tool for performance optimization and resource management. The profile can track the running time, idle cycle ratio and high energy-consuming operations (such as frequent repeated calls) of instructions. Accurate data collection and analysis can reveal hardware execution details, which are crucial for resource and performance tuning. However, it is difficult to accurately obtain the running time of each instruction in the related art. SUMMARY

[0003] Embodiments of the present application provide an instruction scheduling circuit, a chip, a data processing method and an electronic device, which can accurately record the start and end timestamps of each instruction in a multi-threaded scheduler to obtain the running time of each instruction.

[0004] The technical solution of the embodiments of the present application is as follows: An instruction scheduling circuit is provided, comprising a collector, a first timestamp counter and a data buffer. The collector is configured to receive an instruction state signal from an engine, wherein the instruction state signal comprises a start state signal and an end state signal of an instruction received by the engine. The first timestamp counter is configured to receive a first timestamp signal generated based on a sampling clock counter. The data buffer is configured to receive a data packet composed of the instruction state signal, the first timestamp signal and a second timestamp signal, and write the data packet into a memory. The second timestamp signal is generated based on a system clock counter.

[0005] A data processing method is provided, comprising: The collector receives an instruction state signal from an engine, wherein the instruction state signal comprises a start state signal and an end state signal of an instruction received by the engine. The first timestamp counter receives a first timestamp signal generated based on a sampling clock counter. The data buffer receives a data packet composed of the instruction state signal, the first timestamp signal and a second timestamp signal, and writes the data packet into a memory. The second timestamp signal is generated based on a system clock counter.

[0006] An embodiment of the present application provides a data processing apparatus, comprising: An acquisition module is configured to acquire an instruction state signal from an engine, wherein the instruction state signal comprises a start state signal and an end state signal of an instruction received by the engine; A counting module is configured to receive a first time stamp signal generated based on a sampling clock counter by a first time stamp counter; A cache module is configured to receive a data packet composed of the instruction state signal, the first time stamp signal and a second time stamp signal by a data cache, and write the data packet into a memory, wherein the second time stamp signal is generated based on a system clock counter.

[0007] An embodiment of the present application provides a chip, wherein the chip is deployed with the instruction scheduling circuit.

[0008] An embodiment of the present application provides an electronic device, wherein a chip in the electronic device is deployed with the instruction scheduling circuit.

[0009] An embodiment of the present application provides an electronic device, comprising: A memory is configured to store computer executable instructions or computer programs; A processor is configured to execute the computer executable instructions or computer programs stored in the memory, so as to implement the data processing method provided by an embodiment of the present application.

[0010] An embodiment of the present application provides a computer readable storage medium, which stores computer programs or computer executable instructions, and is configured to be executed by a processor, so as to implement the data processing method provided by an embodiment of the present application.

[0011] An embodiment of the present application provides a computer program product, comprising computer programs or computer executable instructions, and the computer programs or computer executable instructions are configured to be executed by a processor, so as to implement the data processing method provided by an embodiment of the present application.

[0012] An embodiment of the present application has the following beneficial effects: The scheduling circuit provided by the embodiment of the present application receives the instruction state signal from the engine through the collector, can ensure the instant feedback of the instruction execution state, and integrates the start and end state signals of the instruction, can obtain the complete life cycle of the instruction, and is convenient for subsequent management and optimization. Secondly, the timestamp signal generated by the clock counter and the system clock counter is respectively sampled through the timestamp counter, which can provide high-precision timing to accurately determine the execution time of different states of the instruction. Thirdly, the instruction state signal is received through the data buffer, and the timestamp signal and the instruction state signal are combined to form a data packet, which provides a temporary storage space for the data packet, can ensure the integrity of the data before the data packet is written into the memory, and reduces the risk of data loss and the number of direct accesses to the memory through the buffered data, which can improve the overall operation efficiency of the system. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 The composition structure of the instruction scheduling circuit provided by the embodiment of the present application is shown Figure One ; Figure 2 The composition structure of the instruction scheduling circuit provided by the embodiment of the present application is shown Figure Two ; Figure 3 The composition structure of the instruction scheduling circuit provided by the embodiment of the present application is shown Figure Three ; Figure 4 The composition structure of the instruction scheduling circuit provided by the embodiment of the present application is shown Figure Four ; Figure 5 The composition structure of the instruction scheduling circuit provided by the embodiment of the present application is shown Figure Five ; Figure 6 The flowchart of the data processing method provided by the embodiment of the present application is shown Figure 7 The structure diagram of the instruction scheduling circuit provided by the embodiment of the present application is shown Figure 8 The performance analysis diagram provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings, and the described embodiments should not be regarded as limiting the present application. All other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0015] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets as each other and can be combined with each other as long as there is no conflict.

[0016] It can be understood that, in the embodiments of the present application, the data related to user information and the like are involved, and when the embodiments of the present application are applied to specific products or technologies, the user permission or consent needs to be obtained, and the collection, use and processing of the related data need to comply with relevant laws, regulations and standards.

[0017] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works together with other related parts to achieve a predetermined target, and can be implemented entirely or partially by using software, hardware (such as a processing circuit or a memory) or a combination thereof. Similarly, one processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be a part of an integral module or unit that includes the functions of the module or unit.

[0018] In the following description, the term "first\second\..." referred to is only to distinguish similar objects, and does not represent a specific order of the objects. It can be understood that "first\second\..." can be interchanged in a specific order or sequence as long as it is allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0020] Before the embodiments of the present application are further described in detail, the terms and phrases involved in the embodiments of the present application are explained, and the terms and phrases involved in the embodiments of the present application are applicable to the following explanations.

[0021] 1) In response to: used to indicate the condition or state on which the operation is performed, when the dependent condition or state is met, one or more operations performed can be real-time or have a set delay; in the absence of special instructions, there is no restriction on the execution order of the multiple operations performed.

[0022] 2) Instruction Scheduler: The instruction scheduler is a component in the processor responsible for optimizing the order of instruction execution to improve the performance of the processor. The purpose of the instruction scheduler is to reduce execution latency by rearranging the order of instruction execution, so that the resources of the processor are used more efficiently. When the processor executes instructions, it encounters various types of instructions, including arithmetic operations, data loading, data storage, and branch instructions, etc. These instructions may have data dependencies (for example, the output of one instruction is the input of another instruction), or they may be completely independent. The instruction scheduler analyzes these dependencies and, where possible, rearranges the order of instruction execution to execute as many instructions in parallel as possible without violating data dependencies.

[0023] 3) Profile Unit: In the instruction scheduler, the Profile Unit analyzes the behavior of the program by collecting statistical information during its execution, such as the number of times each instruction is executed, the execution time, the accuracy of branch prediction, cache hit rate, etc. Through the Profile Unit, the instruction scheduler can more accurately understand the behavior of the program and optimize it based on this information to improve the efficiency and overall performance of the program.

[0024] 4) Timestamp Counter (TC): The timestamp counter is used to record the number of clock cycles elapsed since the processor was started, providing accurate time measurement for programs. The value of the timestamp counter increments every time the processor clock cycle, which can be used to measure time intervals, calculate the execution time of programs, or as a mechanism for synchronizing multiple processors or threads.

[0025] 5) Burst Statistical Counter: The Burst Statistical Counter is a high-performance counter used in processors or network devices to record the number of times or duration of specific events, which can be used to handle a large number of events occurring in a short period of time, such as burst transmission of data packets, burst operations of processors, etc.

[0026] 6) Central Processing Unit (CPU): The central processing unit is the core operation and control component of the computer system, responsible for executing program instructions, processing data, and coordinating the work of various hardware components, and its performance directly affects the overall efficiency of the computer.

[0027] 7) Register: The register is a high-speed storage component used to temporarily store instructions, data, and addresses, composed of flip-flops or latches, with each flip-flop storing 1 bit of binary code.

[0028] 8) Sampling Clock: Sampling Clock is a reference clock signal used to synchronize the sampling of analog signals in digital signal processing systems. Its frequency and stability directly determine the accuracy of analog-to-digital conversion (ADC) and the quality of signal restoration.

[0029] 9) Thread: Thread is the smallest unit of operation scheduling by the operating system, representing an actual execution unit within a process. A process can contain multiple threads, each representing an independent control flow, sharing process resources such as memory and file handles, but having independent call stacks and register states.

[0030] 10) Engine: In the field of computers, Engine refers to a modular component that provides core functional support for systems or applications. Engines encapsulate complex underlying logic and provide standardized interfaces for developers.

[0031] 11) AXI Bus (Advanced eXtensible Interface): AXI Bus is a high-performance, on-chip interconnect protocol, mainly used for high-speed data communication between internal modules of a chip (such as CPU, DMA, accelerator, memory controller, etc.). It supports parallel transmission of address, data, and control signals, thereby improving throughput. A single address transmission can follow multiple data beats, reducing address channel overhead. It includes five independent channels: read address, read data, write address, write data, and write response, supporting full-duplex communication. It can achieve transaction out-of-order completion through ID tags to improve bus utilization. It can be configured with data bit widths such as 32, 64, 128, 256, and 512 bits to adapt to different bandwidth requirements. AXI Bus is widely used in SoC (System-on-Chip) design, serving as a high-performance bridge connecting processors, peripherals, memory, and accelerators.

[0032] In AI chips, the instruction scheduler has a profile function. The profile function of the instruction scheduler is an important tool for performance optimization and resource management. It can track the running time, idle cycle ratio, and high-energy operations (such as frequent repeated calls) of instructions. Accurate data collection and analysis can reveal hardware execution details, which are crucial for resource and performance tuning. However, it is difficult to accurately obtain the running time of each instruction in related technologies.

[0033] Therefore, the embodiments of the present application provide an instruction scheduling circuit, a chip, a data processing method, and an electronic device, which can accurately record the start and end timestamps of each instruction in a multi-threaded scheduler to obtain the running time of each instruction.

[0034] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0035] In some embodiments, Figure 1 The component structure of the instruction scheduling circuit provided in the embodiments of the present application is shown in Figure One As shown in Figure 1 , the instruction scheduling circuit 10 can include a collector 101, a first timestamp counter 102, and a data buffer 103, wherein: The collector 101 is configured to receive an instruction state signal from an engine.

[0036] Here, the instruction state signal includes a start state signal and an end state signal of an instruction received by the engine.

[0037] In some embodiments, the collector can be a communication interface such as RS-485, etc.; can be a sensor module that synchronously acquires the state signal transmitted by the engine; or can be a signal conditioning circuit, etc., which is not limited here.

[0038] It should be noted that the instruction state signal can be represented in different encoding methods, for example, in one-hot encoding, each bit represents the start state or end state of the instruction on different engines; for example, the first three bits represent different engines, and the fourth bit represents the start state or end state of the instruction.

[0039] As an example, taking one-hot encoding as an example, assuming that there are four engines 0 to 3, and the instruction state signal at a certain time includes a start state signal of the instruction of engine 0 and an end state signal of the instruction of engine 3, the instruction state signal can be encoded as 1000, 0001, the first four bits record the start state signal, and the last four bits record the end state signal.

[0040] It should be noted that the high four bits correspond to “engine 0 start, engine 1 start, engine 2 start, engine 3 start” in turn, and the low four bits correspond to “engine 0 end, engine 1 end, engine 2 end, engine 3 end” in turn. When a start or end event occurs on any engine at any time, the corresponding bit position is 1, and the remaining bits are 0; when engine 0 sends a start pulse, the first bit of the high four bits is set to 1, and when engine 3 sends an end pulse, the fourth bit of the low four bits is set to 1, and finally an 8-bit vector 1000_0001 is formed.

[0041] In some embodiments, the instruction state signal further includes a thread signal to which the instruction belongs.

[0042] As an example, assuming there are two threads 0 and 1, four engines 0 to 3, and the instruction state signal at a certain moment includes the start state signal of the instruction of engine 1 of thread 0 and the end state signal of the instruction of engine 2 of thread 1, the instruction state signal can be encoded as 0100, 0000, 0000, 0010, the first eight bits record the start state signal, and the last eight bits record the end state signal.

[0043] It should be noted that the high eight bits are arranged in the order of “start of thread 0 engine 0 → start of thread 0 engine 1 → start of thread 0 engine 2 → start of thread 0 engine 3 → start of thread 1 engine 0 → start of thread 1 engine 1 → start of thread 1 engine 2 → start of thread 1 engine 3”, and the low eight bits correspond to the end state events in the same order; when thread 0 sends a start pulse at engine 1, the second bit of the high eight bits is set to 1; at the same time, thread 1 sends an end pulse at engine 2, the sixth bit of the low eight bits is set to 1; the remaining 14 bits remain 0, and finally a 16-bit vector 0100_0000_0000_0010 is formed.

[0044] The first timestamp counter 102 is configured to receive a first timestamp signal generated based on the sampling clock counter.

[0045] It should be noted that the sampling clock counter is a key component in a digital signal processing and data acquisition system, which is used to accurately control the sampling timing of an analog signal and count the number of clock pulses.

[0046] The data buffer 103 is configured to receive a data packet composed of the instruction state signal, the first timestamp signal, and the second timestamp signal, and write the data packet into the memory.

[0047] Here, the second timestamp signal is generated based on the system clock counter. The system clock counter is a core hardware module in a computer or embedded system for accurately measuring time intervals, which is usually integrated inside the CPU or microcontroller and can provide precise time units through the system clock pulse.

[0048] It should be noted that the data packet composed of the instruction state signal, the first timestamp signal, and the second timestamp signal can be realized by hardware, which transmits data through a parallel bus and packs the instruction state and timestamp into a fixed format frame (for example, [instruction][T1][T2]) through a custom protocol (for example, UART or SPI).

[0049] In some embodiments, the data buffer is a technical component for temporarily storing data, which coordinates the difference in data transmission rate of different hardware or software modules to improve system efficiency.

[0050] In the embodiment of the present application, the collector 101 is configured to receive the instruction state signal from the engine, the instruction state signal comprising a start state signal and an end state signal of the instruction received by the engine, for example, the start state signal of the engine 1 and the end state signal of the engine 2; the first timestamp counter 102 can receive the first timestamp signal generated based on the sampling clock counter, and can provide high-precision timing; the data buffer 103 can receive the data packet composed of the instruction state signal, the first timestamp signal and the second timestamp signal, and write the data packet into the memory, and by associating the time information with the instruction state signal, the running start and end time of different instructions can be accurately recorded, so as to facilitate subsequent analysis of different instruction data.

[0051] As an example, the instruction state signal from the engine is received by the collector , the first timestamp signal received by the first timestamp counter based on the sampling clock counter is , the second timestamp signal generated based on the system clock counter is , the instruction state signal , the first timestamp signal and the second timestamp signal are composed into a data packet for , , , the data buffer receives the data packet and writes the data packet into the memory.

[0052] It should be noted that the collector receives the instruction state signal from the engine , and simultaneously triggers the 700MHz sampling clock counter and the 25MHz system clock counter, respectively, to capture the count value at this moment as and , respectively, and the three are spliced into a complete packet S in a fixed order, and then the buffer compresses the complete packet into the FIFO, and when the accumulated bit width reaches the AXI bus width, it is written into the memory at one time, and one lossless event record with double timestamps is completed.

[0053] In some embodiments, Figure 2 the composition structure of the instruction scheduling circuit provided in the embodiment of the present application is shown Figure Two . As shown in Figure 2 , the instruction scheduling circuit 10 can further include a statistical counter 104.

[0054] a data buffer 103, configured to buffer the received data packets, and write all the buffered data packets in the data buffer into the memory when the amount of data in the data buffer reaches the bus width or the last data packet with the instruction status signal is received.

[0055] It should be noted that the bus width refers to the number of binary data bits that can be transmitted simultaneously in a computer system, and is usually expressed in bits. The bus width determines the amount of data that can be transmitted per clock cycle. The larger the bus width, the larger the amount of data transmitted at a time, and the higher the data transmission efficiency.

[0056] a statistical counter 104, configured to count a first number of data packets written into the memory by the data buffer, and synchronize the first number of data packets to the central processor when the first number of data packets written into the memory reaches a first threshold.

[0057] It should be noted that the first threshold is pre-set to measure whether the amount of data written into the memory needs to be synchronized to the central processor.

[0058] In the embodiments of the present application, the data buffer 103 is configured to buffer the received data packets, and write all the buffered data packets in the data buffer into the memory when the amount of data in the data buffer reaches the bus width or the last data packet with the instruction status signal is received. By buffering the data packets, the number of frequent memory accesses can be reduced, and by batch writing when the amount of data reaches the bus width or the termination signal is received, the bus load can be significantly reduced and the memory writing efficiency can be improved. The statistical counter can count a first number of data packets written into the memory by the data buffer, and synchronize the first number of data packets to the central processor when the first number of data packets written into the memory reaches a first threshold. This can reduce the overhead of frequent polling of the CPU, reduce system delay, and by counting the writing frequency, the CPU can dynamically adjust the memory allocation strategy to avoid performance fluctuations caused by conflict writing.

[0059] As an example, assuming that each data packet size is 5 bits, the bus bit width is 10 bits, and the first threshold is 4, when it is detected that the amount of data in the data buffer reaches 10 bits, all the buffered data in the data buffer is written into the memory, and at the same time, the statistical counter records that the first number of data packets written into the memory by the data buffer is 2, when the first number of writing into the memory reaches 4, the data packets of the first number of 4 writing into the memory are synchronized to the central processor. Here, the buffer is accumulated by bits, and each time a 5-bit packet is received, it is appended to the tail, and the bit width counter is synchronized to add 5, and once the counter reaches 10, the AXI write transaction is triggered, the whole 10-bit data is pushed into the memory, and the buffer and the counter are emptied. At the same time, the statistical counter accumulates the "written number of pens", and each time a write operation is completed, the value is added by 2, and the current value is 2. If subsequent writing continues, when the accumulation result reaches the preset first threshold 4, the control logic immediately packs 4 data packets into a state register, and synchronously reports to the central processor through interruption or bus writing, and informs the central processor that "4 write memory actions have been completed", so that the CPU can make the next scheduling decision in time.

[0060] In some embodiments, Figure 3 The composition structure of the instruction scheduling circuit provided in the embodiments of the present application is shown in Figure Three As shown in Figure 3 , the instruction scheduling circuit 10 can further include a register 105.

[0061] The register 105 is configured to receive the configuration instruction of the central processor, and forward the configuration instruction to the data buffer 103 and the statistical counter 104, so as to configure the space size and the starting write address of the memory and the first threshold of the statistical counter 104.

[0062] It should be noted that the configuration instruction of the central processor is used to configure the space size and the starting write address of the memory and the first threshold of the statistical counter. For example, after the register receives the configuration instruction of the central processor, the register forwards the configuration instruction to the data buffer, and the data buffer opens a storage space of a corresponding size for the memory according to the configuration information in the configuration instruction, and sets the starting write address of the data. For another example, after the register receives the configuration instruction of the central processor, the register forwards the configuration instruction to the statistical counter, and sets the first threshold of the statistical counter based on the configuration information in the configuration instruction. The register is a super-speed storage component for temporarily storing instructions, data and addresses, which is composed of flip-flops or latches, and each flip-flop stores 1-bit binary code.

[0063] In the embodiment of the present application, the register 105 can receive the configuration instruction of the central processor and forward the configuration instruction to the data buffer 103 and the statistical counter 104, and the register 105 is used as a bridge between the central processor (CPU) and the data buffer 103 and the statistical counter 104, and the configuration instruction of the CPU is uniformly received, so that resource competition caused by direct access of multiple components to the CPU can be avoided.

[0064] For example, after the register receives the configuration instruction sent by the central processor, the configuration instruction is forwarded to the data buffer and the statistical counter, the data buffer opens a storage space with a specified size for the memory according to the configuration information of the configuration instruction, and sets the initial write address of the write pointer according to the configuration information of the configuration instruction, and the statistical counter sets the first threshold value of the statistical counter according to the configuration information of the configuration instruction.

[0065] Here, the register obtains the configuration information of the three fields of "space size", "start address" and "first threshold value" after receiving the configuration instruction, and then broadcasts the complete parameter package to the data buffer and the statistical counter through the internal control bus; after the data buffer parses the parameter package, it first applies for a continuous storage area with a specified space size in the memory mapping, initializes the write pointer to the start address given by the configuration, and stores the start address in the register to provide a basis for subsequent rollback judgment; the statistical counter extracts the first threshold value in the same parameter package, and configures the count threshold value (i.e. the first threshold value) of the statistical counter according to the first threshold value.

[0066] In some embodiments, Figure 4 The composition structure of the instruction scheduling circuit provided in the embodiment of the present application is shown in Figure Four As shown in Figure 4 , the instruction scheduling circuit 10 can further include a transmission logic unit 106.

[0067] The transmission logic unit 106 is configured to receive the instruction sent by the thread instruction queue, add a thread identifier to the instruction, and send the instruction with the added thread identifier to the engine corresponding to the instruction.

[0068] It should be noted that the thread identifier added to the instruction can use a label, such as marking the instruction position by an identifier ending with a colon, or adding an identifier and a colon at the beginning of a code line; or use a variable or function name as an identifier, such as indirectly identifying an instruction block by naming a variable or function, or using a local variable or global variable to associate an operation flow; or use a pseudo-instruction or macro definition, such as defining a data label by a pseudo-instruction, or creating a macro identifier with parameters to identify operation logic by #define; or use a comment to assist identification, such as annotating in front of an instruction; or use a structured programming element, such as implicitly identifying a code block by if, while, etc. structure. The specific implementation can be determined according to the actual situation, which is not limited here.

[0069] In the embodiment of the application, the sending logic unit 106 can receive the instruction sent by the thread queue, add a thread identifier to the instruction, and send the instruction with the added thread identifier to the engine corresponding to the instruction. By adding a thread identifier to the instruction, the thread belonging of the instruction can be determined, and the identification conflict in the multi-thread environment can be avoided.

[0070] As an example, it is assumed that thread 1 in the thread instruction queue issues an instruction After receiving the instruction , the sending logic unit adds the identification information of thread 1 to the instruction , obtains the instruction with the added thread identifier , and sends the instruction with the added thread identifier to the engine (such as engine 1) corresponding to the instruction. Here, thread 1 first pushes the instruction into the thread instruction queue, and the sending logic unit reads the instruction immediately after detecting that the queue is not empty. At the same time, the unique ID field of thread 1 is added to the head of the instruction, forming a new instruction carrying a thread identifier . Then, according to the engine selection field in , the entire package is forwarded to the input buffer of engine 1, the binding of the thread identity and the operation instruction is completed, and the engine can accurately identify when returning the state subsequently.

[0071] In some embodiments, Figure 5 the composition structure of the instruction scheduling circuit provided in the embodiment of the application is shown in Figure Five . As shown in Figure 5 , the instruction scheduling circuit 10 can further include a visualization unit 107.

[0072] The visualization unit 107 is configured to perform performance analysis based on the data packet written into the memory, obtain performance analysis data, and generate a performance analysis graph based on the performance analysis data.

[0073] It should be noted that the performance analysis graph can be a timeline lane graph, a histogram, a waterfall chart, a pie chart, etc., which is not limited here.

[0074] In the embodiment of the present application, the visualization unit can perform performance analysis based on the data packets written into the memory, obtain performance analysis data, and generate a performance analysis graph based on the performance analysis data. According to the analysis of the data written into the memory and the generation of the performance analysis graph, the execution time of each instruction and the calling condition of each engine can be determined, thereby facilitating subsequent performance tuning and power tuning.

[0075] In some embodiments, referring to Figure 6 , Figure 6 is a flowchart of a data processing method provided by the embodiment of the present application, which will be described in combination with the steps shown in Figure 6 .

[0076] In step 201, the collector receives an instruction state signal from an engine.

[0077] Here, the instruction state signal includes a start state signal of an instruction received by the engine and an end state signal of the instruction.

[0078] As an example, assuming that there are four engines 0 to 3, the instruction state signal at a certain time includes a start state signal of an instruction of engine 0 and an end state signal of an instruction of engine 3.

[0079] In some embodiments, the instruction state signal further includes a thread signal to which the instruction belongs.

[0080] As an example, assuming that there are two threads 0 and 1, four engines 0 to 3, the instruction state signal at a certain time includes a start state signal of an instruction of engine 1 in thread 0 and an end state signal of an instruction of engine 2 in thread 1.

[0081] In some embodiments, the collector can be a communication interface such as RS-485, etc.; can also be a sensor module, i.e., synchronously acquiring the state signal transmitted by the engine; can also be a signal conditioning circuit, etc., which is not specifically limited here.

[0082] In some embodiments, before step 201 is performed, the following processing can also be performed: in response to receiving an instruction sent by a thread instruction queue, adding a thread identifier to the instruction; sending the instruction with the added thread identifier to the engine indicated by the instruction, so that the engine generates the instruction state signal. In this way, the thread identifier is attached to the instruction, which can determine the thread to which the instruction belongs and avoid identifier conflicts in a multi-thread environment.

[0083] As an example, assuming that thread 2 in the thread instruction queue sends an instruction , after receiving the instruction , the sending logic unit will add a thread identifier to the instruction Add the identifier information for thread 2, and receive the instruction to add the thread identifier. And then send the instruction with the added thread identifier to the engine corresponding to the instruction (e.g., engine 3). Here, thread 2 first sends the instruction... The instruction is pushed into the thread instruction queue. Once the sending logic unit detects that the queue is not empty, it immediately reads the instruction and appends a unique ID field for thread 2 to the instruction header, forming a new instruction carrying the thread identifier. Subsequently, according to The engine selection field forwards the entire packet to the input buffer of engine 3, completing the binding of thread identity and operation instructions, ensuring that the engine can accurately identify the status when it returns it later.

[0084] In step 202, the first timestamp counter receives the first timestamp signal generated based on the sampling clock counter.

[0085] It should be noted that when a sampling event (such as receiving an instruction status signal) occurs, the hardware interrupt controller captures the current timestamp counter's count value and generates a signal with a timestamp. The sampling clock counter is a key component in digital signal processing and data acquisition systems, used to precisely control the sampling timing of analog signals and count the number of clock pulses.

[0086] In step 203, the data buffer receives a data packet consisting of the instruction status signal, the first timestamp signal, and the second timestamp signal, and writes the data packet into memory.

[0087] Here, the second timestamp signal is generated based on the system clock counter. The system clock counter is a core hardware module in a computer or embedded system used to accurately measure time intervals. It is usually integrated inside the CPU or microcontroller and can provide precise time units through the system clock pulse.

[0088] As an example, the data acquisition device receives command status signals from the engine. The first timestamp signal received by the first timestamp counter is the first timestamp signal generated by the sampling clock counter. The second timestamp signal generated based on the system clock counter is , will command status signal First timestamp signal and the second timestamp signal Composition of data packets for[ , , The data buffer receives data packets. and data packets Write to memory.

[0089] It should be noted that the collector receives the instruction state signal from the engine At the same time, the 700MHz sampling clock counter and the 25MHz system clock counter are triggered respectively, and the count values at this moment are captured as And The three are spliced in a fixed order to form a complete packet S, and then the buffer compresses the entire packet into the FIFO, and when the accumulated bit width reaches the AXI bus width, it is written into the memory at one time, completing a lossless event record with double time stamps.

[0090] In some embodiments, before step 203 is performed, the following processing can also be performed: encoding the instruction state signal to obtain a first encoding. In this way, the instruction state signal is compressed into a binary code using field encoding method, which greatly reduces the storage space compared with direct representation method.

[0091] It should be noted that different encoding methods can be used to represent the instruction state signal, for example, in one-hot encoding, each bit represents the start state or end state of the instruction on each engine; for example, the first three bits represent different engines, and the fourth bit represents the start state or end state of the instruction. Not limited here.

[0092] As an example, taking the one-hot encoding method as an example, assuming that there are four engines 0 to 3, and the instruction state signal at a certain moment includes the start state signal of the instruction of engine 1 and the end state signal of the instruction of engine 2, the instruction state signal can be encoded as 0100, 0010, the first four bits record the start state signal, and the last four bits record the end state signal.

[0093] It should be noted that the high four bits correspond to "engine 0 start, engine 1 start, engine 2 start, engine 3 start" in turn, and the low four bits correspond to "engine 0 end, engine 1 end, engine 2 end, engine 3 end" in turn. When a start or end event occurs on any engine at any time, the corresponding bit position is 1, and the remaining bits are 0; when engine 1 sends a start pulse, the second bit of the high four bits is set to 1, and when engine 2 sends an end pulse, the third bit of the low four bits is set to 1, and finally an 8-bit vector 0100_0010 is formed.

[0094] In some embodiments, the instruction state signal also includes a thread signal to which the instruction belongs.

[0095] As an example, taking one-hot encoding, suppose there are two threads 0 and 1, and four engines 0 to 3. At a certain moment, the instruction status signal includes the start status signal of the instruction of engine 1 of thread 0 and the end status signal of the instruction of engine 2 of thread 1. Then the instruction status signal can be encoded as 0100, 0000, 0000, 0010, with the first eight bits recording the start status signal and the last eight bits recording the end status signal.

[0096] It should be noted that the high eight bits are arranged in the following order: "Thread 0 Engine 0 Start → Thread 0 Engine 1 Start → Thread 0 Engine 2 Start → Thread 0 Engine 3 Start → Thread 1 Engine 0 Start → Thread 1 Engine 1 Start → Thread 1 Engine 2 Start → Thread 1 Engine 3 Start". The low eight bits correspond to the end status events in the same order. When Thread 0 emits a start pulse at Engine 1, the second bit of the high eight bits is set to 1. At the same time, when Thread 1 emits an end pulse at Engine 2, the sixth bit of the low eight bits is set to 1. The remaining 14 bits remain 0, ultimately forming a 16-bit vector 0100_0000_0000_0010.

[0097] In some embodiments, the data buffer receiving the data packet composed of the instruction status signal, the first timestamp signal, and the second timestamp signal in step 203 above can be implemented in the following way: the data buffer receives the data packet composed of the first encoding, the first timestamp signal, and the second timestamp signal. Thus, by associating time information with the instruction status signal, the start and end times of different instructions can be accurately recorded, facilitating subsequent analysis of different instruction data.

[0098] It should be noted that the data packet consisting of the first code, the first timestamp signal, and the second timestamp signal can be implemented in hardware, using a parallel bus to transmit data, and using a custom protocol (such as UART or SPI) to package the instruction status and timestamp into a fixed format frame (e.g., [first code][T1][T2]).

[0099] As an example, the data acquisition device receives command status signals from the engine. Regarding the command status signal Encode to obtain the first code. The first timestamp signal received by the first timestamp counter is the first timestamp signal generated by the sampling clock counter. The second timestamp signal generated based on the system clock counter is , the first code First timestamp signal and the second timestamp signal Composition of data packets for[ , , ]Here, the collector receives the instruction state signal from the engine , and sends it to the one-hot encoding module to generate a fixed-width first encoding , and triggers the 700 MHz sampling clock counter and the 25 MHz system clock counter, respectively, to capture the count values at this moment as and ] respectively. The three are spliced in a fixed order to form a complete packet S, and then the buffer pushes the entire packet into the FIFO. When the accumulated bit width reaches the AXI bus width, it is written into the memory at one time, completing a lossless event record with double time stamps.

[0100] In some embodiments, the writing of the data packet into the memory in step 203 can be achieved by the following method: buffering the received data packet; when the amount of buffered data reaches the bus bit width, or when the last data packet of the instruction state signal is received, all the buffered data packets are written into the memory. In this way, by buffering the data packet, the number of frequent memory accesses can be reduced, and when the data amount reaches the bus bit width or the termination signal is received, batch writing can significantly reduce the bus load and improve the memory writing efficiency.

[0101] It should be noted that the bus bit width refers to the number of binary data bits that can be transmitted simultaneously in a computer system, usually expressed in bits (bit), and the bus bit width determines the amount of data that can be transmitted per clock cycle. The larger the bit width, the larger the amount of data transmitted at a time, and the higher the data transmission efficiency.

[0102] As an example, assuming that each data packet is 5 bits in size and the bus bit width is 10 bits, when it is detected that the amount of data in the data buffer reaches 10 bits, all the data in the data buffer is written into the memory; or when the last data packet of the instruction state signal is received, the amount of data in the current data buffer is only 5 bits, which has not reached 10 bits, but the last instruction state signal has been received, so all the data in the data buffer is written into the memory.

[0103] It should be noted that the data buffer is accumulated by bit, and each 5-bit packet is appended to the end, and the bit width counter is incremented by 5 simultaneously. Once the counter reaches 10, an AXI write transaction is triggered to push the entire 10-bit data into the memory, and the buffer and the counter are emptied, ready for the next round. If the process reaches the end, the scheduler sends the last instruction state signal, at which time there is only one 5-bit packet left in the data buffer, and the counter only shows 5, far from being full. To avoid the packet being stranded, the control logic also initiates a write operation to write the only 5-bit data into the memory, and marks the valid byte, to ensure that the memory side knows the actual valid bit width.

[0104] In some embodiments, after step 203 is performed, the following process can also be performed: when the memory is full, the write address of the memory is rolled back to the start address for continued storage. In this way, when the memory is full, the start address is automatically rolled back, forming a ring buffer structure, which can avoid frequent memory allocation or release operations, thereby reducing dynamic memory management overhead.

[0105] As an example, assume that the memory size is 10MB, the start address is During the process of writing data into the memory, when the memory is full, the rollback operation is triggered, and the start address of the memory is used to continue writing data. Here, the write pointer starts from and is incremented by one byte offset for each piece of data written, and the pointer is detected in real time whether it has crossed the +10MB boundary; when it is detected that the next piece of data to be written will exceed the end address, the control logic immediately sets the rollback flag and resets the write pointer to , and the remaining data is split into two segments, i.e., the last segment fills the top space, and the first segment continues to be written from , achieving seamless circular caching.

[0106] In some embodiments, after step 203 is performed, the following process can also be performed: based on the data packet written into the memory, performance analysis is performed to obtain performance analysis data; and based on the performance analysis data, a performance analysis graph is generated. In this way, the execution time of each instruction and the calling condition of each engine can be determined, thereby facilitating subsequent performance tuning and power tuning.

[0107] In the following, an exemplary application of the embodiments of the present application in an actual application scenario will be described. The exemplary application describes the specific implementation process of the instruction scheduling circuit.

[0108] In an AI chip, the instruction scheduler has a profile function, which is an important tool for performance optimization and resource management. The profile function of the instruction scheduler can track the instruction runtime, idle cycle ratio, and high-energy-consuming operations (such as frequent repeated calls). Accurate data collection and analysis can reveal hardware execution details, which are crucial for resource and performance tuning. However, it is difficult to accurately obtain the runtime of each instruction in the related art.

[0109] Based on this, the present application realizes accurate statistics of the start and end timestamps of each instruction in each thread in the multi-threaded scheduler, and in turn, the runtime of each instruction can be obtained. Moreover, the present application supports writing statistical information directly into memory through an AXI bus, and a performance analysis graph can be drawn by reading the contents in the memory, and in turn, software and hardware tuning can be performed.

[0110] In some embodiments, when the scheduler sends an instruction to an accelerator engine, the thread identification of the thread sending the instruction is passed to the engine, the identification being sent as a thread unique identity along with the instruction, the engine sending a start state signal and the thread signal to which the instruction belongs to the scheduler when the instruction starts executing, the scheduler obtaining the instruction state signal and the thread signal to which the instruction belongs after receiving the signals, generating a set of profile flag data in one-hot mode, and combining the current system timestamp and the sampling timestamp data to form a set of profile data, and writing the profile data into a FIFO, and writing the profile data into a memory when the effective data bit width in the FIFO reaches the AXI bus bit width, to ensure that the data is timely stored in the memory.

[0111] It should be noted that the engine also generates a corresponding end state signal and the thread signal to which the instruction belongs when the instruction ends executing, and the processing manner is similar to the above.

[0112] In some embodiments, the Profile flag data is encoded in one-hot mode, wherein each 1 bit corresponds to the start or end state of a thread on an engine, and a sampling period can support the collection of multiple state signals, for example, there are a total of 2 threads 0 and 1, and four engines 0-3, and at a certain moment, the start of the instruction of thread 0 on engine 1 and the end of the instruction of thread 1 on engine 2 occur at the same time, and the Profile flag data is 0100, 0000, 0000, 0010; that is, 2 bits are set to 1, and the other bits are set to 0.

[0113] It should be noted that the one-hot encoding mode is first expanded according to the thread number, then according to the engine number, and finally according to the “start / end” two levels, to form a long bit vector; each bit position uniquely identifies “a certain thread-a certain engine-a certain state”, so that at any moment, as long as the corresponding event occurs, the bit will be set to 1, and the rest will remain 0. When multiple events occur at the same sampling point, the corresponding bits can be set to 1 at the same time to achieve “single-cycle multi-event” lossless recording; as described above, the start state of thread 0 on engine 1 and the end state of thread 1 on engine 2 are completely concurrent, so only these two bits in the vector are 1, and the rest are 0.

[0114] In some embodiments, the software analyzes the Profile data written into the memory, and draws a performance analysis graph, from which the running start and end times of each instruction can be obtained, and then the frequently called engines and instructions with long execution times can be obtained, and performance tuning and power consumption tuning are performed in turn.

[0115] In some embodiments, referring to Figure 7 , Figure 7 is a structural schematic diagram of an instruction scheduling circuit provided by an embodiment of the present application, asFigure 7 As shown, first, different threads are marked with n-bit thread ids (n = clog2 (number of threads) ) in a special field of an instruction when the instruction is sent to an engine, and the id is sent as a unique identity of the thread with the instruction; then, the engine receives the instruction, and start and end state signals are generated to a scheduler when the instruction starts running and the instruction ends, and the n-bit thread id is sent to the scheduler when the engine sends the instruction state signal, to ensure that the scheduler knows the thread corresponding to the current state; subsequently, the Profile unit of the scheduler receives the state signal and the thread id signal from the engine to generate the Profile flag signal, and the timestamp signal of the sampling clock is generated based on a 700M sampling clock counter, and the timestamp signal of the system clock is generated based on a 25M system clock counter, which are used together to record the accurate timing of the event; after that, when the amount of data in the FIFO reaches the bus bit width, or after the scheduler completes the collection of the last instruction state, an AXI write operation to the memory is triggered once, to ensure that the data is timely transferred to the memory; finally, when the data written to the memory reaches a specified number or fills the memory space opened, an interrupt is generated to the CPU, and the memory is also supported to roll back to the start address for continuous writing after being filled.

[0116] It should be noted that the above interrupt is implemented by a burst statistical counter, and each time data is written to the memory as a burst. Assuming that the memory can store 10 bursts, the threshold value of the burst statistical counter is 2, that is, an interrupt is generated every two bursts, and the transmission information is sent to the CPU for information synchronization; after the CPU records 10 bursts written to the memory, the memory is controlled to roll back to the start address for continuous writing through a register. Here, the register is a module in the instruction scheduler, which is used to control the initialization and setting of the burst statistical counter and the FIFO logic, for example, setting the technical threshold of the burst statistical counter, sending the configuration size of the memory space to the FIFO logic, and setting the start address of the memory in the register, which is used when the memory rolls back.

[0117] In some embodiments, referring to Figure 8 , Figure 8 is a performance analysis diagram provided by the embodiments of the present application, as shown in Figure 8 , the software draws a performance analysis diagram according to the profile data written to the memory, and according to the performance analysis diagram, the frequently called engine and the instruction with too long execution time can be known, and performance tuning and power consumption tuning can be performed in turn.

[0118] The chip provided by the embodiments of the present application can include the instruction scheduling circuit 10 in any of the foregoing embodiments.

[0119] The electronic device provided by the embodiment of the present application includes a processor, wherein the processor includes the instruction scheduling circuit 10 of any one of the foregoing embodiments.

[0120] The computer program product provided by the embodiment of the present application includes a computer program or computer executable instructions stored in a computer readable storage medium. The processor of the electronic device reads the computer executable instructions from the computer readable storage medium, and the processor executes the computer executable instructions, so that the electronic device executes the data processing method provided by the embodiment of the present application.

[0121] The computer readable storage medium provided by the embodiment of the present application stores computer executable instructions or computer programs, and when the computer executable instructions or computer programs are executed by the processor, the processor executes the data processing method provided by the embodiment of the present application.

[0122] In some embodiments, the computer readable storage medium can be a Ferroelectric Random Access Memory (FRAM), a ROM, a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a Compact Disc Read-Only Memory (CD-ROM), etc. The computer readable storage medium can also be various devices including one or any combination of the above storage devices.

[0123] In some embodiments, the computer executable instructions can be in the form of programs, software, software modules, scripts or codes, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including being deployed as independent programs or being deployed as modules, components, subroutines or other units suitable for use in a computing environment.

[0124] By way of example, computer executable instructions can comprise or be identified as being part of an object code format that includes statements written in a compiled or interpreted computer programming language or declarative

[0125] By way of example, the computer executable instructions can be deployed to be executed on one electronic device or on multiple electronic devices that are located at one site or that are distributed over multiple sites and are interconnected through a communication network.

[0126] To sum up, the scheduling circuit provided by the embodiment of the application can receive the instruction state signal from the engine through the collector, can ensure the instant feedback of the instruction execution state, and the collector integrates the start and end state signals of the instruction, can obtain the complete life cycle of the instruction, and is convenient for subsequent management and optimization. Secondly, the time stamp signals generated by the clock counter and the system clock counter are respectively sampled through the time stamp counter, can provide high-precision timing, and can accurately determine the execution time of the instruction in different states. Thirdly, the instruction state signal is received through the data buffer, the time stamp signal and the instruction state signal are combined to form a data packet, a temporary storage space is provided for the data packet, the integrity of the data can be ensured before the data packet is written into the memory, and the risk of data loss and the number of direct accesses to the memory are reduced through the buffered data, so that the overall operation efficiency of the system can be improved.

[0127] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in combination with the embodiments disclosed in the present application can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0128] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described device and circuit can refer to the corresponding process in the foregoing method embodiments, and will not be described here.

[0129] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. For example, the apparatus embodiments described above are merely illustrative, for example, the one-hot encoding for the instruction state signal is merely one implementation manner, and other encoding manners can be used in actual implementation, for example, no encoding. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, apparatuses or units, and can be electrical, mechanical or other forms.

[0130] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0131] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium.

[0132] It should be noted that in the present application, the terms "comprising", "including" or any other variants thereof are intended to cover non-exclusive inclusion, so that the processes, methods, articles or apparatuses including a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or apparatuses. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, method, article or apparatus including the element.

[0133] The serial numbers of the embodiments of the present application described above are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0134] The methods disclosed in several method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments.

[0135] The features disclosed in several product embodiments provided by the present application can be combined arbitrarily without conflict to obtain new product embodiments.

[0136] The features disclosed in several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0137] The above merely provides an example of the present application, but is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, and improvement made within the spirit and scope of the present application shall be included in the protection scope of the present application.

Claims

1. An instruction scheduling circuit, characterized by, The instruction scheduling circuit comprises a collector, a first timestamp counter and a data buffer. The collector is configured to receive an instruction state signal from an engine, wherein the instruction state signal comprises a start state signal and an end state signal of an instruction received by the engine. The first timestamp counter is configured to receive a first timestamp signal generated based on a sampling clock counter. The data buffer is configured to receive a data packet composed of the instruction state signal, the first timestamp signal and a second timestamp signal, and write the data packet into a memory. The second timestamp signal is generated based on a system clock counter.

2. The circuit of claim 1, wherein, The instruction scheduling circuit further comprises a statistical counter. The data buffer is configured to buffer the received data packet, and write all buffered data packets in the data buffer into the memory when the amount of data in the data buffer reaches a bus bit width or a data packet of a last instruction state signal is received. The statistical counter is configured to count a first number of data packets written into the memory by the data buffer, and synchronize the first number of data packets to a central processing unit when the first number reaches a first threshold.

3. The circuit of claim 2, wherein, The instruction scheduling circuit further comprises a register. The register is configured to receive a configuration instruction from the central processing unit, and forward the configuration instruction to the data buffer and the statistical counter to configure a space size and a start write address of the memory and the first threshold of the statistical counter.

4. The circuit of claim 1, wherein, The instruction scheduling circuit further comprises a transmission logic unit. The transmission logic unit is configured to receive an instruction sent by a thread instruction queue, add a thread identifier to the instruction, and send the instruction with the added thread identifier to an engine corresponding to the instruction.

5. The circuit of claim 1, wherein, The instruction scheduling circuit further comprises a visualization unit. The visualization unit is configured to perform performance analysis based on the data packet written into the memory, obtain performance analysis data, and generate a performance analysis graph based on the performance analysis data.

6. A chip, characterized by The chip is deployed with the instruction scheduling circuit of any one of claims 1 to 5.

7. An electronic device, comprising: The processor comprises a chip deployed with the instruction scheduling circuit of any one of claims 1 to 5.

8. A data processing method, characterized by, The method comprises: The collector receives an instruction state signal from an engine, wherein the instruction state signal comprises a start state signal and an end state signal of an instruction received by the engine. The first timestamp counter receives a first timestamp signal generated based on a sampling clock counter. The data buffer receives a data packet composed of the instruction state signal, the first timestamp signal and a second timestamp signal, and writes the data packet into a memory. The second timestamp signal is generated based on a system clock counter.

9. The method of claim 8, wherein, The method further comprises: The instruction state signal is encoded to obtain a first encoding. The data buffer receives a data packet composed of the instruction state signal, the first timestamp signal and a second timestamp signal, and writes the data packet into a memory. The data buffer receives a data packet composed of the first encoding, the first timestamp signal and a second timestamp signal.

10. The method of claim 8, wherein, Before the collector receives the instruction status signal from the engine, the method further comprises: adding a thread identification to the instruction in response to receiving the instruction sent by the thread instruction queue; sending the instruction with the thread identification to the engine indicated by the instruction, so that the engine generates the instruction status signal.

11. The method of claim 8, wherein, The storing the data packet into the memory comprises: buffering the received data packet; when the amount of buffered data reaches the bus bit width, or the data packet receiving the last instruction status signal, writing all the buffered data packets into the memory.

12. The method of claim 8, wherein, The method further comprises: when the memory is full, rolling back the write address of the memory to the start address for continuous storage.

13. The method of claim 8, wherein, After the storing the data packet into the memory, the method further comprises: performing performance analysis based on the data packet written into the memory, to obtain performance analysis data; generating a performance analysis graph based on the performance analysis data.

14. An electronic device, comprising: comprise: a memory for storing computer executable instructions or computer programs; a processor for executing the computer executable instructions or computer programs stored in the memory, to implement the data processing method of any one of claims 8 to 13.

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