Large rotary equipment assembly unbalance optimization method based on GPU parallel acceleration and video memory control technology

Abstract

According to the large rotary equipment assembling unbalance optimization method based on GPU parallel acceleration and the video memory control technology, inherent attributes of a rotor are stored in a CUDA constant memory, a dynamic combination batch scheduling mechanism is adopted, and GPU computing resources can be fully utilized in a high-dimensional optimization space of million-level phase combination; and while the calculation accuracy is ensured, the use pressure of a video memory is remarkably reduced, kernel operation interruption and system crash are effectively avoided, and stable execution of a large-scale parallel calculation task is ensured.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of mechanical assembly, in particular to a large-scale rotary equipment assembly unbalance optimization method based on GPU parallel acceleration and a GPU memory control technology. BACKGROUND

[0002] In the assembly process of an aero-engine multi-stage rotor, due to geometric errors, mass deviations and installation errors between a blade disc and blades, unbalance may be easily generated after assembly, and then the stability and vibration performance of the whole machine rotor system are affected. In order to realize the optimization of the mass distribution after assembly, the optimal combination that minimizes the unbalance of the whole machine needs to be found in all possible assembly phase combinations. However, the unbalance is highly related to the installation phase of each stage of the rotor, and the number of phase combinations increases exponentially with the increase of the number of rotor stages, so the traditional serial calculation method cannot meet the dual requirements of efficiency and stability in engineering applications.

[0003] In addition, the current GPU parallel method often ignores the influence of GPU memory allocation on program running, and resource overflow problems may easily occur in the large combination space scenario. Therefore, an optimization scheme is needed to effectively control the GPU memory usage while improving the calculation efficiency. SUMMARY

[0004] The application aims to solve the aero-engine stacking assembly phase optimization problem with the minimum unbalance as the target, and proposes a large-scale rotary equipment assembly unbalance optimization method based on GPU parallel acceleration and a GPU memory control technology.

[0005] The application is implemented by the following technical solutions, and the application proposes a large-scale rotary equipment assembly unbalance optimization method based on GPU parallel acceleration, and the method specifically comprises the following steps: Step 1: Based on the discrete phase angles of each stage of the rotor, a comprehensive unbalance phase combination space is constructed; at the same time, the GPU memory resources are reasonably managed by adopting a batch calculation strategy according to the required GPU memory capacity of a single combination and the number of overall combinations, so as to ensure that the calculation process is efficient and stable; Step 2: A high-performance CUDA parallel kernel function is designed, GPU parallel processing is used for each phase combination, and the rotation transformation of each stage of the rotor, the recursive transmission of the rigid body transformation matrix and the mapping conversion of the centroid coordinates are completed step by step; Step 3: The calculation results are sorted on the CPU side to obtain the phase combination scheme with the minimum unbalance, and efficient and accurate optimization of the assembly is realized.

[0006] Further, in step one, the phase discrete angle is determined according to the number of rotor mounting holes of each stage, all phase combinations are enumerated, and a complete combination space is formed; the input data includes the number of rotor stages rotor_num, the mass center coordinates centrs of each stage of rotor, the mass Ms and the assembly coordinate transformation matrix trans_mat.

[0007] Further, in step one, the rotor inherent properties unrelated to the combination are uniformly preprocessed and stored in the constant memory of the GPU device, avoiding repeated allocation in each combination; only the data directly related to the combination is retained in the dynamically allocated global memory or page-locked memory, thereby significantly reducing the value of the required video memory Memory_per_combination for each combination calculation; the required video memory for single combination calculation is: Memory_per_combination = rotor_num * sizeof(double) / / theta+ sizeof(double) / / unbalance_all Where theta is the phase of each stage of rotor in the combination, and unbalance_all is the total unbalance of the assembly under the combination.

[0008] Further, in step two, the available GPU memory GPU_memory_available is obtained by calling the CUDA native function cudaMemGetInfo(), and the safe reserved memory threshold reserved_memory is set, the number of parallel combinations in a single batch is calculated: max_comb = (GPU_memory_available - reserved_memory) / Memory_per_combination, and then the total number of combinations zuhe_num is divided into several batches according to max_comb, recorded as iterCount, and the GPU calculation task is submitted in an iterative manner, realizing the dynamic scheduling and stable control of the video memory resources.

[0009] Further, in step two, an occupancy awareness mechanism is introduced to dynamically obtain the optimal configuration of thread blocks according to the GPU model and the resource requirements of the kernel function; the specific method is to call the CUDA optimization interface cudaOccupancyMaxPotentialBlockSize(), input the to-be-executed kernel function and the target device identifier, obtain the optimal thread block size optimalBlockSize and the minimum grid size minGridSize, and construct the execution parameters according to the above: blockSize = optimalBlockSize, gridSize = ceil(max_comb / blockSize).

[0010] Further, in step two, an unbalance amount parallel computing kernel based on CUDA is designed, and for each phase combination input, the kernel first calculates the global combination number idx through the thread index, and performs the out-of-bound judgment to ensure the safety of the calculation; all rotor levels are traversed in turn in each thread, the phase rotation matrix of the current rotor is constructed, and the local centroid coordinates are mapped to the first coordinate system of the assembly; the mapped centroid coordinates are weighted and accumulated to obtain the global centroid offset components Mcen_x and Mcen_y in combination with the corresponding rotor mass; the unbalance amount amplitude is calculated by using the Euclidean norm, and is stored in the device array unbalance_all; all intermediate variables in the kernel function are local variables, which are automatically assigned to thread private registers or local memory to avoid thread conflicts; the rotor mass Ms and the centroid centrs data are stored in the CUDA constant memory to reduce the access delay.

[0011] Further, in step three, for all phase combination unbalance amount result arrays unbalance_all stored in the global memory of the GPU, a hierarchical reduction algorithm is used to realize the efficient positioning of the minimum value and the corresponding index; in the specific implementation process, each thread reads the corresponding data according to the global index, and a plurality of rounds of pairwise comparison and reduction are performed in the thread block by using the shared memory; the data consistency is guaranteed through synchronization, and finally the first thread in the thread block outputs the local minimum unbalance amount and its index of the block; then, the second stage reduction is started, and the local minimum values and indexes of all thread blocks are summarized, and similar reduction operations are continued to be performed until the global minimum unbalance amount and its corresponding combination index are obtained.

[0012] The present application has the beneficial effects that: 1. The present application stores the rotor inherent properties in the CUDA constant memory and adopts a dynamic combination batch scheduling mechanism, which can fully utilize the GPU computing resources in the high-dimensional optimization space of million-level phase combinations, significantly reduce the memory usage pressure while ensuring the calculation accuracy, effectively avoid kernel running interruption and system crash, and ensure the stable execution of large-scale parallel computing tasks.

[0013] 2. The application calculates the fast unbalance of all combinations based on GPU parallel kernel function, and selects the global optimal solution directly in the GPU by combining the device end multi-round reduction strategy, which saves a lot of intermediate transmission and sorting operations between CPU and GPU, shortens the overall optimization calculation time by more than 90% compared with the traditional CPU serial scheme, and meets the assembly demand of fast feedback and real-time adjustment in engineering practice. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 A large-scale rotary equipment assembly unbalance optimization method flow chart based on GPU parallel acceleration is proposed in the application.

[0015] Figure 2 A parallel reduction sorting flow chart based on GPU is proposed in the application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0017] Referring to Figure 1 and Figure 2 , the application proposes a large-scale rotary equipment assembly unbalance optimization method based on GPU parallel acceleration, which is specifically: Step one, based on the phase angles of the discrete rotors at all levels, a comprehensive unbalance phase combination space is constructed; at the same time, combined with the required video memory capacity of single combination and the overall combination quantity, a batch calculation strategy is adopted to reasonably manage the video memory resources, ensuring efficient and stable calculation process; Step two, a high-performance CUDA parallel kernel function is designed, and GPU parallel processing is used for each phase combination to complete the rotation transformation of the rotors at all levels, the recursive transmission of the rigid body transformation matrix and the mapping conversion of the center of mass coordinates; Step three, the calculation results are sorted on the CPU side to obtain the phase combination scheme with the smallest unbalance, realizing efficient and accurate optimization of assembly.

[0018] This method significantly improves the evaluation speed and accuracy of rotor unbalance and center of mass coaxiality in the million-level combination space.

[0019] In step one, the phase discrete angle is determined according to the number of rotor mounting holes of each stage, all phase combinations are enumerated, and a complete combination space is formed; the input data includes the number of rotor stages rotor_num, the mass centroid coordinates centrs of each stage of rotor, the mass Ms and the assembly coordinate transformation matrix trans_mat.

[0020] In step one, in order to reduce the video memory pressure required for each group of phase combination calculation and improve resource reuse rate, the rotor inherent properties unrelated to combination (including the mass Ms, mass centroid centrs of each stage of rotor, and the rigid body transformation matrix trans_mat composed of eccentricity and tilt error) are uniformly preprocessed and stored in the constant memory (__constant__) of the GPU device end, avoiding repeated allocation in each combination; only the data directly related to combination (combination angle thetas and unbalance_all) is retained in the globally allocated memory or page-locked memory, thereby significantly reducing the value of the video memory Memory_per_combination required for each combination calculation, providing resource guarantee for subsequent parallel combination number improvement. The video memory required for single combination calculation, the video memory required for each combination calculation Memory_per_combination is: Memory_per_combination = rotor_num * sizeof(double) / / theta+ sizeof(double) / / unbalance_all Wherein, theta is the phase of each stage of rotor in the combination, and unbalance_all is the total unbalance of the assembly under the combination.

[0021] In step two, after obtaining the upper limit of the variable video memory usage of each combination, in order to avoid video memory allocation failure of CUDA kernel in large-scale combination space, the method described in the application obtains the available GPU memory GPU_memory_available by calling the CUDA native function cudaMemGetInfo(), sets the safe reserved video memory threshold reserved_memory (recommended to be 256MB in the application), calculates the number of parallel combinations in a batch: max_comb = (GPU_memory_available - reserved_memory) / Memory_per_combination, and divides the total number of combinations zuhe_num into several batches according to max_comb, recorded as iterCount, to sequentially submit GPU calculation tasks in an iterative manner, to realize dynamic scheduling and stable control of video memory resources.

[0022] In step two, in order to solve the problem of resource waste or low SM scheduling efficiency caused by fixed configuration of thread block blockSize (such as 256) in traditional CUDA programs, the application introduces an occupancy-aware mechanism to dynamically obtain the optimal configuration of thread block according to the GPU model and the resource requirements of the kernel function; the specific method is to call the CUDA optimization interface cudaOccupancyMaxPotentialBlockSize(), pass in the to-be-executed kernel function and the target device identifier, obtain the optimal thread block size optimalBlockSize and the minimum grid size minGridSize, and construct the execution parameters according to the above: blockSize = optimalBlockSize, gridSize = ceil(max_comb / blockSize). This strategy can maximize the SM usage, and enhance the throughput and running efficiency during large-scale combination parallel computing.

[0023] In step two, an unbalance parallel computing kernel based on CUDA is designed. For each phase combination input, the kernel first calculates the global combination number idx through thread index, and performs boundary judgment to ensure the safety of the calculation. Each thread internally traverses all rotor levels in turn, constructs the phase rotation matrix of the current rotor, and maps the local centroid coordinates to the first coordinate system of the assembly. Combined with the mass of the corresponding rotor, the mapped centroid coordinates are weighted and accumulated to obtain the global centroid offset components Mcen_x and Mcen_y. The unbalance amplitude is calculated using the Euclidean norm, and it is stored in the device array unbalance_all. All intermediate variables in the kernel function are local variables, which are automatically assigned to thread private registers or local memory to avoid thread conflicts. In order to improve access efficiency, the rotor mass Ms and the centroid centrs data are stored in the CUDA constant memory to reduce access delay. This design fully utilizes the parallel computing capability of GPU, and realizes fast and high-precision evaluation of unbalance under the space of millions of phase combinations.

[0024] In step three, for the unbalance result array unbalance_all of all phase combinations stored in the global memory of GPU, a hierarchical reduction algorithm is used to realize efficient positioning of the minimum value and the corresponding index. In the specific implementation process, each thread reads the corresponding data according to the global index, and uses shared memory for multiple rounds of pairwise comparison and reduction within the thread block. Through synchronization, data consistency is ensured, and finally the first thread in the thread block outputs the local minimum unbalance and its index. Then, the second stage of reduction is started, and the local minimum values and indexes of all thread blocks are summarized and continue to be reduced in a similar manner until the global minimum unbalance and its corresponding combination index are obtained.

[0025] Although the present application has been disclosed in its preferred embodiments with reference to the accompanying drawings, it is not intended to limit the present application thereto, and various modifications and alterations can be made thereto by those skilled in the art without departing from the spirit and scope of the present application, and the scope of protection of the present application should be defined only by the appended claims.

Claims

1. A method for large-scale slewing equipment assembly imbalance optimization based on GPU parallel acceleration, characterized in that, The method is specifically as follows: Step 1: Based on the discrete phase angles of each rotor stage, construct a comprehensive unbalanced phase combination space; at the same time, combining the memory capacity required for a single combination with the overall number of combinations, adopt a batch calculation strategy to rationally manage memory resources and ensure efficient and stable calculation process. Step 2: Design a high-performance CUDA parallel kernel function to use the GPU to process each phase combination in parallel, and complete the rotational transformation of each rotor, the recursive transfer of the rigid body transformation matrix, and the mapping transformation of the centroid coordinates step by step. Step 3: Sort the calculation results on the CPU to obtain the phase combination scheme with the smallest imbalance, thereby achieving efficient and accurate optimization of the assembly.

2. The method of claim 1, wherein, In step one, the phase discrete angle is determined according to the number of mounting holes of each rotor stage, and all phase combinations are enumerated to form a complete combination space. The input data includes the rotor stage number rotor_num, the centroid coordinates centrs of each rotor stage, the mass Ms, and the assembly coordinate transformation matrix trans_mat.

3. The method of claim 2, wherein, In step one, rotor-specific properties unrelated to the combination are preprocessed and stored in constant memory on the GPU device to avoid redundant allocation in each combination. Only data directly related to the combination is retained in dynamically allocated global memory or page-locked memory, thereby significantly reducing the memory required for each combination calculation. The memory required for a single combination calculation, Memory_per_combination, is as follows: Memory_per_combination = rotor_num * sizeof(double) / / theta+ sizeof(double) / / unbalance_all Where theta represents the phase of each stage of the rotor in this combination, and unbalance_all represents the total unbalance of the assembly under this combination.

4. The method of claim 3, wherein, In step two, the available GPU memory GPU_memory_available is obtained by calling the native CUDA function cudaMemGetInfo(), and the reserved memory threshold reserved_memory is set. The number of parallel combinations in a single batch is calculated: max_comb = (GPU_memory_available - reserved_memory) / Memory_per_combination. The total number of combinations zuhe_num is then divided into several batches according to max_comb, denoted as iterCount. GPU computing tasks are submitted sequentially in an iterative manner to achieve dynamic scheduling and stable control of memory resources.

5. The method of claim 4, wherein, In step two, the occupancy-aware mechanism is introduced to dynamically obtain the optimal configuration of thread blocks according to the GPU model and the resource requirements of the kernel function. The specific method is to call the CUDA optimization interface cudaOccupancyMaxPotentialBlockSize(), pass in the to-be-executed kernel function and the target device identifier, obtain the optimal thread block size optimalBlockSize and the minimum grid size minGridSize, and construct the execution parameters according to the above: blockSize = optimalBlockSize, gridSize = ceil(max_comb / blockSize).

6. The method of claim 5, wherein, In step two, the CUDA-based unbalance amount parallel computing kernel is designed. For each phase combination input, the kernel first calculates the global combination number idx through the thread index and performs boundary judgment to ensure the safety of the calculation. Each thread internally iterates through all rotor levels in turn, constructs the phase rotation matrix of the current rotor, and maps the local centroid coordinates to the first coordinate system of the assembly. Combined with the corresponding rotor mass, the mapped centroid coordinates are weighted and accumulated to obtain the global centroid offset components Mcen_x and Mcen_y. The amplitude of the unbalance amount is calculated using the Euclidean norm, and it is stored in the device-side array unbalance_all. All intermediate variables in the kernel are local variables, which are automatically assigned to thread private registers or local memory to avoid thread conflicts. The rotor mass Ms and the centroid centrs data are stored in the CUDA constant memory to reduce access delay.

7. The method of claim 6, wherein, In step three, for the unbalance amount result array unbalance_all stored in the global memory of the GPU, a hierarchical reduction algorithm is used to efficiently locate the minimum value and the corresponding index. In the specific implementation process, each thread reads the corresponding data according to the global index, and uses shared memory for multiple rounds of pairwise comparison and reduction within the thread block. The data consistency is guaranteed through synchronization, and finally the first thread in the thread block outputs the local minimum unbalance amount and its index. Subsequently, the second stage reduction is started to collect the local minimum values and indexes of all thread blocks, and similar reduction operations are continued until the global minimum unbalance amount and its corresponding combination index are obtained.

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