Processor fault identification method and device, electronic equipment and readable storage medium

Abstract

The invention provides a processor fault identification method and device, electronic equipment and a readable storage medium, and relates to the technical field of processors, and the method comprises the steps: obtaining state change information of a processor, and a first preset operation corresponding to the state change information; the state change information is used for representing that the processor enters an abnormal state or quits the abnormal state; performing a first preset operation on the first count value in the preset flag bit to obtain a second count value; performing a second preset operation on the second count value to obtain a second operation result; wherein the second preset operation comprises at least one of comparison of a pre-designed numerical value and the second count value, comparison of a preset duration and a first duration; the first duration is the duration, obtained according to the second count value, of the processor in the abnormal state; and obtaining a fault identification result of the processor according to the second operation result. Based on the method provided by the invention, the processor fault can be identified timely and accurately.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processors, and in particular to a processor fault identification method and device, an electronic device, and a readable storage medium. BACKGROUND

[0002] In a processor system, an exception response mechanism can interrupt a program currently executed by the processor under certain conditions, and make the processor enter an exception service program.

[0003] During the design and verification phase of the processor, the processor can be simulated by a field programmable gate array (FPGA), and the processor can be fault identified in the simulation phase to locate faults and optimize performance of the processor according to the fault identification result.

[0004] However, in the related art, the processor is usually fault identified by processor-related data recorded by software logs, which can cause the fault identification to be not timely, and thus affect fault location. SUMMARY

[0005] Embodiments of the present application provide a processor fault identification method and device, an electronic device, and a readable storage medium to solve the problem that processor faults cannot be timely and accurately identified in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a processor fault identification method, including: obtaining state change information of a processor and a first preset operation corresponding to the state change information; the state change information is used to represent that the processor enters an abnormal state or exits the abnormal state; performing the first preset operation on a first count value in a preset flag bit to obtain a second count value; the first preset operation includes increasing or decreasing the first count value; performing a second preset operation on the second count value to obtain a second operation result; obtaining a fault identification result of the processor according to the second operation result; the fault identification result includes that the processor is in a fault state or a normal running state; wherein the second preset operation includes at least one of comparing a preset count value with the second count value, and comparing a preset time length with a first time length; the first time length is a time length of the processor in the abnormal state obtained according to the second count value.

[0007] In a second aspect, an embodiment of the present application provides a processor fault identification device, the device comprising: a first obtaining module configured to obtain state change information of a processor and a first preset operation corresponding to the state change information; the state change information is used to represent that the processor enters an abnormal state or exits the abnormal state; a second obtaining module configured to perform the first preset operation on a first count value in a preset flag bit to obtain a second count value; the first preset operation comprises an increasing or decreasing operation on the first count value; a third obtaining module configured to perform a second preset operation on the second count value to obtain a second operation result; the second preset operation comprises at least one of comparing a preset count value with the second count value, comparing a preset time length with a first time length; the first time length is a time length of the processor in the abnormal state obtained according to the second count value; and a fourth obtaining module configured to obtain a fault identification result of the processor according to the second operation result; the fault identification result comprises that the processor is in a fault state or a normal operation state.

[0008] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a processor; a memory configured to store instructions executable by the processor; and wherein the processor is configured to execute the instructions to implement the method of the first aspect.

[0009] In a fourth aspect, an embodiment of the present application further provides a computer readable storage medium, when instructions in the computer readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method of the first aspect.

[0010] In the embodiment of the present application, the first preset operation corresponding to the state change information of the processor is determined; the first preset operation is performed on the first count value in the preset flag bit to obtain a second count value; the first preset operation includes increasing or decreasing the first count value; the second count value can reflect whether the processor is in an abnormal state and the nesting number of the abnormal state. The second preset operation is performed on the second count value to obtain a second operation result, and the second preset operation includes at least one of the following: comparing the preset count value with the second count value; according to the second count value, a first duration of the processor in the abnormal state is obtained, and the preset duration is compared with the first duration; according to the second operation result, a fault identification result of the processor is obtained. The second operation result obtained based on the embodiment can include: a count value comparison result of the preset count value and the second count value, and / or a duration comparison result of the first duration of the processor in the abnormal state and the preset duration. The count value comparison result can reflect whether the nesting number of the abnormal state is relatively large, and the duration comparison result can reflect whether the duration of the processor in the abnormal state is relatively long. According to the count value comparison result and / or the duration comparison result, the fault identification result of the processor is obtained, which is equivalent to obtaining the fault identification result of the processor according to the judgment result of whether the nesting number of the abnormal state is relatively large and / or whether the duration of the processor in the abnormal state is relatively long. Therefore, the fault identification result obtained has high accuracy. Because the method does not need to be implemented based on the log data of the processor, the fault identification result of the processor can be obtained in time and accurately according to the state change information of the processor, thereby solving the problem that the processor fault identification result cannot be obtained in time in the related art.

[0011] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creating labor.

[0013] Figure 1 is a schematic diagram of an application scene of a processor fault identification method provided by the embodiment of the present application; Figure 2 is a step flowchart of a processor fault identification method provided by the embodiment of the present application; Figure 3is a step flow chart of another processor fault identification method provided by an embodiment of the present application. Figure 4 is a block diagram of a processor fault identification device provided by an embodiment of the present application. Figure 5 is a block diagram of an electronic device provided by an embodiment of the present application. Figure 6 is a block diagram of another electronic device according to another embodiment of the present application. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0015] The terms "first", "second", and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually a category and do not limit the number of objects, for example, the first object can be one or more. In addition, the term "and / or" is used to describe the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0016] Figure 1 is a schematic diagram of an application scenario of a processor fault identification method provided by an embodiment of the present application, referring to Figure 1 , the application scenario at least includes an exception nesting layer number counter 10 and an exception state duration timer 20.

[0017] The count value of the preset flag bit is recorded by the exception nesting layer number counter 10, and the duration of the count value of the preset flag bit is obtained by the exception state duration timer 20. According to the count value, and / or the duration of the count value, the fault identification result of the processor is judged.

[0018] In a processor system, an exception response mechanism is used to respond to external devices or internal events, which can interrupt the execution of a current program under certain conditions and switch to an exception service program for processing. In the design and verification phase of the processor, especially on the FPGA-based simulation platform, fault diagnosis and positioning of the processor are very important.

[0019] In the related art, the data of the registers of the processor is usually obtained through software logs, and whether the processor is in a fault state is determined according to the data of the registers, but this method has the problem of not identifying the fault state of the processor in time.

[0020] To solve the problems in the related art, the embodiments of the present application provide a processor fault identification method, which comprises: determining a first preset operation corresponding to state change information of a processor; the state change information is used to represent that the processor enters an exception state or exits the exception state; performing a first preset operation on a first count value in a preset flag bit to obtain a second count value; the first preset operation comprises an increasing or decreasing operation on the first count value; performing a second preset operation on the second count value to obtain a second operation result; the second preset operation comprises at least one of the following: comparing a preset count value with the second count value; according to the second count value, obtaining a first duration for which the processor is in the exception state, and comparing a preset duration with the first duration; according to the second operation result, obtaining a fault identification result of the processor; the fault identification result comprises: the processor is in a fault state or a normal running state.

[0021] The processor fault identification method provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Figure 2 is a step flow chart of a processor fault identification method provided by the embodiments of the present application, as Figure 2 shown, the method can comprise: Step 101, obtaining state change information of a processor and a first preset operation corresponding to the state change information.

[0023] The state change information is used to represent that the processor enters an exception state or exits the exception state.

[0024] For example, the exception state can include a synchronous exception or a synchronous exception. For example, the exception state includes an asynchronous exception, specifically including: a network card sends a message to the processor, the processor interrupts the current processing task and receives the message.

[0025] Step 102, performing a first preset operation on a first count value in a preset flag bit to obtain a second count value.

[0026] The first preset operation comprises an increasing or decreasing operation on the first count value.

[0027] For example, if the state change information indicates that the processor enters an abnormal state, the first preset operation includes increasing the first count value; if the state change information indicates that the processor exits the abnormal state, the first preset operation includes decreasing the first count value. The first count value can represent the number of nested abnormal states.

[0028] At step 103, a second preset operation is performed on the second count value to obtain a second operation result.

[0029] The second preset operation includes at least one of comparing a preset count value with the second count value and comparing a preset time length with the first time length. The first time length is a time length of the processor being in the abnormal state, which is obtained according to the second count value.

[0030] If the second preset operation includes comparing the preset count value with the second count value, the second operation result includes a count value comparison result between the preset count value and the second count value.

[0031] If the second preset operation includes obtaining the first time length of the processor being in the abnormal state according to the second count value and comparing the preset time length with the first time length, the second operation result includes a time length comparison result between the preset time length and the first time length.

[0032] At step 104, a fault recognition result of the processor is obtained according to the second operation result.

[0033] The fault recognition result includes that the processor is in a fault state or a normal operation state.

[0034] For example, if the second count value is greater than or equal to the preset count value, it is determined that the fault recognition result of the processor is that the processor is in the fault state; otherwise, it is determined that the fault recognition result of the processor is that the processor is in the normal operation state.

[0035] For example, if the first time length is greater than or equal to the preset time length, it is determined that the fault recognition result of the processor is that the processor is in the fault state; otherwise, it is determined that the fault recognition result of the processor is that the processor is in the normal operation state.

[0036] In the embodiment of the present application, the first preset operation corresponding to the state change information of the processor is determined, the first preset operation is performed on the first count value in the preset flag bit to obtain a second count value, the first preset operation includes increasing or decreasing the first count value, and the second count value can reflect whether the processor is in an abnormal state and the nesting number of the abnormal state. The second preset operation is performed on the second count value to obtain a second operation result, the second preset operation includes at least one of comparing a preset count value with the second count value and comparing a preset time length with a first time length, the first time length is a time length during which the processor is in the abnormal state and is obtained according to the second count value, and a fault identification result of the processor is obtained according to the second operation result. The second operation result obtained based on the embodiment can include a count value comparison result of the preset count value and the second count value and / or a time length comparison result of the first time length during which the processor is in the abnormal state and the preset time length. The count value comparison result can reflect whether the nesting number of the abnormal state is relatively large, and the time length comparison result can reflect whether the time length during which the processor is in the abnormal state is relatively long. The fault identification result of the processor is obtained according to the count value comparison result and / or the time length comparison result, which is equivalent to obtaining the fault identification result of the processor according to the judgment result of whether the nesting number of the abnormal state is relatively large and / or whether the time length during which the processor is in the abnormal state is relatively long, so that the fault identification result obtained has high accuracy. Because the method does not need to be implemented based on the log data of the processor, the fault identification result of the processor can be obtained in time and accurately according to the state change information of the processor, and the problem that the fault identification result of the processor cannot be obtained in time in the related art is solved.

[0037] Figure 3 is a specific step flowchart of a processor fault identification method provided by the embodiment of the present application, as shown in the figure, the method can include: Figure 3 Step 201, state change information of a processor is obtained, and a first preset operation corresponding to the state change information is obtained.

[0038] The state change information is used to represent that the processor enters an abnormal state or exits the abnormal state, and the first preset operation includes increasing or decreasing the first count value.

[0039] Step 202, if the state change information represents that the processor enters the abnormal state, the first count value and a preset count value are summed to obtain a second count value.

[0040] The preset count value can be set according to requirements, for example, the preset count value can be set as 1 or other values.

[0041] ​For example, the abnormal state is an interrupt exception, and the abnormal state of the processor is the interrupt exception when the network card sends a message to the processor. Before the processor enters the interrupt exception, the value of the preset flag bit is 0. After the processor enters the interrupt exception, the first count value and the preset value are summed to obtain a second count value of 1.

[0042] In step 203, if the state change information indicates that the processor exits the abnormal state, the first count value and the preset value are subtracted to obtain a second count value.

[0043] For example, the first count value of the preset flag bit is 1 when the processor is in the interrupt exception state. When the processor exits the interrupt exception, the first count value 1 and the preset value are subtracted to obtain a second count value of 0.

[0044] If the state change information indicates that the processor enters the abnormal state, the first count value and the preset value are summed to obtain a second count value. If the state change information indicates that the processor exits the abnormal state, the first count value and the preset value are subtracted to obtain a second count value. The first count value refers to the current count value of the preset flag bit, and the second count value is the count value of the preset flag bit after the current state change information of the processor is processed.

[0045] For example, the first count value of the preset flag bit is 0, and the processor enters the interrupt exception. The first count value 0 and the preset value 1 are summed to obtain a second count value corresponding to the current abnormal state information (interrupt exception) of the processor, which is 1. The second count value can represent the number of abnormal nesting layers of the abnormal state of the processor. For example, in this embodiment, the second count value is 1, which represents that the number of abnormal nesting layers of the abnormal state of the processor is 1, and the abnormal state of this layer is the interrupt exception.

[0046] After the processor enters the interrupt exception, the first count value of the preset flag bit is 1. If the processor does not exit the interrupt exception and enters an instruction exception (for example, an exception caused by a divisor of 0 in a division instruction), the first count value 1 and the preset value 1 are summed to obtain a second count value corresponding to the current abnormal state information (instruction exception) of the processor, which is 2. The second count value can represent the number of abnormal nesting layers of the abnormal state of the processor. For example, in this embodiment, the second count value is 2, which represents that the number of abnormal nesting layers of the abnormal state of the processor is 2, and the first layer of the abnormal state is the interrupt exception and the second layer of the abnormal state is the instruction exception.

[0047] The first value of the preset flag bit is 2 when the processor enters the instruction exception. If the processor exits the instruction exception, the first count value 2 and the preset count value 1 are subtracted to obtain a second count value 1 corresponding to the current exception state information (in the interrupt exception) of the processor. At this time, the number of exception nesting layers is 1, and the processor is in the interrupt exception state.

[0048] The processor is in the interrupt exception state when the processor exits the instruction exception. The first value of the preset flag bit is 1. If the processor exits the interrupt exception, the first count value 1 and the preset count value 1 are subtracted to obtain a second count value 0 corresponding to the current exception state information (not in the exception state) of the processor.

[0049] In this embodiment, if the state change information indicates that the processor enters the exception state, the first count value and the preset count value are summed to obtain the second count value. If the state change information indicates that the processor exits the exception state, the first count value and the preset count value are subtracted to obtain the second count value. Thus, as the number of exception nesting layers increases, the second count value increases accordingly. As the number of exception nesting layers decreases, the second count value decreases accordingly. The second count value can accurately reflect the number of exception nesting layers of the processor in the exception state.

[0050] In step 204, a second preset operation is performed on the second count value to obtain a second operation result.

[0051] The second preset operation includes at least one of comparing the preset count value with the second count value and comparing the preset time length with the first time length. The first time length is the time length during which the processor is in the exception state, which is obtained according to the second count value.

[0052] For example, the first time length in step 204 can be obtained according to the following substep: Substep A1: Obtain the first time at which the count value in the preset flag bit is updated from the first count value to the second count value, and the second time at which the count value is restored from the second count value to the first count value.

[0053] The first count value is less than the second count value.

[0054] For example, the first count value is 0. If it is identified that the processor enters the interrupt exception (for example, an interrupt exception caused by a network card sending a message to the processor), the first count value is incremented by 1 to obtain the second count value 1. The time at which the count value of the preset flag bit is updated from 0 to 1 is the first time at which the first count value is updated to the second count value. In the case where the interrupt exception has not been exited, the processor enters the instruction processing exception (for example, the instruction is a division instruction, and the divisor is 0). The second count value is incremented by 1 to obtain the count value 2.

[0055] Further, when the processor exits the instruction processing exception, the count value 2 is decremented by 1 to obtain a second count value 1; when the processor exits the interrupt exception, the count value 1 is decremented by 1 to obtain a first count value 0; the moment when the count value changes from 1 to 0 is the second moment when the second count value recovers to the first count value.

[0056] Sub-step A2: obtaining a time difference value between the first moment and the second moment, and determining the time difference value as a first duration of the processor in the abnormal state.

[0057] In the embodiment, the first moment when the count value of the preset flag changes from the first count value to the second count value, and the second moment when the count value of the preset flag recovers from the second count value to the first count value are obtained; the first count value is less than the second count value; a time difference value between the first moment and the second moment is obtained, which can accurately represent the first duration of the processor in the abnormal state, and the first duration can accurately represent the duration of the processor in the abnormal state.

[0058] Step 205: if the second count value is greater than or equal to the preset count value, determining that the fault recognition result is that the processor is in a fault state.

[0059] The second count value can represent the number of abnormal nesting layers of the processor in the abnormal state. For example, the default count value of the preset flag is 0, if the processor first enters an interrupt exception, and then enters an instruction exception without exiting the interrupt exception, and the preset count value is 1; according to the method of the foregoing embodiment, the second count value is 2, and according to the second count value, the number of abnormal nesting layers of the processor is 2, the first abnormality is the interrupt exception, and the second abnormality is the instruction exception.

[0060] The second count value being greater than or equal to the preset count value indicates that the number of abnormal nesting layers of the abnormal state is relatively large, and in this case, the fault recognition result is determined to be that the processor is in a fault state.

[0061] Step 206: if the second count value is less than the preset count value, determining that the fault recognition result is that the processor is in a normal operation state.

[0062] According to the foregoing analysis, the second count value can represent the number of abnormal nesting layers of the processor in the abnormal state; the second count value being less than the preset count value indicates that the number of abnormal nesting layers of the abnormal state is relatively small, and in this case, the fault recognition result is determined to be that the processor is in a normal operation state.

[0063] In the embodiment, the second count value can reflect the number of nested levels of the abnormal state. If the second count value is greater than or equal to the preset count value, it indicates that the number of nested levels of the abnormal state of the processor is relatively large, and thus the fault identification result is determined as that the processor is in a fault state. If the second count value is less than the preset count value, it indicates that the number of nested levels of the abnormal state of the processor is relatively small, and thus the fault identification result is determined as that the processor is in a normal operation state.

[0064] In step 207, if the first time length is greater than or equal to the preset time length, the fault identification result is determined as that the processor is in a fault state.

[0065] The first time length is the time length during which the processor is in an abnormal state. If the first time length is greater than the preset time length, it indicates that the time length during which the processor is in an abnormal state is relatively long.

[0066] For example, the time point at which the processor enters an interrupt exception is the first time point. After entering the interrupt exception, the processor first enters an instruction exception, then exits the instruction exception, and then exits the interrupt exception. The time point at which the processor exits the interrupt exception from the instruction exception is the second time point. The time difference between the first time point and the second time point is the time length during which the processor is in an abnormal state.

[0067] In step 208, if the first time length is less than the preset time length, the fault identification result is determined as that the processor is in a normal operation state.

[0068] If the first time length is less than the preset time length, it indicates that the time length during which the processor is in an abnormal state is relatively short. This kind of abnormality can be an exception such as processing an interrupt instruction, which is not an abnormality caused by a fault of the processor.

[0069] In the embodiment, if the first time length is greater than or equal to the preset time length, the fault identification result is determined as that the processor is in a fault state. If the first time length is less than the preset time length, the fault identification result is determined as that the processor is in a normal operation state. Based on the comparison result of the first time length and the preset time length, it can be accurately determined whether the processor is in a fault state or a normal operation state.

[0070] For example, in the case where the preset time length includes a first preset time length and a second preset time length, after step 206, the method can further include the following steps: In step 209, if the second operation result includes that the first time length is greater than the first preset time length and less than the second preset time length, a processor fault alarm is performed.

[0071] In step 210, if the second operation result includes that the first time length is greater than or equal to the second preset time length, fault data of the processor is acquired and saved.

[0072] The processor is a processor core in a multi-core processor. A memory segment corresponding to the processor core can be allocated to the processor core. If it is identified that the first time length is greater than or equal to the second preset time length, it is determined that the processor core is faulty. Fault data is obtained from a register of the faulty processor core and stored in the memory segment allocated to the faulty processor core. Then, a fault number is sent to other processor cores in a normal running state, so that the processor cores in the normal running state obtain the fault data from the memory segment of the faulty processor core. In this way, the problem that the register is private to the processor core and the fault data cannot be directly obtained from the register of the processor core when the processor core is faulty can be avoided.

[0073] The abnormal execution time threshold in the related art is fixed and lacks adaptability. Timeout detection is usually performed based on a fixed time length threshold, which is difficult to adapt to differences in execution time requirements of different abnormal service programs and is prone to false positives or false negatives. In the embodiment, different operations are performed on the first time length and the comparison result of different preset time lengths, respectively, to achieve fine processing of processor faults.

[0074] The fault data includes at least one of the following: a program counter value of the processor, stack pointer information of the processor, data in a general register of the processor, an exception vector number of the processor, an exception nesting layer number of the exception state, and the first time length. Based on the foregoing fault data, the processor can be accurately located.

[0075] In a processor system, an exception response mechanism can be used to respond to external devices or internal transactions, and can interrupt the execution of a current program and switch to an exception service program for processing under certain conditions. During the design and verification of a processor, especially during the design and verification of a processor based on an FPGA simulation platform, the correctness and stability of the exception mechanism are crucial to the verification of system functions and performance.

[0076] When the exception nesting is too deep and the exception nesting layer number is too large, the processor can be in an exception context for a long time. The monitoring method in the related art lacks hardware-level real-time detection capability for arbitrating the nesting depth, which can cause lag or incompleteness of the debugging information acquisition. For example, the related art can analyze processor faults through logs or read register data through an external debugger to analyze processor faults. However, software logs can not be output or the output content can not be complete in an exception stuck state, and the data read by the external debugger from the register has a delay and is difficult to capture key context information at the moment of exception occurrence, which makes it difficult to reproduce and analyze the problem.

[0077] The method of the related art needs manual intervention and cannot accurately and timely identify processor failure to automatically trigger suspension of the processor, saving of a trace or other debugging actions at the moment when the processor is detected to be abnormally dead-stuck, and the processor abnormality processing method lacks automatic response capability and affects debugging efficiency and verification quality. Moreover, based on the method of the related art, when an abnormal service program falls into a dead loop or executes for too long, the system cannot timely find the problem, which causes the processor to be abnormally dead-stuck and difficult to be located, the method of the related art cannot monitor the abnormal execution time of the processor in real time, cannot identify the number of abnormal nesting layers, and cannot solve the problem of priority conflict.

[0078] According to the above analysis, the abnormal monitoring and debugging method of the related art usually has the following problems: relying on software participation or manual intervention; in a processor abnormal dead-stuck state, the method of the related art is prone to failure and lacks real-time and refinement, and it is difficult to capture the moment of abnormal occurrence; it cannot automatically respond to hardware linkage, and the debugging efficiency is low. Therefore, a method is needed that can monitor the processor abnormal execution state in real time and refinement, and when an abnormal dead-stuck occurs, can automatically trigger the FPGA to perform signal acquisition and saving, so as to improve the identification and positioning efficiency of processor abnormal problems and improve the verification quality.

[0079] The method of the embodiment realizes monitoring of the abnormal execution state of the processor, identification of the failure state, and further processor failure positioning based on processor failure data collected by the FPGA. When the processor enters an abnormal service program, a specific register bit (i.e., the preset flag bit in the foregoing embodiment) is set by hardware logic to identify the abnormal context state, and then combined with timing detection, abnormal nesting depth monitoring, vector level independent monitoring, and failure data saving by the FPGA, real-time detection and automatic response of processor failure are realized.

[0080] The method of the embodiment is further exemplarily described as follows.

[0081] The processor failure detection method of the embodiment can be realized by the following five mechanisms: an abnormal state flag control mechanism, a multi-level timeout detection mechanism, an abnormal nesting monitoring mechanism, an abnormal vector level independent monitoring mechanism, and an FPGA signal saving and positioning mechanism.

[0082] The abnormal state flag control mechanism is used to add one to a first count value of the abnormal state flag bit (i.e., the preset flag bit in the foregoing embodiment) to obtain a second count value in a case where it is identified that the processor is in an abnormal state. Specifically, hardware automatically adds one to the first count value of the abnormal state flag bit at a processor abnormality entry (for example, the first instruction of an abnormality vector entry) through the nesting level counter in a case where it is identified that the processor is in an abnormal state. The count value of the abnormal state flag bit is used to reflect the nesting level of the abnormality.

[0083] The FPGA can directly collect the count value of the nesting level counter and output, analyze the processor abnormality according to the count value of the nesting level counter, and perform processor debugging or alarm triggering according to the analysis result.

[0084] Specifically, a special bit segment can be reserved in a control state register (Control and Status Registers, CSR) as the nesting level counter, or a register is added in the interrupt control logic, and the nesting level of the abnormality is recorded in the register.

[0085] For example, the first count value of the abnormal state flag bit is decremented before the execution of an abnormality return instruction (such as sret of RISC-V), indicating that the abnormal state of this layer has been released.

[0086] Further, the hardware automatically clears the flag bit before the execution of the abnormality return instruction corresponding to the abnormal state of the last layer, indicating that the abnormality processing has ended. That is, the nesting level counter adds one to the first count value representing the nesting level at the interrupt entry when the processor is in an abnormal state, and decrements the first count value representing the nesting level before the execution of the abnormality return instruction. In the process of implementing the foregoing method through the abnormal state flag control mechanism, the software does not need to intervene in the abnormal state flag bit, and the hardware guarantees the accuracy and consistency of the count value in the abnormal state flag bit, thereby providing a reliable real-time monitoring signal for the FPGA.

[0087] Based on the abnormal state flag control mechanism, the hardware can monitor the abnormal execution state in real time, and can automatically set the bit at the abnormality entry and the return instruction, and clear the count value in the abnormal state flag bit when the processor exits all abnormal states, to realize real-time tracking of the abnormal context state of the processor.

[0088] Based on the abnormal state flag control mechanism of the embodiment, the FPGA can directly collect the signal of the abnormal state flag bit without relying on software logs or external debuggers, thereby solving the problem that the processor in an abnormal state cannot be monitored in real time in the related art.

[0089] For example, the first count value of the abnormal state flag bit is 0, when the processor enters the abnormal state, the abnormal state flag bit is automatically set to 1 at the processor abnormal entry by the hardware logic; before the execution of the abnormal return instruction, the count value in the abnormal state flag bit is automatically cleared to 0; the abnormal state flag bit is used to identify the abnormal context state, and the whole process does not need software intervention, ensuring the real-time and consistency of the state; this mechanism can be used for FPGA real-time acquisition of processor abnormal state signals.

[0090] In the multi-level timeout detection mechanism, the count value in the abnormal state flag bit can be recorded in real time by a timer module configured in the processor system, and the holding time of the count value is equivalent to the first time length in the foregoing embodiments. When the holding time is greater than the first preset time threshold and less than the second preset time threshold, a warning is given for the processor abnormality. When the holding time is greater than the second time threshold, it is determined that the processor is abnormal and stuck, and the FPGA is triggered to collect data in the registers of the abnormal processor.

[0091] The embodiment supports multi-level threshold setting. The multi-level threshold includes a first preset time threshold and a second preset time threshold, and the second preset time threshold is greater than the first preset time threshold. The short threshold is used for fast warning, and the long threshold is used for confirming abnormality and triggering FPGA signal acquisition.

[0092] The threshold can be dynamically configured through the register to adapt to the execution time of different abnormal service programs and reduce false positives and false negatives. The FPGA can collect the abnormal holding time of the processor in the abnormal state in real time through the timer output signal to provide a basis for engineers to judge the severity of the abnormality. Based on the method, a multi-level timeout detection mechanism is realized.

[0093] Based on the multi-level timeout detection mechanism, multi-level timeout detection can be realized to improve the accuracy of abnormal detection. When the abnormal processing lasts for more than the threshold, the FPGA signal is automatically generated by the hardware to perform real-time abnormal positioning of the processor. A configurable timer can be built in to time the holding time of the abnormal state and support setting of different time thresholds. Specifically, through the first preset time threshold and the second preset time threshold, short-time timeout and long-time abnormality can be distinguished, and the processor fault can be processed in detail according to the distinguishing result to reduce false positives and false negatives of the processor fault. The problem of poor adaptability of processor fault processing caused by setting a fixed threshold in the related art is solved.

[0094] In the abnormal nesting monitoring mechanism, an abnormal nesting layer number counter is added to record the abnormal nesting layer number of the current processor, the abnormal nesting layer number can be represented by a count value, and the abnormal nesting layer number is used to reflect the nesting depth. When the abnormal nesting layer number exceeds a preset threshold, or the holding time of the same abnormal layer exceeds a corresponding preset time threshold, the hardware generates an abnormal detection event signal and outputs it to the FPGA.

[0095] Based on the abnormal nesting monitoring mechanism, abnormal nesting and priority conflict monitoring can be achieved. An abnormal nesting layer number counter is added, and the abnormal nesting layer number is monitored in real time through the abnormal nesting layer number counter. When the nesting is too deep or the priority conflict causes the abnormal to return for a long time, an FPGA signal is generated for processor fault positioning, solving the problem of difficulty in capturing the abnormal nesting layer number or priority exception in the related art.

[0096] In the independent monitoring mechanism based on the abnormal vector level, independent flag bits and timers can be allocated to each exception type and each exception vector in the exception vector table to achieve precise monitoring at the vector level. For example, when a certain exception service program is stuck, the hardware generates an FPGA signal corresponding to the vector and outputs it. After the FPGA receives the signal, it views the exception execution state and duration in combination with a logical analysis tool or a trace buffer, and quickly locates the exception source. This embodiment can achieve independent monitoring at the exception vector level, solving the problem of inaccurate positioning in the related art in a multi-exception scenario.

[0097] In the FPGA signal saving and positioning mechanism, when an abnormal stall event is confirmed, the hardware outputs the abnormal state data in the form of a signal to the FPGA. The abnormal state data includes at least one of the following: program counter (PC), stack pointer (SP), CSR register value, exception vector number, nesting depth, and timer count value.

[0098] The FPGA automatically collects these signals and saves them to a special buffer or trace storage unit to achieve complete recording of the abnormal scene. Engineers can replay the FPGA waveforms or perform trace analysis to accurately reproduce the processor state and instruction execution before and after the exception occurs to provide data for debugging, thereby implementing the FPGA signal saving and positioning mechanism, and solving the problem of lagging, incomplete, or unreproducible debugging information in the related art.

[0099] When an abnormal stall event is triggered, the hardware automatically outputs key context information (such as PC, SP, CSR, exception vector number, nesting depth, timer count value, etc.) in the form of a signal to the FPGA for saving. Based on this mechanism, the processor state at the moment of abnormal occurrence can be recorded completely on the FPGA, achieving high-precision debugging and on-site analysis of processor faults.

[0100] The abnormal state monitoring, timeout detection and FPGA signal collection process in the embodiment are automatically completed by hardware without software intervention; after the FPGA receives the signal, subsequent analysis can be performed in combination with a trace buffer or a logic analyzer to realize automatic abnormal debugging of processor failure. Through automatic abnormal monitoring and debugging, the hardware can record the abnormal history execution time and dynamically adjust the timeout threshold, thereby realizing adaptive monitoring of different abnormal service programs; by setting different preset time thresholds and according to the comparison result of the different preset time thresholds and the abnormal holding time, corresponding processing is performed, which can reduce false positives and false negatives of processor failure and improve the reliability of abnormal detection.

[0101] In the embodiment, based on the above five mechanisms, real-time monitoring and positioning of processor failure such as abnormal freezing can be realized on the FPGA platform, and the abnormal scene is saved in the FPGA in the form of a signal to facilitate engineers to debug and analyze the processor abnormality.

[0102] The method of the embodiment does not require software intervention or reset operation, and the entire abnormal monitoring and FPGA signal collection process is completely realized by hardware without software participation or manual intervention; the defects of related technologies that rely on manual intervention or reset to locate problems are avoided, and the automation and debugging efficiency are improved. Through automatic setting and clearing of the abnormal state flag bit by hardware and real-time monitoring of the abnormal duration by the timer, the processor abnormal freezing event can be captured at the moment of processor abnormality. The delay problem caused by relying on software logs or external debuggers in related technologies is avoided, and nanosecond-level precision abnormal monitoring is realized.

[0103] Further, the embodiment can accurately identify specific abnormal types, nesting levels and priority conflict situations through vector-level independent monitoring and abnormal nesting level counters. The FPGA signal saving mechanism ensures that the processor state is collected at the first time when the abnormal freezing occurs, provides a reliable basis for engineers to quickly locate the problem, and realizes accurate positioning of the abnormal source. Based on the embodiment, engineers can directly play back the processor behavior information before and after the abnormality occurs through the data collected by the FPGA, trace data or data collected by a logic analyzer, greatly reducing the repeated reproduction and manual analysis time, and improving the debugging efficiency and automation level.

[0104] In the embodiment, the multi-level timeout threshold and vector level monitoring can be configured, so that the system can adapt to the execution time difference of different types of abnormal service procedures, reduce the false positive and false negative rates, and then adapt to different abnormal characteristics. Based on the FPGA signal saving mechanism, the key context at the moment of abnormal occurrence can be recorded, including the program counter, stack pointer, register value, nesting level and timer state. By recording the key context at the moment of abnormal occurrence, the debugging personnel can obtain complete data, which helps to accurately analyze the cause and processing flow of processor exception. By comprehensively recording the abnormal context information, combining hardware monitoring and FPGA signal acquisition, the processor exception can be found in time in the verification stage, and the exception can be located, so as to improve the system function verification efficiency and reliability, and improve the FPGA verification and processor debugging quality.

[0105] In the related art, the CPU register, stack and exception state can be periodically read through a standard processing method (Joint Test Action Group, JTAG) or a serial debugging interface (Serial Wire Debug, SWD) or the like, to determine whether there is an abnormal deadlock. Although this method can obtain the internal state information of the CPU for abnormal analysis, the debugging interface reading has a delay and cannot be continuously monitored at a high frequency; in a multi-exception or nesting scenario, transient exceptions are easily missed, and the method of the related art needs manual intervention or additional software control, and cannot be fully automated.

[0106] In the related art, the processor control signal can also be captured by a logic analyzer. Specifically, the CPU key control signal (such as exception entry, PC change, etc.) is led out to the logic analyzer, and the processor exception state is determined by waveform analysis. However, this method needs to determine the monitoring point in advance, and cannot cover all exception vectors and nesting situations, it is difficult to automatically save complete context at the moment of exception occurrence, and the hardware wiring of this method is complex. Compared with the related art, the present application realizes real-time, fine and automatic abnormal deadlock detection and positioning through hardware flag, timer, multi-level timeout, vector level independent monitoring and FPGA signal saving, so it has the characteristics of high efficiency and reliability in FPGA verification and processor debugging.

[0107] The embodiment can optimize the timeout threshold by an adaptive method, and then detect the processor failure according to the optimized timeout threshold. For example, a multi-level time threshold (such as a first preset time threshold and a second preset time threshold) can be used to analyze and process the processor failure. In an example, a hardware learning module or a statistical unit can be added to automatically record the historical abnormal execution time of the processor, and dynamically adjust the timeout threshold according to the historical abnormal execution time, so as to realize adaptive monitoring and reduce the false positive and false negative rates of the processor failure.

[0108] In an example, more context information can be saved by hardware, such as data of a general register group, data of a memory access track, data of an exception entry instruction sequence, and the like, so as to comprehensively perform processor exception scene reproduction.

[0109] In a high-frequency exception triggering or long-time verification process, the data amount of signals saved by the FPGA can be large, and the storage pressure is large. A signal compression and buffering mechanism can be added at the FPGA end, based on the signal compression and buffering mechanism, only key events or incremental changes are saved, the storage overhead is reduced, the accuracy of exception positioning is ensured, and then FPGA signal compression and storage optimization is realized.

[0110] In the following, taking functional verification of a processor based on an RSIC-V architecture on an FPGA platform as an example, the processor exception detection method of the present application is further exemplarily described: In the application scenario of functional verification of a processor based on an RSIC-V architecture on an FPGA platform, when the processor needs to run multiple peripheral device drivers and operating system tasks, peripheral device exceptions, priority conflicts, or abnormal nesting that fails to return normally can occur.

[0111] If a certain exception service program falls into a dead loop or takes too long to execute, the system will appear to be deadlocked. In the related art, the method of software log or external debugger usually cannot discover the exception in time and locate it. To solve the problem in the related art, an exception execution state monitoring module is added in the FPGA verification logic of the processor core.

[0112] The exception execution state monitoring module is used to implement an exception state flag control mechanism. Specifically, when the processor enters an exception service program entry, the hardware logic automatically sets the exception flag bit in the CSR or a special state register to 1, indicating that the CPU is currently in an exception context state; before the execution of an exception return instruction (such as sret of RISC-V), the hardware automatically clears the flag bit, indicating that the exception processing has been normally completed.

[0113] This mechanism does not need to be intervened by software, and can guarantee the accuracy and real-time performance of the flag state. Even if the exception service program falls into a dead loop, the count value of the flag bit can still be kept at 1. Based on the count value of the flag bit, the FPGA can provide a reliable monitoring signal. The FPGA can directly read the count value of the flag bit through a monitoring register or a special signal bus, and then accurately track the entry and exit of the exception context.

[0114] The abnormal execution state monitoring module is also used to implement a multi-level timeout detection mechanism. Specifically, a configurable timer module is used to count the time during which the abnormal state flag bit is continuously 1. The timer supports multi-level threshold setting. A short timeout threshold (i.e., a first preset time threshold) is used to quickly warn of a processor failure. If the holding time of the abnormal state exceeds the short time threshold, it indicates that the abnormal processing time exceeds the expectation, but the processor is not completely deadlocked. A long timeout threshold (i.e., a second preset time threshold) is used to confirm that the processor is in an abnormal deadlocked state. If the holding time of the abnormal state exceeds the long time threshold, the FPGA is triggered to save the signal operation.

[0115] The abnormal execution state monitoring module is also used to implement an abnormal nesting monitoring mechanism. The abnormal execution state monitoring module is also used to implement independent monitoring at the vector level. Through independent monitoring at the vector level, the problem of ambiguous alarm can be avoided, the accuracy of the fault recognition result is improved, the specific abnormal source can be quickly locked by an engineer, and the positioning efficiency is improved.

[0116] The abnormal execution state monitoring module is also used to implement saving of the FPGA signal and positioning of the processor failure. When it is confirmed that the processor is in an abnormal deadlocked failure state (for example, the flag bit duration exceeds the long threshold or the nesting number is too deep), the hardware outputs the failure data in the form of a signal to the FPGA. The failure data can include a current program counter (PC) value, a stack pointer (SP) and related register value, an exception vector number and a nesting depth, an abnormal state flag and a timer count value, and an FPGA received signal.

[0117] The failure data can be automatically written into a special buffer or a trace storage unit. Thus, an engineer can use a logic analyzer or a trace tool to replay the signal waveform on the FPGA side, and then accurately analyze the instruction flow, the register state and the abnormal context before and after the abnormality occurs. Thus, even if the CPU continues to run or enters a dead loop, the FPGA can still record the abnormal scene completely, and provide related failure data for debugging. The embodiment can realize real-time and fine abnormal deadlocked detection and positioning on the FPGA platform, and save the abnormal state in the form of a signal to the FPGA for subsequent waveform analysis and debugging. Compared with the traditional method of relying on software logs or manual intervention, the embodiment has the advantages of high real-time performance, automation, accurate positioning of the vector level exception, and complete saving of the scene information, and greatly improves the FPGA verification and processor debugging efficiency.

[0118] Reference Figure 4The embodiment of the application provides a processor fault identification device, and the device 30 comprises: a first acquisition module 301, configured to acquire state change information of a processor and a first preset operation corresponding to the state change information; the state change information is used for representing that the processor enters an abnormal state or exits the abnormal state; a second acquisition module 302, configured to perform a first preset operation on a first count value in a preset flag bit to obtain a second count value; the first preset operation comprises increasing or decreasing operation on the first count value; a third acquisition module 303, configured to perform a second preset operation on the second count value to obtain a second operation result; wherein the second preset operation comprises at least one of comparing a preset count value with the second count value and comparing a preset time length with a first time length; the first time length is a time length of the processor in the abnormal state acquired according to the second count value; and a fourth acquisition module 304, configured to acquire a fault identification result of the processor according to the second operation result; the fault identification result comprises that the processor is in a fault state or a normal operation state.

[0119] Optionally, the second acquisition module 302 can comprise: a first acquisition submodule, configured to perform summation processing on the first count value and the preset count value to obtain the second count value if the state change information represents that the processor enters the abnormal state; and a second acquisition submodule, configured to perform difference processing on the first count value and the preset count value to obtain the second count value if the state change information represents that the processor exits the abnormal state.

[0120] Optionally, the third acquisition module 303 can comprise: a third acquisition submodule, configured to acquire a first time point at which the count value in the preset flag bit is updated from the first count value to the second count value and a second time point at which the count value in the preset flag bit is restored from the second count value to the first count value; the first count value is smaller than the second count value; and a fourth acquisition submodule, configured to acquire a time difference value between the first time point and the second time point and determine the time difference value as the first time length of the processor in the abnormal state.

[0121] Optionally, the fourth acquisition module 304 can comprise: a fifth acquisition submodule, configured to determine that the fault identification result is that the processor is in the fault state if the second count value is greater than or equal to the preset count value; and a sixth acquisition submodule, configured to determine that the fault identification result is that the processor is in the normal operation state if the second count value is smaller than the preset count value.

[0122] Optionally, the fourth acquisition module 304 can comprise: a seventh acquisition submodule, configured to determine that the fault identification result is that the processor is in the fault state if the first time length is greater than or equal to the preset time length; and an eighth acquisition submodule, configured to determine that the fault identification result is that the processor is in the normal operation state if the first time length is smaller than the preset time length.

[0123] Optionally, in the case where the preset time length comprises a first preset time length and a second preset time length, the apparatus 30 can further comprise: a fifth obtaining module, configured to, after obtaining the fault identification result of the processor according to the second operation result, if the second operation result comprises that the first time length is greater than the first preset time length and less than the second preset time length, perform processor fault alarm; and a sixth obtaining module, configured to, if the second operation result comprises that the first time length is greater than or equal to the second preset time length, obtain fault data of the processor and save the fault data.

[0124] Optionally, the fault data comprises at least one of: a program counter value of the processor, stack pointer information of the processor, data in a general register of the processor, an exception vector number of the processor, an exception nesting number of the exception state, and the first time length.

[0125] In summary, in the embodiments of the present application, a first preset operation corresponding to the state change information of the processor is determined; a first preset operation is performed on a first count value in a preset flag bit to obtain a second count value; the first preset operation comprises an increasing or decreasing operation on the first count value; the second count value can reflect whether the processor is in an exception state and a nesting number of the exception state. A second preset operation is performed on the second count value to obtain a second operation result, and the second preset operation comprises at least one of: comparing a preset count value with the second count value; obtaining a first time length during which the processor is in the exception state according to the second count value, and comparing a preset time length with the first time length, and obtaining a fault identification result of the processor according to the second operation result. The second operation result obtained based on the embodiments can comprise: a count value comparison result of the preset count value and the second count value, and / or a time length comparison result of the first time length during which the processor is in the exception state and the preset time length. The count value comparison result can reflect whether the nesting number of the exception state is relatively large, and the time length comparison result can reflect whether the time length during which the processor is in the exception state is relatively long. The fault identification result of the processor is obtained according to the count value comparison result and / or the time length comparison result, which is equivalent to obtaining the fault identification result of the processor according to a judgment result of whether the nesting number of the exception state is relatively large and / or whether the time length during which the processor is in the exception state is relatively long, and thus the fault identification result obtained is of high accuracy. Because the method does not need to be implemented based on log data of the processor, the fault identification result of the processor can be obtained in time and accurately according to the state change information of the processor, thereby solving the problem that the fault identification result of the processor cannot be obtained in time in the related art.

[0126] Figure 5 FIG. 5 is a block diagram of an electronic device 500 according to an example embodiment. The electronic device 500 can be, for example, a mobile phone, a computer, a digital broadcasting terminal, a message transmitting / receiving device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like.

[0127] Referring to Figure 5 The electronic device 500 can include one or more of the following components: a processing component 502, a memory 504, a power supply component 506, a multimedia component 508, an audio component 510, an input / output (I / O) interface 512, a sensor component 514, and a communication component 516.

[0128] The processing component 502 usually controls overall operations of the electronic device 500, such as operations associated with displaying, making phone calls, data communications, camera operations and recording operations. The processing component 502 can include one or more processors 520 to execute instructions to complete all or part of steps of the methods described above. In addition, the processing component 502 can include one or more modules to facilitate the interaction between the processing component 502 and other components. For example, the processing component 502 can include a multimedia module to facilitate the interaction between the multimedia component 508 and the processing component 502.

[0129] The memory 504 is used to store various types of data to support operations of the electronic device 500. Examples of these data include instructions for any application or method operating on the electronic device 500, contact data, phonebook data, messages, pictures, multimedia and so on. The memory 504 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0130] The power supply component 506 provides power to various components of the electronic device 500. The power supply component 506 can include a power supply management system, one or more power supplies, and other components associated with generating, managing and distributing power for the electronic device 500.

[0131] The multimedia component 508 includes a screen providing an output interface between the electronic device 500 and a user. In some embodiments, the screen includes a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touch, slide and gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 508 includes a front camera and / or a rear camera. When the electronic device 500 is in an operating mode, such as a camera mode or a multimedia mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front and rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0132] The audio component 510 is configured to output and / or input audio signals. For example, the audio component 510 includes a microphone (MIC) to receive an external audio signal when the electronic device 500 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 504 or transmitted via the communication component 516. In some embodiments, the audio component 510 further includes a speaker to output audio signals.

[0133] The I / O interface 512 provides an interface between the processing component 502 and peripheral interface modules, which can be a keypad, a click wheel, buttons, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0134] The sensor component 514 includes one or more sensors to provide various state assessments for the electronic device 500. For example, the sensor component 514 can detect an open / closed state of the electronic device 500, relative positioning of components, such as a display and a keypad of the electronic device 500, a change in position of the electronic device 500 or a component of the electronic device 500, presence or absence of user contact with the electronic device 500, a direction or acceleration / deceleration of the electronic device 500, and a change in temperature of the electronic device 500. The sensor component 514 can include a proximity sensor configured to detect presence of a nearby object without any physical touch. The sensor component 514 can further include a light sensor, such as a CMOS or CCD image sensor, for use in an imaging application. In some embodiments, the sensor component 514 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0135] The communication component 516 is configured to facilitate wired or wireless communication between the electronic device 500 and other devices. The electronic device 500 can access a wireless network based on a communication standard, such as WiFi, a cellular network (e.g., 2G, 3G, 4G or 5G), or a combination thereof. In an example embodiment, the communication component 516 receives broadcast signals or broadcast-related information from external broadcast management systems via a broadcast channel. In an example embodiment, the communication component 516 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) techniques, infrared data association (IrDA) techniques, ultra-wideband (UWB) techniques, Bluetooth (BT) techniques and other techniques.

[0136] In an example embodiment, the electronic device 500 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic elements, for implementing a processor fault identification method provided by embodiments of the present application.

[0137] In an example embodiment, a non-transitory computer-readable storage medium including instructions, such as the memory 504 including instructions, is also provided, which can be executed by the processor 520 of the electronic device 500 to complete the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk and an optical data storage device, etc.

[0138] Figure 6 is a block diagram of an electronic device 600 according to an example embodiment. For example, the electronic device 600 can be provided as a server. Referring to Figure 6 The electronic device 600 includes a processing component 622, which further includes one or more processors, and a memory resource represented by a memory 632, for storing instructions executable by the processing component 622, such as an application program. The application program stored in the memory 632 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 622 is configured to execute the instructions to perform a processor fault identification method provided by embodiments of the present application.

[0139] The electronic device 600 can also include a power supply component 626 configured to perform power management of the electronic device 600, a wired or wireless network interface 650 configured to connect the electronic device 600 to a network, and an input / output (I / O) interface 658. The electronic device 600 can operate based on an operating system stored in the memory 632, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or the like.

[0140] The embodiment of the present application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement a processor fault identification method.

[0141] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The specification and examples given are exemplary only and the true scope and spirit of the application is indicated by the claims. The specification and examples are to be regarded as illustrative only, the true scope and spirit of the application being indicated by the following claims.

[0142] It should be understood that the application is not limited to the precise construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application.

[0143] The above merely provides a preferred embodiment of the present application, and is not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

[0144] The above has introduced in detail a processor fault identification method, device, electronic device and computer readable storage medium provided by the present application, the principle and implementation mode of the present application have been described in the text by applying specific examples, the above embodiment explanation is only for helping to understand the method and core idea of the present application; at the same time, for the general technical personnel in the art, according to the idea of the present application, the specific implementation mode and application range will have changes, and the above, the content of the specification should not be understood as the limitation of the present application.

Claims

1. A processor fault identification method, characterized by, The method comprises: obtaining state change information of a processor and a first preset operation corresponding to the state change information; the state change information is used to represent that the processor enters an abnormal state or exits the abnormal state; performing the first preset operation on a first count value in a preset flag bit to obtain a second count value; the first preset operation comprises increasing or decreasing the first count value; performing a second preset operation on the second count value to obtain a second operation result; obtaining a fault identification result of the processor according to the second operation result; the fault identification result comprises that the processor is in a fault state or a normal operation state; the second preset operation comprises at least one of comparing a preset count value with the second count value and comparing a preset time length with a first time length; the first time length is a time length during which the processor is in the abnormal state and is obtained according to the second count value.

2. The method of claim 1, wherein, The method further comprises: obtaining a first time point at which the count value in the preset flag bit is updated from a first count value to the second count value and a second time point at which the count value is restored from the second count value to the first count value; the first count value is smaller than the second count value; obtaining a time difference value between the first time point and the second time point and determining the time difference value as the first time length during which the processor is in the abnormal state.

3. The method of claim 2, wherein, The method further comprises: if the second count value is greater than or equal to the preset count value, determining that the fault identification result is that the processor is in the fault state; if the second count value is smaller than the preset count value, determining that the fault identification result is that the processor is in the normal operation state.

4. The method of claim 1, wherein, The method further comprises: if the first time length is greater than or equal to the preset time length, determining that the fault identification result is that the processor is in the fault state; if the first time length is smaller than the preset time length, determining that the fault identification result is that the processor is in the normal operation state.

5. The method of claim 1, wherein, In the case where the preset time length comprises a first preset time length and a second preset time length, after the step of obtaining the fault identification result of the processor according to the second operation result, the method further comprises: if the second operation result comprises that the first time length is greater than the first preset time length and smaller than the second preset time length, performing processor fault alarm; if the second operation result comprises that the first time length is greater than or equal to the second preset time length, obtaining fault data of the processor and saving the fault data.

6. The method of claim 1, wherein, ​ ​ ​ 7. The method of claim 6, wherein, The fault data includes at least one of a program counter value of the processor, stack pointer information of the processor, data in a general register of the processor, an exception vector number of the processor, an exception nesting level of the exception state, and the first time length.

8. A processor fault identification apparatus, comprising: The apparatus includes: A first obtaining module is configured to obtain state change information of a processor and a first preset operation corresponding to the state change information; the state change information is used to represent that the processor enters an exception state or exits the exception state; A second obtaining module is configured to perform the first preset operation on a first count value in a preset flag bit to obtain a second count value; the first preset operation includes an increasing or decreasing operation on the first count value; A third obtaining module is configured to perform a second preset operation on the second count value to obtain a second operation result; the second preset operation includes at least one of comparing a preset count value with the second count value and comparing a preset time length with a first time length; the first time length is a time length of the processor in the exception state obtained according to the second count value; A fourth obtaining module is configured to obtain a fault identification result of the processor according to the second operation result; the fault identification result includes that the processor is in a fault state or a normal operation state.

9. An electronic device, comprising: includes: A processor; A memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method of any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device can perform the method of any one of claims 1-7.

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