Memory access time delay acquisition method and electronic equipment

Abstract

The invention provides a memory access time delay obtaining method and electronic equipment, and relates to the technical field of communication, a target memory region corresponding to a cache of a processor is divided, a region set is obtained, and the length of each region in the region set is the same as the size of a cache line of the processor; randomizing the integer array corresponding to the region set to obtain a random chain table corresponding to the region set; performing circular traversal memory access operation on the random linked list to obtain traversal information which comprises traversal duration, traversal times and the number of traversal nodes corresponding to the random linked list; and obtaining the memory access time delay corresponding to the cache of the processor according to the traversal information. The universality and portability of access time delay acquisition can be improved, and the convenience and accuracy of access time delay acquisition can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of communication, and particularly relates to a memory access latency acquisition method and an electronic device. BACKGROUND

[0002] With the development of science and technology, the requirements of big data and artificial intelligence (AI) field on storage and servers are higher and higher, and the performance of storage and servers is also continuously improved. Among them, the performance of memory is very crucial to the overall performance of the system. For example, latency parameters can measure important parameters of memory performance. For example, the acquisition of the latency of the corresponding central processing unit (CPU) underlying instruction code can be set, but different CPU underlying instruction codes need to be used for different CPU architectures, and there is dependency for specific CPU architectures, and the portability is poor, so that the convenience of memory access latency acquisition is poor. SUMMARY

[0003] The present disclosure provides a memory access latency acquisition method and an electronic device. The main purpose is to solve the problem that different CPU underlying instruction codes need to be used for different CPU architectures, and there is dependency for specific CPU architectures, and the portability is poor, so that the convenience of memory access latency acquisition is poor.

[0004] According to a first aspect of the present disclosure, a memory access latency acquisition method is provided, comprising: dividing a target memory region corresponding to a cache of a processor to obtain a region set, wherein the length of each region in the region set is the same as the cache line size of the processor; randomizing an integer array corresponding to the region set to obtain a random linked list corresponding to the region set; performing a loop traversal memory access operation on the random linked list to obtain traversal information, wherein the traversal information includes a traversal time length, a traversal number, and a number of traversal nodes corresponding to the random linked list; acquiring a memory access latency corresponding to the cache of the processor according to the traversal information.

[0005] According to a second aspect of the present disclosure, a memory access latency acquisition apparatus is provided, comprising: a set acquisition unit configured to divide a target memory region corresponding to a cache of a processor to obtain a region set, wherein the length of each region in the region set is the same as the cache line size of the processor; a linked list acquisition unit configured to randomize an integer array corresponding to the region set to obtain a random linked list corresponding to the region set; a linked list traversal unit, configured to perform a circular traversal memory access operation on the random linked list to obtain traversal information, wherein the traversal information comprises a traversal duration, a traversal frequency, and a number of traversal nodes corresponding to the random linked list; a memory access latency obtaining unit, configured to obtain a memory access latency corresponding to a cache of the processor according to the traversal information.

[0006] According to a third aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of the first aspect.

[0007] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to perform the method of the first aspect.

[0008] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the method of the first aspect.

[0009] According to the present disclosure, a target memory region corresponding to a cache of a processor is divided to obtain a region set, wherein the length of each region in the region set is the same as the cache line size of the processor; a randomization process is performed on an integer array corresponding to the region set to obtain a random linked list corresponding to the region set; a circular traversal memory access operation is performed on the random linked list to obtain traversal information, wherein the traversal information comprises a traversal duration, a traversal frequency, and a number of traversal nodes corresponding to the random linked list; and a memory access latency corresponding to the cache of the processor is obtained according to the traversal information. Therefore, the memory access latency corresponding to the cache of the processor can be obtained by constructing a random linked list and performing a circular traversal on the random linked list, without the need to set different CPU underlying instruction codes for different CPU architectures, reducing the dependency on specific CPU architectures, reducing the poor portability of CPU underlying instruction codes, and reducing the probability of hitting the accessed cache line and the CPU pre-fetch cache line, improving the generality and portability of the memory access latency obtaining, and improving the convenience and accuracy of the memory access latency obtaining.

[0010] It is to be understood that the details set forth in this section are intended to be illustrative only and are not intended to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. In the drawings: Figure 1 A flowchart of a memory access latency acquisition method provided by an embodiment of the present disclosure; Figure 2 An example schematic diagram of another memory access latency acquisition method provided by an embodiment of the present disclosure; Figure 3 A flowchart of a memory access latency acquisition method provided by an embodiment of the present disclosure; Figure 4 An example schematic diagram of an integer array provided by an embodiment of the present disclosure; Figure 5 An example schematic diagram of a processed integer array provided by an embodiment of the present disclosure; Figure 6 A structural schematic diagram of a memory access latency acquisition device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Exemplary embodiments of the present disclosure are described herein with reference to the accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. Embodiments of the present disclosure are described and their features are identified to assist with an understanding of them. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

[0013] The memory access latency acquisition method and electronic device of an embodiment of the present disclosure are described below with reference to the accompanying drawings.

[0014] Figure 1 A flowchart of a memory access latency acquisition method provided by an embodiment of the present disclosure. As shown in Figure 1 the method includes the following steps: Step 101, dividing a target memory region corresponding to a cache of a processor to obtain a region set, wherein the length of each region in the region set is the same as the cache line size of the processor; According to some embodiments, the execution subject of the embodiments of the present disclosure can be an electronic device, for example. The name of the electronic device is not limited. The electronic device is not particularly limited to a fixed device. For example, when the structure of the electronic device changes, the electronic device can also change accordingly. For example, when the device identifier of the electronic device changes, the electronic device can also change accordingly.

[0015] In some embodiments, the cache of the processor can be a cache corresponding to the processor, for example, which can be a CPU cache. The cache of the processor is not particularly limited to a fixed cache. For example, when the processor changes, the cache of the processor can also change accordingly.

[0016] According to some embodiments, the target memory region can be a memory region applied for the cache of the processor, for example. The name of the target memory region is not limited. For example, the target memory region can also be referred to as a memory region, an applied memory region, etc. The target memory region is not particularly limited to a fixed region. For example, when the size corresponding to the target memory region changes, the target memory region can also change accordingly. For example, when the cache of the processor changes, the target memory region can also change accordingly.

[0017] According to some embodiments, the region set can be a collection gathered by at least one region, for example. The region set is not particularly limited to a fixed set. For example, when the number of regions corresponding to the region set changes, the region set can also change accordingly. For example, when the length of each region in the region set changes, the region set can also change accordingly.

[0018] In some embodiments, the length of each region in the region set is the same as the cache line size of the processor.

[0019] According to some embodiments, the target memory region corresponding to the cache of the processor can be divided to obtain a region set, wherein the length of each region in the region set is the same as the cache line size of the processor.

[0020] In step 102, the integer array corresponding to the region set is randomized to obtain a random linked list corresponding to the region set. According to some embodiments, the random linked list can be a linked list obtained after the region set is randomly processed. The random linked list is not particularly limited to a fixed linked list. For example, when the randomization processing mode changes, the random linked list can also change accordingly. For example, when the region set changes, the random linked list can also change accordingly. For example, when the algorithm used in the randomization processing changes, the random linked list can also change accordingly.

[0021] According to some embodiments, the integer array corresponding to the region set is randomized to obtain a random linked list corresponding to the region set.

[0022] In step 103, a loop traversal memory access operation is performed on the random linked list to obtain traversal information, wherein the traversal information includes a traversal time length, a traversal frequency, and a number of traversal nodes corresponding to the random linked list. In some embodiments, the memory access operation can traverse the nodes in the random linked list, and can read the memory region according to the address corresponding to each node. The loop traversal memory access operation on the random linked list can be performed once or multiple times, which is not limited in the embodiments of the present disclosure.

[0023] In some embodiments, the traversal information can be obtained when the loop traversal memory access operation is performed on the random linked list. The traversal information is not limited to a fixed information. For example, when the type of information included in the traversal information changes, the traversal information can also change accordingly. For example, when the number of information corresponding to the traversal information changes, the traversal information can also change accordingly. For example, when the traversal memory access operation changes, the traversal information can also change accordingly.

[0024] In some embodiments, the loop traversal memory access operation can be performed on the random linked list to obtain the traversal information, wherein the traversal information includes a traversal time length, a traversal frequency, and a number of traversal nodes corresponding to the random linked list.

[0025] According to some embodiments, the traversal time length can be a total time length corresponding to the loop traversal memory access operation on the random linked list. The traversal time length is not limited to a fixed time length. When the specific value corresponding to the traversal time length changes, the traversal time length can also change accordingly. For example, when the traversal memory access operation changes, the traversal time length can also change accordingly.

[0026] In some embodiments, the traversal frequency can be the number of times of the loop traversal memory access operation on the random linked list. For example, the number of times of the traversal on the random linked list can be obtained.

[0027] According to some embodiments, the number of traversal nodes corresponding to the random linked list can be the total number of nodes accessed when the loop traversal memory access operation is performed on the random linked list.

[0028] In step 104, the memory access delay corresponding to the cache of the processor is obtained according to the traversal information.

[0029] In some embodiments, the memory access delay can be a memory access delay parameter of the memory, and the memory access time length can be the time required for waiting when accessing the memory. The memory access delay corresponding to the cache of the processor can be obtained according to the traversal information.

[0030] According to the present disclosure, the target memory region corresponding to the cache of the processor is divided to obtain a region set, wherein the length of each region in the region set is the same as the cache line size of the processor; the integer array corresponding to the region set is randomized to obtain a random linked list corresponding to the region set; the random linked list is circularly traversed to obtain traversal information, wherein the traversal information includes the traversal time, the traversal times, and the number of traversal nodes corresponding to the random linked list; and the memory access latency corresponding to the cache of the processor is obtained according to the traversal information. Therefore, the memory access latency corresponding to the cache of the processor can be obtained by constructing the random linked list and circularly traversing the random linked list, without setting different CPU underlying instruction codes for different CPU architectures, reducing the dependency on specific CPU architectures, reducing the poor portability of CPU underlying instruction codes, and reducing the limitation of the application scenario of the memory access latency. In addition, the probability of hitting the accessed cache line and the CPU pre-fetch cache line can be reduced, the generality and portability of the memory access latency acquisition can be improved, and the convenience and accuracy of the memory access latency acquisition can be improved.

[0031] Further, in a possible implementation manner of the present embodiment, Figure 2 Another flowchart of the memory access latency acquisition method provided by the present embodiment is shown in FIG. 6. As shown in FIG. 6, the method comprises the following steps: Figure 2 The method comprises the following steps: Step 201, the target memory region corresponding to the cache of the processor is divided to obtain a region set, wherein the length of each region in the region set is the same as the cache line size of the processor. For example, the related process can be as described above, and details are not repeated here.

[0032] In some embodiments, the memory access latency acquisition method of the present embodiment can be applied to the performance evaluation and optimization of the system platform.

[0033] In some embodiments, the cache of the processor is a three-level cache, and before the target memory region corresponding to the cache of the processor is divided, the method further comprises: According to the memory size corresponding to the three-level cache of the processor, the target memory region is applied, wherein the size of the target memory region is greater than the memory size.

[0034] In some embodiments, the cache of the processor can be, for example, a CPU cache, and a memory region larger than the CPU cache, i.e., a target memory region, can be applied. The level 3 cache can be, for example, a cache architecture in a CPU, which can be integrated on a CPU chip. The level 3 cache of the CPU is not a fixed cache. For example, when the memory size corresponding to the level 3 cache of the CPU changes, the level 3 cache of the CPU can also change accordingly. For example, when the CPU changes, the level 3 cache of the CPU can also change accordingly.

[0035] According to some embodiments, a memory region larger than the CPU cache can be applied. Specifically, for example, the total size of the level 3 cache (L3) of the CPU can be at least several times larger. If it is a system platform of a non-uniform memory access (Non-Uniform Memory Access, NUMA) architecture, the memory region and the CPU performing the memory access test need to specify the NUMA node to which they belong. Because the memory access latency across the NUMA node and the local memory access latency are affected by the distance between the NUMA nodes, there can be a large difference. Therefore, the specified NUMA node can improve the accuracy of the memory access latency acquisition.

[0036] In step 202, the integer array corresponding to the region set is randomized to obtain a random linked list corresponding to the region set. The related process can be, for example, as described above, and will not be described here.

[0037] According to some embodiments, the integer array corresponding to the region set can be randomized by, for example, using the Knuth shuffle algorithm to obtain a random linked list corresponding to the region set. The Knuth shuffle algorithm can also be referred to as the Knuth shuffle algorithm.

[0038] In some embodiments, the integer array corresponding to the region set is randomized to obtain a random linked list corresponding to the region set, including: According to the address order, the index number corresponding to each region in the region set is obtained. According to the index number corresponding to each region, the integer array corresponding to the region set is obtained. The integer array is randomized to obtain a random linked list corresponding to the region set. Therefore, the random linked list can be obtained through the index number and the integer array, which can improve the accuracy of the random linked list acquisition and the accuracy of the memory access latency acquisition.

[0039] According to some embodiments, the index number can be used to mark different regions, and different regions can correspond to different index numbers. The index number does not specifically refer to a fixed index number. For example, when the region changes, the index number can also change accordingly. For example, when the composition of the index number changes, the index number of each region can also change accordingly.

[0040] According to some embodiments, the memory region address is aligned to CPU cache lines (e.g., 64 bytes) and divided into small regions according to the CPU cache line size. The length of each small region is equal to the CPU cache line size. Each small region has a corresponding index number in address order, and the address of each small region can be calculated using the index number. According to some embodiments, Figure 3 This is a flowchart illustrating a method for obtaining memory access latency provided in an embodiment of this disclosure. Figure 3 As shown, the index number of the first small region is idx=1, and its address is equal to the starting address m_addr of the entire memory region (target memory region) requested; the index number of the second small region is idx=2, and its address is m_addr+Cache_Line, where Cache_Line represents the size of the CPU cache line, that is, the length of the small region; the index number of the third small region is idx=3, and its address is m_addr+2*Cache_Line; the index number of the j-th small region is idx=j, and its address is m_addr+(j-1)*Cache_Line.

[0041] Each small region of memory can be constructed as a node in a linked list, as defined below: struct node { struct node *next_node; bytepad[Cache_Line - sizeof(struct node *)]; }, Here, `next_node` represents the address of the next sub-region in the linked list, and `pad` is used for byte padding. Therefore, accessing each sub-region can be done, for example, by reading the `next_node` field of each sub-region.

[0042] In some embodiments, the integer array is randomized to obtain a random linked list corresponding to the region set, including: Iterate through the integer array starting from the first element, and randomly select the second element corresponding to the first element from the integer array, where the first element is the last element of the integer array; In a case where the second element meets the element requirement, the first element and the second element are exchanged; In a case where the first element processing is completed, a third element in the integer array is randomized until all elements in the integer array are randomized, and a random linked list corresponding to the region set is obtained, where the third element is a previous element adjacent to the first element. Therefore, the accuracy of the random linked list acquisition can be improved by randomizing each element, the accuracy of the memory access latency acquisition can be improved, and the accuracy of the random linked list acquisition can be improved by reducing the exchange of elements that have been processed.

[0043] According to some embodiments, the first element may, for example, be a last element of the integer array, and the second element may, for example, be an element corresponding to the first element randomly selected from the integer data, i.e., the second element is an element randomly selected from the elements of the integer array except the first element. The second element is not a specific fixed element, for example, when the random selection method changes, the second element can also change accordingly.

[0044] According to some embodiments, the element requirement may, for example, be a requirement for whether to exchange the first element and the second element. The element requirement may, for example, be that the randomly selected element is between the starting element of the integer array and the first element, and in a case where the second element meets the element requirement, i.e., the second element is between the starting element of the integer array and the first element, the first element and the second element can be exchanged. In a case where the second element does not meet the element requirement, i.e., the second element is not between the starting element of the integer array and the first element, the first element and the second element can not be exchanged, and the second element can be reacquired.

[0045] According to some embodiments, the third element may, for example, be a previous element adjacent to the first element, and the third element is used to distinguish the remaining elements and does not refer to a specific fixed element.

[0046] In some embodiments, the method further comprises: In a case where the randomization operation for the integer array is completed, the number of exchanged elements corresponding to the integer array is acquired; In a case where the number of exchanged elements is consistent with the number of elements corresponding to the integer array, it is determined that all elements in the integer array have completed the randomization. Therefore, the accuracy of the random linked list acquisition can be improved, the probability of elements not being randomized can be reduced, and the accuracy of the memory access latency acquisition can be improved.

[0047] According to some embodiments, the index numbers of each small region can be sequentially stored in the integer array idx_array[N], and the content in the array idx_array[N] may, for example, be as follows: Figure 4As shown. Among them, the integer array may be a data structure, for example, which is not specific to a fixed array. The integer array may be a set of integers, for example, each integer may be an element of the array. The integer array may be composed of at least one element. For example, when the number of elements corresponding to the integer array changes, the integer array may also change accordingly.

[0048] Among them, the randomization of idx_array by the classic highlander shuffle algorithm may include: 1) Start from the last element of idx_array and traverse forward to the second element; 2) For the current element idx_array[i], randomly select an idx_array[j] that satisfies 0<=j<=i; then exchange the values of idx_array[i] and idx_array[j]; 3) Continue to process the previous element until the second element of idx_array is processed. The processed integer array may be, for example, as shown. Figure 5 Among them, rand_i, rand_j, rand_p …… rand_k, rand_m …… may be the index numbers of the regions disturbed by the highlander shuffle algorithm.

[0049] In some embodiments, the randomization of the integer array obtains a random linked list corresponding to the region set, including: Randomizing the integer array to obtain a processed integer array; According to the index numbers of the regions corresponding to each position in the processed integer array, obtaining the addresses of the regions corresponding to each position; Converting the addresses, constructing linked list nodes, and inserting the linked list nodes into the random linked list. Therefore, the random linked list can be obtained according to the processed integer array, which can improve the accuracy of random linked list acquisition, reduce the probability of hitting the accessed cache line and CPU prefetch cache line when accessing the memory, and improve the accuracy of access latency acquisition.

[0050] According to some embodiments, the process of constructing the linked list may be the process of traversing the array idx_array, converting the address of each small region according to its index number, and then constructing the memory of the small region into linked list nodes and inserting them into the linked list one by one. The specific process is as follows: A small region with index number idx=rand_i, whose address is m_addr+(rand_i-1)*Cache_line, can be selected, the address is forcibly converted, a node struct node of the chain table defined in the above is constructed, and the node is inserted into the chain table as the head node. Then, a small region with index number idx=rand_j, whose address is m_addr+(rand_j-1)*Cache_line, is selected, a node of the chain table is constructed, and the node is inserted into the chain table. rand_p ……rand_k, rand_m can be processed one by one and inserted into the chain table. Finally, a chain table with randomized addresses is generated, that is, a random chain table is obtained.

[0051] In step 203, a loop traversal memory access operation is performed on the random chain table to obtain traversal information, where the traversal information includes a traversal time length, a traversal number, and a number of traversal nodes corresponding to the random chain table. For example, the related process can be as described above, and details are not described herein.

[0052] In some embodiments, the loop traversal memory access operation on the random chain table includes: In each loop traversal memory access operation on the random chain table, pointer information in the random chain table is read. According to the pointer information, a traversal operation is performed on the random chain table. Therefore, since the next node of each node in the chain table is random, the probability of hitting an accessed cache line and a CPU-prefetched cache line is reduced in each memory access operation, so that each memory access needs to be read from the memory, and the accuracy of the memory access delay can be improved.

[0053] The memory access operation is to traverse the nodes in the chain table, and when accessing the small regions, only one read operation can be performed, for example, only the next pointer can be read, for example, 4 or 8 bytes.

[0054] In some embodiments, the method further includes: According to the latency accuracy information corresponding to the cache of the processor, the traversal number is determined. Therefore, the matching between the latency accuracy information and the traversal number can be improved, the accuracy of the traversal number can be improved, and the accuracy of the memory access delay can be improved.

[0055] According to some embodiments, the latency accuracy information is not a fixed information. For example, when a modification instruction for the latency accuracy information is received, the latency accuracy information can also be changed accordingly. For example, when the accuracy value corresponding to the latency accuracy information changes, the latency accuracy information can also be changed accordingly. For example, the higher the latency accuracy information, the more the traversal number.

[0056] In some embodiments, the number of traversals can also be determined according to the number of times setting instructions.

[0057] At step 204, the total number of traversal nodes corresponding to the circular traversal memory access operation on the random linked list is obtained according to the number of traversals and the number of traversal nodes corresponding to the random linked list. For example, the related process can be as described above, and will not be described here again.

[0058] According to some embodiments, the number of traversal nodes may, for example, be the number corresponding to one traversal of the random linked list. The number of traversal nodes does not refer to a fixed number. When the specific value of the number of traversal nodes changes, the number of traversal nodes can also change accordingly.

[0059] According to some embodiments, the total number of traversal nodes may, for example, be the total number of nodes traversed in the entire process of the circular traversal memory access operation on the random linked list. The total number of traversal nodes does not refer to a fixed total number. For example, when the number of traversals changes, the total number of traversal nodes can also change accordingly. For example, when the number of traversal nodes corresponding to the random linked list changes, the total number of traversal nodes can also change accordingly.

[0060] In some embodiments, the total number of traversal nodes corresponding to the circular traversal memory access operation on the random linked list is obtained according to the number of traversals and the number of traversal nodes corresponding to the random linked list.

[0061] At step 205, the memory access latency corresponding to the cache of the processor is obtained according to the traversal duration and the total number of nodes.

[0062] For example, the related process can be as described above, and will not be described here again.

[0063] In some embodiments, the memory access latency corresponding to the cache of the processor is obtained according to the traversal duration and the total number of nodes.

[0064] According to some embodiments, a total time consumption can be obtained through the random linked list constructed by the circular traversal shuffling algorithm, that is, the traversal duration is obtained, and the memory access latency is equal to the total time consumption divided by the number of traversal nodes. For example, the number of traversal nodes of the nodes in the random linked list is N, the number of circular traversals is M, and the total time consumption is t. Then, the memory access latency of the memory is t / (N*M).

[0065] In one or related embodiments, the total number of traversal nodes corresponding to the loop traversal memory access operation of the random linked list is obtained according to the number of traversals and the number of traversal nodes corresponding to the random linked list; and the memory access latency corresponding to the cache of the processor is obtained according to the traversal duration and the total number of nodes. Therefore, by traversing the random linked list, the probability of hitting the accessed cache line and the CPU pre-fetch cache line can be reduced, the dependence on the CPU architecture can be reduced, and good universality and portability are achieved.

[0066] According to embodiments of the present disclosure, the present disclosure also provides a memory access latency obtaining device.

[0067] For example, Figure 6 A structural schematic diagram of a memory access latency obtaining device provided by an embodiment of the present disclosure. The memory access latency obtaining device 600 comprises a set obtaining unit 601, a linked list obtaining unit 602, a linked list traversal unit 603, and a memory access latency obtaining unit 604; wherein, The set obtaining unit 601 is configured to divide a target memory region corresponding to the cache of the processor, and obtain a region set, wherein the length of each region in the region set is the same as the cache line size of the processor. The linked list obtaining unit 602 is configured to perform randomization processing on an integer array corresponding to the region set, and obtain a random linked list corresponding to the region set. The linked list traversal unit 603 is configured to perform a loop traversal memory access operation on the random linked list, and obtain traversal information, wherein the traversal information comprises a traversal duration, a number of traversals, and a number of traversal nodes corresponding to the random linked list. The memory access latency obtaining unit 604 is configured to obtain the memory access latency corresponding to the cache of the processor according to the traversal information.

[0068] Further, the cache of the processor is a three-level cache, and the set obtaining unit 601 is further configured to, before dividing the target memory region corresponding to the cache of the processor: According to the memory size corresponding to the three-level cache of the processor, the target memory region is applied, wherein the size of the target memory region is greater than the memory size.

[0069] Further, the linked list traversal unit 603 is configured to, when performing the loop traversal memory access operation on the random linked list, specifically configured to: In each case of performing the loop traversal memory access operation on the random linked list, the pointer information in the random linked list is read; According to the pointer information, the random linked list is traversed.

[0070] Further, the linked list obtaining unit 602 is configured to, when performing the randomization processing on the integer array corresponding to the region set to obtain the random linked list corresponding to the region set, specifically configured to: obtain an index number corresponding to each region in the region set in address order; obtain an integer array corresponding to the region set according to the index number corresponding to each region; randomize the integer array to obtain a random linked list corresponding to the region set.

[0071] Further, the linked list obtaining unit 602 is configured to randomize the integer array to obtain a random linked list corresponding to the region set, and includes: randomly obtain a second element corresponding to the first element from the integer array, starting from the first element of the integer array, wherein the first element is the last element of the integer array; if the second element meets the element requirement, exchange the first element and the second element; if the first element is processed, randomize a third element in the integer array until all elements in the integer array are randomized to obtain a random linked list corresponding to the region set, wherein the third element is the last element adjacent to the first element.

[0072] Further, the linked list obtaining unit 602 is further configured to: if the randomization operation on the integer array is completed, obtain the number of exchanged elements corresponding to the integer array; if the number of exchanged elements is consistent with the number of elements corresponding to the integer array, determine that all elements in the integer array are randomized.

[0073] Further, when the linked list obtaining unit 602 randomizes the integer array to obtain a random linked list corresponding to the region set, the linked list obtaining unit 602 is specifically configured to: randomize the integer array to obtain a processed integer array; obtain the address of each region corresponding to each position in the processed integer array according to the index number of the region corresponding to each position; transform the address, construct a linked list node, and insert the linked list node into the random linked list.

[0074] Further, the linked list traversal unit 603 is further specifically configured to: determine the number of traversals according to the latency accuracy information corresponding to the cache of the processor.

[0075] Further, the memory access latency obtaining unit 604 is configured to obtain the memory access latency corresponding to the cache of the processor according to the traversal information, and specifically configured to: obtain the total number of traversal nodes corresponding to the loop traversal memory access operation on the random linked list according to the number of traversals and the number of traversal nodes corresponding to the random linked list; According to the traversal duration and the total number of nodes, the memory access latency corresponding to the cache of the processor is obtained.

[0076] It should be noted that the features of the embodiments corresponding to the memory access latency obtaining device can be referred to the related descriptions of the embodiments corresponding to the memory access latency obtaining method, which will not be repeated here.

[0077] Embodiments of the present disclosure also provide an electronic device, comprising a memory and a processor, the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any of the above memory access latency obtaining method embodiments.

[0078] Embodiments of the present disclosure also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to perform the steps in any of the above memory access latency obtaining method embodiments when executed.

[0079] In an example embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0080] Embodiments of the present disclosure also provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps in any of the above memory access latency obtaining method embodiments.

[0081] Embodiments of the present disclosure also provide another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above memory access latency obtaining method embodiments.

[0082] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0083] The above describes in detail the memory access latency acquisition method provided by the present disclosure. The principles and implementation manners of the present disclosure are described by applying specific examples, and the above description of the embodiments is only used to help understand the method of the present disclosure and its core idea. It should be pointed out that, for those skilled in the art, without departing from the principles of the present disclosure, the present disclosure can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the claims of the present disclosure.

Claims

1. A memory access latency acquisition method, characterized in that, The method comprises the following steps: dividing a target memory region corresponding to a cache of a processor to obtain a region set, wherein the length of each region in the region set is the same as the cache line size of the processor; randomizing an integer array corresponding to the region set to obtain a random linked list corresponding to the region set; performing a circular traversal memory access operation on the random linked list to obtain traversal information, wherein the traversal information comprises a traversal time length, a traversal number and the number of traversal nodes corresponding to the random linked list; obtaining a memory access delay of the cache of the processor according to the traversal information.

2. The method of claim 1, wherein, The cache of the processor is a three-level cache, and before the target memory region corresponding to the cache of the processor is divided, the method further comprises the following steps: applying the target memory region according to the memory size corresponding to the three-level cache of the processor, wherein the size of the target memory region is greater than the memory size.

3. The method of claim 1, wherein, The circular traversal memory access operation on the random linked list comprises the following steps: reading pointer information in the random linked list in each circular traversal memory access operation on the random linked list; performing a traversal operation on the random linked list according to the pointer information.

4. The method of claim 1, wherein, The randomization processing of the integer array corresponding to the region set to obtain the random linked list corresponding to the region set comprises the following steps: obtaining index numbers corresponding to each region in the region set in address order; obtaining an integer array corresponding to the region set according to the index numbers corresponding to each region; randomizing the integer array to obtain the random linked list corresponding to the region set.

5. The method of claim 4, wherein, The randomization processing of the integer array to obtain the random linked list corresponding to the region set comprises the following steps: randomly obtaining a second element corresponding to a first element in the integer array from the first element, wherein the first element is the last element of the integer array; swapping the first element and the second element when the second element meets the element requirement; randomizing a third element in the integer array when the processing of the first element is completed, until all elements in the integer array are randomly processed to obtain the random linked list corresponding to the region set, wherein the third element is the last element adjacent to the first element.

6. The method of claim 5, wherein, The method further comprises the following steps: obtaining the number of swapped elements corresponding to the integer array when the randomization operation on the integer array is completed; determining that all elements in the integer array are randomly processed when the number of swapped elements is consistent with the number of elements corresponding to the integer array.

7. The method of claim 4, wherein, The randomization processing of the integer array to obtain the random linked list corresponding to the region set comprises the following steps: randomizing the integer array to obtain a processed integer array; obtaining the address of each region corresponding to each position in the processed integer array according to the index number of each region corresponding to each position; performing conversion processing on the address to construct a linked list node and insert the linked list node into the random linked list.

8. The method of claim 1, wherein, The method further comprises the following steps: According to the latency accuracy information corresponding to the cache of the processor, the number of traversals is determined.

9. The method of claim 1, wherein, According to the traversal information, the memory access latency corresponding to the cache of the processor is obtained, including: According to the number of traversals and the number of traversal nodes corresponding to the random link list, the total number of traversal nodes corresponding to the loop traversal memory access operation on the random link list is obtained. According to the traversal time length and the total number of nodes, the memory access latency corresponding to the cache of the processor is obtained.

10. An electronic device, comprising: Including: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement the memory access latency acquisition method according to any one of claims 1 to 9.

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