Millimeter wave band MOS tube small signal equivalent circuit correction model and parameter extraction method

Abstract

The invention belongs to the field of semiconductor devices, particularly provides a millimeter wave band MOS tube small signal equivalent circuit correction model and a parameter extraction method, and is used for solving the problem that a traditional device model such as a BSIM4 model lacks consideration of a longitudinal distribution effect. According to the method, an equivalent circuit correction model capable of accurately describing the longitudinal distribution effect of the device is obtained by deducing the grid RC network under the influence of the longitudinal distribution effect and then performing mathematical approximate analysis on the physical meaning of the grid RC network; meanwhile, a matched parameter extraction process is developed, firstly, the working frequency of the device is divided into a low-frequency band and a full-frequency band, then, an equivalent circuit is divided into an external circuit and an internal circuit based on different bias conditions of the MOSFET, the external circuit is stripped by using a de-embedding technology to obtain the internal circuit, and finally, by means of auxiliary fitting of a mathematic tool, the internal circuit is extracted. Realizing extraction of model parameters; based on this, the correction model provided by the invention reduces the difficulty in extracting small signal model parameters, and significantly improves the simulation precision in the millimeter wave frequency band.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of semiconductor devices, and relates to a small-signal equivalent circuit model of a MOS transistor, in particular to a small-signal equivalent circuit correction model of a MOS transistor suitable for a millimeter wave band and a parameter extraction method. BACKGROUND

[0002] With the growth of mobile cloud services, the Internet of Things, smart home devices, the development of Internet of Vehicles technology, and the popularity of telemedicine services, the capacity of wireless networks has been significantly improved, and the capacity of various wireless access technologies operating in the microwave frequency band (300 MHz to 3 GHz) cannot meet this data demand. The fifth generation (5G) mobile communication technology emerged as the times require. Compared with 3G and 4G, the uniqueness of 5G is to use millimeter wave frequencies in mobile communication. There are two unique points in using millimeter wave frequencies for mobile communication: first, the current sub-6 GHz range is already full, and many frequency bands are dedicated to cellular, satellite and air communication, as well as wireless local area networks. On the contrary, there are multiple unlicensed frequency bands in the 6 GHz to 300 GHz range, meaning that bandwidth is abundant. In summary, millimeter wave frequency mobile communication has great significance for information globalization and Internet of Everything.

[0003] The small-signal equivalent circuit model is a bridge between circuit design and device characteristics, but for MOS devices working in the millimeter wave band, the traditional model lacks consideration of the longitudinal distribution effect along the gate finger, that is, when the gate finger length and the wavelength of the bias signal are comparable or even shorter, the high-frequency parasitic phenomenon has a great impact on the high-frequency performance of the MOS transistor. SUMMARY

[0004] The purpose of the application is to solve the problem that the original traditional MOS small-signal model lacks consideration of the longitudinal distribution effect along the gate finger, and to provide a millimeter wave band MOS transistor small-signal equivalent circuit correction model and a parameter extraction method. The core creation of the application is to use a gate RC network considering the longitudinal distribution effect to replace the gate resistance in the traditional BSIM4 model, and to develop a corresponding parameter extraction process, which includes solving two-port network parameter equations, de-embedding operations, and function fitting using mathematical tools. Nonlinear rational functions are fitted using MATLAB or Mathematica. Based on this, the application realizes the development of the millimeter wave band MOS transistor small-signal equivalent model parameter extraction process, and significantly improves the accuracy of the millimeter wave band MOS transistor small-signal equivalent model.

[0005] To achieve the above purpose, the specific technical scheme of the application is:

[0006] A small-signal equivalent circuit correction model for millimeter-wave MOSFETs includes a gate RC network considering longitudinal distribution effects and a BSIM RF small-signal equivalent circuit model. The equivalent circuit correction model includes: a gate RC network R considering longitudinal distribution effects. g0 R g1 R g2 C g0 C g1 and C g2 Source resistance R s Drain resistance R d Gate-source external capacitance C gso Shallow-doped source-level extended region resistance R gs Gate-source internal parasitic capacitance C gsi Gate-drain external capacitance C gdo Lightly doped drain extension region resistance R gd The internal parasitic capacitance C of the gate-drain junction gdi Resistance R of the drain and substrate sub The capacitance C between the source / drain and the substrate jd , subject to gate voltage V gs Controlled current source VCCS, channel output resistance R between source and drain ds The equivalent inductance L reflects the transistor output delay at high frequencies. ds And characterizing the drain voltage V caused by the DIBL (drain-induced barrier reduction) effect. ds The equivalent parasitic capacitance C of the control effect on the charge carriers in the channel sdx ;

[0007] Among them, the gate RC network R considering the longitudinal distribution effect g0 and C g0 The gate RC network R, which considers the longitudinal distribution effect, is connected in parallel between the outer gate node G and the middle gate node G1. g1 and C g1 The gate RC network R, which considers the longitudinal distribution effect, is first connected in series and then connected between the outer gate node G and the middle gate node G1. g2 and C g2 The source resistor R is first connected in series and then connected between the external gate node G and the middle gate node G1. s The drain resistor R is connected between the external source node S and the middle source node S1. d The gate-source external capacitor C is connected between the external drain node D and the middle drain node D1. gso The shallowly doped source extension region resistor R is connected between the middle gate node G1 and the middle source node S1. gs and gate-source internal parasitic capacitance C gsifirst connected in series and then connected between the middle gate node G1 and the middle source node S1, the gate-drain external capacitance C gdo connected between the middle gate node G1 and the middle drain node D1, the shallow-doped drain extension region resistance R gd and the gate-drain internal parasitic capacitance C gdi first connected in series and then connected between the middle gate node G1 and the middle drain node D1, the drain and substrate resistance R sub and the capacitance C between the source-drain and the substrate jd first connected in series and then connected between the middle drain node D1 and the middle source node S1, the voltage-controlled current source VCCS connected between the middle drain node D1 and the middle source node S1, the channel output resistance R between the source-drain ds and the equivalent inductance L ds first connected in series and then connected between the middle drain node D1 and the middle source node S1, the equivalent parasitic capacitance C sdx connected between the middle drain node D1 and the middle source node S1.

[0008] A parameter extraction method of the millimeter wave band MOS tube small signal equivalent circuit correction model, comprising:

[0009] Step 1, in the range of 0-10GHz, according to the cold field theory, when the MOSFET device is in a zero bias state, the channel is off, and the device is in a cutoff region, at this time the device is only affected by the external circuit, and the internal circuit can be ignored. The cutoff device is regarded as a two-port network, and the impedance parameter Z parameter matrix of the two-port network is solved to extract the resistance R g , R s and R d of the external circuit, then the inverse matrix of the Z parameter matrix is obtained to obtain the admittance parameter Y parameter, and the Y parameter is used to extract the capacitance C gdo , C gso , C jd and the resistance R sub of the external circuit, so as to obtain the external circuit model; then the bias condition is adjusted so that the device is in a conducting state, at this time the device is affected by the external and internal circuits. The conducting device is regarded as a two-port network, and the Z parameter and Y parameter of the two-port network are solved to obtain the Z parameter matrix Z tol of the complete circuit, and then the effects of the gate resistance, the drain resistance, the source resistance, the substrate network, the gate-drain external capacitance and the gate-source external capacitance are removed in turn to realize de-embedding and peel off the internal circuit, so as to obtain the internal circuit model. The internal circuit model is regarded as a two-port network, and the Y parameter matrix of the two-port network is solved to extract the values of various parasitic parameters of the internal circuit model; finally, the low-frequency band correction model is obtained by combining the internal and external circuit models;

[0010] Step 2: Within the 10-100GHz range, a full-band correction model is obtained by calculating and replacing the gate equivalent resistance with a gate RC network, thereby characterizing the device's AC performance below 100GHz. This includes: firstly, by adjusting the gate resistance R in the low-frequency correction model... g Multiply by the impedance coefficient α g The gate impedance network Z is obtained. g Using gate impedance network Z g The gate resistance R replaces the low-frequency correction model g The rest remain unchanged; then the impedance coefficient α g Using the Pad approximation with a first-order numerator and a second-order denominator, the gate impedance Z is obtained. g The simplified expression for impedance Z; and the simplified expression for impedance Z. g Includes total gate admittance Y g And Y g The expression includes the gate-drain capacitance C. gd and gate-source capacitance C gs It is a frequency-dependent function, which makes the coefficient α g It also changes with frequency; finally, the simplified expression is represented in circuit form using capacitors and resistors to obtain the gate RC network that considers the longitudinal distribution effect and replaces the gate resistor in the low-frequency correction model.

[0011] Step 3: Verify the full-band correction model within the 0-100GHz range, including: building a gate RC network in the ADS simulation tool to obtain the small-signal correction model of the device across the entire frequency band; and performing simulations within the 0-100GHz frequency range, comparing the simulation results of the correction model, the traditional model, and TCAD, using E... max The error function evaluates the accuracy of the model.

[0012] Furthermore, in step 1, the impedance parameters, i.e., the Z-parameter matrix, of the two-port network are solved to extract the resistance R of the external circuit. g R s and R d The value is as follows:

[0013]

[0014] Z 11 =R g +R s +(Z sub +Z gd )||Z gs

[0015]

[0016] Z22 = R s + R d + Z gs + Z gd || Z sub

[0017] where U1 is the voltage of port 1, U2 is the voltage of port 2, I1 is the current flowing through port 1, I2 is the current flowing through port 2, Z 11 , Z 12 , Z 21 , Z 22 are four elements in the Z-parameter matrix, the impedance between the gate and the source the impedance between the source and the drain and the substrate the impedance between the gate and the drain where j is an imaginary number, ω is an angular frequency, and since the external circuit is a passive network, Z 12 and Z 21 parameters are equal, so the relationship between the real parts of the obtained Z parameters is:

[0018]

[0019] where B 10 , B 11 , B 12 , B 20 , B 21 , B 22 , B 30 , B 31 , B 32 are irrelevant terms obtained by solving, and the values of R g , R s , R d can be obtained by mathematical tools in the form of curve fitting; here, the equivalent resistance R g of the gate is obtained.

[0020] Further, step 1 describes the inverse matrix of the Z parameter matrix to obtain the admittance parameter, i.e., the Y parameter, and the values of the capacitances C gdo , C gso , C jd and the resistance R sub of the external circuit are extracted using the Y parameter, specifically:

[0021]

[0022] where Y 11 , Y 12 , Y 21 , Y 22 are four elements in the Y parameter matrix, A / 0 = C gdo + Cgso , A 00 = -C gdo , A 20 = C gso + C jd , A 50 = C gso 2 (R d + R g ) + C jd 2 (R d + R s + R sub ) + 2*C gdo C jd R d , ω is the angular frequency, A 41 , A 42 , A 51 , A 52 , A 61 , A 62 , A 71 , A 72 , B 40 , B 41 , B 42 , B 50 , B 51 , B 52 , B 60 , B 61 , B 62 , B 70 , B 71 , B 72 are the solved irrelevant terms, and finally the values of R g , R s , R d , C gdo , C gso and C jd are substituted into the expression of A 70 , R sub is solved, and finally all external parasitic parameters are obtained.

[0023] Further, the step 1 removes the effects of the gate resistance, the drain resistance, the source resistance, the substrate network, the gate-drain external capacitance and the gate-source external capacitance in turn, realizes de-embedding, and strips the internal circuit, so as to obtain the internal circuit model, specifically:

[0024] Define the Z parameter matrix of the gate resistance and the drain resistance

[0025]

[0026] In the Z parameter matrix, the effect of the gate resistance and the drain resistance is removed, and the matrix Z tol1 :

[0027]

[0028] The Z parameter matrix defining the source resistance

[0029]

[0030] In the Z parameter matrix, the effect of the source resistance is removed, and the matrix Z tol2 :

[0031]

[0032] where Z tol2 The circuit without R g , R d , R s and the corresponding Z parameter are obtained, and Z tol2 is converted into Y parameter Y tol2 The Y parameter matrix defining the substrate network R sub and C jd

[0033]

[0034] In the Y parameter matrix, the effect of the substrate network R sub and C jd is removed, and the matrix Y tol3 :

[0035]

[0036] The Y parameter matrix defining the gate-drain external capacitance C gdo and the gate-source external capacitance C gso

[0037]

[0038] In the Y parameter matrix, the effect of the gate-drain external capacitance C gso and the gate-source external capacitance C gso is removed, and the matrix Y int :

[0039]

[0040] The Y int matrix is a two-port admittance parameter containing only internal parasitic parameters, and all the embedding is completed, and the external circuit has been completely removed from the complete circuit model.​​

[0041] Further, the internal circuit model is regarded as a two-port network in step 1, and each parasitic parameter value of the internal circuit model is extracted by solving the Y parameter matrix of the two-port network, specifically: the gate and the source are regarded as port 1, and the drain and the source are regarded as port 2, and the two-port network of the internal circuit model satisfies the following equation:

[0042]

[0043] wherein, are four elements of the Y parameter matrix obtained by solving the internal circuit model, and eight rational function expressions about the angular frequency ω can be obtained by solving, and the coefficients M ij , N ij of ω are composed of internal parasitic parameters;

[0044]

[0045]

[0046] wherein the specific values of the coefficients M 10 -M 90 can be obtained by function fitting with the aid of mathematical tools, so that the shallow-doped source extension region resistance R gs , the gate-source internal parasitic capacitance C gsi , the shallow-doped drain extension region resistance R gd , the gate-drain internal parasitic capacitance C gdi , the channel output resistance R ds between the source and the drain, the equivalent inductance L ds reflecting the output delay of the transistor under high frequency, the equivalent parasitic capacitance C sdx reflecting the control action of the channel carrier on the drain voltage V ds , and the value of the current source VCCS controlled by the gate voltage V gs of the internal circuit model can be calculated.

[0047] Further, the impedance coefficient α g is approximated by the Padé approximation with the numerator of the first order and the denominator of the second order in step 2, and a simplified expression of the gate impedance Z g is obtained, specifically:

[0048]

[0049] Then, the simplified expression is represented in the form of a circuit by using capacitors and resistors, and R g , R g1 , and R g2 , Cg0 ,C g1 and C g2 The values are as follows:

[0050]

[0051] R g1 = 5R gs

[0052] R g2 = 5R gd

[0053] C g0 = (C gso + C gdo ) / 5

[0054] C g1 = C gsi / 5

[0055] C g2 = C gdi / 5.

[0056] Further, the E max error function in step 3 evaluates the model as:

[0057]

[0058] Where Y ij model and Y ij TCAD are the Y parameters obtained by correcting the model ADS simulation and the Y parameters obtained by TCAD simulation, respectively.

[0059] Compared with the prior art, the present application has the beneficial effects that:

[0060] The present application takes TCAD simulation as data basis, and takes the physical mechanism of distribution effect as a starting point, and proposes a radio frequency small signal equivalent circuit model which can accurately describe the distribution characteristics of MOS devices, and takes other high frequency effects into account, and gives the corresponding parameter extraction process combined with the physical mechanism and parameter characteristics. Compared with the traditional BSIM4 model, the accuracy of the millimeter wave MOS transistor small signal equivalent model is significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0061] Figure 1 The external equivalent circuit diagram of the MOS device in the cut-off state in the present application;

[0062] Figure 2 The internal equivalent circuit model diagram of the MOSFET in the on state in the present application;

[0063] Figure 3A millimeter wave band MOS transistor small signal equivalent circuit correction model diagram is provided in the present application;

[0064] Figure 4 A parameter extraction flowchart of the shown small signal equivalent circuit correction model is provided;

[0065] Figures 5-12 A comparison diagram of the parameter real part and the parameter imaginary part is provided. gs ds 11 12 21, 22 A comparison diagram of the parameter real part and the parameter imaginary part is provided. DETAILED DESCRIPTION

[0066] The present application provides a millimeter wave band MOS transistor small signal equivalent circuit correction model and a parameter extraction method thereof. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0067] Embodiment 1

[0068] The equivalent circuit correction model structure is shown in Figure 3 The equivalent circuit correction model structure is shown in g0 g1 g2 g0 g1 g2 s d gso gs gsi gdo gd gdi sub jd ds ​​​​​​​​​​​​​​​​​​​​​The equivalent inductance L reflects the transistor output delay at high frequencies. ds And characterizing the drain voltage V caused by the DIBL (drain-induced barrier reduction) effect. ds The equivalent parasitic capacitance C of the control effect on the charge carriers in the channel sdx ;

[0069] Among them, the gate RC network R considering the longitudinal distribution effect g0 and C g0 The gate RC network R, which considers the longitudinal distribution effect, is connected in parallel between the outer gate node G and the middle gate node G1. g1 and C g1 The gate RC network R, which considers the longitudinal distribution effect, is first connected in series and then connected between the outer gate node G and the middle gate node G1. g2 and C g2 The source resistor R is first connected in series and then connected between the external gate node G and the middle gate node G1. s The drain resistor R is connected between the external source node S and the middle source node S1. d The gate-source external capacitor C is connected between the external drain node D and the middle drain node D1. gso The shallowly doped source extension region resistor R is connected between the middle gate node G1 and the middle source node S1. gs and gate-source internal parasitic capacitance C gsi The gate-drain external capacitor C is first connected in series and then connected between the middle gate node G1 and the middle source node S1. gdo The shallowly doped drain extension region resistance R is connected between the middle gate node G1 and the middle drain node D1. gd and the internal parasitic capacitance C of the gate-drain gdi First, connect them in series, then connect them between the middle gate node G1 and the middle drain node D1. The resistance R between the drain and the substrate... sub The capacitance C between the source / drain and the substrate jd First, a series connection is made between the middle drain node D1 and the middle source node S1. The voltage-controlled current source VCCS is connected between the middle drain node D1 and the middle source node S1. The channel output resistance R between the source and drain is... ds With equivalent inductance L ds First, connect them in series, then connect them between the middle drain node D1 and the middle source node S1. The equivalent parasitic capacitance C sdx It is connected between the middle drain node D1 and the middle source node S1.

[0070] Furthermore, this embodiment also provides the parameter extraction process for the above-mentioned small signal model, the flowchart of which is shown below. Figure 4As shown, specifically in 40nm CMOS process W = 20um single finger MOS transistor as an example, its test and verification frequency band is 0-100GHz; specifically including the following steps:

[0071] Step 1, in the range of 0-10GHz, use the traditional model as the low frequency band correction model to extract the external equivalent circuit model parameters, including: by extracting the external circuit Z parameter of MOSFET device under zero bias to ignore the internal parasitic, its equivalent circuit diagram is as shown in Figure 1 As shown, after separating the real part and the imaginary part, the equation group is obtained to obtain the external circuit model parameters, wherein the Z parameter of the external circuit parameter extraction is:

[0072]

[0073] Z 11 = R g + R s + (Z sub + Z gd ) || Z gs

[0074]

[0075] Z 22 = R s + R d + (Z gs + Z gd ) || Z sub

[0076]

[0077]

[0078] Wherein the value of R g , R s , R d can be obtained by MATLAB software in the form of curve fitting.

[0079] Wherein the Y parameter of the external circuit parameter extraction is as follows:

[0080]

[0081] A 40 = C gdo + C gso

[0082] A 50 = -C gdo

[0083] A 60 = C gdo + C jd

[0084] A 70 = C gdo 2 (R d + R g )+ C jd 2 (R d + R s + R sub )+ 2*C gdo C jd R d

[0085] Substitute the values of R g , R s , R d , C gdo , C gso and C jd into the expression of A 70 , then R sub can be obtained, and finally all the external parasitic parameters are obtained.

[0086] Step 2, in the range of 0-10GHz, use the traditional model as the low frequency band correction model to extract the internal equivalent circuit model parameters, including: obtain the complete Z parameter model by adjusting the MOSFET bias condition, the equivalent circuit diagram is shown in Figure 2 , then use the de-embedding method to remove the external circuit, peel off the internal circuit from the complete model to obtain the two-port circuit model parameters containing only internal parasitic parameters, and perform de-embedding operation on the Z parameters Z tol of the complete circuit of the device as follows:

[0087]

[0088]

[0089] Among them, Z tol2 obtained is the circuit without R g , R d , R s and the corresponding Z parameters.

[0090]

[0091] Among them, the Y parameter Y tol3 is obtained after Z tol2 is converted into Y parameter, and then the influence of the substrate network R sub and C jd is removed.

[0092]

[0093] where Y int The matrix is removed C gdo and C gso Two-port admittance parameters containing only internal parasitic parameters after.

[0094]

[0095] Simultaneous equations, the arrangement can be obtained as follows:

[0096] C gsi = M 10

[0097]

[0098] C gdi = M 30

[0099]

[0100] g m = M 60

[0101]

[0102] R ds = M 80

[0103]

[0104] Where the coefficient M 10 -M 90 The specific value can be obtained by MATLAB or Mathematica software function fitting.

[0105] Step 3, two-port model considering longitudinal distribution effect, by the original BSIM4 model gate resistance R g Multiply the impedance coefficient α g , get the gate impedance Z g Network instead of the original model of the gate resistance part, the rest of the original model remains unchanged, including: the impedance coefficient α g Molecular 1 order, denominator 2 order Padé approximation is obtained:

[0106]

[0107] Finally, the value of R g1 , R g2 , C g0 , C g1 and C g2 In the gate RC network considering longitudinal distribution effect in the modified model is as follows:

[0108]

[0109] R g1 = 5R gs

[0110] R g2 = 5R gd

[0111] C g0 = (C gso + C gdo ) / 5

[0112] C g1 = C gsi / 5

[0113] C g2 = C gdi / 5

[0114] Step 4, verify the full-band correction model in the range of 0-100GHz, including: using E max error function to evaluate the accuracy of the model:

[0115]

[0116] Wherein, Y ij model and Y ij TCAD are Y parameters obtained by the correction model ADS simulation and Y parameters obtained by the TCAD simulation, respectively.

[0117] For the single-finger MOS transistor with W=20um in the 40nm CMOS process in the embodiment, the measurement frequency range is 0-100GHz, and under the bias condition V gs =-0.6V, V ds =0V, the finally extracted external circuit parameter values are shown in Table 1:

[0118] Table 1

[0119] Resistance parameter Parameter value (Ω) Capacitance parameter Parameter value (F) [R eff ]] 593.265 C gdo ]]> 4.2047e-15 [R s ]] 6.982 [C gso ]]> 6.1770e-15 [R d ]]> 4.427 C jd ]]> 1.7165e-14 [R sub ]] 13.580

[0120] For the single-finger MOS transistor with W=20um in the 40nm CMOS process in the embodiment, the measurement frequency range is 0-100GHz, and under the bias condition V gs =0.7V, V ds =0.7V, the finally extracted internal circuit parameter values are shown in Table 2:

[0121] Table 2

[0122] Parasitic parameter Parameter value Parasitic parameter Parameter value C gsi ]]> 4.1258e-15 F [R gd ]] 715.95 Ω C gdi ]]> 5.6801e-16 F m ]]> ​ 1.1226e-12 s [R gs ]]> 318.7935 Ω g m ]]> 0.0136S [R ds ]]> 598.4614 Ω L ds ]]> 1.1669e-10 H C sdx ]]> 3.5894e-15 F

[0123] For the single-finger MOS transistor with W = 20um in the 40nm CMOS process of this embodiment, the measurement frequency range is 0-100GHz, and the bias condition is V. gs =0.7V, V ds With a voltage of 0.7V, the final extracted gate RC network parameters are shown in Table 3:

[0124] Table 3

[0125] Parasitic parameter Parameter value Parasitic parameter Parameter value C g0 ]]> 2.08e-15 F [R g1 ]]> 3579.75 Ω C g1 ]]> 1.13e-16 F [R g2 ]]> 1593.98 Ω C g1 ]]> 8.25e-16 F [R eff ]]> 593.265 Ω

[0126] Based on the parameters extracted from Table 1-3, the test results of the Y parameter of a single-finger MOS transistor with W=20um in a 40nm CMOS process, obtained using Synopsys TACD simulation, the traditional model, and the modified model, are as follows: Figures 5-12 As shown:

[0127] Figure 5 This invention provides an example of a single-finger MOS transistor with W=20um in a 40nm CMOS process, obtained using Synopsys TACD simulation, a traditional model, and a modified model, at V... gs =0.7V, V ds Y = 0.7V 11 Comparison chart of the real parts of the parameters;

[0128] Figure 6 This invention provides an example of a single-finger MOS transistor with W=20um in a 40nm CMOS process, obtained using Synopsys TACD simulation, a traditional model, and a modified model, at V... gs =0.7V, V ds Y = 0.7V 11 Comparison chart of the imaginary parts of the parameters;

[0129] Figure 7 This invention provides an example of a single-finger MOS transistor with W=20um in a 40nm CMOS process, obtained using Synopsys TACD simulation, a traditional model, and a modified model, at V... gs =0.7V, V ds Y = 0.7V 12 Comparison chart of the real parts of the parameters;

[0130] Figure 8 This invention provides an example of a single-finger MOS transistor with W=20um in a 40nm CMOS process, obtained using Synopsys TACD simulation, a traditional model, and a modified model, at V... gs =0.7V, V ds Y = 0.7V 12Comparison chart of the imaginary parts of the parameters;

[0131] Figure 9 This invention provides an example of a single-finger MOS transistor with W=20um in a 40nm CMOS process, obtained using Synopsys TACD simulation, a traditional model, and a modified model, at V... gs =0.7V, V ds Y = 0.7V 21 Comparison chart of the real parts of the parameters;

[0132] Figure 10 This invention provides an example of a single-finger MOS transistor with W=20um in a 40nm CMOS process, obtained using Synopsys TACD simulation, a traditional model, and a modified model, at V... gs =0.7V, V ds Y = 0.7V 21 Comparison chart of the imaginary parts of the parameters;

[0133] Figure 11 This invention provides an example of a single-finger MOS transistor with W=20um in a 40nm CMOS process, obtained using Synopsys TACD simulation, a traditional model, and a modified model, at V... gs =0.7V, V ds Y = 0.7V 22 Comparison chart of the real parts of the parameters;

[0134] Figure 12 This invention provides an example of a single-finger MOS transistor with W=20um in a 40nm CMOS process, obtained using Synopsys TACD simulation, a traditional model, and a modified model, at V... gs =0.7V, V ds Y = 0.7V 22 Comparison chart of the imaginary parts of the parameters;

[0135] As can be seen from the figure, the small-signal equivalent circuit correction model of this invention has higher accuracy than the traditional model and can better describe the performance of millimeter-wave MOS transistors.

[0136] The above embodiments are merely preferred implementations of the present invention and are not intended to limit the scope of protection of the present invention. Any equivalent implementations of the present invention, as well as any changes made without creative effort on this basis, should be included within the scope of the claims of the present invention.

Claims

1. A millimeter-wave MOSFET small-signal equivalent circuit modified model, characterized by, The equivalent circuit correction model includes: gate RC network R g0 , R g1 , R g2 , C g0 , C g1 and C g2 , source resistance R s , drain resistance R d , gate-source external capacitance C gso , shallow doped source level extension area resistance R gs , gate-source internal parasitic capacitance C gsi , gate-drain external capacitance C gdo , shallow doped drain extension area resistance R gd , gate-drain internal parasitic capacitance C gdi , resistance R sub of drain and substrate, capacitance C jd between source drain and substrate, current source VCCS controlled by gate voltage V gs , channel output resistance R ds between source drain, equivalent inductance L ds reflecting transistor output delay under high frequency condition, and equivalent parasitic capacitance C ds characterizing control effect of channel part carrier on drain voltage V sdx DIBL effect. The gate RC network R considering longitudinal distribution effect g0 and C g0 are connected in parallel between the external gate node G and the middle gate node G1, respectively, the gate RC network R considering longitudinal distribution effect g1 and C g1 are connected in series first and then between the external gate node G and the middle gate node G1, the gate RC network R considering longitudinal distribution effect g2 and C g2 are connected in series first and then between the external gate node G and the middle gate node G1, the source resistance R s is connected between the external source node S and the middle source node S1, the drain resistance R d is connected between the external drain node D and the middle drain node D1, the gate-source external capacitance C gso is connected between the middle gate node G1 and the middle source node S1, the shallow-doped source extension region resistance R gs and the gate-source internal parasitic capacitance C gsi are connected in series first and then between the middle gate node G1 and the middle source node S1, the gate-drain external capacitance C gdo is connected between the middle gate node G1 and the middle drain node D1, the shallow-doped drain extension region resistance R gd and the gate-drain internal parasitic capacitance C gdi are connected in series first and then between the middle gate node G1 and the middle drain node D1, the drain and substrate resistance R sub and the capacitance between the source drain and the substrate C jd are connected in series first and then between the middle drain node D1 and the middle source node S1, the voltage-controlled current source VCCS is connected between the middle drain node D1 and the middle source node S1, the channel output resistance R between the source drain ds and the equivalent inductance L ds are connected in series first and then between the middle drain node D1 and the middle source node S1, the equivalent parasitic capacitance C sdx is connected between the middle drain node D1 and the middle source node S1.

2. The method for extracting parameters of the small-signal equivalent circuit correction model of the millimeter-wave MOS transistor according to claim 1, characterized in that, The method comprises: Step 1: Within the 0-10GHz range, according to the cold field theory, when the MOSFET device is in a zero-bias state, the channel is turned off, and the device is in the cutoff region. At this time, the device is only affected by the external circuit, and the internal circuit can be ignored. The cutoff device is regarded as a two-port network. The impedance parameters, i.e., the Z-parameter matrix, of this two-port network are solved to extract the resistance R of the external circuit. g R s and R d The value of Z is obtained, and then the inverse matrix of the Z parameter matrix is ​​taken to obtain the admittance parameter, i.e., the Y parameter. The capacitance C of the external circuit is extracted using the Y parameter. gdo C gso C jd and resistance R sub The values ​​of Z and Y are obtained to derive the external circuit model. Then, the bias conditions are adjusted to put the device in a conducting state. At this point, the device is simultaneously affected by both the external and internal circuits. The conducting device is considered as a two-port network, and the Z and Y parameters are solved for this two-port network to obtain the Z-parameter matrix Z0 of the complete circuit. tol Then, the effects of the gate resistor, drain resistor, source resistor, substrate network, gate-drain external capacitance, and gate-source external capacitance are removed in sequence to achieve de-embedding and isolate the internal circuit, thereby obtaining the internal circuit model. This internal circuit model is regarded as a two-port network, and the Y-parameter matrix is ​​solved for the two-port network to extract the values ​​of various parasitic parameters of the internal circuit model. Finally, the internal and external circuit models are combined to obtain the low-frequency correction model. Step 2, in the range of 10-100GHz, the full-band modified model is obtained by calculating and using the gate RC network to replace the gate equivalent resistance, and then the AC performance of the device within 100GHz is characterized, including: first, the gate resistance Rg in the low-frequency modified model is multiplied by the impedance coefficient a g to obtain the gate impedance network Z g , the gate impedance network Z g is used to replace the gate resistance R g of the low-frequency modified model, and the rest remains unchanged; then the impedance coefficient a g is approximated by the Padé approximation with the numerator 1st order and the denominator 2nd order to obtain the simplified expression of the gate impedance Z g ; the impedance Z g contains the total gate fringing admittance Y g , and the expression of Y g contains the gate-drain capacitance C gd and the gate-source capacitance C gs , which is a function related to frequency, which makes the coefficient a g also change with frequency; finally, the capacitance and resistance are used in the form of a circuit to represent the simplified expression, and the gate RC network considering the longitudinal distribution effect is obtained and replaces the gate resistance in the low-frequency modified model; Step 3, verifying the full-band correction model in the range of 0-100 GHz, comprising: building a gate RC network in an ADS simulation tool to obtain a full-band small signal correction model of the device; and simulating in the frequency range of 0-100 GHz, comparing the simulation results of the correction model, the traditional model and TCAD, and adopting E max Error function to evaluate the accuracy of the model.

3. The parameter extraction method according to claim 2, characterized by, Solving the two-port network for impedance parameters, i.e. Z parameter matrix, to extract the resistance R of the external circuit g , R s , and R d values, in particular: Z 11 = R g + R s + (Z sub + Z gd ) || Z gs Z 22 = R s + R d + (Z gs + Z gd ) || Z sub where U1 is the voltage at port 1, U2 is the voltage at port 2, I1 is the current flowing through port 1, I2 is the current flowing through port 2, Z 11 , Z 12 , Z 21 , Z 22 are four elements in the Z parameter matrix, the impedance between the gate and the source the impedance between the source and the drain the impedance between the gate and the drain where j is the imaginary number, ω is the angular frequency, and since the external circuit is a passive network, Z 12 and Z 21 parameters are equal, and thus the relationship between the real parts of the obtained Z parameters is: where B 10 , B 11 , B 12 , B 20 , B 21 , B 22 , B 30 , B 31 , B 32 are the irrelevant terms obtained by solving, and the value of R g , R s , R d can be obtained by mathematical tools in the form of curve fitting; here the equivalent resistance of the gate R g is obtained.

4. The parameter extraction method according to claim 2, wherein, The Z parameter matrix is inverted as described in step 1 to obtain the admittance parameter, i.e. Y parameter, and the value of the capacitance C of the external circuit is extracted from the Y parameter gdo gso jd and the resistance R sub , specifically:​​ where Y 11 , Y 12 , Y 21 , Y 22 are four elements in the Y parameter matrix, A 40 = C gdo + C gso , A 50 = -C gdo , A 60 = C gdo + C jd , A 70 = C gdo 2 (R d + R g ) + C jd 2 (R d + R s + R sub ) + 2*C gdo C jd R d , ω is the angular frequency, A 41 , A 42 , A 51 , A 52 , A 61 , A 62 , A 71 , A 72 , B 40 , B 41 , B 42 , B 50 , B 51 , B 52 , B 60 , B 61 , B 62 , B 70 , B 71 , B 72 are the irrelevant terms solved, and finally the values of R g , R s , R d , C gdo , C gso and C jd are substituted into the expression of A 70 , R sub is solved, and finally all the external parasitic parameters are obtained.

5. The parameter extraction method according to claim 2, wherein Step 1 removes the effects of the gate resistance, the drain resistance, the source resistance, the substrate network, the gate-drain external capacitor and the gate-source external capacitor in sequence, realizes de-embedding, peels off the internal circuit, and thus obtains the internal circuit model, specifically as follows: Z-parameter matrix defining gate resistance and drain resistance In the Z parameter matrix, the effect of the gate resistance and the drain resistance is removed, resulting in the matrix Z tol1 : Z-parameter matrix defining source resistance In the Z parameter matrix, the effect of the source resistance is removed, resulting in the matrix Z tol2 : where Z tol2 The result is a circuit free of R g , R d , R s and the corresponding Z parameters, which are converted to Y parameters Y tol2 , defining a Y parameter matrix of the substrate network R tol2 and C sub jd ​​ In the Y parameter matrix, the influence of the substrate network R sub and C jd is removed, resulting in the matrix Y tol3 : Y-parameter matrix of the gate-drain external capacitance C gdo and the gate-source external capacitance C gso Y-parameter matrix of the gate-drain external capacitance C In the Y parameter matrix, the effect of the gate-drain external capacitance C gdo and the gate-source external capacitance C gso is removed, resulting in the matrix Y int : Y int The matrix is a two-port admittance parameter containing only internal parasitic parameters, and all the de-embedding is completed, and the external circuit has been completely removed from the complete circuit model.

6. The parameter extraction method according to claim 2, wherein Step 1 takes the internal circuit model as a two-port network, solves the Y parameter matrix of the two-port network, and extracts the values of various parasitic parameters of the internal circuit model, specifically as follows: the gate and the source are taken as port 1, and the drain and the source are taken as port 2; the two-port network of the internal circuit model satisfies the following equation: wherein, are four elements of the Y parameter matrix obtained by solving the internal circuit model, and eight rational function expressions about the angular frequency ω can be obtained by solving, and the coefficients M ij , N ij are composed of internal parasitic parameters; Where the coefficient M 10 -M 90 The specific value is obtained by function fitting using mathematical tools, which allows us to calculate the resistance R of the shallowly doped source-level extension region in the internal circuit model. gs Gate-source internal parasitic capacitance C gsi Lightly doped drain extension region resistance R gd The internal parasitic capacitance C of the gate-drain junction gdi The channel output resistance R between the source and drain ds The equivalent inductance L reflects the transistor output delay at high frequencies. ds Characterizing the drain voltage V caused by the DIBL effect ds The equivalent parasitic capacitance C of the control effect on the charge carriers in the channel sdx and gate voltage V gs The value of the controlled current source VCCS.

7. The parameter extraction method according to claim 2, wherein The impedance coefficient α is calculated as described in step 2 g Using Padé approximation of order 1 in the numerator and order 2 in the denominator, a simplified expression for the gate impedance Z g is obtained, which is given by Then the simplified expression is expressed in the form of circuit using capacitance and resistance, and the values of R g , R g1 , R g2 , C g0 , C g1 and C g2 in the gate RC network considering the longitudinal distribution effect in the modified model are as follows: R g1 = 5R gs R g2 = 5R gd C g0 = (C gso + C gdo ) / 5 C g1 = C gsi / 5 C g2 = C gdi / 5.

8. The parameter extraction method according to claim 2, wherein, E in step 3 max The error function evaluates the model as: where Y ij model and Y ij TCAD are the Y-parameters obtained from the ADS simulation with the modified model and the Y-parameters obtained from the TCAD simulation, respectively.

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