Morphological and logical separated gridding circuit diagram labeling method

Abstract

The invention relates to the field of artificial intelligence and electronic design automation, in particular to a form and logic separated gridding circuit diagram labeling method, which comprises the following steps of: 1, importing circuit data; 2, form and logic decoupling is carried out; step 3, data storage and optimization; and step 4, outputting an analysis result: step 1, extracting vector data from the EDA tool or the circuit diagram. According to the method, layout optimization is carried out through a form and logic decoupling labeling mode by adopting a self-adaptive grid technology and combining GNN, the circuit form analysis precision is improved, a circuit diagram is converted into a grid storage structure by adopting a form labeling method, the spatial analysis capability is improved, logic information can be used for training a neural network so as to learn a circuit topological structure and functions, and the circuit form analysis precision is improved. The method is used for automatically generating DSL codes, the logic annotation is used for modeling component relations, the form annotation is used for optimizing physical layout and independently processing logic and form information, the layout is optimized in combination with GNN, and the automatic design capacity of a circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of artificial intelligence and electronic design automation, in particular to a morphological and logical separation grid circuit diagram labeling method. BACKGROUND

[0002] At present, the industry's research on circuit analysis mainly focuses on the following directions: neural network-based circuit recognition: using deep learning and graph neural networks (GNN) for circuit analysis, but relying on a large amount of labeled data, and the mixed processing of logic and morphology reduces the model generalization ability; rule-based EDA tools: EDA tools usually rely on heuristic algorithms for layout optimization, but manual adjustment costs are high, and lack intelligent layout optimization capabilities; vector diagram analysis method: some studies use vectorization methods to analyze circuit structure, but there are computational bottlenecks when dealing with complex circuit topologies.

[0003] Electronic design automation (EDA) technology has made some progress in circuit analysis and generation, but there are still the following problems: logic and morphology coupling, insufficient generalization ability: existing circuit analysis methods usually rely on rule modeling or deep learning, but most methods do not distinguish between the logical structure and physical morphology of the circuit when analyzing, making it difficult for the model to adapt to circuits with different arrangements; high difficulty in analyzing circuit morphology: due to the complex spatial distribution of electronic components, directly processing raw images or circuit files requires high computational cost; existing methods are difficult to handle different types of layout styles, such as high-density IC wiring, low-density power circuits, etc.; lack of a morphological and logical separation analysis method: existing methods mix the logical and morphological information of the circuit, resulting in a decrease in the accuracy of circuit analysis in different physical layouts; morphological information affects the accuracy of logical analysis, and logical information is difficult to model independently, reducing the scalability of circuit analysis. SUMMARY

[0004] (I) Technical problems solved

[0005] To address the shortcomings of the prior art, the present application provides a morphological and logical separation grid circuit diagram labeling method, which can efficiently analyze circuit logic and morphology, improve the generalization ability of circuit analysis, and optimize the layout of large-scale circuits, etc., solving the above problems.

[0006] (II) Technical solutions

[0007] To achieve the above purpose, the present application provides the following technical solutions:

[0008] The morphological and logical separation grid circuit diagram labeling method comprises the following steps:

[0009] Step 1: Circuit data import;

[0010] Step two: decoupling of morphology and logic;

[0011] Step three: data storage and optimization;

[0012] Step four: output analysis results.

[0013] Preferably, the step one extracts vector data from EDA tools or circuit diagrams.

[0014] Preferably, the morphology part in the step two adopts grid labeling storage, mainly for circuit layout generation; the logic part adopts DSL language for description, mainly for generating overall circuit node association.

[0015] Preferably, the step three adopts an adjacency matrix to record circuit topology structure, and combines GNN to learn layout optimization strategy.

[0016] Preferably, the step four includes visualizing circuit analysis results and generating optimized circuit layout.

[0017] (Three) beneficial effects

[0018] Compared with the prior art, the present application provides a grid-based circuit diagram labeling method with separated morphology and logic, which has the following beneficial effects:

[0019] The present application adopts a grid labeling method to store the circuit morphology in a structured manner by decoupling morphology and logic, adopts a logical labeling method to efficiently analyze the topology structure of the circuit, adopts an adaptive grid technology to dynamically adjust the grid size according to the density of the circuit elements, improves the calculation efficiency, combines GNN for layout optimization, improves the accuracy of circuit morphology analysis, adopts a morphology labeling method to convert the circuit diagram into a grid storage structure, improves the spatial analysis capability, the logical information can be used to train the neural network to learn the circuit topology structure and function, and is used for automatic generation of DSL code, the logical labeling is used to model the component relationship, the morphology labeling is used to optimize the physical layout, the logical and morphology information are processed independently, the generalization ability is improved, the GNN is combined to optimize the layout, and the automatic design ability of the circuit is improved. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0021] The present application relates to a grid-based circuit diagram labeling method with separated morphology and logic, comprising the following steps:

[0022] Step one: circuit data import; extract vector data from EDA tools or circuit diagrams;

[0023] Step two: decoupling of morphology and logic; the morphology part uses grid-based annotation storage, mainly for circuit arrangement generation; the logic part uses DSL language for description, mainly for generating overall circuit node association;

[0024] The decoupling of circuit logic and morphology information is realized, and the core goals include: 1. The idea of separating morphology and logic: in circuit analysis, logical information (component association, current flow direction) and morphological information (physical layout) are annotated independently, which improves the model generalization ability; logical information can be used to generate DSL code, and also can be used to train neural networks for automatic circuit design; morphological information is used for optimizing circuit arrangement and improving circuit routing efficiency; 2. Improve the adaptability of circuit analysis: use grid-based annotation method to store the structure of circuit morphology; use logical annotation method to efficiently analyze the topological structure of circuit; 3. Optimize large-scale circuit analysis: use adaptive grid technology to dynamically adjust the grid size according to the density of circuit elements, improve the calculation efficiency; combine GNN for layout optimization to improve the accuracy of circuit morphology analysis; 4. Improve the scalability of circuit data: store logical data and morphological data hierarchically, support efficient analysis of large-scale circuits;

[0025] Step three: data storage and optimization; use adjacency matrix to record circuit topology, and combine GNN to learn layout optimization strategy;

[0026] Step four: output analysis results, including visualized circuit analysis results and generated optimized circuit layout.

[0027] The key technical points of the present application include morphology annotation: converting circuit diagrams into grid-based storage structure to improve spatial analysis capability, which includes pure node annotation: mainly used for model pre-training, only contains nodes and their positions in the grid, provides the adjacency matrix of the circuit, does not contain any node attributes; mainly used to learn the basic layout mode of the circuit, without involving element types or connection relationships; real circuit annotation: used for model fine-tuning, adds node attributes such as element type, pin information, etc. based on pure node annotation; example: in an amplifier circuit, morphology annotation may include the relative positions of resistors, capacitors, and transistors, without involving their connection relationships;

[0028] Logical annotation: which includes adjacency matrix + node information: records the types, parameters, and connection methods of circuit elements; example: in an amplifier circuit, logical annotation may describe "R1 connected to Q1 base", "C1 connected to Q1 collector";

[0029]

[0030] ​Current flow direction: record the transmission path of current in the circuit; example: mark "Vcc through R1 to Q1" as the current flow direction of the circuit in the figure;

[0031] Bias current is provided to Q1 through R1;

[0032] Logical information can be used to train neural networks to learn circuit topology and function, and

[0033] Automatic generation of DSL code;

[0034] Morphology and logic separation grid optimization:

[0035] Logical annotation is used to model component relationships, and morphological annotation is used to optimize physical layout;

[0036] Independent processing of logical and morphological information improves generalization ability;

[0037] Optimize layout with GNN to improve the automated design capability of the circuit;

[0038] Example case: in the power management circuit, logical annotation ensures the correct connection of each voltage regulator module, and morphological annotation optimizes PCB wiring to reduce signal interference; in the signal amplification circuit, logical annotation defines the connection relationship of the gain stage, input stage and output stage, and morphological annotation optimizes the layout of transistors and filters.

[0039] The beneficial effects of the present application are: through the decoupling of morphology and logic annotation, the circuit morphology is stored in a structured manner using grid annotation method, the topology of the circuit is efficiently analyzed using logical annotation method, the grid size is dynamically adjusted according to the density of circuit elements using adaptive grid technology, the calculation efficiency is improved, the layout optimization is performed using GNN to improve the accuracy of circuit morphology analysis, the circuit diagram is converted into a grid storage structure using morphological annotation method to improve spatial analysis capability, logical information can be used to train neural networks to learn circuit topology and function, and used for automatic generation of DSL code, logical annotation is used to model component relationships, and morphological annotation is used to optimize physical layout.

[0040] Although embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and alterations can be made thereto without departing from the principles and spirit of the present application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for annotating a grid-based circuit diagram with a separation of form and logic, characterized in that, Comprising the following steps: Step one: circuit data import; Step two: decoupling of morphology and logic; Step three: data storage and optimization; Step four: output analysis results.

2. The form and logic separated gridded circuit diagram annotation method of claim 1, wherein: The step one extracts vector data from EDA tools or circuit diagrams.

3. The form and logic separated gridded circuit diagram annotation method of claim 1, wherein: In the step two, the morphology part uses grid-based labeling storage, mainly for circuit arrangement generation; the logic part uses DSL language for description, mainly for generating overall circuit node association.

4. The form and logic separated gridded circuit icon annotation method of claim 1, wherein: The step three uses an adjacency matrix to record the circuit topology structure, combined with GNN learning layout optimization strategy.

5. The form and logic separated gridded circuit icon annotation method of claim 1, wherein: The step four includes visualizing circuit analysis results and generating optimized circuit layout.