A method for filling virtual patterns in a circuit layout and a circuit layout

Abstract

The application discloses a filling method of virtual patterns in a circuit layout and the circuit layout, and belongs to the technical field of semiconductors. The filling method of virtual patterns comprises the following steps: providing a circuit layout of a semiconductor device, and forming a gap virtual pattern filling area between adjacent device patterns; filling the gap virtual patterns one by one in the gap virtual pattern filling area. When filling the gap virtual patterns, the width of the serial connection pattern is determined according to the width of the gap virtual pattern filling area, and the width of the finger pattern is determined according to the length of the gap virtual pattern filling area. When filling the gap virtual patterns one by one, the number of the finger patterns in each gap virtual pattern is determined according to the to-be-filled interval of the gap virtual pattern filling area. The filling method of virtual patterns in the circuit layout and the circuit layout can improve the uniformity of the virtual patterns.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a filling method of virtual patterns in a circuit layout and a circuit layout. BACKGROUND

[0002] In the circuit layout of a semiconductor device, due to a small common process window of dense patterns and sparse patterns in device patterns, a virtual pattern is arranged around the sparse patterns to improve the quality of the device patterns in a photolithography process.

[0003] However, since the positions and quantity relationships of the virtual active patterns and the virtual gate patterns in each virtual pattern are relatively fixed, the virtual pattern cannot be filled in a small to-be-filled region, thereby causing the problem of uneven filling of the virtual pattern. The uneven filling of the virtual pattern has a great influence on the uniformity of a chemical mechanical polishing (CMP) process and an etching process. In the CMP process, there is a large difference in polishing rate when different pattern densities are processed, thereby causing surface sagging of a device region after polishing, for example, surface sagging of a shallow trench isolation structure after polishing. In the etching process, there is a large difference in etching rate when different pattern densities are processed, thereby causing the size of an active region or a polysilicon gate after etching to be inconsistent with the expectation, resulting in polysilicon residue and causing short circuit between devices. More seriously, the uneven filling of the virtual pattern causes overexposure or underexposure of a chip during a manufacturing process, thereby causing etching failure. SUMMARY

[0004] The present application aims to provide a filling method of virtual patterns in a circuit layout and a circuit layout, which can solve the problem of uneven filling of virtual patterns caused by the fact that a virtual pattern cannot be filled in a small to-be-filled region.

[0005] To solve the above technical problems, the present application is implemented by the following technical scheme:

[0006] The present application provides a filling method of virtual patterns in a circuit layout, comprising the following steps:

[0007] providing a circuit layout of a semiconductor device, and forming a gap virtual pattern filling region between adjacent device patterns; and

[0008] filling gap virtual patterns in the gap virtual pattern filling region one by one, and each gap virtual pattern comprising one string pattern and at least one finger pattern, the string pattern and the finger pattern overlapping, and the string pattern being perpendicular to each finger pattern;

[0009] The width of the serial connection pattern is determined according to the width of the gap virtual pattern filling area, and the width of the finger pattern is determined according to the length of the gap virtual pattern filling area.

[0010] In an embodiment of the present application, the length of the gap virtual pattern filling area is the distance of the gap virtual pattern filling area in the extending direction, and the direction in which the width of the gap virtual pattern filling area is located is perpendicular to the direction in which the length of the gap virtual pattern filling area is located.

[0011] In an embodiment of the present application, the finger patterns are arranged side by side, and the distance between adjacent finger patterns is equal to the width of the finger pattern.

[0012] In an embodiment of the present application, when the extending direction of the first gap virtual pattern filling area is the extending direction of the active pattern in the device pattern, in the first gap virtual pattern filling area, the serial connection pattern is a virtual active pattern, and the finger pattern is a virtual gate pattern.

[0013] In an embodiment of the present application, in the first gap virtual pattern filling area, the width of the serial connection pattern is less than one third of the width of the first gap virtual pattern filling area, and the width of the serial connection pattern is less than an upper limit value of the width of the virtual active pattern; the width of the finger pattern is less than one third of the length of the first gap virtual pattern filling area, and the width of the finger pattern is less than an upper limit value of the width of the virtual gate pattern.

[0014] In an embodiment of the present application, when the extending direction of the second gap virtual pattern filling area is the extending direction of the gate pattern in the device pattern, in the second gap virtual pattern filling area, the serial connection pattern is a virtual gate pattern, and the finger pattern is a virtual active pattern.

[0015] In an embodiment of the present application, in the second gap virtual pattern filling area, the width of the serial connection pattern is less than one third of the width of the second gap virtual pattern filling area, and the width of the serial connection pattern is less than an upper limit value of the width of the virtual gate pattern; the width of the finger pattern is less than one third of the length of the second gap virtual pattern filling area, and the width of the finger pattern is less than an upper limit value of the width of the virtual active pattern.

[0016] In an embodiment of the present application, when filling the first gap dummy pattern in the gap dummy pattern filling area, the interval to be filled in the gap dummy pattern filling area is equal to the length of the gap dummy pattern filling area, and when filling the gap dummy pattern other than the first one in the gap dummy pattern filling area, the interval to be filled in the gap dummy pattern filling area is equal to the length of the gap dummy pattern filling area minus the distance of the gap dummy pattern that has been filled.

[0017] In an embodiment of the present application, in each of the gap dummy patterns, the number of the finger patterns ranges from 1 to 5.

[0018] The present application also provides a circuit layout, comprising:

[0019] a plurality of device patterns, and a gap dummy pattern filling area formed between adjacent device patterns; and

[0020] a gap dummy pattern, and each of the gap dummy patterns comprises a string pattern and at least one finger pattern, the string pattern and the finger pattern overlap, and the string pattern is perpendicular to each of the finger patterns;

[0021] wherein, when filling the gap dummy pattern, the width of the string pattern is determined according to the width of the gap dummy pattern filling area, the width of the finger pattern is determined according to the length of the gap dummy pattern filling area, and when filling the gap dummy pattern one by one, the number of the finger patterns in each of the gap dummy patterns is determined according to the interval to be filled in the gap dummy pattern filling area.

[0022] In summary, the present application provides a filling method of virtual patterns in a circuit layout and a circuit layout, and the unexpected effect is that when the extending direction of the gap dummy pattern filling area is different, the type of the string pattern and the finger pattern can be changed, so that the overall structure of the gap dummy pattern, including the string pattern and the finger pattern connected by the string pattern, is unchanged. When the interval to be filled in the gap dummy pattern filling area is insufficient to accommodate the gap dummy pattern including the maximum number of finger patterns, the number of finger patterns in the gap dummy pattern can be adjusted according to the interval to be filled, so that the gap dummy pattern filling area is uniformly filled with the gap dummy pattern, ensuring the process quality and thus the quality of the shallow trench isolation structure, the active area and the gate. The filling method of virtual patterns in the circuit layout provided by the present application can also be used in combination with the traditional filling of virtual patterns.

[0023] Of course, implementing any product of the present application does not necessarily require all the advantages described above to be achieved at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart of a method for filling virtual graphics in a circuit layout in one embodiment.

[0026] Figure 2 This is a schematic diagram of a circuit layout structure without virtual graphics in one embodiment.

[0027] Figure 3 This is a schematic diagram of the circuit layout structure after filling the annular virtual graphic filling area with virtual graphics in one embodiment.

[0028] Figure 4 This is a flowchart illustrating the process of filling a virtual graphic in the first gap virtual graphic filling area in one embodiment.

[0029] Figure 5 This is a flowchart illustrating the process of filling a virtual graphic in the virtual graphic filling area of ​​the second gap, as described in one embodiment.

[0030] Figure 6 This is a schematic diagram of the circuit layout structure after filling in virtual graphics in one embodiment.

[0031] Figure 7 for Figure 6 A schematic diagram of the circuit layout structure of the virtual graphic filling area in the middle gap.

[0032] Label Explanation:

[0033] 101. Device pattern; 1011. Active pattern; 1012. Gate pattern; 102. Annular virtual pattern filled area; 103. Gap virtual pattern filled area; 1031. First gap virtual pattern filled area; 1032. Second gap virtual pattern filled area; 104. First annular virtual pattern; 1041. First annular simulated active pattern; 1042. First annular simulated gate pattern; 105. Second annular virtual pattern; 1051. Second annular simulated active pattern; 1052. Second annular simulated gate pattern; 201. First gap virtual pattern; 2011. First serial connection pattern; 2012. First finger pattern; 301. Second gap virtual pattern; 3011. Second serial connection pattern; 3012. Second finger pattern. Detailed Implementation

[0034] Following, the embodiments of the present application will be described in detail by specific examples. Other advantages and effects of the present application can be easily understood by those skilled in the art from this disclosure. The present application can also be implemented or applied by other different embodiments, and various modifications or changes can be made to the details in this specification based on different views and applications without departing from the spirit of the present application.

[0035] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The shapes, number and proportions of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0036] In the present application, it should be noted that, when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like appear, the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, when the terms "first" and "second" appear, they are only for description and differentiation purposes, and cannot be understood as indicating or implying relative importance.

[0037] In the process of semiconductor integrated circuits, first, the circuit design is performed, and then the circuit design scheme is formed into a circuit layout through layout design, and the circuit layout is transferred to a mask. For example, the circuit layout can be exposed by an electron beam exposure machine, and the pattern is exposed to the mask, and then the pattern is accurately imaged on the mask through development, dry etching and other processes. After the mask is formed, the mask pattern can be transferred to the wafer by photolithography, and the required semiconductor integrated circuit can be formed.

[0038] In the layout pattern of semiconductor design, there are dense patterns and sparse patterns in the device pattern, but the photolithography process window of the dense pattern and the sparse pattern is not consistent. The exposure conditions suitable for the dense pattern in the layout may not be suitable for the exposure of the sparse pattern. Therefore, for a circuit layout that contains both dense patterns and sparse patterns, the common process window is relatively small. A virtual pattern can be set around the sparse pattern of the layout. The virtual pattern can scatter light, and improve the depth of focus during the exposure process.

[0039] Please refer to Figures 1 to 7As shown, the present application provides a filling method of virtual patterns in a circuit layout, which can fill the virtual patterns uniformly in the gaps between adjacent device patterns 101, thereby ensuring the uniformity of the virtual pattern filling. Specifically, the filling method of virtual patterns in a circuit layout provided by the present application comprises steps S10 to S30.

[0040] Step S10, providing a circuit layout of a semiconductor device, which comprises a plurality of device patterns.

[0041] Step S20, forming at least one layer of annular virtual patterns in the annular virtual pattern filling area surrounding the plurality of device patterns and outside the plurality of device patterns.

[0042] Step S30, in the gap virtual pattern filling area between adjacent device patterns, determining the width of the virtual string pattern and the width and number of the finger pattern according to the size of the gap virtual pattern filling area to be filled.

[0043] Please refer to Figure 2 As shown, in an embodiment of the present application, the circuit layout of the semiconductor device comprises a plurality of device patterns 101. The plurality of device patterns 101 are arranged in an array, and an annular virtual pattern filling area 102 is arranged around the periphery of the plurality of device patterns 101 arranged in an array. In the plurality of device patterns 101 arranged in an array, a gap virtual pattern filling area 103 is formed by arranging a spacing between each device pattern 101. In this application, a source pattern 1011 and a gate pattern 1012 are arranged in the device pattern 101, and the source pattern 1011 and the gate pattern 1012 are arranged in an overlapping manner, and the extension direction of the source pattern 1011 is perpendicular to the extension direction of the gate pattern 1012. In this application, for the convenience of description, the extension direction of the source pattern 1011 in the device pattern 101 is defined as the first direction X, and the direction perpendicular to the extension direction of the source pattern 1011 is defined as the second direction Y.

[0044] Please refer to Figures 1 to 2 As shown, in this application, the order of steps S20 and S30 is not limited, that is, when filling the virtual pattern, step S20 can be performed first, and then step S30 can be performed. That is, the virtual pattern is first formed in the annular virtual pattern filling area 102 outside the plurality of device patterns 101, and then the virtual pattern is formed in the gap virtual pattern filling area 103 between adjacent device patterns 101. Step S30 can be performed first, and then step S20 can be performed. That is, the virtual pattern is first formed in the gap virtual pattern filling area 103 between adjacent device patterns 101, and then the virtual pattern is formed in the annular virtual pattern filling area 102 outside the plurality of device patterns 101.

[0045] Please refer to Figure 2As shown in the embodiment of the present application, a plurality of device patterns 101 are arranged in an array. A plurality of device patterns 101 are surrounded by a ring-shaped dummy pattern filling region 102.

[0046] As shown in the embodiment of the present application, a plurality of device patterns 101 are arranged in an array. A plurality of device patterns 101 are surrounded by a ring-shaped dummy pattern filling region 102. Figure 2 As shown in the embodiment of the present application, a plurality of device patterns 101 are arranged in an array. A plurality of device patterns 101 are surrounded by a ring-shaped dummy pattern filling region 102.

[0047] As shown in the embodiment of the present application, a plurality of device patterns 101 are arranged in an array. A plurality of device patterns 101 are surrounded by a ring-shaped dummy pattern filling region 102. Figure 2 and Figure 3 As shown in the embodiment of the present application, a plurality of device patterns 101 are arranged in an array. A plurality of device patterns 101 are surrounded by a ring-shaped dummy pattern filling region 102.

[0048] As shown in the embodiment of the present application, a plurality of device patterns 101 are arranged in an array. A plurality of device patterns 101 are surrounded by a ring-shaped dummy pattern filling region 102. Figure 2 and Figure 3As shown, in one embodiment of the present invention, a plurality of first annular virtual patterns 104 surround a plurality of device patterns 101 arranged in an array. Each first annular virtual pattern 104 has the same structure and size. Each first annular virtual pattern 104 includes a first annular analog active pattern 1041 and at least one first annular analog gate pattern 1042. The first annular analog active pattern 1041 and the active pattern 1011 in the device pattern 101 both extend along a first direction X, and the first annular analog gate pattern 1042 and the gate pattern 1012 in the device pattern 101 both extend along a second direction Y. The first annular analog gate patterns 1042 are arranged in parallel, and each first annular analog gate pattern 1042 overlaps with a first annular analog active pattern 1041. In a first annular virtual pattern 104, the spacing between adjacent first annular analog gate patterns 1042 is equal. In this embodiment, both the first annular analog active pattern 1041 and the first annular analog gate pattern 1042 are arranged in a square shape. The dimensions of the first annular simulated active pattern 1041 and the first annular simulated gate pattern 1042 are set in conjunction with the size of the annular virtual pattern filling region 102 and the limited size of the virtual pattern. In this embodiment, the size of the annular virtual pattern filling region 102 is greater than the upper limit of the virtual pattern size. Therefore, the dimensions of the first annular simulated active pattern 1041 and the first annular simulated gate pattern 1042 are set to the upper limit of the simulated active pattern and simulated gate pattern sizes. The number of first annular simulated gate patterns 1042 in each first annular virtual pattern 104 is also the upper limit of the number of simulated gate patterns, for example, 5.

[0049] Please see Figure 2 and Figure 3As shown in the figure, in an embodiment of the present application, a plurality of second ring-shaped dummy patterns 105 are arranged around the plurality of device patterns 101 arranged in an array, and the second ring-shaped dummy patterns 105 are located between the device patterns 101 and the first ring-shaped dummy pattern 104. Each of the second ring-shaped dummy patterns 105 has the same structure and size. The second ring-shaped dummy pattern 105 includes a second ring-shaped simulated active pattern 1051 and at least one second ring-shaped simulated gate pattern 1052. The second ring-shaped simulated active pattern 1051 extends along the first direction X like the active pattern 1011 in the device pattern 101, and the second ring-shaped simulated gate pattern 1052 extends along the second direction Y like the gate pattern 1012 in the device pattern 101. The second ring-shaped simulated gate patterns 1052 are arranged in parallel, and each of the second ring-shaped simulated gate patterns 1052 overlaps the second ring-shaped simulated active pattern 1051. In one second ring-shaped dummy pattern 105, the distance between adjacent second ring-shaped simulated gate patterns 1052 is equal. In this embodiment, the second ring-shaped simulated active pattern 1051 and the second ring-shaped simulated gate pattern 1052 are both arranged in a square shape. The size of the second ring-shaped simulated active pattern 1051 and the second ring-shaped simulated gate pattern 1052 is set in combination with the size of the ring-shaped dummy pattern filling area 102 and the limit size of the dummy pattern. In this embodiment, after the first ring-shaped dummy pattern 104 is filled, the size of the second ring-shaped dummy pattern 105 is reduced because the remaining area of the ring-shaped dummy pattern filling area 102 is not enough to fill a dummy pattern with a size equal to the upper limit of the size of the dummy pattern. The size of the second ring-shaped simulated active pattern 1051 and the second ring-shaped simulated gate pattern 1052 in the second ring-shaped dummy pattern 105, and the number of the second ring-shaped simulated gate patterns 1052 in each second ring-shaped dummy pattern 105 are set according to the size of the remaining area to be filled in the ring-shaped dummy pattern filling area 102. The size of the second ring-shaped simulated active pattern 1051 and the second ring-shaped simulated gate pattern 1052, and the number of the second ring-shaped simulated gate patterns 1052 in each second ring-shaped dummy pattern 105 can gradually decrease from the upper limit of the size of the simulated active pattern and the simulated gate pattern, and the upper limit of the number of the simulated gate pattern, until the size of the second ring-shaped simulated active pattern 1051 and the second ring-shaped simulated gate pattern 1052, and the number of the second ring-shaped simulated gate patterns 1052 in each second ring-shaped dummy pattern 105 meet the size of the remaining area to be filled in the ring-shaped dummy pattern filling area 102.

[0050] As shown in the figure, Figure 2 and Figure 3 It should be noted that, in other embodiments, if there is still a ring-shaped dummy pattern filling area 102 to be filled after two layers of ring-shaped dummy patterns are arranged, a third ring-shaped dummy pattern or a fourth ring-shaped dummy pattern can be arranged inside the second ring-shaped dummy pattern 105 in sequence. If the size of the ring-shaped dummy pattern filling area 102 is small, only the first ring-shaped dummy pattern 104 can be arranged in the ring-shaped dummy pattern filling area 102.

[0051] As shown in the figure,Figures 1 to 7 As shown in the figure, in an embodiment of the present application, in step S30, when filling the gap virtual patterns in the gap virtual pattern filling area 103, each gap virtual pattern comprises a serial pattern and at least one finger pattern, the serial pattern and the finger pattern overlap, and the serial pattern is perpendicular to each finger pattern. Specifically, when filling the gap virtual patterns, the width of the serial pattern is determined according to the width of the gap virtual pattern filling area 103, and the width of the finger pattern is determined according to the length of the gap virtual pattern filling area 103. When filling the gap virtual patterns one by one, the number of the finger patterns in each gap virtual pattern is determined according to the gap to be filled in the gap virtual pattern filling area 103. Wherein, the length of the gap virtual pattern filling area 103 is the distance of the gap virtual pattern filling area 103 in the extending direction, and the direction of the width of the gap virtual pattern filling area 103 is perpendicular to the direction of the length of the gap virtual pattern filling area 103.

[0052] Please refer to Figures 4 to 7 As shown in the figure, in an embodiment of the present application, when the extending direction of the gap virtual pattern filling area 103 is different, in order to meet the shape requirement of the formed gap virtual patterns, the type of the serial pattern and the finger pattern can be flexibly set, that is, the serial pattern can be a virtual active pattern or a virtual gate pattern, and the finger pattern can be a virtual gate pattern or a virtual active pattern.

[0053] Please refer to Figures 4 to 7 As shown in the figure, in an embodiment of the present application, the maximum width of the serial pattern and the finger pattern is set according to the type of the pattern. When the serial pattern is a virtual active pattern, the maximum width of the serial pattern is less than the upper limit value of the width of the virtual active pattern. When the serial pattern is a virtual gate pattern, the maximum width of the serial pattern is less than the upper limit value of the width of the virtual gate pattern. When the finger pattern is a virtual active pattern, the maximum width of the finger pattern is less than the upper limit value of the width of the virtual active pattern. When the finger pattern is a virtual gate pattern, the maximum width of the finger pattern is less than the upper limit value of the width of the virtual gate pattern.

[0054] Please refer to Figures 4 to 7 As shown in the figure, in an embodiment of the present application, in a gap virtual pattern, the number of the finger patterns ranges from 1 to 5, when the number of the finger patterns is greater than 1, the finger patterns are arranged side by side, the distance between the adjacent finger patterns is equal, and the distance between the adjacent finger patterns is equal to the width of the finger pattern.

[0055] Please refer to Figures 4 to 7As shown in the figure, in an embodiment of the present application, first gap virtual pattern filling area 1031 and second gap virtual pattern filling area 1032 are arranged between adjacent graphic devices. First gap virtual pattern filling area 1031 and second gap virtual pattern filling area 1032 are arranged in a strip shape, and first gap virtual pattern filling area 1031 extends along first direction X, and second gap virtual pattern filling area 1032 extends along second direction Y. Then, the serial connection pattern in first gap virtual pattern filling area 1031 extends along first direction X, the finger pattern in first gap virtual pattern filling area 1031 extends along second direction Y, the serial connection pattern in second gap virtual pattern filling area 1032 extends along second direction Y, and the finger pattern in second gap virtual pattern filling area 1032 extends along first direction X.

[0056] Please refer to Figures 4 to 7 As shown in the figure, in an embodiment of the present application, first gap virtual pattern 201 is filled in first gap virtual pattern filling area 1031, and first gap virtual pattern 201 includes first serial connection pattern 2011 and first finger pattern 2012, and first serial connection pattern 2011 is virtual active pattern, and first finger pattern 2012 is virtual gate pattern. At this time, when first gap virtual pattern 201 is filled in first gap virtual pattern filling area 1031, it specifically includes steps S3011 to S3013.

[0057] Step S3011, the width of first serial connection pattern is determined according to the width of first gap virtual pattern filling area.

[0058] Please refer to Figures 4 to 7 As shown in the figure, in an embodiment of the present application, the width of first serial connection pattern 2011 is less than one third of the width of first gap virtual pattern filling area 1031. At the same time, the width of first serial connection pattern 2011 is less than the upper limit value of virtual active pattern width. Wherein, the upper limit value of virtual active pattern width is determined according to photolithography process.

[0059] Step S3012, the width of first finger pattern in first gap virtual pattern is determined according to the length of first gap virtual pattern filling area.

[0060] Please refer to Figures 4 to 7 As shown in the figure, in an embodiment of the present application, the width of first finger pattern 2012 is less than one third of the length of first gap virtual pattern filling area 1031. At the same time, the width of first finger pattern 2012 is less than the upper limit value of virtual gate pattern width. Wherein, the upper limit value of virtual gate pattern width is determined according to photolithography process.

[0061] Step S3013: Determine the number of first finger-shaped graphics in each first gap virtual graphic based on the spacing to be filled in the first gap virtual graphic filling area.

[0062] Please see Figures 4 to 7 As shown, in one embodiment of the present invention, when filling the first gap virtual graphic 201 in the first gap virtual graphic filling area 1031, the spacing to be filled in the first gap virtual graphic filling area 1031 is equal to the length of the first gap virtual graphic filling area 1031. When filling the first gap virtual graphic filling area 1031 with any first gap virtual graphic 201 other than the first one, the spacing to be filled in the first gap virtual graphic filling area 1031 is equal to the length of the first gap virtual graphic filling area 1031 minus the length of the already filled first gap virtual graphic 201. When filling the first gap virtual graphic filling area 1031 with any first gap virtual graphic 201 other than the second one, the spacing to be filled in the first gap virtual graphic filling area 1031 is as follows: Figure 7 The length H1 shown is given.

[0063] Please see Figures 4 to 7 As shown, in one embodiment of the present invention, when filling the first gap virtual graphic 201 in the first gap virtual graphic filling area 1031, if the gap to be filled in the first gap virtual graphic filling area 1031 is long enough, then the number of first finger-shaped graphics 2012 in the first gap virtual graphic 201 is set to the maximum value of the number of finger-shaped graphics, for example, 5. That is, the first gap virtual graphic 201 includes a first serial graphic 2011 and five first finger-shaped graphics 2012 connected in series by the first serial graphic 2011. When filling the second gap virtual graphic 201 in the first gap virtual graphic filling area 1031, if the gap to be filled in the first gap virtual graphic filling area 1031 cannot accommodate five finger-shaped graphics, then the number of first finger-shaped graphics 2012 in the second gap virtual graphic 201 is set to 4. That is, the second gap virtual graphic 201 includes a first serial graphic 2011 and four first finger-shaped graphics 2012 connected in series by the first serial graphic 2011. In other embodiments, the first gap virtual graphic 201 that is filled last may also include three, two or one first finger graphic 2012.

[0064] Please see Figures 4 to 7As shown, in one embodiment of the present invention, a second gap virtual pattern 301 is filled in the second gap virtual pattern filling region 1032. The second gap virtual pattern 301 includes a second serial pattern 3011 and a second finger pattern 3012, wherein the second serial pattern 3011 is a virtual gate pattern and the second finger pattern 3012 is a virtual active pattern. When filling the second gap virtual pattern 301 in the second gap virtual pattern filling region 1032, steps S3021 to S3023 are specifically included.

[0065] Step S3021: Determine the width of the second serialized graphic based on the width of the filling area of ​​the second gap virtual graphic.

[0066] Please see Figures 4 to 7 As shown, in one embodiment of the present invention, the width of the second serial connection pattern 3011 is less than one-third of the spacing between the device patterns 101. Simultaneously, the width of the second serial connection pattern 3011 is less than the upper limit of the width of the virtual gate pattern. The upper limit of the width of the virtual gate pattern is determined based on the photolithography process.

[0067] Step S3022: Determine the width of the second finger-shaped graphic in the second gap virtual graphic based on the length of the filling area of ​​the second gap virtual graphic.

[0068] Please see Figures 4 to 7 As shown, in one embodiment of the present invention, the width of the second finger-shaped graphic 3012 is less than one-third of the length of the second gap virtual graphic filling area 1032. Simultaneously, the width of the second finger-shaped graphic 3012 is less than the upper limit of the width of the virtual active graphic.

[0069] Step S3023: Determine the number of second finger-shaped graphics in each second gap virtual graphic based on the spacing to be filled in the second gap virtual graphic filling area.

[0070] Please see Figures 4 to 7 As shown, in one embodiment of the present invention, when filling the second gap virtual graphic filling area 1032 with a first second gap virtual graphic 301, the spacing to be filled in the second gap virtual graphic filling area 1032 is equal to the length of the second gap virtual graphic filling area 1032. When filling the second gap virtual graphic filling area 1032 with a second gap virtual graphic 301 other than the first one, the spacing to be filled in the second gap virtual graphic filling area 1032 is equal to the length of the second gap virtual graphic filling area 1032 minus the length of the already filled second gap virtual graphic 301. When filling the second gap virtual graphic filling area 1032 with a second second gap virtual graphic 301, the spacing to be filled in the second gap virtual graphic filling area 1032 is as follows: Figure 7 The length H2 is shown.

[0071] Please refer to Figures 4 to 7 As shown in the figure, in an embodiment of the present application, when filling the first second-gap virtual pattern 301 in the second-gap virtual pattern filling area 1032, if the distance to be filled in the second-gap virtual pattern filling area 1032 is long enough, the number of the second finger pattern 3012 in the first second-gap virtual pattern 301 is set to the maximum number of the finger pattern, for example, 5. That is, the first second-gap virtual pattern 301 includes the second concatenated pattern 3011 and five second finger patterns 3012 concatenated by the second concatenated pattern 3011. When filling the second second-gap virtual pattern 301 in the second-gap virtual pattern filling area 1032, if the distance to be filled in the second-gap virtual pattern filling area 1032 can accommodate five finger patterns, the number of the second finger pattern 3012 in the second second-gap virtual pattern 301 is set to 5. That is, the second second-gap virtual pattern 301 includes the second concatenated pattern 3011 and five second finger patterns 3012 concatenated by the second concatenated pattern 3011. In other embodiments, the last filled second-gap virtual pattern 301 can also include four, three, two or one second finger pattern 3012.

[0072] Please refer to Figures 1 to 7 As shown in the figure, the present application also provides a circuit layout, which is provided with the circuit layout formed by the filling method of the virtual pattern in the circuit layout as described above. In the formed circuit layout, there are annular virtual pattern filling areas and gap virtual pattern filling areas. In the annular virtual pattern filling areas, there are annular virtual patterns formed by the method as described above, and in each gap virtual pattern filling area, there are gap virtual patterns formed by the method as described above.

[0073] The application provides a filling method of virtual patterns in a circuit layout and the circuit layout, and the filling method comprises the following steps: providing a circuit layout of semiconductor devices, and forming a gap virtual pattern filling area between adjacent device patterns; filling gap virtual patterns one by one in the gap virtual pattern filling area, and each gap virtual pattern comprises a string pattern and at least one finger pattern, the string pattern and the finger pattern overlap, and the string pattern is perpendicular to each finger pattern; wherein, when filling the gap virtual patterns, the width of the string pattern is determined according to the width of the gap virtual pattern filling area, and the width of the finger pattern is determined according to the length of the gap virtual pattern filling area, and when filling the gap virtual patterns one by one, the number of the finger patterns in each gap virtual pattern is determined according to the to-be-filled interval of the gap virtual pattern filling area. The filling method of virtual patterns in a circuit layout and the circuit layout have the unexpected effect that: when the extension direction of the gap virtual pattern filling area is different, the type of the string pattern and the finger pattern can be changed, so that the overall structure of the gap virtual pattern, including the string pattern and the finger pattern connected by the string pattern, is unchanged. When the to-be-filled interval of the gap virtual pattern filling area is insufficient to accommodate a gap virtual pattern comprising a maximum number of finger patterns, the number of finger patterns in the gap virtual pattern can be adjusted according to the to-be-filled interval, so that the gap virtual pattern filling area is uniformly filled with gap virtual patterns, the process quality is ensured, and the quality of the shallow trench isolation structure, the active region and the gate is ensured. Moreover, the filling method of virtual patterns in a circuit layout provided by the application can also be used in combination with the traditional filling of virtual patterns.

[0074] The above disclosed embodiments of the application are only used to help explain the application. The embodiments do not describe all the details, nor limit the application to the specific embodiments. Obviously, according to the content of the specification, many modifications and changes can be made. The specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the application, so that those skilled in the art can well understand and utilize the application. The application is limited by the claims and their entire scope and equivalents.

Claims

1. A method for filling virtual graphics in a circuit layout, characterized in that, Includes the following steps: A circuit layout of a semiconductor device is provided, and a gap virtual graphic fill area is formed between adjacent device patterns; as well as The gap virtual graphic filling area is filled one by one with gap virtual graphics, and each gap virtual graphic includes a serial graphic and at least one finger graphic, the serial graphic and the finger graphic overlap, and the serial graphic is perpendicular to each finger graphic; Specifically, when filling the gap virtual graphics, the width of the serial graphics is first determined based on the width of the filling area of ​​the gap virtual graphics, and the width of the finger graphics is determined based on the length of the filling area of ​​the gap virtual graphics. When filling the gap virtual graphics one by one, the number of finger graphics in each gap virtual graphics is determined based on the spacing to be filled in the filling area of ​​the gap virtual graphics. When the extension direction of the first gap virtual graphic filling region is the extension direction of the active graphic in the device pattern, the serial graphic in the first gap virtual graphic filling region is a virtual active graphic, and the finger graphic is a virtual gate graphic. When the extension direction of the second gap virtual graphic filling region is the extension direction of the gate graphic in the device pattern, the serial pattern is a virtual gate graphic and the finger pattern is a virtual active graphic in the second gap virtual graphic filling region.

2. The method for filling virtual graphics according to claim 1, characterized in that, The length of the gap virtual graphic filling area is the distance of the gap virtual graphic filling area in the extending direction, and the direction of the width of the gap virtual graphic filling area is perpendicular to the direction of the length of the gap virtual graphic filling area.

3. The method for filling virtual graphics according to claim 1, characterized in that, The finger-shaped patterns are arranged side by side, and the distance between adjacent finger-shaped patterns is equal to the width of the finger-shaped patterns.

4. The method for filling virtual graphics according to claim 1, characterized in that, In the first gap virtual graphic filling region, the width of the serial graphic is less than one-third of the width of the first gap virtual graphic filling region, and the width of the serial graphic is less than the upper limit of the width of the virtual active graphic; the width of the finger graphic is less than one-third of the length of the first gap virtual graphic filling region, and the width of the finger graphic is less than the upper limit of the width of the virtual gate graphic.

5. The method for filling virtual graphics according to claim 1, characterized in that, In the second gap virtual pattern filling region, the width of the serial pattern is less than one-third of the width of the second gap virtual pattern filling region, and the width of the serial pattern is less than the upper limit of the width of the virtual gate pattern; the width of the finger pattern is less than one-third of the length of the second gap virtual pattern filling region, and the width of the finger pattern is less than the upper limit of the width of the virtual active pattern.

6. The method for filling virtual graphics according to claim 1, characterized in that, When filling the gap virtual graphic filling area with the first gap virtual graphic, the unfilled spacing of the gap virtual graphic filling area is equal to the length of the gap virtual graphic filling area. When filling the gap virtual graphic filling area with gap virtual graphics other than the first one, the unfilled spacing of the gap virtual graphic filling area is equal to the length of the gap virtual graphic filling area minus the distance of the already filled gap virtual graphics.

7. The method for filling virtual graphics according to claim 1, characterized in that, In each of the said gap virtual graphics, the number of the finger-shaped graphics ranges from 1 to 5.

8. A circuit layout, characterized in that, include: Multiple device patterns, with gap virtual graphic filling areas formed between adjacent device patterns; as well as In the gap virtual graphics, each gap virtual graphics includes a concatenated graphic and at least one finger-shaped graphic, the concatenated graphic and the finger-shaped graphic overlap, and the concatenated graphic is perpendicular to each finger-shaped graphic; Specifically, when filling the gap virtual graphics, the width of the serial graphics is first determined based on the width of the filling area of ​​the gap virtual graphics, and the width of the finger graphics is determined based on the length of the filling area of ​​the gap virtual graphics. When filling the gap virtual graphics one by one, the number of finger graphics in each gap virtual graphics is determined based on the spacing to be filled in the filling area of ​​the gap virtual graphics. When the extension direction of the first gap virtual graphic filling region is the extension direction of the active graphic in the device pattern, the serial graphic in the first gap virtual graphic filling region is a virtual active graphic, and the finger graphic is a virtual gate graphic. When the extension direction of the second gap virtual graphic filling region is the extension direction of the gate graphic in the device pattern, the serial pattern is a virtual gate graphic and the finger pattern is a virtual active graphic in the second gap virtual graphic filling region.

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