A method and system for stress relief in a high-power semiconductor device

Abstract

This invention relates to the field of semiconductor technology, specifically a method and system for stress relief within a high-power semiconductor device. The method includes: assessing the stress sensitivity of different regions of the chip based on chip material and structural data to obtain estimated stress generation data for each region; evaluating the stability of stress distribution in different regions of the chip under various semiconductor driving schemes based on the estimated stress generation data and semiconductor operating status data, determining whether the switching parameters of each region need adjustment; and obtaining and implementing a semiconductor driving scheme based on the evaluation results of the stability of stress distribution in different regions of the chip under various driving schemes. This method proactively assesses the stability of stress distribution at different points under different schemes during the driving scheme design phase, thereby enabling adaptive adjustment of switching parameters and improving the reliability and lifespan of high-power semiconductor devices under dynamic operating conditions.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and is a method and system for stress relief in high-power semiconductors. Background Technology

[0002] With the rapid development of power semiconductor technology, its application in the field of high-power converters for electric vehicle traction inverters is becoming increasingly widespread; high-power insulated gate bipolar transistor modules are gradually replacing traditional power devices due to their advantages such as high power density and high switching frequency; reliable and efficient stress control is the core objective of improving the life and reliability of semiconductor devices, and stress management strategies directly determine the thermal fatigue life, mechanical integrity and ultimate system reliability of the devices.

[0003] However, current mainstream semiconductor stress management technologies still have the following significant drawbacks: First, most stress management solutions are based on the assumption of uniform heat generation of devices under steady-state conditions, using fixed heat sinks and uniform thermal conductive materials for heat dissipation and stress buffering; the core problem is that they ignore the heterogeneity of multiple physical fields that objectively exist inside the chip; due to uneven current density distribution, concentrated switching losses, and mismatch of material thermal expansion coefficients, the thermal and mechanical stresses of the device often vary significantly at different locations on the chip; uniform static design inevitably leads to stress concentration in some areas, accelerating material fatigue, while over-design in some areas results in cost waste and increased system size;

[0004] Secondly, existing technologies typically pre-set based on ideal steady-state or single operating conditions during the design phase. However, in actual operation, semiconductor devices are inevitably affected by dynamic factors such as frequent switching operations, sudden load changes, and changes in cooling conditions. These factors can trigger strong coupling of multiple physical fields such as electro-thermal-mechanical fields, resulting in instantaneous thermal shock and alternating stress, the amplitude and distribution of which far exceed the scope of static design. Especially in the center of the chip and the root area of ​​the bonding wire, cracks, delamination, or solder fatigue are prone to occur. Existing methods lack a real-time assessment and compensation mechanism for the stability of stress distribution in semiconductors under actual dynamic operating conditions.

[0005] In addition, existing methods usually treat chip design, drive parameter setting, and thermal management as relatively independent modules. The decision on whether to adjust the switching parameters to mitigate stress impact is often based on simple rules or post-failure analysis. There is a lack of forward-looking assessment of the stress distribution stability of each chip region under different drive strategies during the drive scheme design stage, and the selection of suitable drive and stress co-management schemes accordingly. Summary of the Invention

[0006] The purpose of this section is to outline some aspects of embodiments of the present invention and to briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0007] This invention proposes a technical solution for stress relief in high-power semiconductors, comprising the following steps:

[0008] S1: Obtain reference semiconductor device stress tolerance data, reference switch parameter adjustment data, semiconductor operating status data, and chip material and structure data;

[0009] S2: Based on chip material and structure data, assess the stress sensitivity of each region of the chip, and obtain the estimated stress generation data for each region of the chip based on the assessment results.

[0010] S3: Based on the estimated stress generation data of each region of the chip and the semiconductor operating status data, evaluate the stability of stress distribution in each region of the chip in each semiconductor driving scheme, and determine whether the switching operation parameters of each region of the chip in each semiconductor driving scheme need to be adjusted according to the evaluation results.

[0011] S4: Obtain the semiconductor driving operation scheme by evaluating the stability of stress distribution in each region of the chip in each semiconductor driving scheme, and perform semiconductor switching operation according to the obtained semiconductor driving operation scheme.

[0012] It should be noted that, as a preferred technical solution for stress relief in a high-power semiconductor device, the specific steps of S1 are as follows:

[0013] S11: Obtain reference semiconductor device stress tolerance data and reference switch parameter adjustment data from the database;

[0014] S12: Obtain semiconductor operating status data from the database, including junction temperature fluctuation data, current density data of each region of the chip in each semiconductor driving scheme, and switching loss data.

[0015] S13: Obtain chip material and structural data through thermistors, chip simulation models, and structural scanning;

[0016] The chip material and structure data include: thermal expansion coefficient data for each region of the chip and thermal conductivity data for interlayer materials of the chip.

[0017] S14: Store the collected data in the storage component for use in the analysis process.

[0018] It should be noted that, as a preferred technical solution for stress relief in a high-power semiconductor device, the specific steps of S2 are as follows:

[0019] S21: Based on the thermal expansion coefficient data of each region of the chip and the thermal conductivity data of the interlayer material of the chip, the stress sensitivity of each region of the chip is evaluated. The formula for calculating the stress sensitivity evaluation value of the i-th region of the chip is as follows:

[0020] ;

[0021] Where i is the number corresponding to each region of the chip; i is any one of 1 to N; Let be the actual coefficient of thermal expansion of the material in the i-th region of the chip; This is a reference value for the coefficient of thermal expansion of the chip substrate material; It is the thermo-mechanical coupling coefficient; Let be the thermal conductivity of the interlayer interface material in the i-th region of the chip. Let be the thermal conductivity of the bulk material of the i-th region of the chip;

[0022] It should be noted that in this formula Its function is to reflect the potential for thermal stress generation in different regions of the chip due to differences in material composition or process. Its function is to describe the intensity of the thermo-mechanical coupling effect caused by heat flow passing through the interface of different materials; A decay factor describing the effect of interfacial thermal resistance on overall thermal stress; As a benchmark, By comparing the thermal conductivity of the quantified interface with that of the bulk material, the degree of heat flow obstruction and the corresponding risk of heat concentration are reflected; in this formula... Some studies compare the actual thermal expansion effect with theoretical expectations based on interface characteristics, quantifying the stress sensitivity of various regions in the chip caused by material mismatch and interface thermal resistance. The results are positively correlated with the amount of stress generated, i.e., the stress sensitivity assessment value of a certain area of ​​the chip. The larger the value, the greater the potential stress generation in that region during operation;

[0023] S22: Obtain the stress sensitivity assessment results for each region of the chip, and obtain the estimated stress generation amount for each region of the chip based on the stress sensitivity assessment values ​​for each region of the chip and the stress tolerance data of the reference semiconductor device.

[0024] It should be noted that, as a preferred technical solution for stress relief in a high-power semiconductor device, the specific steps of S3 are as follows:

[0025] S31: Evaluate the electrothermal stability of each semiconductor driving scheme by using the estimated current load data and junction temperature fluctuation data of each region of the chip in each semiconductor driving scheme.

[0026] S32: Evaluate the dynamic response of thermal stress in each region of the chip in each semiconductor driving scheme based on the switching loss distribution data and instantaneous junction temperature data in each region of the chip in each semiconductor driving scheme.

[0027] S33: Obtain the calculated electrothermal stability evaluation results of each semiconductor driving scheme and the dynamic response evaluation results of thermal stress in each region of the chip in each semiconductor driving scheme;

[0028] S34: The evaluation results of the electrothermal stability of each semiconductor driving scheme are negatively correlated and then weighted and added to the evaluation results of the dynamic response of thermal stress in each region of the chip in each semiconductor driving scheme to obtain the evaluation value of the stress distribution stability of each region of the chip in each semiconductor driving scheme.

[0029] It should be noted that the purpose of negative correlation conversion of the electrothermal stability evaluation results of various semiconductor driving schemes is to establish a positive correlation between electrothermal instability and stress distribution instability. By comprehensively evaluating the electrothermal stability evaluation results of various semiconductor driving schemes and the dynamic response evaluation results of thermal stress in various regions of the chip in various semiconductor driving schemes, the evaluation value of stress distribution stability in various regions of the chip in various semiconductor driving schemes is evaluated, thereby improving the accuracy of the evaluation value.

[0030] S35: Based on the stability assessment value of stress distribution in each region of the chip in each semiconductor driving scheme, determine whether the switching operation parameters of each region of the chip in each semiconductor driving scheme need to be adjusted, and mark the regions of the chip in each semiconductor driving scheme that need to be adjusted as the parameter adjustment regions.

[0031] S36: Obtain the required parameter adjustment amount for each parameter adjustment area by taking the stress distribution stability assessment value of each region of the chip in each semiconductor driving scheme that needs adjustment and the reference switch parameter adjustment amount data. Then, perform switch parameter adjustment processing on each parameter adjustment area according to the required parameter adjustment amount.

[0032] It should be noted that, as a preferred technical solution for stress relief in a high-power semiconductor device, the specific steps of S31 are as follows:

[0033] S311: Obtain the estimated stress generation amount in each region of the chip and the data of each semiconductor driving scheme, and obtain the estimated current load in each region of the chip in each semiconductor driving scheme based on the estimated stress generation amount in each region of the chip and the data of each semiconductor driving scheme.

[0034] S312: Based on the estimated current load data and junction temperature fluctuation data of each region of the chip in each semiconductor driving scheme, the electrothermal stability of each semiconductor driving scheme is evaluated. The calculation formula for the electrothermal stability of the j-th semiconductor driving scheme is as follows: Where j is the number corresponding to each semiconductor driving scheme, and j is any one of 1 to M. To estimate the current density of the i-th region of the chip in the j-th driving scheme of the semiconductor, For reference average current density, Let be the junction temperature fluctuation amplitude of the i-th region of the chip in the j-th driving scheme of the semiconductor. This represents the maximum allowable junction temperature fluctuation. It should be noted that in this formula... This directly reflects the degree of electrical load concentration in different areas of the chip under different driving schemes; As a benchmark for measuring the uniformity of current distribution; This reflects the intensity of transient thermal shock caused by switching losses and current concentration; Used for normalization, characterizing the thermal shock resistance of devices; in this formula Part of it represents the non-uniformity of current distribution, used to quantify local fluctuations in electrical load; in this formula The severity of thermal shock is partially quantified by the ratio of junction temperature fluctuation to the maximum permissible fluctuation; in this formula... The overall electrothermal stability was evaluated by comprehensively considering the electrothermal performance of all regions of the chip under different driving schemes. The smaller the value, the more stable the electrothermal state under this driving scheme, and the lower the risk of stress generation.

[0035] It should be noted that, as a preferred technical solution for stress relief in a high-power semiconductor device, the specific steps of S32 are as follows:

[0036] Based on the switching loss distribution data and instantaneous junction temperature data of each region of the chip in various semiconductor driving schemes, the dynamic response of thermal stress in each region of the chip in various semiconductor driving schemes is evaluated. The calculation formula for the dynamic response of thermal stress in the i-th region of the chip in the j-th semiconductor driving scheme is as follows:

[0037] ;

[0038] in, One work cycle; Let be the switching loss of the i-th region of the chip in the j-th driving scheme of the semiconductor at time t within the period; For reference average switching losses; The instantaneous junction temperature of the i-th region of the chip in the j-th driving scheme of the semiconductor at time t within the period; This is the rated junction temperature; Maximum allowable junction temperature;

[0039] It should be noted that in this formula It represents a complete dynamic working process; This represents transient power loss, which is the direct source of thermal stress. This is a temperature influence factor used to amplify the contribution of switching losses to stress generation at high junction temperatures, reflecting the accelerating effect of temperature on material performance degradation and stress increase. This formula uses a time integral form to accumulate the dynamic thermal stress response over a complete operating cycle, comprehensively considering switching losses and their temperature effects. The evaluation value... The lower the value, the more moderate the dynamic response of thermal stress in the region under this driving scheme, and the more stable the stress distribution.

[0040] It should be noted that, as a preferred technical solution for stress relief in a high-power semiconductor device, the specific steps of S35 are as follows:

[0041] The system obtains the stress distribution stability assessment value of each region of the chip in each semiconductor driving scheme. This value is then compared with a set stress distribution stability assessment threshold. If the stress distribution stability assessment value of a certain region of the chip in a particular semiconductor driving scheme is greater than the set threshold, it is determined that the switching parameters of that region of the chip in that driving scheme do not need adjustment. If the stress distribution stability assessment value of a certain region of the chip in a particular semiconductor driving scheme is less than or equal to the set threshold, it is determined that the switching parameters of that region of the chip in that driving scheme need adjustment. The region of the chip in that driving scheme corresponding to this stress distribution stability assessment value is marked as the parameter adjustment region. This method is used to obtain the parameter adjustment regions.

[0042] It should be noted that, as a preferred technical solution for stress relief in a high-power semiconductor device, the specific steps of S36 are as follows:

[0043] Obtain the stress distribution stability assessment value corresponding to each parameter adjustment area. Based on the stress distribution stability assessment value corresponding to each parameter adjustment area and the reference switch parameter adjustment data, obtain the required parameter adjustment amount for each parameter adjustment area. Among them, the formula for calculating the required switch on-time adjustment amount for the y-th parameter adjustment area is:

[0044] ;

[0045] Where y is the number corresponding to each parameter adjustment region, and y is any one of the terms from 1 to b. The threshold value for stress distribution stability assessment. This represents the stress distribution stability assessment value corresponding to the adjustment region of the y-th parameter. Adjust the baseline amount for the set reference activation time. It should be noted that... The minimum range of parameter adjustment is defined in this formula; Partially reflects the stress distribution stability assessment value The lower the current level, the greater the required adjustment in a nonlinear relationship. The rate of current change during switching can be reduced by appropriately extending the turn-on time. and voltage change rate This smooths out the switching process, reducing instantaneous losses and thermal shock.

[0046] It should be noted that, as a preferred technical solution for stress relief in a high-power semiconductor device, the specific steps of S4 are as follows:

[0047] The process involves obtaining the stress distribution stability assessment values ​​for each region of the chip in each semiconductor driving scheme, calculating the arithmetic mean of these values ​​to obtain the overall stress distribution stability assessment value for each driving scheme, and then sorting these values ​​in ascending order. The scheme ranked first is selected as the semiconductor driving scheme. It should be noted that by comprehensively evaluating the stress distribution stability of the entire chip across all regions, a global driving scheme is selected, which improves the scientific rigor and reliability of the scheme selection.

[0048] In addition, the stress relief system in a high-power semiconductor device according to the present invention includes the following modules:

[0049] The system includes a stress control data acquisition module, a chip stress sensitivity assessment module, a drive scheme stability assessment module, and a drive scheme output module.

[0050] The stress control data acquisition module is used to acquire reference semiconductor device stress tolerance data, reference switch parameter adjustment data, semiconductor operating status data, and chip material and structure data;

[0051] The chip stress sensitivity assessment module is used to assess the stress sensitivity of each region of the chip based on chip material and structure data, and to obtain the estimated stress generation data of each region of the chip based on the stress sensitivity assessment results.

[0052] The drive scheme stability evaluation module is used to evaluate the stress distribution stability of each region of the chip in each drive scheme based on the estimated stress generation data of each region of the chip and the semiconductor operating status data, and to determine whether the switching operation parameters of each region of the chip in each drive scheme need to be adjusted based on the evaluation results.

[0053] The drive scheme output module is used to obtain a semiconductor drive operation scheme by evaluating the stability of stress distribution in each region of the chip in each semiconductor drive scheme, and to control the semiconductor to perform switching operations according to the obtained semiconductor drive operation scheme.

[0054] Compared with the prior art, the technical effects of the present invention are as follows:

[0055] 1. This invention obtains reference semiconductor device stress tolerance data, reference switch parameter adjustment data, semiconductor operating status data, and chip material and structure data; based on the chip material and structure data, it evaluates the stress sensitivity of each region of the chip, and obtains the estimated stress generation data of each region of the chip based on the stress sensitivity evaluation results;

[0056] 2. This invention evaluates the stability of stress distribution in each region of the chip in each semiconductor driving scheme based on the estimated stress generation data and semiconductor operating status data. Based on the evaluation results, it determines whether the switching operation parameters of each region of the chip in each semiconductor driving scheme need to be adjusted.

[0057] 3. This invention obtains a semiconductor driving operation scheme by evaluating the stability of stress distribution in various regions of the chip under different driving schemes. The semiconductor switching operation is controlled according to the obtained scheme. In the driving scheme design stage, the stability of stress distribution in various regions of the chip under different driving strategies is evaluated in advance. The stress is actively managed by intelligently adjusting the switching parameters, thereby significantly improving the reliability and lifespan of the device under dynamic operating conditions. Attached Figure Description

[0058] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0059] Figure 1 This is a schematic flowchart of a stress relief method for a high-power semiconductor according to the present invention.

[0060] Figure 2 This is a schematic diagram of the structure of a stress relief system in a high-power semiconductor according to the present invention. Detailed Implementation

[0061] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0062] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0063] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0064] Example 1:

[0065] like Figure 1 As shown, an embodiment of the present invention provides a stress relief method for a high-power semiconductor, such as... Figure 1 As shown, the specific steps include the following:

[0066] S1: Obtain reference semiconductor device stress tolerance data, reference switch parameter adjustment data, semiconductor operating status data, and chip material and structure data;

[0067] In this embodiment, the specific steps of S1 are as follows:

[0068] S11: Obtain reference semiconductor device stress tolerance data and reference switch parameter adjustment data from the database;

[0069] S12: Obtain semiconductor operating status data from the database, including junction temperature fluctuation data, current density data of each region of the chip in each semiconductor driving scheme, and switching loss data.

[0070] S13: Obtain chip material and structure data through thermistors, chip simulation models and structural scanning. The chip material and structure data includes thermal expansion coefficient data of each region of the chip and thermal conductivity data of interlayer materials of the chip.

[0071] S14: Store the collected data in the storage component for use in the analysis process.

[0072] In one implementation of this invention, reference semiconductor device stress tolerance data and reference switch parameter adjustment data are obtained from a database to analyze the stress threshold that the semiconductor can withstand and the baseline amount of switch parameter adjustment when stress management is performed in various regions of the chip, preventing stress exceeding limits and causing failure. Chip material and structure data, including thermal expansion coefficient data for various regions of the chip and thermal conductivity data for interlayer materials, are obtained through thermistors, chip simulation models, and structural scanning to analyze the inherent stress generation potential of various regions of the chip. Semiconductor operating status data, including junction temperature fluctuation data, current density data for various regions of the chip in various semiconductor driving schemes, and switching loss data, are obtained from a database to analyze the stability of stress distribution in various regions of the chip in various semiconductor driving schemes. Poor stress distribution stability will directly affect device reliability and lifespan.

[0073] S2: Based on chip material and structure data, assess the stress sensitivity of each region of the chip, and obtain the estimated stress generation data for each region of the chip based on the assessment results.

[0074] In this embodiment, S2 includes the following specific steps:

[0075] S21: Based on the thermal expansion coefficient data of each region of the chip and the thermal conductivity data of the interlayer material, the stress sensitivity of each region of the chip is evaluated. The formula for calculating the stress sensitivity of the i-th region of the chip is as follows:

[0076] ;

[0077] Where i is the number corresponding to each region of the chip; i is any one of 1 to N; Let be the actual coefficient of thermal expansion of the material in the i-th region of the chip; This is a reference value for the coefficient of thermal expansion of the chip substrate material; It is the thermo-mechanical coupling coefficient; Let be the thermal conductivity of the interlayer interface material in the i-th region of the chip. Let be the thermal conductivity of the bulk material of the i-th region of the chip;

[0078] It should be noted that in this formula Its function is to reflect the potential for thermal stress generation in different regions of the chip due to differences in material composition or process. Its function is to describe the intensity of the thermo-mechanical coupling effect caused by heat flow passing through the interface of different materials; A decay factor describing the effect of interfacial thermal resistance on overall thermal stress; As a benchmark, By comparing the thermal conductivity of the quantified interface with that of the bulk material, the degree of heat flow obstruction and the corresponding risk of heat concentration are reflected; in this formula... Some studies compare the actual thermal expansion effect with theoretical expectations based on interface characteristics, quantifying the stress sensitivity of various regions in the chip caused by material mismatch and interface thermal resistance. The results are positively correlated with the amount of stress generated, i.e., the stress sensitivity assessment value of a certain area of ​​the chip. The larger the value, the greater the potential stress generation in that region during operation;

[0079] For example, this formula combines the thermo-mechanical coupling coefficient to calculate the theoretical thermal stress sensitivity of the chip under the influence of material interface characteristics. By comparing it with the actual thermal expansion characteristics of the material, the accuracy of the stress sensitivity assessment value is improved. It is suitable for assessing the risk of interface delamination of multilayer chips under thermal cycling.

[0080] S22: Obtain the stress sensitivity assessment results for each region of the chip. Based on the stress sensitivity assessment values ​​for each region of the chip and the stress tolerance data of the reference semiconductor device, obtain the estimated stress generation amount for each region of the chip. It should be noted that by comprehensively analyzing the stress sensitivity assessment values ​​for each region of the chip and the stress tolerance data of the reference semiconductor device, the stress level that may be generated in each region of the chip under dynamic operating conditions is improved, thus improving the accuracy of the estimated stress generation amount for each region of the chip.

[0081] S3: Based on the estimated stress generation data of each region of the chip and the semiconductor operating status data, evaluate the stability of stress distribution in each region of the chip in each semiconductor driving scheme, and determine whether the switching operation parameters of each region of the chip in each semiconductor driving scheme need to be adjusted according to the evaluation results.

[0082] In this embodiment, the specific steps of S3 are as follows:

[0083] S31: Evaluate the electrothermal stability of each semiconductor driving scheme by using the estimated current load data and junction temperature fluctuation data of each region of the chip in each semiconductor driving scheme.

[0084] In this embodiment, the specific steps of S31 are as follows:

[0085] S311: Obtain the estimated stress generation amount in each region of the chip and the data of each semiconductor driving scheme, and obtain the estimated current load in each region of the chip in each semiconductor driving scheme based on the estimated stress generation amount in each region of the chip and the data of each semiconductor driving scheme.

[0086] S312: Based on the estimated current load data and junction temperature fluctuation data of each region of the chip in each semiconductor driving scheme, the electrothermal stability of each semiconductor driving scheme is evaluated. The formula for calculating the electrothermal stability evaluation result of the j-th semiconductor driving scheme is as follows:

[0087] Where j is the number corresponding to each semiconductor driving scheme, and j is any one of 1 to M. To estimate the current density of the i-th region of the chip in the j-th driving scheme of the semiconductor, For reference average current density, Let be the junction temperature fluctuation amplitude of the i-th region of the chip in the j-th driving scheme of the semiconductor. This represents the maximum allowable junction temperature fluctuation. It should be noted that in this formula... It directly reflects the concentration of electrical load in different areas of the chip under different driving schemes; As a benchmark for measuring the uniformity of current distribution; This reflects the intensity of transient thermal shock caused by switching losses and current concentration; Used for normalization, characterizing the thermal shock resistance of devices; in this formula Part of it represents the non-uniformity of current distribution, used to quantify local fluctuations in electrical load; in this formula The severity of thermal shock is partially quantified by the ratio of junction temperature fluctuation to the maximum permissible fluctuation; in this formula... By comprehensively evaluating the electrothermal performance of all regions of the chip in different driving schemes, the overall electrothermal stability is assessed, and the electrothermal stability evaluation results of the j-th semiconductor driving scheme are obtained. The smaller the value, the more stable the electrothermal state under the driving scheme, and the lower the risk of stress generation.

[0088] For example, this formula comprehensively evaluates the electrothermal stability of semiconductor chips under different driving schemes. By taking into account the uniformity of current distribution and the amplitude of junction temperature fluctuations, it can effectively identify high-risk driving strategies that are prone to hot spots and fatigue failures, providing a quantitative basis for optimizing driving schemes and helping to improve the service life of devices under harsh conditions.

[0089] S32: Evaluate the dynamic response of thermal stress in each region of the chip in each semiconductor driving scheme based on the switching loss distribution data and instantaneous junction temperature data in each region of the chip in each semiconductor driving scheme.

[0090] In this embodiment, the specific steps of S32 are as follows:

[0091] Based on the switching loss distribution data and instantaneous junction temperature data of each region of the chip in various semiconductor driving schemes, the dynamic response of thermal stress in each region of the chip in various semiconductor driving schemes is evaluated. The calculation formula for the dynamic response of thermal stress in the i-th region of the chip in the j-th semiconductor driving scheme is as follows:

[0092] ;

[0093] in, One work cycle; Let be the switching loss of the i-th region of the chip in the j-th driving scheme of the semiconductor at time t within the period; For reference average switching losses; The instantaneous junction temperature of the i-th region of the chip in the j-th driving scheme of the semiconductor at time t within the period; This is the rated junction temperature; Maximum allowable junction temperature;

[0094] It should be noted that in this formula It represents a complete dynamic working process; This represents transient power loss, which is the direct source of thermal stress. This is a temperature influence factor used to amplify the contribution of switching losses to stress generation at high junction temperatures, reflecting the accelerating effect of temperature on material performance degradation and stress increase. This formula uses a time integral form to accumulate the dynamic thermal stress response over a complete operating cycle, comprehensively considering switching losses and their temperature effects. The evaluation value... The lower the value, the more moderate the dynamic response of thermal stress in the region under this driving scheme, and the more stable the stress distribution.

[0095] For example, it should be noted that this formula, by introducing a temperature influence factor and integral calculation, can accurately capture the stress shock amplification effect caused by switching action at high junction temperatures. This is crucial for evaluating the device lifespan under frequent acceleration and braking conditions of electric vehicles, and avoids the underestimation of transient stress shock by traditional average power consumption evaluation methods.

[0096] S33: Obtain the calculated electrothermal stability evaluation results of each semiconductor driving scheme and the dynamic response evaluation results of thermal stress in each region of the chip in each semiconductor driving scheme;

[0097] S34: The electrothermal stability evaluation results of each semiconductor driving scheme are negatively correlated and then weighted and added to the dynamic response evaluation results of thermal stress in each region of the chip in each semiconductor driving scheme to obtain the stress distribution stability evaluation value of each region of the chip in each semiconductor driving scheme. It should be noted that the purpose of negatively correlated conversion of the electrothermal stability evaluation results of each semiconductor driving scheme is to establish a positive correlation between electrothermal instability and stress distribution instability. By comprehensively evaluating the electrothermal stability evaluation results of each semiconductor driving scheme and the dynamic response evaluation results of thermal stress in each region of the chip in each semiconductor driving scheme, the accuracy of the evaluation value is improved.

[0098] S35: Based on the stability assessment value of stress distribution in each region of the chip in each semiconductor driving scheme, determine whether the switching parameters need to be adjusted during the switching operation of each region of the chip in each semiconductor driving scheme. Mark the regions of the chip in each semiconductor driving scheme that need adjustment as the parameter adjustment regions.

[0099] In this embodiment, the specific steps of S35 are as follows:

[0100] The system obtains the stress distribution stability assessment value of each region of the chip in each semiconductor driving scheme. This value is then compared with a set stress distribution stability assessment threshold. If the stress distribution stability assessment value of a certain region of the chip in a particular semiconductor driving scheme is greater than the set threshold, it is determined that the switching parameters of that region of the chip in that driving scheme do not need adjustment. If the stress distribution stability assessment value of a certain region of the chip in a particular semiconductor driving scheme is less than or equal to the set threshold, it is determined that the switching parameters of that region of the chip in that driving scheme need adjustment. The region of the chip in that driving scheme corresponding to this stress distribution stability assessment value is marked as the parameter adjustment region. This method is used to obtain the parameter adjustment regions.

[0101] S36: Obtain the required parameter adjustment amount for each parameter adjustment area by taking the stress distribution stability assessment value of each region of the chip in each semiconductor driving scheme that needs adjustment and the reference switch parameter adjustment amount data. Then, perform switch parameter adjustment processing on each parameter adjustment area according to the required parameter adjustment amount.

[0102] In this embodiment, the specific steps of S36 are as follows:

[0103] Obtain the stress distribution stability assessment value corresponding to each parameter adjustment area. Based on the stress distribution stability assessment value corresponding to each parameter adjustment area and the reference switch parameter adjustment data, obtain the required parameter adjustment amount for each parameter adjustment area. Among them, the formula for calculating the required switch on-time adjustment amount for the y-th parameter adjustment area is:

[0104] ;

[0105] Where y is the number corresponding to each parameter adjustment region, and y is any one of the terms from 1 to b. The threshold value for stress distribution stability assessment. This represents the stress distribution stability assessment value corresponding to the adjustment region of the y-th parameter. Adjust the baseline amount for the set reference activation time. It should be noted that... Determine the minimum extension time to avoid A value of 0 indicates insufficient stress management; in this formula Partially reflects the stress distribution stability assessment value The lower the value (i.e., the more unstable), the greater the required adjustment in a nonlinear relationship; (Example provided). The setting is based on the principle that the minimum adjustment should be ensured when the stress distribution stability assessment value is equal to the threshold, so as to prevent stress shock. The value can be set based on the device's safe operating area and the system response speed requirements.

[0106] S4: Obtain the semiconductor driving operation scheme by evaluating the stability of stress distribution in each region of the chip in each semiconductor driving scheme, and perform semiconductor switching operation according to the obtained semiconductor driving operation scheme.

[0107] In this embodiment, the specific steps of S4 are as follows:

[0108] The stability assessment values ​​of stress distribution in each region of the chip in each semiconductor driving scheme are obtained. The arithmetic mean of these values ​​is then calculated to obtain the overall stress distribution stability assessment value for each driving scheme. These values ​​are then sorted in ascending order (smaller values ​​indicate more stable overall stress distribution), and the scheme ranked first is selected as the semiconductor driving scheme. It should be noted that by comprehensively analyzing the stress distribution stability assessment values ​​of all regions of the chip in each driving scheme, the overall stress management performance of each driving scheme is improved, enhancing the accuracy and global optimization of driving scheme selection.

[0109] It should be noted that the parameters set in this embodiment (such as weights and thresholds) need to be set by those skilled in the art based on relevant experiments. The specific experimental method is as follows: obtain reference semiconductor device stress tolerance data, reference switch parameter adjustment data, semiconductor operating status data, and chip material and structure data, substitute them into each step of this embodiment to calculate the stress distribution stability evaluation value of each driving scheme, obtain the ascending order of the overall stress distribution stability evaluation value of the driving scheme and the implementation results of each semiconductor driving scheme (such as the actual junction temperature distribution observed by a thermal imager and the lifetime data obtained by accelerated life test), import the driving scheme evaluation ranking results and the actual implementation results into the fitting software for continuous fitting, and output the stress distribution stability evaluation value that conforms to the set parameters (such as weights and thresholds) of the semiconductor driving scheme.

[0110] Example 2:

[0111] like Figure 2 As shown, an embodiment of the present invention provides a stress relief system within a high-power semiconductor, such as... Figure 2 As shown, it includes the following modules:

[0112] The system includes a stress control data acquisition module, a chip stress sensitivity assessment module, a drive scheme stability assessment module, and a drive scheme output module.

[0113] The stress control data acquisition module is used to acquire reference semiconductor device stress tolerance data, reference switch parameter adjustment data, semiconductor operating status data, and chip material and structure data;

[0114] The chip stress sensitivity assessment module is used to assess the stress sensitivity of each region of the chip based on chip material and structure data, and to obtain the estimated stress generation data of each region of the chip based on the stress sensitivity assessment results.

[0115] The drive scheme stability evaluation module is used to evaluate the stress distribution stability of each region of the chip in each drive scheme based on the estimated stress generation data of each region of the chip and the semiconductor operating status data, and to determine whether the switching operation parameters of each region of the chip in each drive scheme need to be adjusted based on the evaluation results.

[0116] The drive scheme output module is used to obtain a semiconductor drive operation scheme by evaluating the stability of stress distribution in each region of the chip in each semiconductor drive scheme, and to control the semiconductor to perform switching operations according to the obtained semiconductor drive operation scheme.

[0117] Example 3:

[0118] This embodiment provides an electronic device, including: a processor and a memory, wherein the memory stores a computer program that can be called by the processor;

[0119] The processor executes the stress relief method described above in a high-power semiconductor by calling a computer program stored in memory.

[0120] The electronic device can vary considerably depending on its configuration or performance. It may include one or more Central Processing Units (CPUs) and one or more memories, wherein the memory stores at least one computer program, which is loaded and executed by the processor to implement the stress relief method for a high-power semiconductor provided in the above-described method embodiment. The electronic device may also include other components for implementing its functions; for example, it may have wired or wireless network interfaces and input / output interfaces for data input and output. Further details are omitted here.

[0121] Example 4:

[0122] This embodiment proposes a computer-readable storage medium on which an erasable and rewritable computer program is stored.

[0123] When a computer program runs on a computer device, it causes the computer device to perform the stress relief method described above in a high-power semiconductor.

[0124] For example, computer-readable storage media can be read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage devices.

[0125] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0126] It should be understood that determining B based on A does not mean determining B solely based on A; it also means determining B based on A and / or other information.

[0127] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the flow or function according to the embodiments of the present invention is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired network and / or wireless network. A computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. Semiconductor media can be solid-state drives (SSDs).

[0128] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0129] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0130] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only one method, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0131] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0132] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0133] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0134] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A method for stress relief in a high-power semiconductor device, characterized in that, The method includes the following specific steps: S1: Obtain reference semiconductor device stress tolerance data, reference switch parameter adjustment data, semiconductor operating status data, and chip material and structure data; S2: Based on chip material and structure data, assess the stress sensitivity of each region of the chip, and obtain the estimated stress generation data for each region of the chip based on the assessment results. S3: Based on the estimated stress generation data of each region of the chip and the semiconductor operating status data, evaluate the stability of stress distribution in each region of the chip in each semiconductor driving scheme, and determine whether the switching operation parameters of each region of the chip in each semiconductor driving scheme need to be adjusted according to the evaluation results. S3 includes: Based on the switching loss distribution data and instantaneous junction temperature data of each region of the chip in various semiconductor driving schemes, the dynamic response of thermal stress in each region of the chip in various semiconductor driving schemes is evaluated. Specifically, the evaluation result of the dynamic response of thermal stress in the ith region of the chip in the j-th semiconductor driving scheme is presented. The calculation formula is: ； in, One work cycle; Let be the switching loss of the i-th region of the chip in the j-th driving scheme of the semiconductor at time t within the period; For reference average switching losses; The instantaneous junction temperature of the i-th region of the chip in the j-th driving scheme of the semiconductor at time t within the period; This is the rated junction temperature; Maximum allowable junction temperature; S3 further includes: Obtain the stress distribution stability assessment value corresponding to each parameter adjustment area. Based on the stress distribution stability assessment value corresponding to each parameter adjustment area and the reference switch parameter adjustment data, obtain the required parameter adjustment amount for each parameter adjustment area. Among them, the required switch on-time adjustment amount for the y-th parameter adjustment area is... The calculation formula is: ； Where y is the number corresponding to each parameter adjustment region. The threshold value for stress distribution stability assessment. This represents the stress distribution stability assessment value corresponding to the adjustment region of the y-th parameter. Adjust the baseline amount for the set reference activation time; S4: Obtain the semiconductor driving operation scheme by evaluating the stability of stress distribution in each region of the chip in each semiconductor driving scheme, and perform semiconductor switching operation according to the obtained semiconductor driving operation scheme.

2. The stress relief method in a high-power semiconductor device according to claim 1, characterized in that, S2 includes: S21: Based on the thermal expansion coefficient data of each region of the chip and the thermal conductivity data of the interlayer material of the chip, the stress sensitivity of each region of the chip is evaluated; S22: Obtain the stress sensitivity assessment results for each region of the chip, and obtain the estimated stress generation amount for each region of the chip based on the stress sensitivity assessment values ​​for each region of the chip and the stress tolerance data of the reference semiconductor device.

3. The stress relief method in a high-power semiconductor device according to claim 2, characterized in that, S3 includes: S31: Evaluate the electrothermal stability of each semiconductor driving scheme by using the estimated current load data and junction temperature fluctuation data of each region of the chip in each semiconductor driving scheme. S32: Evaluate the dynamic response of thermal stress in each region of the chip in each semiconductor driving scheme based on the switching loss distribution data and instantaneous junction temperature data in each region of the chip in each semiconductor driving scheme. S33: Obtain the calculated electrothermal stability evaluation results of each semiconductor driving scheme and the dynamic response evaluation results of thermal stress in each region of the chip in each semiconductor driving scheme; S34: The evaluation results of the electrothermal stability of each semiconductor driving scheme are negatively correlated and then weighted and added to the evaluation results of the dynamic response of thermal stress in each region of the chip in each semiconductor driving scheme to obtain the evaluation value of the stress distribution stability of each region of the chip in each semiconductor driving scheme. S35: Based on the stability assessment value of stress distribution in each region of the chip in each semiconductor driving scheme, determine whether the switching parameters need to be adjusted during the switching operation of each region of the chip in each semiconductor driving scheme. Mark the regions of the chip in each semiconductor driving scheme that need adjustment as the parameter adjustment regions. S36: Obtain the required parameter adjustment amount for each parameter adjustment area by taking the stress distribution stability assessment value of each region of the chip in each semiconductor driving scheme that needs adjustment and the reference switch parameter adjustment amount data. Then, perform switch parameter adjustment processing on each parameter adjustment area according to the required parameter adjustment amount.

4. The stress relief method in a high-power semiconductor device according to claim 3, characterized in that, S31 further includes: S311: Obtain the estimated stress generation amount in each region of the chip and the data of each semiconductor driving scheme, and obtain the estimated current load in each region of the chip in each semiconductor driving scheme based on the estimated stress generation amount in each region of the chip and the data of each semiconductor driving scheme. S312: Evaluation value of the electrothermal stability of each semiconductor driving scheme based on the estimated current load data and junction temperature fluctuation data of each region of the chip in each semiconductor driving scheme.

5. The stress relief method in a high-power semiconductor device according to claim 4, characterized in that, The S35 includes: Obtain the stress distribution stability assessment value of each region of the chip in each semiconductor driving scheme. Compare the stress distribution stability assessment value of each region of the chip in each semiconductor driving scheme with the set stress distribution stability assessment value threshold. If the stress distribution stability assessment value of a certain region of the chip in a certain semiconductor driving scheme is greater than the set stress distribution stability assessment value threshold, it is determined that the switching parameter of that region of the chip in that driving scheme does not need to be adjusted. If the stress distribution stability assessment value of a certain region of the chip in a certain semiconductor driving scheme is less than or equal to the set stress distribution stability assessment value threshold, it is determined that the switching parameter of that region of the chip in that driving scheme needs to be adjusted. Mark the region of the chip in that driving scheme corresponding to this stress distribution stability assessment value as the parameter adjustment region to obtain each parameter adjustment region.

6. The stress relief method in a high-power semiconductor device according to claim 5, characterized in that, S4 includes: Obtain the stress distribution stability assessment value of each region of the chip in each semiconductor driving scheme. Calculate the arithmetic mean of the stress distribution stability assessment values ​​of each region of the chip in each semiconductor driving scheme to obtain the overall stress distribution stability assessment value corresponding to each semiconductor driving scheme. Sort the overall stress distribution stability assessment values ​​corresponding to each semiconductor driving scheme in ascending order and take the one ranked first as the semiconductor driving operation scheme.

7. A stress relief system for a high-power semiconductor, used to implement the stress relief method for a high-power semiconductor as described in any one of claims 1-6, characterized in that, The system includes the following modules: The system includes a stress control data acquisition module, a chip stress sensitivity assessment module, a drive scheme stability assessment module, and a drive scheme output module. The stress control data acquisition module is used to acquire reference semiconductor device stress tolerance data, reference switch parameter adjustment data, semiconductor operating status data, and chip material and structure data; The chip stress sensitivity assessment module is used to assess the stress sensitivity of each region of the chip based on chip material and structure data, and to obtain the estimated stress generation data of each region of the chip based on the stress sensitivity assessment results. The drive scheme stability evaluation module is used to evaluate the stress distribution stability of each region of the chip in each drive scheme based on the estimated stress generation data of each region of the chip and the semiconductor operating status data, and to determine whether the switching operation parameters of each region of the chip in each drive scheme need to be adjusted based on the evaluation results. The drive scheme output module is used to obtain a semiconductor drive operation scheme by evaluating the stability of stress distribution in each region of the chip in each semiconductor drive scheme, and to control the semiconductor to perform switching operations according to the obtained semiconductor drive operation scheme.

Images