Low-resource and low-energy-consumption remote sensing image brain-like computing system based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a low-resource and low-energy-consumption remote sensing image brain-like computing system based on an FPGA (Field Programmable Gate Array), which belongs to the cross technical field of brain-like computing and remote sensing information processing, and comprises a data interaction module which is used for high-speed data transmission between a PC (Personal Computer) end and the FPGA and comprises a PCIe (Peripheral Component Interconnect Express) interface sub-module and a data transmission control sub-module; the storage control module is used for data interaction control of the off-chip DDR and the on-chip BRAM and providing efficient data supply for the processing engine; the processing engine module is used for simulating a brain-like pulse neural network to complete convolution calculation of the remote sensing image; comprising a convolution processing sub-module, a data storage sub-module, an input buffer sub-module and an output buffer sub-module. According to the low-resource and low-energy-consumption remote sensing image brain-like computing system based on the FPGA, the brain-like pulse neural network is adopted, the BRAM is allocated to store the intermediate computing result, and the computing unit is designed in combination with SNN characteristics, so that energy consumption and resource waste are effectively reduced, and computing efficiency is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of brain-computer computing and remote sensing information processing, and particularly relates to a low-resource and low-energy remote sensing image brain-computer computing system based on FPGA. BACKGROUND

[0002] Satellite remote sensing on-orbit data processing technology based on a deep neural network mainly relies on a lightweight artificial neural network (ANN) and has played a role in disaster warning and emergency, marine application and the like.

[0003] However, the prior art has the following disadvantages: the lightweight artificial neural network occupies a large amount of resources, the model often has millions or even billions of parameters, and a large amount of resources is consumed during calculation and storage, and when processing time series data, due to structural limitations, the system cannot efficiently transmit sparse and effective information like the human brain, resulting in high power consumption; the existing brain-like spiking neural network (SNN) has a transmission bottleneck when processing large-scale remote sensing data due to the difference in data access efficiency within and between channels; the existing field programmable gate array (FPGA) design relies on a digital signal processor (DSP), which increases energy consumption and wastes computing resources, and a single task is completed in multiple clock cycles in the traditional design, resulting in low computing efficiency.

[0004] Therefore, a new system is urgently needed. SUMMARY

[0005] The application aims to provide a low-resource and low-energy remote sensing image brain-computer computing system based on FPGA, which adopts a brain-like spiking neural network, reasonably allocates BRAM storage intermediate calculation results, and combines the SNN characteristics to design a LUT-based computing unit, effectively reducing energy consumption and resource waste, and improving computing efficiency.

[0006] To achieve the above-mentioned purpose, the application provides a low-resource and low-energy remote sensing image brain-computer computing system based on FPGA, which comprises:

[0007] A data interaction module for high-speed data transmission between a PC end and FPGA, comprising a PCIe interface submodule and a data transmission control submodule;

[0008] A storage control module connected with the data interaction module, for data interaction control of off-chip DDR and on-chip BRAM, and providing efficient data supply for a processing engine;

[0009] A processing engine module connected with the storage control module, for simulating a brain-like spiking neural network to complete convolution calculation of remote sensing images; comprising a convolution processing submodule, a data storage submodule, an input buffer submodule and an output buffer submodule.

[0010] Preferably, the PCIe interface sub-module adopts a high-speed PCIe interface hardware design, supports TLP protocol analysis, realizes address mapping between a PC and an FPGA, and completes writing of raw remote sensing image data into a cache and reading and returning of processing results.

[0011] Preferably, the data transmission control sub-module includes a soft core processor, an AXI bus interconnection and a DDR controller; the soft core processor serves as a control core to process transmission control logic, the AXI bus interconnection supports concurrent access of multiple master devices, and the DDR controller provides high-bandwidth off-chip storage access and is provided with an input-output buffer area as a data transfer station.

[0012] Preferably, the storage control module realizes interaction between off-chip DDR and on-chip BRAM and the processing engine module through an AHB bus protocol; the address space of the on-chip BRAM is divided into 32 areas according to an address interval of 32, corresponding to 32 input channels, and data in the same channel is stored continuously according to an address interval of 1, and data in different channels is distributed according to an address offset of 32.

[0013] Preferably, the on-chip BRAM includes an INPUT BRAM, an FCBRAM / CONVBRAM, PARAM BRAMs and RESULT BRAMs for classified storage, respectively corresponding to storage of raw data, intermediate feature maps, quantization parameters and final results.

[0014] Preferably, the convolution processing sub-module includes a processing unit composed of AND gates, registers and adders realized by LUTs; the processing unit receives single-bit feature maps, input valid timing signals and quantization parameters, completes weighted mapping through an AND gate array, temporarily stores intermediate results in registers, and accumulates convolution calculation results by an adder to output the results and valid timing signals of the results.

[0015] Preferably, the data storage sub-module is composed of no less than two BRAMs, a single BRAM stores 32 feature maps output by a convolution layer, and single-channel data is continuously stored in a single BRAM, and multi-channel data is distributed in different BRAMs.

[0016] Preferably, the input buffer sub-module adopts a rotation architecture of dual-port BRAMs and registers, for continuously supplying data for a 3x3 convolution sliding window.

[0017] Preferably, the output buffer sub-module includes a result counting module, a calculation result BRAM control module and a data buffer unit, for realizing buffering of convolution calculation results, sliding window timing control and timing matching with the on-chip BRAM.

[0018] Therefore, the low-resource and low-energy remote sensing image brain-like computing system based on FPGA is adopted in the present application, and compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0019] (1) The brain-like spiking neural network (SNN) is adopted in the present application, and the time sequence pulse processing mechanism and information sparse transmission characteristics thereof are utilized to significantly reduce the system power consumption and the computing and storage resource occupation;

[0020] (2) The data access strategy of the balance between the intra-channel and the inter-channel is proposed in the present application, the problem of the inconsistent data access efficiency between the intra-channel and the inter-channel is solved by reasonably allocating the intermediate calculation results in the BRAM storage, the data read / write efficiency is improved, and the data transmission bottleneck is eliminated;

[0021] (3) The computing unit based on LUT is designed in combination with the computing characteristics of the pulse neural network in the present application, the traditional DSP is replaced, the energy consumption and resource waste are reduced, the parallel computing capability of the FPGA is released, and the computing efficiency is improved.

[0022] The technical scheme of the present application will be further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 It is a structure diagram of the low-resource and low-energy remote sensing image brain-like computing system based on FPGA embodiment of the present application;

[0024] Figure 2 It is a processing engine module structure diagram of the low-resource and low-energy remote sensing image brain-like computing system based on FPGA embodiment of the present application;

[0025] Figure 3 It is a data transmission control submodule structure diagram of the low-resource and low-energy remote sensing image brain-like computing system based on FPGA embodiment of the present application;

[0026] Figure 4 It is a BRAM address planning diagram of the low-resource and low-energy remote sensing image brain-like computing system based on FPGA embodiment of the present application;

[0027] Figure 5 It is an on-chip BRAM classified storage and data routing design diagram of the low-resource and low-energy remote sensing image brain-like computing system based on FPGA embodiment of the present application;

[0028] Figure 6 It is a processing unit hardware structure diagram of the convolution processing submodule of the low-resource and low-energy remote sensing image brain-like computing system based on FPGA embodiment of the present application;

[0029] Figure 7This is a 3×3 convolution sliding window logic diagram of the input buffer submodule of the present invention, which is based on an FPGA and is characterized by low resource and low power consumption, making it suitable for neuromorphic computing of remote sensing images.

[0030] Figure 8 This is a design diagram of FIFO buffer and sliding window control for an embodiment of the low-resource, low-power remote sensing image neuromorphic computing system based on FPGA of the present invention;

[0031] Figure 9 This is a counting control and BRAM writing logic diagram of an embodiment of the low-resource, low-power remote sensing image neuromorphic computing system based on FPGA of the present invention;

[0032] Figure 10 This is an architecture diagram of the all-input parallel algorithm mapping strategy of an embodiment of the low-resource, low-energy remote sensing image neuromorphic computing system based on FPGA of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used in the present invention should have the ordinary meaning understood by those skilled in the art.

[0034] Example 1

[0035] like Figures 1-2 As shown, the FPGA-based low-resource, low-power remote sensing image brain-like computing system of the present invention includes a data interaction module, a storage control module, and a processing engine module.

[0036] The data interaction module is used to realize high-speed data transmission between the PC and the FPGA, ensuring stable interaction of remote sensing image data and processing results. It includes a PCIe interface submodule and a data transmission control submodule.

[0037] The PCIe interface submodule adopts a high-speed PCIe interface hardware design, supports TLP (Transaction Layer Packet) protocol parsing, realizes address mapping between the PC and FPGA (maps the PCIE address to the DDR memory address space), completes the writing of raw image data to the buffer (write operation) and the reading and return of processing results (read operation), and reduces transmission latency.

[0038] like Figure 3As shown, the data transmission control submodule is used to realize high-speed data transmission control between the FPGA and the DDR3. Through the architecture of "MicroBlaze + AXI bus interconnection + DMA + DDR3 controller (MIG)", the high-throughput transmission requirement of remote sensing image data is solved, specifically as follows:

[0039] MicroBlaze is a soft-core processor, which is the control core of data transmission. It configures AXI_DMA, MIG and other peripherals through AXI bus, and processes the control logic (such as starting / stopping transmission, error detection) in the transmission process.

[0040] AXI Interconnect is a bus interconnection module, which is the bus hub, realizing high-speed data interaction between MicroBlaze, AXI_DMA, AXI_UART, AXI_GPIO and other devices, supporting concurrent access of multiple master devices.

[0041] AXI_DMA (AXI Direct Memory Access) is used to realize memory mapping to stream (MM2S) and stream to memory mapping (S2MM) data transfer.

[0042] Among them, the MM2S mode is to transmit the data (such as original remote sensing image) in the DDR3 to the "input / output buffer area" in the form of data stream; the S2MM mode is to write the processing result of the "input / output buffer area" back to the DDR3.

[0043] AXI_UART is the UART interface of AXI bus, which is used for serial communication (such as outputting transmission status, receiving control instructions) in the debugging stage, and assists system development.

[0044] MIG (Memory Interface Generator) is a DDR3 memory controller, which realizes high-speed data interaction between FPGA and DDR3, supports clock frequency of up to hundreds of MHz, and provides high-bandwidth off-chip memory access.

[0045] AXI_GPIO is the general input / output interface of AXI bus, which is used to control external devices or transmission status signals.

[0046] The input / output buffer area is an on-chip cache area, which is a data transfer station of AXI_DMA, temporarily storing data read from (MM2S) or written to (S2MM) DDR3, and adapting the timing difference between AXI bus and external devices.

[0047] The data transmission process of the data transmission control submodule is as follows:

[0048] In the configuration phase, MicroBlaze configures the transmission parameters (such as source address, target address, transmission length) of AXI_DMA through AXI Interconnect, and initializes DDR3 through MIG;

[0049] In the start transmission phase, MicroBlaze sends a start instruction, and AXI_DMA enters MM2S mode to read raw remote sensing image data from DDR3;

[0050] In the data transfer phase, AXI_DMA writes DDR3 data in the form of a data stream to the "input-output buffer interval", and MIG is responsible for the timing control of DDR3;

[0051] In the state feedback phase, AXI_GPIO outputs transmission state signals (such as done), and AXI_UART outputs debugging information (such as the number of transmission bytes and time consumption);

[0052] In the result return phase, if the processing result needs to be written back to DDR3, AXI_DMA switches to S2MM mode to write the result data of the "input-output buffer interval" back to DDR3.

[0053] As shown in Figure 4 , the storage control module optimizes the data interaction timing through hardware programming, coordinates the read-write rhythm of off-chip DDR (storing raw data and final results) and on-chip BRAM (storing intermediate data), and realizes the interaction between DDR3 and internal storage and processing engine modules through AHB bus protocol. Specifically:

[0054] The address space of a single BRAM is divided into 32 regions according to an address interval of 32, and each region corresponds to an input channel (Channelx); the feature map data in the same channel (such as Channelx(0,0), Channelx(0,1)…Channelx(0,y)) is stored continuously according to an address interval of 1, which ensures continuous access of data in the channel and improves the reading efficiency of a single channel;

[0055] The feature map data of different channels (such as Channel0(0,0), Channel1(0,0)…Channel31(0,0)) is distributed in the BRAM according to an address offset of 32, and supports multi-channel data parallel reading, that is, each channel corresponds to an independent address offset to avoid access conflicts; through the continuous BRAM address planning within the channel and the interval between channels, the multi-channel data access efficiency is balanced;

[0056] Figure 4The middle diagonal line represents the parallel access path of cross-channel data. When the processing engine needs to read the feature maps of n channels at the same time, the data can be obtained in parallel by the offset rule of "address interval 32" through the multi-port characteristics (or time division multiplexing) of the BRAM, and the access efficiency between channels is balanced.

[0057] As shown in Figure 5 The read and write of the on-chip BRAM adopt the design of classified storage and data routing. The storage and access efficiency of remote sensing image data on the chip are optimized through hardware-level BRAM function division and signal interaction. Specifically,

[0058] The INPUT BRAM stores the original remote sensing image data (such as multi-spectral feature maps) read from the off-chip DDR, receives kpa_bram_* series signals such as address, enable, data bus, etc., and provides input data buffer for the processing engine;

[0059] The FC BRAM / CONV BRAM stores the intermediate feature map data according to the classification of the neural network level, and supports multi-channel parallel access. For example, the CONV 1BRAM stores the output feature map of the first convolutional layer, and the CONV 2BRAM stores the output of the second convolutional layer. The inter-layer data transmission is realized through the conv_*_bram_* series signals;

[0060] The PARAM BRAMs store the quantized neural network parameters, and provide the parameters for the processing engine through the param_*_bram_* series signals;

[0061] The RESULT BRAMs store the final processing result, and complete the result feedback with the subsequent modules (such as the data interaction subsystem) through the result_*_bram_* series signals;

[0062] After the original remote sensing image data is buffered by the INPUT BRAM, the subsequent processing is completed through the kpa_bram_done (8) and other signals. The PARAM BRAMs provide the convolution kernel weight or fully connected parameter for the FC BRAM / CONV BRAM through the param_*_bram_addr (address), param_*_bram_en (enable) and other signals. The output of the CONV 1BRAM triggers the input data reading of the CONV 2BRAM through the conv_1_bram_done (4) and other signals, realizing the pipelined data transmission between convolutional layers. The final processing result is stored in the RESULT BRAMs, and the result is fed back to the off-chip data transmission submodule DDR data transmission submodule or data transmission submodule PC data transmission submodule through the result_*_bram_addr (address), result_*_bram_en (enable) and other signals.

[0063] The processing engine module is used for simulating a brain-like pulse neural network to complete convolution calculation of a remote sensing image, and includes a convolution processing submodule, a data storage submodule, an input buffer submodule, and an output buffer submodule.

[0064] As shown in Figure 6 The convolution processing submodule includes a convolution processing unit (PE) hardware structure. In view of the characteristic that the input feature map pixels of the SNN are single bits, an AND gate, a register, and an adder are implemented by using the LUT resource of the FPGA to replace the traditional DSP operation, thereby significantly reducing the resource dependence. Specifically, the convolution processing submodule includes:

[0065] The input part of the PE structure receives three types of signals, namely, an input single-bit feature map, an input valid timing signal, and a quantized parameter.

[0066] The calculation logic of the PE structure includes an AND gate array, a register, and an adder. The AND gate array performs a bitwise AND operation on the feature map and the parameter to complete the weighted mapping of the weight and the input. In the single-bit case, a single-bit multiplication (0x0=0, 0x1=0, 1x0=0, 1x1=1) is implemented by using the LUT to replace the multiplier, thereby reducing the dependence on the DSP. The register temporarily stores the intermediate results output by the AND gate to realize the result caching of the pipeline stage and ensure the timing synchronization. The adder adds the intermediate results output by the multiple registers to complete the partial sum calculation of the convolution operation and support the parallel convolution of the multi-channel feature map.

[0067] The output part of the PE structure generates the convolution calculation results, namely, the result and the result valid timing signal, to ensure the timing matching of the calculation results and the subsequent modules.

[0068] The input feature map pixels of the pulse neural network are single bits. When the PE performs processing, after receiving the single-bit input feature map pixels and the convolution kernel weight, the PE does not need to perform a complex fixed-point multiplication operation like the traditional artificial convolutional neural network, but uses the operation characteristics of the single-bit data to design a simplified hardware logic to complete the calculation. This special logic avoids the dependence on the DSP (digital signal processor) and instead makes more use of the LUT (lookup table) resource of the FPGA, thereby greatly reducing the use amount of the DSP, reducing the energy consumption, improving the utilization efficiency of the hardware resources, and meeting the design goal of low resource and low energy consumption.

[0069] The module responsible for storing intermediate calculation results in the data storage submodule is composed of a plurality of BRAMs, each of which is allocated to store 32 feature maps output by a previous convolutional layer, i.e., the calculation results corresponding to 32 convolutional kernels. This allocation mode enables single-channel data to be continuously stored in a single BRAM, ensuring the continuity and efficiency of data access within the channel; at the same time, multi-channel data can be distributed in different BRAMs to support parallel reading and balance the data access efficiency between channels.

[0070] As shown in Figure 7 , the input buffer submodule is used to realize continuous data supply for 3x3 convolution sliding window, and solves the data delay problem in remote sensing image convolution calculation through a rotating architecture of double-port BRAM and register, specifically as follows:

[0071] RAMrow1 / RAMrow2 are double-port BRAMs, which store the first row and the second row of data of the input feature map respectively; support "read-write" parallel operation, and write new row data while outputting the current row data;

[0072] RAMrow3 is a register (Reg) for storing the third row of data of the input feature map; through "register-level cache", the data is quickly updated and output;

[0073] fib_dout is a sliding window data output port, which outputs 9 pixels continuously according to the timing requirements of 3x3 convolution;

[0074] The data output by fib_dout is fed back to BRAM through feedback logic to realize rotating update of data and ensure the continuity of the sliding window;

[0075] Initially, RAMrow1 stores the first row of data, RAMrow2 stores the second row of data, and RAMrow3 stores the third row of data;

[0076] When outputting, fib_dout outputs the first column of RAMrow1, the first column of RAMrow2, and the first column of RAMrow3 in sequence, i.e., the first column of the first 3x3 sliding window, and then outputs the subsequent columns in turn to complete a sliding window calculation;

[0077] During the update, when new row data is input, RAMrow1 writes the new first row data, RAMrow2 writes the old data of the original RAMrow1, and RAMrow3 writes the old data of the original RAMrow2, realizing the rotation update of row data and preparing data for the next sliding window calculation; the feedback path and rotation update mechanism ensure that the 9 pixels of the 3×3 convolution are continuously supplied, adapting to the pulse timing requirements of SNN.

[0078] like Figure 8 As shown, the output buffer module consists of a result counting module, a computation result BRAM control module, and a data buffer FIFO. It is used to implement caching of convolution computation results and sliding window timing control. Through the architecture of the FIFO buffer and sliding window module, the problem of asynchronous output and synchronous processing of multi-channel convolution results is solved. Specifically:

[0079] The FIFO buffer receives result data (Result_bram_dout) from RESULT BRAMs, and controls data writing through Result_bram_ena (enable signal) and addr (address signal); it also supports asynchronous read and write operations, and avoids data overflow or empty reads through almost_full (near full) and empty (empty) signals; by outputting buffered data to the sliding window module (fifo_dout), it realizes temporary storage of result data and flow control;

[0080] The sliding window module receives the buffered data (fifo_dout) output from the FIFO, and generates output data that conforms to the multi-channel processing timing through the sliding_en (sliding window enable) and sliding_window(valid) (sliding window valid) signals; and adapts to the parallel processing requirements of multi-channel feature maps of remote sensing images, ensuring that the result data is synchronized with the timing of subsequent modules (such as Multi Channel Processing);

[0081] The data processing flow of the output buffer module includes a write phase, a read phase, and a sliding window control phase. In the write phase, when RESULT BRAMs output result data, the Result_bram_ena and addr signals trigger a write operation in the FIFO (wr_en is set high), and the data is written to the FIFO buffer. In the read phase, when the sliding window module needs to process data, it triggers a read operation in the FIFO (rd_en is set high), and the buffered data is output to the sliding window module via fifo_dout. In the sliding window control phase, the sliding window module reorganizes the data output from the FIFO according to the timing requirements of a 3×3 sliding window or multi-channel parallel processing based on the sliding_en and sliding_window(valid) signals, and outputs it to the subsequent processing unit.

[0082] The asynchronous read-write characteristics of the FIFO solve the clock domain difference between the RESULT BRAMs and the subsequent processing modules, avoid data loss, and use the almost_full and empty signals to realize intelligent adjustment of read-write flow and improve the utilization rate of on-chip storage resources.

[0083] As shown in Figure 9 The output buffer sub-module is used for implementing counting control and BRAM write logic of convolution calculation results, and solves the timing matching problem of PE output and on-chip BRAM write through the collaborative architecture of "result counting module + calculation result BRAM control module + result buffer RAM", and specifically:

[0084] The result counting module receives the pe_data_vld (data valid signal) output by the PE, triggers the internal counter to generate result_cnt (result count, records the number of feature maps currently processed) and addr_cnt (address count, generates the BRAM write address), realizes accurate control of "counting by channel" and "address offset", and adapts to the parallel writing needs of multi-channel feature maps.

[0085] The calculation result BRAM control module receives result_cnt and addr_cnt, generates result_bram_ena (BRAM enable signal) and result_bram_addr (BRAM write address), and dynamically adjusts the BRAM writing rhythm through the count signal feedback counting state to avoid multi-channel data conflict.

[0086] The result buffer RAM temporarily stores the pe_data_out (convolution calculation result) output by the PE, solves the timing difference between the PE output and the BRAM write, and outputs the temporary stored data to result_bram_dina (BRAM write data bus) to ensure data integrity.

[0087] The data processing flow of the output buffer sub-module includes counting triggering, BRAM control and data buffering.

[0088] When pe_data_vld is high, the result counting module starts counting to generate result_cnt and addr_cnt; the calculation result BRAM control module generates result_bram_ena and result_bram_addr according to result_cnt and addr_cnt, triggers the BRAM write operation; the result buffer RAM temporarily stores pe_data_out, and outputs to result_bram_dina when the BRAM write is enabled, to complete the data write;

[0089] As shown in Figure 10As shown, the all-input parallel algorithm mapping strategy realizes efficient convolution calculation through channel-level parallel design according to the single-bit characteristics of the spiking neural network, and specifically:

[0090] All Input Channels provides 32 input channels (CHAN0-CHANn), each of which corresponds to a feature dimension of a remote sensing image; the input is a single-bit feature map, and the data volume is reduced by using the information sparse transmission characteristics of SNN;

[0091] Input Buffer configures an independent buffer unit (BUF1-BUFn) for each input channel; a dual-port BRAM is used to temporarily store the feature map data of the corresponding channel; through channel-level parallel design, the waste of cache resources caused by mixed storage of multi-channel data is avoided, while ensuring continuous access of data for each channel;

[0092] Weights&Neuron params is a storage unit for quantized convolution kernel weights and SNN-specific neuron parameters, which is transmitted to each PE in parallel through a hardware bus to support the parallelism of brain-like spiking calculation;

[0093] PE Array is composed of n processing units (PE1-PEn), each of which corresponds to an input channel; the PE receives the feature map data output by the Input Buffer and the quantized convolution kernel weights and SNN neuron parameters provided by the Weights&Neuron params in parallel, and independently completes single-channel convolution calculation;

[0094] Multi Channel Processing integrates the calculation results of n PEs to realize parallel convolution processing of multi-channel feature maps and outputs multi-channel convolution results;

[0095] The brain-like computing method for remote sensing images based on FPGA includes the following steps:

[0096] S1, the PC transmits raw remote sensing image data to the FPGA through the PCIe interface; the PCIe interface submodule of the data interaction subsystem parses the TLP protocol and writes the data into the DDR3 of the storage control subsystem, completing the import of raw data;

[0097] S2, a single BRAM stores 32 channels of feature map data, and the data in the same channel is stored continuously with an address interval of 1, and the data of different channels is distributed with an address interval of 32; an independent dual-port BRAM buffer unit (BUF1-BUF32) is configured for each input channel to temporarily store the single-bit feature map data of the corresponding channel; quantized convolution kernel weights and SNN neuron parameters are transmitted to each processing unit of the processing engine module in parallel through a hardware bus;

[0098] S3, a double-port BRAM + register sliding window architecture is adopted to generate a continuous data supply of 3*3 convolution sliding window for each channel, 32 processing units (PE1~PE32) are included, each PE corresponds to an input channel; a LUT is used to replace a multiplier to complete parallel convolution calculation and obtain calculation results;

[0099] S4, the multi-channel calculation results in S3 are integrated, and the DDR3 of the storage control module is written back;

[0100] S5, the data interaction module reads the result data from the DDR3 and returns to the PC end through the PCIe interface.

[0101] The single-bit characteristics of the SNN input feature map are used to reduce the data storage and transmission overhead, release the parallel computing capability of the FPGA, and improve the processing efficiency of the remote sensing image.

[0102] Therefore, the low-resource and low-energy remote sensing image brain-like computing system based on the FPGA has the brain-like pulse neural network, the intermediate calculation results are reasonably allocated in the BRAM storage, the calculation unit based on the LUT is designed in combination with the SNN characteristics, the energy consumption and resource waste are effectively reduced, and the calculation efficiency is improved.

[0103] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present application but not to limit it, although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that: the technical solutions of the present application can still be modified or replaced by the equivalent, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present application.

Claims

1. A low-resource, low-energy remote sensing image brain-like computing system based on FPGA, characterized in that, The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. 2.The FPGA-based low-resource and low-energy remote sensing image brain-like computing system according to claim 1, wherein, The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. 3.The FPGA-based low-resource and low-energy remote sensing image brain-like computing system of claim 1, wherein, The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. 4.The FPGA-based low-resource and low-energy remote sensing image brain-like computing system of claim 1, wherein, The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. 5.The FPGA-based low-resource and low-energy remote sensing image brain-like computing system of claim 4, wherein, The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. 6.The FPGA-based low-resource and low-energy remote sensing image brain-like computing system of claim 1, wherein, The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network.

7. The FPGA-based low-resource, low-energy remote sensing image brain-like computing system of claim 1, wherein, The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. 8.The FPGA-based low-resource and low-energy remote sensing image brain-like computing system of claim 1, wherein, The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. 9.The FPGA-based low-resource and low-energy remote sensing image brain-like computing system of claim 1, wherein, The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image processing system based on a convolutional neural network. The application relates to a high-efficiency remote sensing image

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