Double-sampling sensing circuit applied to MRAM (Magnetic Random Access Memory)

Abstract

The invention discloses a double-sampling sensing circuit applied to an MRAM (Magnetic Random Access Memory), and relates to the technical field of memory circuit design, the circuit comprises at least one SOT-MRAM, a pre-charging and discharging control module, a sampling module and a sensing amplification module; each SOT-MRAM comprises a data unit and a reference unit, and the magnetization state of the data unit is opposite to that of the reference unit; the pre-charging and discharging control module is used for controlling whether bit lines BL and BLB of the target SOT-MRAM are charged or discharged; the sampling module is used for respectively collecting voltages on the bit line BL and the bit line BLB in the discharging process of the bit line BL and the bit line BLB so as to obtain the maximum voltage difference; and the sensing amplification module is used for amplifying the maximum voltage difference and outputting a corresponding digital signal to represent data stored in the MRAM. According to the invention, high-speed read operation can be maintained, the sensing margin can be improved, the bit error rate can be reduced, and low read energy consumption can be realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of memory circuit design, and particularly relates to a double-sampling sensing circuit applied to MRAM. BACKGROUND

[0002] With the continuous shrinkage of the complementary metal-oxide-semiconductor (CMOS) process, traditional memories, such as static random access memory (SRAM), face severe challenges in terms of leakage power consumption. New non-volatile memories have become a research hotspot, among which spin-transfer torque magnetic random access memory (STT-MRAM) has been widely concerned due to its non-volatility, low power consumption and CMOS compatibility. However, STT-MRAM has deficiencies in terms of write speed and power consumption.

[0003] To this end, spin-orbit torque magnetic random access memory (SOT-MRAM) is proposed, which significantly reduces write delay and energy consumption by using spin Hall effect separated read and write paths. However, SOT-MRAM still has the problem of low tunnel magnetoresistance ratio and insufficient read margin in the read operation, resulting in the need for large read energy to ensure reliability.

[0004] The traditional voltage mode sensing method improves energy consumption to some extent, but the sensing margin is insufficient under process deviation, and it is still difficult to ensure low error rate and high-speed read operation. Therefore, a new sensing scheme is urgently needed to ensure high speed while improving sensing reliability and reducing energy consumption. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a double-sampling sensing circuit applied to MRAM.

[0006] The technical problem to be solved by the application is solved by the following technical scheme: The application provides a double-sampling sensing circuit applied to MRAM, comprising: at least one SOT-MRAM, a pre-charge and discharge control module, a sampling module and a sensing amplification module. Each SOT-MRAM comprises a data cell and a reference cell, the magnetization state of the data cell in each SOT-MRAM is opposite to that of the reference cell, each SOT-MRAM is used to access a read control signal RL and a write control signal WL, the read control signal RL and the write control signal WL are used to control whether one SOT-MRAM is a target SOT-MRAM; The pre-charge and discharge control module is used to control whether the bit line BL of the data cell and the bit line BLB of the reference cell in the target SOT-MRAM are charged or discharged, wherein the discharge speeds of the bit line BL and the bit line BLB are different; The sampling module is used to collect the voltages on the bit line BL and the bit line BLB respectively in the process that the bit line BL of the data cell and the bit line BLB of the reference cell in the target SOT-MRAM are discharged, so that the maximum voltage difference between the collected voltage on the bit line BL and the voltage on the bit line BLB is obtained; The sense amplifier module is used to amplify the maximum voltage difference between the bit line BL and the bit line BLB and output a corresponding digital signal.

[0007] Compared with the prior art, the application has the following beneficial effects: The double-sampling sensing circuit applied to the MRAM can dynamically and alternately sample the voltages of the bit lines BL and BLB by monitoring the discharge sequence of the bit lines BL and BLB, so that the input voltage difference between the two ends of the sense amplifier is maximized, thereby significantly improving the read margin and reliability. The application does not need additional repeated sensing or complex offset cancellation circuit, and the data reading can be realized by using the simple sense amplifier in the last part of the sensing circuit, so that the energy consumption and area overhead are small. In addition, the application can guarantee the target error rate while reducing the pre-charge voltage of the bit lines BL and BLB, thereby saving the read energy consumption.

[0008] The application will be further described in detail below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a structural schematic diagram of a double-sampling sensing circuit applied to the MRAM provided by the embodiment of the application; Figure 2A is a schematic diagram of the voltage changes on the bit line BL and the bit line BLB when the data in the data cell is read by using the traditional scheme; Figure 2B is a schematic diagram of the voltage changes on the bit line BL and the bit line BLB when the data in the data cell is read by using the technical scheme provided by the application, the signals BL inv and BLB output by the buffer Buff0 and the buffer Buff1inv a variation diagram of the voltage on the bit line BL and the bit line BLB when reading data from the data unit; Figure 2C is a variation diagram of the voltage on the bit line BL and the bit line BLB when reading data from the data unit. DETAILED DESCRIPTION

[0010] The application will be further described below in connection with specific embodiments, but the embodiments of the application are not limited thereto.

[0011] The application provides a dual-sampling sensing circuit applied to MRAM, which can improve sensing margin, reduce bit error rate and realize lower read energy consumption while maintaining high-speed read operation. The circuit comprises a pre-charge and discharge control module, a sampling module, a sensing amplification module and at least one SOT-MRAM. Each SOT-MRAM comprises a data unit and a reference unit, the magnetization state of the data unit in each SOT-MRAM is opposite to that of the reference unit, each SOT-MRAM is used to access a read control signal RL and a write control signal WL, and the read control signal RL and the write control signal WL are used to control whether a SOT-MRAM is a target SOT-MRAM. It should be noted that the data unit and the reference unit are both storage units, and the magnetization state comprises a low state and a high state, and the low state can be referred to as a P state, and the high state can be referred to as an AP state. The magnetization state of the data unit in each SOT-MRAM is opposite to that of the reference unit, that is, the data stored in the data unit in each SOT-MRAM is opposite to the data stored in the reference unit in the SOT-MRAM, for example, for a SOT-MRAM, when the data stored in the data unit is 1, the data stored in the reference unit is 0. The pre-charge and discharge control module is used to control whether the bit line BL of the data unit and the bit line BLB of the reference unit in the target SOT-MRAM are charged or discharged, wherein the discharge speeds of the bit line BL and the bit line BLB are different. It should be noted that BL is the abbreviation of Bit Line. The sampling module is used to collect the voltages on the bit line BL and the bit line BLB respectively in the process of discharging the bit line BL of the data unit and the bit line BLB of the reference unit in the target SOT-MRAM, so that the collected voltage on the bit line BL and the voltage on the bit line BLB have the maximum voltage difference. The sensing amplification module is used to amplify the maximum voltage difference between the bit line BL and the bit line BLB and output a corresponding digital signal. It should be noted that one digital signal output by the sensing amplification module each time is one data read from the data unit in the target SOT-MRAM, and the digital signal is 0 or 1. It should be noted that the target SOT-MRAM means a SOT-MRAM that needs to perform data reading.

[0012] It should be noted that for a target SOT-MRAM, when the magnetization state of a magnetoresistive tunnel junction (MTJ) device in a data cell is in a low state, the discharge speed of the bit line BL is greater than the discharge speed of the bit line BLB, and the digital signal corresponding to the output of the sense amplification module is 0; and when the magnetization state of the MTJ device in the data cell is in a high state, the discharge speed of the bit line BL is less than the discharge speed of the bit line BLB, and the digital signal corresponding to the output of the sense amplification module is 1.

[0013] The working process of the double-sampling sensing circuit provided by the present application is as follows: in a read operation, the bit line BL and the bit line BLB of the target SOT-MRAM are first pre-charged, and then the bit line BL and the bit line BLB of the target SOT-MRAM enter a discharge phase; in the discharge phase, according to the magnetization state of the data cell in the target SOT-MRAM, there is a difference in the discharge speed of the bit line BL and the bit line BLB, wherein when the voltage on the bit line BL or BLB drops to a preset threshold voltage , the voltage on the BLB or BL is collected at different time points, thereby maximizing the voltage margin; finally, the sense amplification module compares the voltages sampled at the two different times to determine the logic value of the data cell in the target SOT-MRAM. Specifically, when data needs to be read from a data cell in any one of at least one SOT-MRAM, the voltages on the bit line BL of the data cell and the bit line BLB of the reference cell in the SOT-MRAM are charged to the power supply voltage VDD by the pre-charging and discharge control module, then the SOT-MRAM is selected as a target SOT-MRAM by the read control signal RL and the write control signal WL, and the bit line BL of the data cell and the bit line BLB of the reference cell in the SOT-MRAM are discharged by the pre-charging and discharge control module, the voltages on the bit line BL and the bit line BLB are collected by the sampling module during the discharge of the bit line BL and the bit line BLB in the data cell of the SOT-MRAM, so that the collected voltages on the bit line BL and the bit line BLB have the maximum voltage difference, the maximum voltage difference between the bit line BL and the bit line BLB is amplified by the sense amplification module, and the corresponding digital signal is output, thereby realizing the reading of the data stored in the data cell in the SOT-MRAM.

[0014] In the present application, the sampling module is specifically configured to: during the discharge of the bit line BL of the data cell and the bit line BLB of the reference cell in the target SOT-MRAM, when the voltage on the first bit line drops to a threshold voltage the voltage on the second bit line at this moment is collected and kept, and then, when the voltage on the second bit line drops to a threshold voltage the voltage on the first bit line at this moment is collected and kept, wherein, when the first bit line is bit line BL, the second bit line is bit line BLB, and when the first bit line is bit line BLB, the second bit line is bit line BL. When the magnetization state of the MTJ device in the data unit in the target SOT-MRAM is low, the first bit line is bit line BL, and the second bit line is bit line BLB, and vice versa, when the magnetization state of the MTJ device in the data unit in the target SOT-MRAM is high, the first bit line is bit line BLB, and the second bit line is bit line BL. Specifically, for a SOT-MRAM reading data, when the magnetization state of the MTJ device in the data unit is low, the discharge speed of bit line BL is greater than that of bit line BLB, and the voltage on bit line BL drops to a threshold voltage at this moment is collected and kept, and then, when the voltage on bit line BLB drops to a threshold voltage at this moment is collected and kept; vice versa, when the magnetization state of the MTJ device in the data unit is high, the discharge speed of bit line BL is less than that of bit line BLB, and the voltage on bit line BLB drops to a threshold voltage at this moment is collected and kept, and then, when the voltage on bit line BL drops to a threshold voltage at this moment is collected and kept. In this way, the voltages on bit line BLB and bit line BL with the largest voltage difference can be collected.

[0015] Specifically, the sampling module comprises a buffer unit, a switch tube unit and a voltage keeping unit; the buffer unit is configured to control the switch tube unit to close the switch tube on the second bit line when the voltage on the first bit line drops to a threshold voltage at this moment; the voltage keeping unit is configured to keep the voltage on the second bit line when the switch tube on the second bit line is closed. Specifically, the buffer unit comprises buffer Buff0 and buffer Buff1, the switch tube unit comprises switch tube T0 and switch tube T1, and the voltage keeping unit comprises capacitor C0 and capacitor C1, and the threshold voltage of buffer Buff0 and Buff1 is The switch tube T0 and the switch tube T1 are NMOS tubes. An input end of the buffer Buff0 is electrically connected with the bit line BL, an output end of the buffer Buff0 is electrically connected with a gate of the switch tube T1, a drain of the switch tube T1 is electrically connected with the bit line BLB, a source of the switch tube T1 is electrically connected with one end of the capacitor C1, and the other end of the capacitor C1 is electrically connected with a common ground terminal VSS. An input end of the buffer Buff1 is electrically connected with the bit line BLB, an output end of the buffer Buff1 is electrically connected with a gate of the switch tube T0, a drain of the switch tube T0 is electrically connected with the bit line BL, a source of the switch tube T0 is electrically connected with one end of the capacitor C0, and the other end of the capacitor C0 is electrically connected with the common ground terminal VSS. Exemplarily, the buffer Buff0 and the buffer Buff1 are both buffers composed of two inverters, and, = 0.5VDD.

[0016] Exemplarily, the sensing amplification module comprises a sensing amplifier SA, one input end of the sensing amplifier SA is electrically connected with the ungrounded end of the capacitor C0, the other input end of the sensing amplifier SA is electrically connected with the ungrounded end of the capacitor C1, and the output end of the sensing amplifier SA is used for outputting a digital signal.

[0017] Exemplarily, each data unit comprises a switch tube N0, a switch tube N1 and a data MTJ device, and each reference unit comprises a switch tube N2, a switch tube N3 and a reference MTJ device, and the switch tubes N0, N1, N2 and N3 are all NMOS tubes. The drain of the switch tube N0 is electrically connected with the bit line BL, the source of the switch tube N0 is electrically connected with one end of the data MTJ device, the drain of the switch tube N1 is electrically connected with the bit line BL, and the source of the switch tube N1 is electrically connected with the other end of the data MTJ device. The data MTJ device is also electrically connected with a source line SL, and the source line SL is also electrically connected with the pre-charge and discharge control module. The drain of the switch tube N2 is electrically connected with the bit line BLB, the source of the switch tube N2 is electrically connected with one end of the reference MTJ device, the drain of the switch tube N3 is electrically connected with the bit line BLB, and the source of the switch tube N3 is electrically connected with the other end of the reference MTJ device. The reference MTJ device is also electrically connected with a source line SLB, and the source line SLB is also electrically connected with the pre-charge and discharge control module. The gates of the switch tubes N0 and N2 are both used for inputting a read control signal RL, and the gates of the switch tubes N1 and N3 are both used for inputting a write control signal WL. It should be noted that when a SOT-MRAM needs to be selected as a target SOT-MRAM, the switch tubes N0 and N2 in the SOT-MRAM are controlled to be always turned on during reading data by the read control signal RL, and the switch tubes N1 and N3 in the SOT-MRAM are controlled to be always turned off during reading data by the write control signal WL.

[0018] Exemplarily, the pre-charge and discharge control module comprises a switch tube P0, a switch tube P1, a switch tube N4 and a switch tube N5, wherein the switch tubes P0 and P1 are both PMOS tubes, the switch tubes N4 and N5 are both NMOS tubes, the source of the switch tube P0 is used for connecting to a power supply voltage VDD, the drain of the switch tube P0 is electrically connected to a bit line BL of a data cell in each SOT-MRAM, the gate of the switch tube P0 and the gate of the switch tube P1 are both used for connecting to a pre-charge control signal PRE, the source of the switch tube P1 is used for connecting to the power supply voltage VDD, and the drain of the switch tube P1 is electrically connected to a bit line BLB of a reference cell in each SOT-MRAM. The gates of the switch tubes N4 and N5 are both used for connecting to a discharge control signal DIS, the drain of the switch tube N4 is electrically connected to a source line SL of the data cell in each SOT-MRAM, the source of the switch tube N4 is electrically connected to a common ground terminal VSS, the drain of the switch tube N5 is electrically connected to a source line SLB of the reference cell in each SOT-MRAM, and the source of the switch tube N5 is electrically connected to the common ground terminal VSS. It should be noted that when a target SOT-MRAM needs to be charged, the switch tube P0 and the switch tube P1 are turned on through the pre-charge control signal PRE, so that the bit line BL and the bit line BLB of the SOT-MRAM can be charged simultaneously under the condition that the switch tubes N1 and N3 in the SOT-MRAM are turned off, the switch tubes N0 and N2 are turned on, and the switch tubes N4 and N5 are turned off, until the voltages on the bit line BL and the bit line BLB are charged to the power supply voltage VDD. When the bit line BL and the bit line BLB of a target SOT-MRAM need to be discharged, the switch tubes N4 and N5 are turned on through the discharge control signal DIS, so that the bit line BL and the bit line BLB of the SOT-MRAM can be discharged when the switch tubes N4 and N5 are turned on under the condition that the switch tubes N0 and N2 in the SOT-MRAM are turned on and the switch tubes N1 and N3 are turned off.

[0019] Exemplarily, the double sampling sensing circuit applied to the MRAM is realized by using a 28nm CMOS process.

[0020] Exemplarily, Figure 1 is a structural schematic diagram of the double sampling sensing circuit applied to the MRAM provided by the present application, Figure 1 Exemplarily, a SOT-MRAM is shown in the figure, and the SOT-MRAM is a 4T2M SOT-MRAM, wherein 4T2M represents four transistors and two MTJ devices. The working principle of the double sampling sensing circuit provided by the present application will be further exemplarily described below. Figure 1 The working principle of the double sampling sensing circuit provided by the present application will be further exemplarily described below.

[0021] First stage: pre-charge stage When signal PRE is set low, P0 and P1 are turned on, charging bit lines BL and BLB to the power supply voltage VDD. At this time, since the voltages on bit lines BL and BLB are both higher than the threshold voltages of buffers Buff0 and Buff1... Therefore, the signals output by buffers Buff0 and Buff1 and signal The voltage level is high. Therefore, T0 and T1 are also in the on state, and the voltage at sampling node A is high. and the voltage of sampling node B It is also pre-charged to the power supply voltage VDD.

[0022] Phase Two: Discharge and Sampling Phase The precharge signal PRE is set high, P0 and P1 are turned off, precharging stops. Simultaneously, signal RL turns on N0 and N2, and read current begins to flow through the data MTJ and reference MTJ devices. Bit line BL begins to discharge through the data MTJ device, and bit line BLB begins to discharge through the reference MTJ device. This stage is divided into two cases based on the magnetization state of the data MTJ device: Scenario 1: The magnetization state of the data MTJ device is in a low-resistance state. 1) Initial Trigger and Sampling: Since the data MTJ device is in a low-resistance state while the reference MTJ device is in a high-resistance state, the resistance of the data MTJ device is less than that of the reference MTJ device. Therefore, the discharge rate of bit line BL is much faster than that of bit line BLB. Consequently, the voltage on bit line BL will drop to the threshold voltage first. When the voltage on bit line BL drops to When Buff0 is triggered, the signal output by Buff0 is... The voltage level is low; this change causes T1 to turn off, so the voltage value on the bit line BLB at this moment is captured. And it remains on the sampling capacitor C1. At this time, because the bit line BLB discharges slowly, the sampling node B maintains a high voltage; 2) Secondary triggering and sampling: Subsequently, the voltage on the slower-discharging bit line BLB also drops to... This triggers buffer Buff1, and the signal output by Buff1... It is also low; this change causes T0 to turn off, so the voltage value on bit line BL is captured at this moment. And it remains on the sampling capacitor C0. At this time, because the bit line BL discharges quickly, the sampling node A maintains a low voltage.

[0023] 3) At this point, the positive input terminal of the sensing amplifier SA is at a low voltage and the negative input terminal is at a high voltage.

[0024] Case 2: the magnetization state of the data MTJ device is high resistance state 1) First trigger and sampling: since the magnetization state of the data MTJ device is high resistance state and the magnetization state of the reference MTJ device is low resistance state, the resistance of the data MTJ device is greater than that of the reference MTJ device, and thus the discharge speed of the bit line BLB is much faster than that of the bit line BL, so the voltage on the bit line BLB will drop to the threshold voltage first; when the voltage on the bit line BLB drops to , the buffer Buff1 is triggered, and the signal output by the Buff1 is low; this change causes T0 to be closed, so that the voltage value on the bit line BL at this moment is captured as and kept on the sampling capacitor C0. At this time, since the bit line BL discharges slowly, the sampling node A keeps a relatively high voltage.

[0025] 2) Second trigger and sampling: subsequently, the voltage on the bit line BL which discharges slowly also drops to , triggering the buffer Buff 0, and the signal output by the Buff 0 is also low; this change causes T1 to be closed, so that the voltage value on the bit line BLB at this moment is captured as and kept on the sampling capacitor C1. At this time, since the bit line BLB discharges quickly, the sampling node B keeps a relatively low voltage.

[0026] 3) At this time, the positive input of the sense amplifier Sa is high voltage and the negative input is low voltage.

[0027] Third stage: sensing and output stage 1) the sense amplifier SA amplifies and latches the voltage difference between the sampling node A and the sampling node B; 2) according to the size relationship between and in case 1 or case 2, the corresponding digital signal "0" or "1" is output, completing a read operation, specifically, when is greater than , the Data out output by the sense amplifier SA is "0", and when is less than , the Data out output by the sense amplifier SA is "1".

[0028] In order to verify the effects of the present application, simulation experiments were carried out in the case that the magnetization state of the data MTJ device is low resistance state, for example, Figures 2A-2C are a plurality of simulation result graphs in the case that the magnetization state of the data MTJ device is low resistance state; wherein, Figure 2Ais a schematic diagram of voltage changes on the bit line BL and the bit line BLB when data is read from the data unit using a conventional scheme; Figure 2B is a schematic diagram of signal changes of the buffer Buff0 and the buffer Buff1 output when data is read from the data unit using the technical scheme provided by the application; inv and BLB inv ; Figure 2C is a schematic diagram of voltage changes on the bit line BL and the bit line BLB when data is read from the data unit using the technical scheme provided by the application; Figure 2A , 2B and 2C, the horizontal axis represents time in nanoseconds (ns), and the vertical axis represents voltage in volts (V). As can be seen from Figure 2A , 2B and 2C, when data is read from the data unit using the conventional scheme, the maximum sensing margin is about 95 mV, while when data is read from the data unit using the technical scheme provided by the application, the maximum sensing margin is about 225 mV. Obviously, the sensing margin is more than twice that of the conventional scheme, greatly improving the reading margin and reliability.

[0029] The application has the following beneficial technical effects: 1) The application significantly improves the sensing margin by sampling the data voltage and the reference voltage at different time points through the generation mode of the double-sampling voltage; 2) Compared with the sensing mode of the conventional voltage comparison at a fixed time point under the same conditions, the application can achieve more than twice the sensing margin and reduce the read error rate by more than two orders of magnitude; 3) The application does not require additional repeated sensing or complex offset cancellation circuits, and can achieve data reading using a simple sensing amplifier (for example, a 5-tube sensing amplifier) in the last part of the sensing circuit, thus having small energy consumption and area overhead; 4) The application can still guarantee the target error rate while reducing the pre-charge voltage, thereby saving the reading energy consumption.

[0030] It should be noted that the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0031] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in the specification.

[0032] In the specification, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude a plurality. Some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0033] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as belonging to the protection scope of the present application.

Claims

1. A dual sampling sensing circuit applied to MRAM, characterized in that, The application relates to a SOT-MRAM read / write control method and device. The SOT-MRAM read / write control device comprises at least one SOT-MRAM, a pre-charge and discharge control module, a sampling module and a sense amplifier module. Each SOT-MRAM comprises a data unit and a reference unit, the magnetization state of the data unit in each SOT-MRAM is opposite to that of the reference unit, each SOT-MRAM is used to access a read control signal RL and a write control signal WL, and the read control signal RL and the write control signal WL are used to control whether one SOT-MRAM is a target SOT-MRAM. The pre-charge and discharge control module is used to control whether a bit line BL of the data unit and a bit line BLB of the reference unit in the target SOT-MRAM are charged or discharged, wherein the discharging speeds of the bit line BL and the bit line BLB are different. The sampling module is used to collect voltages on the bit line BL and the bit line BLB respectively in the process that the bit line BL and the bit line BLB of the data unit and the reference unit in the target SOT-MRAM are discharged, so that the collected voltage on the bit line BL and the voltage on the bit line BLB have a maximum voltage difference. The sense amplifier module is used to amplify the maximum voltage difference between the bit line BL and the bit line BLB and output a corresponding digital signal.

2. The dual sampling sensing circuit for MRAM according to claim 1, wherein, For the target SOT-MRAM, when the magnetization state of an MTJ device in the data unit is a low state, the discharging speed of the bit line BL is greater than that of the bit line BLB, and the digital signal output by the sense amplifier module is 0; when the magnetization state of the MTJ device in the data unit is a high state, the discharging speed of the bit line BL is less than that of the bit line BLB, and the digital signal output by the sense amplifier module is 1.

3. The dual sampling sensing circuit for MRAM according to claim 1, wherein, The sampling module is specifically configured to: in the process of discharging the bit line BL of the data unit and the bit line BLB of the reference unit in the target SOT-MRAM, when the voltage on the first bit line first drops to a threshold voltage , collect and hold the voltage on the second bit line at this moment, and then, when the voltage on the second bit line drops to the threshold voltage , collect and hold the voltage on the first bit line at this moment, wherein when the first bit line is the bit line BL, the second bit line is the bit line BLB, and when the first bit line is the bit line BLB, the second bit line is the bit line BL.

4. The dual sampling sensing circuit for MRAM according to claim 3, wherein, When the magnetization state of the MTJ device in the data unit is a low state, the first bit line is the bit line BL, and the second bit line is the bit line BLB; when the magnetization state of the MTJ device in the data unit is a high state, the first bit line is the bit line BLB, and the second bit line is the bit line BL.

5. The dual sampling sensing circuit for MRAM according to claim 3, wherein, The sampling module comprises a buffer unit, a switch tube unit and a voltage holding unit. The buffer unit is configured to control the switch tube unit to close the switch tube located on the second bit line when the voltage on the first bit line drops to the threshold voltage. The buffer unit is configured to control the switch tube unit to close the switch tube located on the second bit line when the voltage on the first bit line drops to the threshold voltage. The voltage holding unit is used to hold the voltage on the second bit line when a switch tube on the second bit line is closed.

6. The dual sampling sensing circuit for MRAM according to claim 5, wherein, The buffer unit comprises a buffer Buff0 and a buffer Buff1, the switch tube unit comprises a switch tube T0 and a switch tube T1, and the voltage holding unit comprises a capacitor C0 and a capacitor C1. The input end of the buffer Buff0 is electrically connected with the bit line BL, the output end of the buffer Buff0 is electrically connected with the gate of the switch tube T1, the drain of the switch tube T1 is electrically connected with the bit line BLB, the source of the switch tube T1 is electrically connected with one end of the capacitor C1, and the other end of the capacitor C1 is electrically connected with the common ground terminal VSS; the input end of the buffer Buff1 is electrically connected with the bit line BLB, the output end of the buffer Buff1 is electrically connected with the gate of the switch tube T0, the drain of the switch tube T0 is electrically connected with the bit line BL, the source of the switch tube T0 is electrically connected with one end of the capacitor C0, and the other end of the capacitor C0 is electrically connected with the common ground terminal VSS.

7. The dual sampling sensing circuit for MRAM according to claim 6, wherein, The sensing amplification module comprises a sensing amplifier, one input end of the sensing amplifier is electrically connected with one end of the capacitor C0 not grounded, the other input end of the sensing amplifier is electrically connected with one end of the capacitor C1 not grounded, and the output end of the sensing amplifier is used for outputting the digital signal.

8. The dual sampling sensing circuit for MRAM according to claim 1, wherein, Each data unit comprises a switch tube N0, a switch tube N1 and a data MTJ device, wherein the drain of the switch tube N0 is electrically connected with the bit line BL, the source of the switch tube N0 is electrically connected with one end of the data MTJ device, the drain of the switch tube N1 is electrically connected with the bit line BL, and the source of the switch tube N1 is electrically connected with the other end of the data MTJ device; the data MTJ device is further electrically connected with a source line SL, and the source line SL is further electrically connected with the pre-charge and discharge control module; Each reference unit comprises a switch tube N2, a switch tube N3 and a reference MTJ device, wherein the drain of the switch tube N2 is electrically connected with the bit line BLB, the source of the switch tube N2 is electrically connected with one end of the reference MTJ device, the drain of the switch tube N3 is electrically connected with the bit line BLB, and the source of the switch tube N3 is electrically connected with the other end of the reference MTJ device; the reference MTJ device is further electrically connected with a source line SLB, and the source line SLB is further electrically connected with the pre-charge and discharge control module. The gate of the switch tube N0 and the gate of the switch tube N2 are both used for inputting the read control signal RL, and the gate of the switch tube N1 and the gate of the switch tube N3 are both used for inputting the write control signal WL.

9. The dual sampling sensing circuit for MRAM according to claim 1, wherein, The pre-charge and discharge control module comprises a switch tube P0, a switch tube P1, a switch tube N4 and a switch tube N5; The source electrode of the switch tube P0 is used for accessing a power supply voltage VDD, the drain electrode of the switch tube P0 is electrically connected with a bit line BL of a data cell in each SOT-MRAM, the gate electrode of the switch tube P0 and the gate electrode of the switch tube P1 are both used for accessing a charging control signal PRE, the source electrode of the switch tube P1 is used for accessing the power supply voltage VDD, and the drain electrode of the switch tube P1 is electrically connected with a bit line BLB of a reference cell in each SOT-MRAM; the gate electrodes of the switch tube N4 and the switch tube N5 are both used for accessing a discharging control signal DIS, the drain electrode of the switch tube N4 is electrically connected with a source line SL of the data cell in each SOT-MRAM, the source electrode of the switch tube N4 is electrically connected with a common ground terminal VSS, the drain electrode of the switch tube N5 is electrically connected with a source line SLB of the reference cell in each SOT-MRAM, and the source electrode of the switch tube N5 is electrically connected with the common ground terminal VSS.

10. The dual sampling sensing circuit for MRAM according to claim 1, wherein, When it is required to read data from the data cell in any one SOT-MRAM of the at least one SOT-MRAM, the voltages on the bit line BL of the data cell and the bit line BLB of the reference cell in the any one SOT-MRAM are both charged to the power supply voltage VDD by the pre-charging and discharging control module, then the any one SOT-MRAM is selected as a target SOT-MRAM by the read control signal RL and the write control signal WL, and the bit line BL of the data cell and the bit line BLB of the reference cell in the target SOT-MRAM are discharged by the pre-charging and discharging control module, the voltages on the bit line BL and the bit line BLB are collected by the sampling module during the discharging of the bit line BL and the bit line BLB, so that the voltage on the bit line BL and the voltage on the bit line BLB have a maximum voltage difference, the maximum voltage difference between the bit line BL and the bit line BLB is amplified by the sense amplifier module, and a corresponding digital signal is output.

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