A resistive readout cell circuit for in-memory computation of FLASH

Abstract

The application discloses a resistance type readout unit circuit for FLASH in-memory computing and relates to the technical field of integrated circuits, comprising a conversion module and a quantization module, the conversion module comprises positive weight current conversion units and negative weight current conversion units which are identical in structure, the input ends of the positive weight current conversion units and the negative weight current conversion units are connected with positive weight bit lines and negative weight bit lines respectively, and each of the positive weight current conversion units and the negative weight current conversion units comprises an operational amplifier, a driving transistor, a compensation resistor, a compensation capacitor and a compensation transistor; the quantization module comprises two sampling switches, two CDACs, a comparator and a SAR logic circuit, the input ends of the two sampling switches are connected with the output ends of positive weight resistance modules and negative weight resistance modules respectively, and the output ends of the two sampling switches are connected with the upper plates of the two CDACs and the positive input end and the negative input end of the comparator respectively. The resistance type readout unit circuit can stably drive and analog-digital convert the fast-changing memory-computing current with small area and power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a resistance type readout unit circuit for in-memory computing of FLASH. BACKGROUND

[0002] In recent years, artificial intelligence technologies represented by neural networks have developed rapidly and made significant breakthroughs in natural language and image / video processing. However, the inherent limitations of the traditional von Neumann computing architecture have caused the "memory wall" and "power wall" problems, leading to the increasing contradiction between the high computing power demand of neural networks and the low power requirement of edge and terminal devices, which has seriously restricted the further development and application of artificial intelligence technologies. In this context, the in-memory computing (CIM) architecture has emerged. CIM directly performs data operations and processing within the memory, fundamentally eliminating the overhead generated by data transfer, realizing the integration of storage and computing, and becoming one of the important research directions in the field of integrated circuits in the post-moore era.

[0003] Currently, the main memory devices used in CIM architecture include static random access memory (SRAM), dynamic random access memory (DRAM), resistive random access memory (RRAM), phase-change memory (PCM), and FLASH memory. Among them, FLASH memory has become an important storage carrier for CIM technology due to its high storage density, non-volatility, and strong compatibility with CMOS (Complementary Metal Oxide Semiconductor) process. In CIM circuits based on FLASH memory, the multiply-add computation operation is performed in the form of analog current signals in the memory-computing array, and the computation results need to be accurately read out by a dedicated readout unit circuit. To achieve a computing power of Tera Operations Per Second (TOPS) level, the memory-computing array is usually composed of a matrix of hundreds of rows and hundreds of columns of memory cells, and the memory cells in the same row are connected to a readout unit circuit through a bit line. As the computing power requirement of CIM continues to increase, the size of the memory-computing array continues to expand, and the number of readout unit circuits required also increases significantly, making the readout unit circuit gradually become the main bottleneck restricting the area and power efficiency of CIM. Therefore, improving the working speed and current handling range of the readout unit circuit while reducing its power consumption and area has become an important problem to be solved for the further development of CIM technology.

[0004] The readout unit circuitry for FLASH memory arrays typically consists of a current-to-voltage converter (IVC) and an analog-to-digital converter (ADC). The primary function of the IVC is to clamp the voltage and drive the current of the bit lines in the FLASH memory array, converting the stored current on the bit lines into an analog voltage signal. The classic transimpedance amplifier structure performs well in this function; however, this structure is prone to instability when driving rapidly changing stored currents. Therefore, existing structures usually employ two operational amplifiers to implement the voltage clamping and current-to-voltage conversion functions separately, but this increases the IVC's area and power consumption. The primary function of the ADC is to quantize the analog voltage signal output by the IVC into digital code. Among various ADC structures, the Successive Approximation Register (SAR) ADC, with its low power consumption advantage, has become the mainstream choice for CIM applications. To ensure linearity during sampling, general-purpose SAR ADCs require their input signals to have strong driving capability. This means that traditional readout unit circuits typically add a buffer between the output of the IVC and the input of the SAR ADC to drive the SAR ADC sampling, but this incurs additional area and power consumption overhead. Summary of the Invention

[0005] Based on the shortcomings of the existing technology, the present invention provides a resistive readout unit circuit for FLASH memory computation, which solves the problem of large area and power consumption of traditional readout unit circuits.

[0006] This invention provides a resistive readout unit circuit for FLASH memory computation, including a conversion module and a quantization module;

[0007] The conversion module comprises positive weight current conversion units and negative weight current conversion units with the same structure, and positive weight resistance modules and negative weight resistance modules with the same structure; wherein the input ends of the positive weight current conversion units and the negative weight current conversion units are connected with positive weight bit lines and negative weight bit lines respectively, and the output ends are connected with the input ends of the positive weight resistance modules and the negative weight resistance modules respectively; the positive weight current conversion units and the negative weight current conversion units each comprise an operational amplifier, a driving transistor, a compensation resistor, a compensation capacitor and a compensation transistor; the positive end of the operational amplifier is connected with a clamping voltage source, the negative end is connected with the source of the driving transistor, a corresponding bit line and the drain of the compensation transistor, and the output end is connected with the gate of the driving transistor; the compensation resistor and the compensation capacitor are connected in series between the gate and the drain of the driving transistor, the gate of the compensation transistor is connected with a bias voltage source, and the source is grounded; the output ends of the positive weight resistance modules and the negative weight resistance modules are used for outputting corresponding voltage signals;

[0008] The quantization module comprises two sampling switches, two CDACs, a comparator and a SAR logic circuit, wherein the input ends of the two sampling switches are connected with the output ends of the positive weight resistance modules and the negative weight resistance modules respectively, the output ends are connected with the upper plates of the two CDACs and the positive input end and the negative input end of the comparator respectively, the output end of the comparator is connected with the input end of the SAR logic circuit, and the SAR logic circuit is used for outputting N a digital code.

[0009] Preferably, the positive weight current conversion unit comprises a first operational amplifier , a first driving transistor , a first compensation resistor , a first compensation capacitor and a first compensation transistor ; the positive end of the first operational amplifier is connected with a clamping voltage source , the negative end is connected with the source of the first driving transistor , a positive weight bit line and the drain of the first compensation transistor , the output end is connected with the gate of the first driving transistor , the first compensation resistor and the first compensation capacitor are connected in series between the gate and the drain of the first driving transistor , the gate of the first compensation transistor is connected with a bias voltage source , and the source is grounded.

[0010] The negative weight current conversion unit comprises a second operational amplifier , a second driving transistor , a second compensation resistor Second compensation capacitor and the second compensation transistor Second operational amplifier The positive terminal and the clamping voltage source Connect the negative terminal to the second driving transistor. The source, negative weight bit line, and second compensation transistor The drain is connected, and the output is connected to the second driving transistor. Gate connection, second compensation resistor Second compensation capacitor Connected in series with the second driving transistor Between the gate and drain of the second compensation transistor Gate and bias voltage source Connect, source grounded.

[0011] Preferably, both the positive weight resistor module and the negative weight resistor module include multiple resistors of different resistance values ​​connected in parallel and multiple switches. One end of each of the multiple switches is connected to the drain of the driving transistor and the output terminal for outputting voltage; the other end is connected to one end of each of the multiple resistors, and the other end of each of the multiple resistors is connected to a power supply voltage source.

[0012] Preferably, the positive weighting resistor module includes a first positive resistor R. P1 The second positive resistor R P2 The third positive resistor R P3 Fourth positive resistor R P4 Fifth positive resistor R P5 First positive switch S P1 Second positive switch S P2 Third positive switch S P3 Fourth positive switch S P4 and the fifth positive switch S P5 Among them, the first positive switch S P1 Second positive switch S P2 Third positive switch S P3 Fourth positive switch S P4 and the fifth positive switch S P5 One end is connected to the first driving transistor The drain and positive output terminals are connected, and the other terminals are connected to the first positive resistor R. P1 The second positive resistor R P2 The third positive resistor R P3 Fourth positive resistor R P4 and the fifth positive resistor R P5 One end of the resistor is connected, and the other ends of the multiple positive resistors are all connected to the power supply voltage source. The positive output terminal is used to output a positive weighted voltage signal.

[0013] The negative weight resistance module comprises a first negative resistance R N1 , a second negative resistance R N2 , a third negative resistance R N3 , a fourth negative resistance R N4 , and a fifth negative resistance R N5 , a first negative switch S N1 , a second negative switch S N2 , a third negative switch S N3 , a fourth negative switch S N4 , and a fifth negative switch S N5 , wherein one end of the first negative switch S N1 , the second negative switch S N2 , the third negative switch S N3 , the fourth negative switch S N4 , and the fifth negative switch S N5 is connected with the drain of the first driving transistor and a negative output end, and the other end is connected with one end of the first negative resistance R N1 , the second negative resistance R N2 , the third negative resistance R N3 , the fourth negative resistance R N4 , and the fifth negative resistance R N5 respectively, and the other end of the plurality of negative resistances is connected with a power voltage source , and the negative output end is used for outputting a negative weight voltage signal.

[0014] Preferably, the resistance values of the first positive resistance R P1 , the second positive resistance R P2 , the third positive resistance R P3 , the fourth positive resistance R P4 , and the fifth positive resistance R P5 and the first negative resistance R N1 , the second negative resistance R N2 , the third negative resistance R N3 , the fourth negative resistance R N4 , and the fifth negative resistance R N5 are configured in a ratio of 1:2:4:8:16, and the voltage difference output by the positive weight resistance module and the negative weight resistance module is specifically as follows:

[0015] ;

[0016] wherein, is the voltage difference, R S is the resistance value of the selected positive resistance and negative resistance, is the negative weight accumulation current, is the positive weight accumulation current.

[0017] Preferably, the two sampling switches include a first sampling switch and a second sampling switch, and the two CDACs include a first CDAC and a second CDAC; the first CDAC includes a plurality of first high-order capacitors, a plurality of first low-order capacitors and a first bridge capacitor; the second CDAC includes a plurality of second high-order capacitors, a plurality of second low-order capacitors and a second bridge capacitor;

[0018] In the sampling stage, the lower plates of the plurality of first high-order capacitors and the lower plates of the first low-order capacitors in the first CDAC are connected with a reference voltage source , the upper plates of the plurality of first high-order capacitors and the upper plate of the first bridge capacitor are connected with an output end of the first sampling switch and one input end of the comparator; the lower plates of the plurality of second high-order capacitors and the lower plates of the second low-order capacitors in the second CDAC are connected with a reference voltage source , the upper plates of the second high-order capacitors and the upper plate of the second bridge capacitor are connected with an output end of the second sampling switch and the other input end of the comparator;

[0019] In the quantization stage, the SAR logic circuit generates a first clock signal to control the comparator to compare the voltages at the two input ends, and transmits the comparison result back to the SAR logic circuit to generate a digital code of a current bit and a second clock signal to control switching of the two CDACs;

[0020] The quantization module generates a digital code representing a result of in-memory calculation and an indication signal representing completion of quantization after the sampling stage and the quantization stage.

[0021] Compared with the prior art, the above at least one technical solution of the present application can achieve the following beneficial effects:

[0022] The readout unit circuit of the present application includes a conversion module and a quantization module, wherein the conversion module includes a positive weight current conversion unit and a negative weight current conversion unit which have the same structure and each include an operational amplifier, a driving transistor, a compensation resistor, a compensation capacitor and a compensation transistor; the operational amplifier and the driving transistor jointly clamp a corresponding bit line to a fixed voltage to provide stable current driving for the bit line; the compensation resistor and the compensation capacitor are connected in series between the gate and the drain of the driving transistor to ensure stability of the clamping circuit; the compensation transistor has a gate connected with a bias voltage source and a source connected with the ground to provide a basic working current for the clamping circuit, so that the clamping circuit can still maintain a saturated state of the driving transistor when the memory and calculation current is small or 0. This design avoids the influence of the conversion resistor on the stability of the clamping loop, so that the conversion module can stably drive the rapidly changing memory and calculation current with a smaller area and power consumption.

[0023] The quantization module comprises two sampling switches, two CDACs, a comparator and a SAR logic circuit, wherein the input ends of the two sampling switches are connected with the output ends of the positive weight resistance module and the negative weight resistance module respectively, the output ends are connected with the upper plates of the two CDACs and the positive input end and the negative input end of the comparator respectively, the output end of the comparator is connected with the input end of the SAR logic circuit, and the SAR logic circuit is used for outputting N bit digital code. The application connects the CDAC to the output end of the conversion module through the sampling switch, so that it participates in the current-voltage conversion process of the next cycle as the load of the conversion module, without increasing the buffer, reduces the area, and completes the sampling of the quantization module at the same time when the conversion module completes the conversion, thereby avoiding the additional overhead required for the quantization module to wait for the output voltage of the conversion module to be stable before sampling, and improving the working speed and power efficiency of the readout unit circuit. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0025] Figure 1 The schematic structure of the in-memory computing macro circuit based on the FLASH memory;

[0026] Figure 2 The traditional readout unit circuit structure diagram;

[0027] Figure 3 The resistance type readout unit circuit structure diagram of the present application;

[0028] Figure 4 The structure diagram of the conversion module in the resistance type readout unit circuit of the present application;

[0029] Figure 5 The structure diagram of the quantization module in the resistance type readout unit circuit of the present application;

[0030] Figure 6 The working timing diagram of the resistance type readout unit circuit of the present application;

[0031] Figure 7 The input-output characteristic curve of the resistance type readout unit circuit of the present application;

[0032] Figure 8 The output time domain simulation result of the conversion module in the resistance type readout unit circuit of the present application;

[0033] Figure 9 FFT results output by the quantization module in the resistance type readout unit circuit of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of the present application.

[0035] In order to explain the principles and effects of the present application, the structure of the in-memory computing macro circuit based on the FLASH memory and the structure and principles of the conventional readout unit circuit are first described.

[0036] Figure 1 The schematic structure of the in-memory computing macro circuit based on the FLASH memory includes a computing array composed of m rows and n columns of FLASH memory units, m rows of readout unit circuits, a digital shift adder and a general memory. The computing array is mainly responsible for storing weight data and performing multiplication and addition operation of the weight data and input data on the word line. Since the multiplication and addition operation is performed in the form of analog current, and the weight data of the computing array is usually in differential form (divided into positive weight data and negative weight data), the operation results of the positive weight data and the input data are converged in the form of current on the positive weight bit line BLP, and the operation results of the negative weight data and the input data are converged in the form of current on the negative weight bit line BLN. Therefore, the multiplication and addition results of the m rows in the computing array are converged on m pairs of differential bit lines (BLP1 and BLN1, BLP2 and BLN2, … BLPm and BLNm), which need to be read out by the m rows of readout unit circuits one by one. Then, the digital codes converted by the m rows of readout unit circuits are subjected to shift addition operation by the digital shift adder, and the calculation results are stored in the general memory. m and BLN m ), which need to be read out by the m rows of readout unit circuits one by one. Then, the digital codes converted by the m rows of readout unit circuits are subjected to shift addition operation by the digital shift adder, and the calculation results are stored in the general memory.

[0037] Figure 2 The structure diagram of the conventional readout unit circuit includes a Trans-Impedance Amplifier (TIA), an output buffer and an Analog-to-Digital Converter (ADC). The circuit adopts a TIA to realize the IVC function, and the voltages of the positive weight bit line BLP and the negative weight bit line BLN are clamped to preset values by two TIAs and The storage and calculation current on the BLP and the BLN is converted into an analog voltage. Then, the analog voltage is driven to an ADC through an output buffer for sampling, and a digital code is obtained by quantization of the ADC The circuit can quickly complete current-voltage conversion, but since sampling of the ADC is performed after the TIA completes conversion, in order to ensure stability of the TIA output voltage, a unit gain buffer needs to be additionally used to drive the voltage to the ADC, which greatly increases power consumption and area overhead of the circuit. In addition, in order to avoid the resistors and affecting stability of the clamping loop, the circuit usually uses a TIA structure composed of two operational amplifiers to respectively implement clamping and voltage-current conversion functions, which also increases overhead of the circuit.

[0038] To further improve area and power efficiency of the CIM chip, the readout unit circuit also needs to further optimize structure and sampling timing of the ADC according to the output voltage range and driving capability of the IVC.

[0039] To overcome the shortcomings of the prior art, the present application provides a resistance type readout unit circuit for FLASH in-memory computing. The circuit is used for converting an analog current signal representing a multiplication and addition calculation result in a storage and calculation array into a digital code, and includes a conversion module (implementing an IVC function) and a quantization module (implementing an SAR ADC function). The conversion module is composed of a clamping circuit based on a low dropout linear regulator (LDO) and a multi-gear programmable resistance module. This structure avoids the influence of resistors in a traditional transimpedance amplifier on stability of a clamping loop, realizes clamping, driving and current-voltage conversion functions of the FLASH storage and calculation array with small overhead, and effectively improves an input dynamic range of the readout circuit. The quantization module adopts a capacitor digital-to-analog converter (CDAC) structure combining scaled capacitors and one-way switching logic, so that the quantization range can accurately adapt to the output voltage range of the conversion module. In addition, the present application cooperatively optimizes working timing of the conversion module and the quantization module, completes sampling of the quantization module at the same time as current-voltage conversion of the conversion module, and improves working speed and power efficiency of the readout circuit.

[0040] To better understand the principles and advantages of the present application, the following will be described in combination with Figures 3 to 9 The readout unit circuit of the present application includes a conversion module and a quantization module. The function of the conversion module is to clamp and drive a voltage of a bit line of the FLASH storage and calculation array, and convert storage and calculation current on the bit line into an analog voltage; the main function of the quantization module is to quantize the analog voltage signal output by the conversion module, and output a digital code representing a result of in-memory calculation.

[0041] The conversion module comprises positive weight current conversion units and negative weight current conversion units with the same structure, and positive weight resistance modules and negative weight resistance modules; wherein, the input ends of the positive weight current conversion units and the negative weight current conversion units are connected with the positive weight bit line and the negative weight bit line respectively, and the output ends are connected with the input ends of the positive weight resistance modules and the negative weight resistance modules respectively; each of them comprises an operational amplifier, a driving transistor, a compensation resistor, a compensation capacitor and a compensation transistor; the positive end of the operational amplifier is connected with a clamping voltage, the negative end is connected with the source of the driving transistor, the corresponding bit line and the drain of the compensation transistor, the output end is connected with the gate of the driving transistor, the compensation resistor and the compensation capacitor are connected in series between the gate and the drain of the driving transistor, the gate of the compensation transistor is connected with a bias voltage, and the source is grounded; the output ends of the positive weight resistance modules and the negative weight resistance modules are used for outputting corresponding voltage signals. N The quantization module comprises two sampling switches, two CDACs, a comparator and a SAR logic circuit, wherein, the input ends of the two sampling switches are connected with the output ends of the positive weight resistance modules and the negative weight resistance modules respectively, the output ends are connected with the upper plates of the two CDACs and the positive input end and the negative input end of the comparator respectively, the output end of the comparator is connected with the input end of the SAR logic circuit, and the SAR logic circuit is used for outputting

[0042] In one embodiment, the resistance type readout unit circuit structure of the present application is as shown in Figure 3 The input end is connected with the positive weight bit line BLP and the negative weight bit line BLN of the FLASH memory array, the voltage of BLP and BLN is clamped to a preset value by the conversion module , so that the two sides of each memory cell in the FLASH memory array keep a fixed pressure difference, thereby generating stable memory and calculation current. When the CIM system performs multiplication and addition calculation operation, the memory cells selected by the memory and calculation array word line group WL<255:0> (i.e. the input data of the CIM system) will form current from the bit line to the ground, which will converge on BLP or BLN and form positive weight memory and calculation current and negative weight memory and calculation current respectively. In addition, the resistance type readout unit circuit of the present application converts the memory and calculation current into analog voltage and by the multi-gear programmable resistance in the conversion module and , and the CDAC (Capacitive Digital-to-Analog Converter) in the quantization module is connected to the output end of the conversion module before the conversion module starts conversion, so that the sampling of the quantization module is completed at the same time when the current-voltage conversion of the conversion module is completed. Then, the output voltage of the conversion module is quantized into digital code by the quantization module immediately, and an indication signal CK D representing the end of quantization is generated.

[0043] In one embodiment, the structure of the conversion module in the resistive readout unit circuit of the present invention is as follows: Figure 4 As shown, it includes a positive-weighted current conversion unit connected to the positive-weighted bit line BLP and a negative-weighted current conversion unit connected to the negative-weighted bit line BLN. Both conversion units employ the same structure, each including an LDO-based clamping circuit and a multi-stage programmable resistor module. The clamping circuit is used to clamp the voltages of bit lines BLP and BLN to preset values. Simultaneously driving the storage current on the bit lines and This ensures the stability of the stored current; the multi-position programmable resistor module is used to convert the stored current on the bit line into a voltage signal and output it to the quantization module.

[0044] In one embodiment, the LDO-based clamping circuit in the positive weighted current conversion unit includes a first operational amplifier. First driving transistor First compensation resistor First compensation capacitor and the first compensation transistor that provides compensation current. First operational amplifier The positive terminal is connected to the clamping voltage. The negative end connects to the bit line BLP. The drain and The source and output terminals are connected to The gate. First compensation resistor. and the first compensation capacitor Connected to The gate and drain of the first compensation transistor are positioned to ensure the stability of the clamping circuit. Gate connection bias voltage The source is grounded to provide the basic operating current for the clamping circuit. This allows the clamping circuit to maintain the first driving transistor even when the storage current is small or zero. The saturation state. Furthermore, the clamping circuit structure in the negative-weighted current conversion unit is the same as that in the positive-weighted current conversion unit; the difference lies in the input of the clamping circuit in the positive-weighted current conversion unit ( The source is connected to the bit line BLP, and the output is ( (drain) connection The input of the clamping circuit in the negative weighted current conversion unit ( The source is connected to the bit line BLN, and the output is ( (drain) connection .

[0045] The negative weighted current conversion unit includes a second operational amplifier. Second driving transistor Second compensation resistor Second compensation capacitor and the second compensation transistor Second operational amplifier positive terminal and clamping voltage Connect the negative terminal to the second driving transistor. The source, negative weight bit line, and second compensation transistor The drain is connected, and the output is connected to the second driving transistor. Gate connection, second compensation resistor Second compensation capacitor Connected in series with the second driving transistor Between the gate and drain of the second compensation transistor Gate and bias voltage Connect, source grounded.

[0046] In one embodiment, both the positive-weighted resistor module and the negative-weighted resistor module include multiple resistors of different resistance values ​​connected in parallel and multiple switches. One end of each switch is connected to the drain and output terminal of the driving transistor for outputting voltage; the other end is connected to one end of each of the multiple resistors, and the other end of each of the multiple resistors is connected to the power supply voltage. The multi-position programmable resistor module includes a resistor R. P1 ~R P5 and switch S P1 ~S P5 The multi-position programmable resistor module in the negative weight current conversion unit includes resistor R. N1 ~R N5 and switch S N1 ~S N5 Resistance R P1 ~R P5 The resistance values ​​are configured in a ratio of 1:2:4:8:16, and the resistor R N1 ~R N5 The resistance value and R P1 ~R P5 Correspondingly equal, the positive terminals of these resistors are all connected to the power supply voltage. The negative terminals are connected to switch S respectively. P1 ~S P5 and S N1 ~S N5 .

[0047] Specifically, the positive weighted resistor module includes a first positive resistor R. P1 The second positive resistor R P2 The third positive resistor R P3 Fourth positive resistor RP4 , fifth positive resistor R P5 , first positive switch S P1 , second positive switch S P2 , third positive switch S P3 , fourth positive switch S P4 , and fifth positive switch S P5 , wherein one end of the first positive switch S P1 , second positive switch S P2 , third positive switch S P3 , fourth positive switch S P4 , and fifth positive switch S P5 is connected with the first driving transistor drain and positive output end, and the other end is connected with one end of the first positive resistor R P1 , second positive resistor R P2 , third positive resistor R P3 , fourth positive resistor R P4 , and fifth positive resistor R P5 , respectively, and the other end of the plurality of positive resistors is connected with the power supply voltage , and the positive output end is used for outputting a positive weight voltage signal.

[0048] The negative weight resistor module includes first negative resistor R N1 , second negative resistor R N2 , third negative resistor R N3 , fourth negative resistor R N4 , fifth negative resistor R N5 , first negative switch S N1 , second negative switch S N2 , third negative switch S N3 , fourth negative switch S N4 , and fifth negative switch S N5 , wherein one end of the first negative switch S N1 , second negative switch S N2 , third negative switch S N3 , fourth negative switch S N4 , and fifth negative switch S N5 is connected with the first driving transistor drain and negative output end, and the other end is connected with one end of the first negative resistor R N1 , second negative resistor R N2 , third negative resistor R N3 , fourth negative resistor R N4 , and fifth negative resistor R N5 , respectively, and the other end of the plurality of negative resistors is connected with the power supply voltage , and the negative output end is used for outputting a negative weight voltage signal.

[0049] In different application scenarios, the CIM system programs the multi-grade programmable resistance modules in the positive weight current conversion unit and the negative weight current conversion unit to select a pair of resistors R P1 ~R P5 and R N1 ~R N5 as the conversion resistor and , and connects the negative end of the conversion resistor to the drain of the driving transistor and in the clamping circuit, respectively. At this time, the current flowing through the resistor is the positive weight storage current of the branch and the compensation current and . The negative end voltage of the resistor , that is, the output voltage of the positive weight current conversion unit, can be represented as . Similarly, the relationship between the output voltage of the negative weight current conversion unit and the negative weight storage current can be represented as . Since , and let the resistance value be , the relationship between the voltage difference ( ) between the positive and negative output ends of the conversion module and , can be represented as:

[0050] ;

[0051] wherein is the voltage difference, R S is the resistance value of the selected positive resistor and negative resistor, is the negative weight storage current, is the positive weight storage current.

[0052] In this embodiment, the CIM system has five storage current maximum values, and the resistance type readout unit circuit of the present application programs the size of the conversion resistor in the conversion module to make the voltage difference between the positive and negative output ends of the conversion module in the five current grades change in the range of 200 mV, that is, the peak-to-peak value of is 400 mV.

[0053] The two sampling switches include a first sampling switch and a second sampling switch, and the two CDACs include a first CDAC and a second CDAC.

[0054] In one embodiment, the structure of the 8-bit quantization module in the resistance type readout unit circuit of the present application is shown in Figure 5 which includes a first sampling switch, a second sampling switch, a first CDAC, a second CDAC, a comparator and a SAR logic circuit. The CDAC is a capacitive digital-to-analog converter. The first CDAC includes a capacitor C P1 C P7 , a first bridge capacitor C B1 , a first unit capacitor C U1 , and a first scaling capacitor C S1 . The second CDAC includes a capacitor C N1 C N7 , a second bridge capacitor C B2 , a second unit capacitor C U2 , and a second scaling capacitor C S2 . In the first CDAC, the capacitor C P1 C P4 and the first unit capacitor C U1 are first low-bit capacitors, and the capacitor C P5 C P7 is a first high-bit capacitor. In the second CDAC, the capacitor C N1 C N4 and the second unit capacitor C U2 are second low-bit capacitors, and the capacitor C N5 C N7 is a second high-bit capacitor.

[0055] The first CDAC and the second CDAC are both segmented 8-bit structures (including 5 low bits and 3 high bits) to reduce the total capacitance size that needs to be driven by the conversion module during the sampling stage of the quantization module. The first bridge capacitor C B1 and the second bridge capacitor C B2 are used to connect the low-bit capacitors and the high-bit capacitors. The capacitance values of the first unit capacitor C U1 and the second unit capacitor C U2 are C U , which are used to complete the binary relationship of the capacitor array. The first scaling capacitor C S1 and the second scaling capacitor C S2 are used to scale the quantization range of the quantization module to the same peak-to-peak value as the voltage difference between the positive output terminal and the negative output terminal of the conversion module. Since the equivalent sampling capacitance size of the first CDAC is 8C U , and the reference voltage in this embodiment is 1.5V, peak-to-peak value of 400 mV, and according to the charge conservation, C S1 is 22 C U . Similarly, the size of C S2 in the second CDAC is also 22 C U . In addition, in order to further adapt the output voltage range of the conversion module, the CDAC adopts one-way switching logic, that is, during the sampling stage of the quantization module, the lower plate of C P1 C P7 and C N1 C N7 is connected to , and during the quantization stage, it is switched from to GND or remains unchanged . During the sampling of the quantization module, the upper plate of C P5 C P7 in the first CDAC and the upper plate of the bridging capacitor C B1 are connected to the output end of the first sampling switch and one input end of the comparator; the upper plate of C N5 C N7 in the second CDAC and the upper plate of the bridging capacitor C B2 are connected to the output end of the second sampling switch and the other input end of the comparator. The two sampling switches are used to sample the output voltage and of the conversion module and keep them on the first CDAC and the second CDAC respectively. After the sampling is completed, the quantization module enters the quantization stage, and the first clock signal CK C generated by the SAR logic circuit is used to control the comparator to compare the voltages at its positive and negative ends, and the comparison result is transmitted back to the SAR logic circuit, so as to generate the digital code B N of the current bit (in this embodiment, B N is 0 7) and the second clock signal CK N for controlling the switching of the two CDACs. After 8 cycles of the above quantization process, the quantization module will generate an 8-bit digital code representing the in-memory calculation result and an indication signal CK D representing the completion of quantization.

[0056] In an embodiment, the working timing of the resistance type readout unit circuit of the present application is shown in Figure 6 . At time t , the CIM system controls the signal CK WLThe word line group WL<255:0> of the FLASH memory array is driven, thereby selecting or disabling some memory cells and changing the memory current values ​​on BLP and BLN. Subsequently, the conversion module converts the changed memory current into analog voltage. and At the same time, the CIM system uses the signal CK S CK0 is reset on the rising edge, and the conversion is completed in the conversion module. At that moment, through CK S The falling edge of the signal samplees the output voltage of the conversion module and holds it on the CDAC of the quantization module. arrive At that moment, the SAR logic circuit in the quantization module will generate signal CK7. CK0 (CK5~CK1 are represented by ellipses in the diagram) quantizes the output voltage of the conversion module, and immediately after quantization, controls the sampling switch via CK0 to connect the upper plates of the high 3 bits of the CDAC capacitor and the bridging capacitor to the output terminal of the conversion module. arrive At any given moment, the CIM control system uses the indication signal CK generated by the quantization module. D To collect the 8-bit digital code representing the in-memory calculation result .exist After a certain time, the CIM control system will change the stored current values ​​on BLP and BLN according to the stored results it has collected, while the CDAC in the quantization module will directly participate in the current-voltage conversion process as the load of the conversion module, and then continue to participate in the quantization process of the quantization module.

[0057] Figure 7 This is the input-output characteristic curve of the resistive readout unit circuit of this invention. The vertical axis represents the negative weighted computing current value in the FLASH computing array. With positive weighted storage current value The difference The difference serves as the input to the readout unit circuit; the horizontal axis represents the digital code output by the readout unit circuit after its input has been converted by the conversion module and quantized by the quantization module. In this embodiment, the maximum storage current of the CIM system used in this invention has five levels, namely 3.125... A, 6.25 A, 12.5 A, 25 A and 50 A, and the resistance type readout unit circuit of the application can make the output digital code range of the conversion module in the case of different gear current input between 0-255 by adjusting the size of the conversion resistance in the conversion module. Therefore, the resistance type readout unit circuit of the application has higher input dynamic range and linearity, and can effectively adapt to various application scenarios of the CIM system.

[0058] Figure 8 is the output time domain simulation result of the conversion module in the resistance type readout unit circuit of the application. Wherein, and The initial value is 0 A, at 10nS, becomes the maximum value 12.5 of the storage and calculation current of the third gear of the CIM system A, becomes the unit value 97.6nA of the storage and calculation current under the third gear 3. In and After the change, the conversion module immediately starts the current-voltage conversion work and can establish the output voltage and within 50nS. Therefore, the working frequency of the conversion module in the embodiment is maximum 20MHz, which can meet the speed requirement of the readout unit circuit of the CIM system.

[0059] The power spectrum density diagram obtained by performing fast Fourier transform (FFT) on the output of the quantization module (8 bits in the embodiment) in the resistance type readout unit circuit of the application is shown in Figure 9 , wherein the sampling frequency of the quantization module is 10 MSPS, and the input signal is a single-frequency sine wave of 998.5 kHz. It can be seen that the effective number of bits (ENOB) of the quantization module in the embodiment is 7.55bit, the signal-to-noise distortion ratio (SNDR) is 47.19dB, the spurious-free dynamic range (SFDR) is 66.8dB, the signal-to-noise ratio (SNR) is 47.3dB, and the total harmonic distortion (THD) is 63.38dB. The overall performance can meet the accuracy requirement of the readout unit circuit of the CIM system.

[0060] In summary, the resistance type readout unit circuit for FLASH in-memory computing proposed in the application can quickly and stably convert the storage and calculation current signal into a digital signal, and has the advantages of multiple gears, high input dynamic range, low power consumption and small area.

[0061] In the conversion module, the clamping circuit based on LDO is used to clamp and drive the bit line of the FLASH storage and calculation array, and by isolating the clamping loop and the conversion resistance from each other, the influence of the conversion resistance on the stability of the clamping loop is avoided, so that the conversion module can stably drive the rapidly changing storage and calculation current with small area and power consumption.

[0062] The application adopts a multi-gear programmable conversion resistance in the conversion module, so that the peak-to-peak value of the output voltage of the conversion module can remain consistent when processing different gears of the computing current, and the application adopts a combination of scaling capacitance and one-way switching logic in the CDAC of the quantization module, so that the quantization range of the quantization module can adapt to the output voltage range of the conversion module. Therefore, through the collaborative design of the conversion module and the quantization module, the input dynamic range and the readout accuracy of the readout circuit are effectively improved.

[0063] The application directly connects the CDAC to the output end of the conversion module after the quantization module completes quantization, so that it participates in the current-voltage conversion process of the next cycle as a load of the conversion module, and the sampling of the quantization module is completed at the same time as the conversion of the conversion module is completed, thereby avoiding the additional overhead required for waiting for the conversion of the conversion module to complete before sampling, and improving the working speed and power efficiency of the readout circuit.

[0064] The application provides a resistance type readout unit circuit for FLASH in-memory computing, including a conversion module and a quantization module. The conversion module is composed of a low dropout linear regulator (LDO) based clamping circuit and a multi-gear programmable resistance module, which not only improves the stability and current processing range of the circuit, but also avoids the additional overhead caused by using multiple operational amplifiers. Secondly, the application adopts a CDAC structure combining scaling capacitance and one-way switching logic in the quantization module, so that the quantization range can accurately adapt to the output voltage range of the conversion module. In addition, the application optimizes the working timing of the conversion module and the quantization module, completes the sampling of the quantization module at the same time as the current-voltage conversion of the conversion module, and improves the working speed and power efficiency of the readout unit circuit.

[0065] Although the preferred embodiments of the application have been described, those skilled in the art can make additional changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the application.

[0066] Obviously, those skilled in the art can make various modifications and changes to the application without departing from the spirit and scope of the application. Thus, if these modifications and changes of the application fall within the scope of the claims of the application and their equivalents, the application also intends to include these modifications and changes.

Claims

1. A resistive readout unit circuit for FLASH memory calculation, characterized in that, Includes a conversion module and a quantization module; The conversion module includes a positive weighted current conversion unit and a negative weighted current conversion unit with identical structures, as well as a positive weighted resistor module and a negative weighted resistor module with identical structures. The input terminals of the positive weighted current conversion unit and the negative weighted current conversion unit are connected to the positive weighted bit line and the negative weighted bit line, respectively, and their output terminals are connected to the input terminals of the positive weighted resistor module and the negative weighted resistor module, respectively. Each positive weighted current conversion unit and the negative weighted current conversion unit includes an operational amplifier, a driving transistor, a compensation resistor, a compensation capacitor, and a compensation transistor. The positive terminal of the operational amplifier is connected to a clamping voltage source, the negative terminal is connected to the source of the driving transistor, the corresponding bit line, and the drain of the compensation transistor, and the output terminal is connected to the gate of the driving transistor. The compensation resistor and the compensation capacitor are connected in series between the gate and the drain of the driving transistor. The gate of the compensation transistor is connected to a bias voltage source, and its source is grounded. The output terminals of the positive weighted resistor module and the negative weighted resistor module are used to output corresponding voltage signals. The quantization module includes two sampling switches, two CDACs, a comparator, and a SAR logic circuit. The inputs of the two sampling switches are connected to the outputs of the positive and negative weighting resistor modules, respectively. Their outputs are connected to the upper plates of the two CDACs and the positive and negative inputs of the comparator, respectively. The output of the comparator is connected to the input of the SAR logic circuit, which is used for output... N A digit code.

2. The resistive readout unit circuit for FLASH memory calculation as described in claim 1, characterized in that, The positive weighted current conversion unit includes a first operational amplifier ( ), first driving transistor ( ), first compensation resistor ( ), first compensation capacitor ( ) and the first compensation transistor ( ); First operational amplifier ( The positive terminal of ) and the clamping voltage source ( The negative terminal is connected to the first driving transistor ( ). The source, positive weight bit line, and first compensation transistor () The drain of the transistor is connected, and the output is connected to the first driving transistor. The gate connection of ) and the first compensation resistor ( ) and the first compensation capacitor ( ) connected in series with the first driving transistor ( Between the gate and drain of the first compensation transistor () The gate of ) and the bias voltage source ( (Connection, source grounded;) The negative weighted current conversion unit includes a second operational amplifier ( ), second driving transistor ( ), second compensation resistor ( ), second compensation capacitor ( ) and the second compensation transistor ( ); second operational amplifier ( The positive terminal of ) and the clamping voltage source ( The negative terminal is connected to the second driving transistor ( ). The source, negative weight bit line, and second compensation transistor () The drain of the transistor is connected, and the output is connected to the second driving transistor. The gate connection of the second compensation resistor () ) and second compensation capacitor ( ) connected in series with the second driving transistor ( Between the gate and drain of the second compensation transistor () The gate of ) and the bias voltage source ( (Connection, source grounded.) 3. The resistive readout unit circuit for FLASH memory calculation as described in claim 1, characterized in that, Both the positive weighted resistor module and the negative weighted resistor module include multiple resistors of different resistance values ​​connected in parallel and multiple switches. One end of each of the multiple switches is connected to the drain of the driving transistor and the output terminal for outputting voltage; the other end is connected to one end of each of the multiple resistors, and the other end of each of the multiple resistors is connected to a power supply voltage source.

4. The resistive readout unit circuit for FLASH memory calculation as described in claim 2, characterized in that, The positive weighted resistor module includes a first positive resistor (R). P1 ), second positive resistor (R) P2 ), third positive resistor (R) P3 ), fourth positive resistor (R) P4 ), the fifth positive resistor (R) P5 ), first positive switch (S) P1 ), second positive switch (S) P2 ), third positive switch (S) P3 ), fourth positive switch (S) P4 ) and the fifth positive switch (S P5 ), of which the first positive switch (S) P1 ), second positive switch (S) P2 ), third positive switch (S) P3 ), fourth positive switch (S) P4 ) and the fifth positive switch (S P5 One end of ) is connected to the first driving transistor ( The drain and positive output terminals are connected, and the other end is connected to the first positive resistor (R). P1 ), second positive resistor (R) P2 ), third positive resistor (R) P3 ), fourth positive resistor (R) P4 ) and the fifth positive resistor (R P5 One end of the resistor is connected to the power supply voltage source, and the other end of the multiple positive resistors is connected to the power supply voltage source. The positive output terminal is used to output a positive weighted voltage signal. The negative weighting resistor module includes a first negative resistor (R) N1 ), second negative resistor (R) N2 ), third negative resistor (R) N3 ), fourth negative resistor (R) N4 ), the fifth negative resistor (R) N5 ), first negative switch (S) N1 ), second negative switch (S) N2 ), third negative switch (S) N3 ), fourth negative switch (S) N4 ) and the fifth negative switch (S N5 ), of which the first negative switch (S) N1 ), second negative switch (S) N2 ), third negative switch (S) N3 ), fourth negative switch (S) N4 ) and the fifth negative switch (S N5 One end of ) is connected to the first driving transistor ( The drain and negative output terminals are connected, and the other terminals are connected to the first negative resistor (R). N1 ), second negative resistor (R) N2 ), third negative resistor (R) N3 ), fourth negative resistor (R) N4 ) and the fifth negative resistor (R N5 One end of the resistor is connected to the power supply voltage source, and the other end of the multiple negative resistors is connected to the power supply voltage source. The negative output terminal is used to output a negative weighted voltage signal.

5. The resistive readout unit circuit for FLASH memory calculation as described in claim 4, characterized in that, The first positive resistor (R) P1 ), second positive resistor (R) P2 ), third positive resistor (R) P3 ), fourth positive resistor (R) P4 ) and the fifth positive resistor (R P5 ) and the first negative resistor (R) N1 ), second negative resistor (R) N2 ), third negative resistor (R) N3 ), fourth negative resistor (R) N4 ) and the fifth negative resistor (R N5 The resistance values ​​of the resistors are configured in a ratio of 1:2:4:8:16, and the voltage difference output by the positive weight resistor module and the negative weight resistor module is as follows: ； In the formula, R is the voltage difference. S The values ​​of the selected positive and negative resistors are... For negative weighted storage current, The current is stored with positive weights.

6. The resistive readout unit circuit for FLASH memory calculation as described in claim 1, characterized in that, The two sampling switches include a first sampling switch and a second sampling switch, and the two CDACs include a first CDAC and a second CDAC; the first CDAC includes multiple first high-order capacitors, multiple first low-order capacitors, and a first bridging capacitor; the second CDAC includes multiple second high-order capacitors, multiple second low-order capacitors, and a second bridging capacitor; During the sampling phase, the lower plates of multiple first high-order capacitors and the lower plates of multiple first low-order capacitors in the first CDAC are all connected to the reference voltage source ( The upper plates of multiple first high-order capacitors and the upper plate of the first bridge capacitor are connected to the output terminal of the first sampling switch and one input terminal of the comparator; the lower plates of multiple second high-order capacitors and the lower plates of the second low-order capacitors in the second CDAC are connected to the reference voltage source ( The upper plate of the second high-level capacitor and the upper plate of the second bridge capacitor are both connected to the output terminal of the second sampling switch and the other input terminal of the comparator. During the quantization stage, the SAR logic circuit generates a first clock signal to control the comparator to compare the voltages at its two input terminals and transmits the comparison result back to the SAR logic circuit to generate the digital code of the current bit and a second clock signal to control the switching of the two CDACs. After the sampling and quantization phases, the quantization module generates a digital code representing the in-memory calculation result and an indication signal representing the completion of quantization.

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