Silicon direct bonded chip resistor strip structure and dry etching method

Abstract

The application relates to the technical field of silicon direct bonding chip process technology, in particular to a silicon direct bonding chip barrier structure and a dry etching method. The method sets the target thickness of a top silicon layer of a silicon direct bonding chip as a predetermined thickness range; a three-stage etching process is used to etch the top silicon layer, the three stages include a starting stage, a main etching stage and an endpoint control stage; in the main etching stage and the endpoint control stage, the intensity change of a silicon fluoride compound characteristic peak is monitored in real time through an optical emission spectrum monitoring system; when the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold value, the endpoint control stage is triggered; in the endpoint control stage, a pulse process of a fluorocarbon-containing gas is introduced, and the etching power is gradually reduced to realize the gradient reduction of the etching rate, so that the problems of large thickness deviation and insufficient sidewall angle in the etching of the silicon direct bonding chip are solved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of silicon direct bonding chip process, and particularly relates to a silicon direct bonding chip barrier structure and a dry etching method. BACKGROUND

[0002] In the field of semiconductor three-dimensional integration technology, the preparation of the barrier structure of a silicon direct bonding (SDB) chip depends on a high-precision etching process. The stability of the thickness of a top silicon layer directly affects the electrical performance and reliability index of a device. In particular, in high-end devices with strict requirements, thickness deviation may cause key electrical parameter drift and yield loss. Therefore, developing an etching method capable of achieving submicron precision control has become a core link to meet the needs of advanced semiconductor manufacturing.

[0003] A related technical solution monitors the etching process by means of optical emission spectrum endpoint detection. A typical method includes collecting a specific wavelength spectrum signal as a basis for process adjustment, and using a fluorine-based gas combination to achieve anisotropic etching. This type of solution attempts to make endpoint judgment through fixed-threshold spectrum analysis, and relies on constant process parameters to maintain etching directionality.

[0004] However, this type of solution still has significant limitations: systematic deviation in thickness control leads to unstable device threshold characteristics and yield loss; insufficient anisotropy of the etching profile causes enhanced parasitic effects; and the formation of bottom microdefects significantly degrades the voltage resistance characteristics of the device. The root cause lies in the lack of a real-time dynamic regulation mechanism, making it difficult to simultaneously address the three challenges of precision control, profile optimization and defect suppression, and failing to meet the manufacturing standards of high-reliability semiconductor devices. SUMMARY

[0005] The application provides a silicon direct bonding chip barrier structure and a dry etching method to solve the problems of large thickness deviation and insufficient sidewall angle in the etching of a silicon direct bonding chip.

[0006] The first aspect of the application provides a dry etching method for a silicon direct bonding chip barrier structure, which comprises the following steps:

[0007] Setting a target thickness of a top silicon layer of a silicon direct bonding chip as a predetermined thickness range;

[0008] Using a three-stage etching process to etch the top silicon layer, the three stages including a start-up stage, a main etching stage and an endpoint control stage;

[0009] In the main etching stage and the endpoint control stage, the intensity change of a silicon fluoride compound characteristic peak is monitored in real time by an optical emission spectrum monitoring system;

[0010] When the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold, the endpoint control stage is triggered.

[0011] In the endpoint control stage, a pulse process of fluorocarbon-containing gas is introduced, and the etching power is gradually reduced to realize the gradient decline of etching rate.

[0012] The dry etching method realizes the gradient decline of etching rate by adopting the three-stage etching process and the optical emission spectrum monitoring system to monitor the intensity change of silicon fluoride compound characteristic peak in real time, triggering the endpoint control stage when the absolute value of second derivative exceeds the set threshold, introducing the pulse process of fluorocarbon-containing gas in the endpoint control stage and gradually reducing the etching power, thereby reducing the thickness deviation of the top silicon layer and improving the side wall angle, so as to solve the problems of large thickness deviation and insufficient side wall angle in the etching of silicon direct bonding chips.

[0013] Optionally, the start-up stage uses a first mixed gas, and the first mixed gas includes carbon tetrafluoride, oxygen and argon;

[0014] The main etching stage uses a second mixed gas, and the second mixed gas includes carbon tetrafluoride, oxygen and argon;

[0015] The endpoint control stage introduces a third gas, and the third gas is octafluorocyclobutane.

[0016] The three stages adopt the mixed gas containing carbon tetrafluoride, oxygen and argon in the start-up stage and the main etching stage, and introduce octafluorocyclobutane as the third gas in the endpoint control stage. The combination of this gas combination and process stage helps to maintain the stability of the etching process and adjust the etching characteristics in the key stage, thereby positively affecting the improvement of etching uniformity and side wall morphology.

[0017] Optionally, the volume ratio of the first mixed gas is that carbon tetrafluoride accounts for 40% to 60%, oxygen accounts for 5% to 15%, and argon accounts for 30% to 50%;

[0018] The third gas is introduced in a pulse mode, and the pulse period is 2 seconds to 5 seconds, and the duty cycle is 30% to 40%.

[0019] By controlling the volume ratio of the first mixed gas in the range of carbon tetrafluoride accounting for 40% to 60%, oxygen accounting for 5% to 15%, and argon accounting for 30% to 50%, and introducing the third gas in a pulse period of 2 seconds to 5 seconds and a duty cycle of 30% to 40%, the optimized gas ratio combined with the pulse parameters helps to improve the process controllability, thereby positively affecting the improvement of etching uniformity and the control of etching profile.

[0020] Optionally, the etching rate of the endpoint control stage presents an exponential decay trend over time, and the etching rate of the endpoint control stage is:

[0021] ;

[0022] wherein, is the etching rate; is the etching time, A is the initial etching rate; B is the attenuation amplitude parameter of the etching rate in the time dimension; τ is the time constant.

[0023] The etching rate of the endpoint control stage follows an exponential decay model, realizing precise and gradual regulation of the etching rate. This controlled rate decay helps to reduce the possibility of over-etching and improve the control accuracy of etching depth and morphology.

[0024] Optionally, the characteristic peak monitored by the optical emission spectrum monitoring system is the emission peak of silicon fluoride at a wavelength of 440 nanometers; and the set threshold value is 0.5.

[0025] By setting the characteristic peak of the optical emission spectrum monitoring system as the emission peak of silicon fluoride at a wavelength of 440 nanometers and setting the determination threshold value as 0.5, this explicit monitoring condition improves the signal specificity and response sensitivity of the endpoint detection, thereby helping to reduce the risk of misjudgment of the etching endpoint and improving the accuracy of controlling the stopping time of the etching process.

[0026] Optionally, in the endpoint control stage, the etching power is reduced every predetermined time interval, and each time the power value is reduced by 50 watts until the etching rate is reduced below the target value.

[0027] By gradually reducing the etching power at predetermined time intervals in the endpoint control stage, each time the power value is reduced by a fixed 50 watts until the etching rate is reduced below the target value, this gradual power regulation method helps to realize smooth transition of the etching rate, thereby reducing process fluctuations and improving control of the consistency of the final etching depth.

[0028] Optionally, the method further comprises: pretreating the silicon direct bonding chip before etching, the pretreatment comprising the steps of coating photoresist, exposure, development and hardening to form a mask layer and a resist strip pattern.

[0029] By implementing the pretreatment steps including coating photoresist, exposure, development and hardening before etching to form a mask layer with a resist strip pattern, this step helps to improve the transfer accuracy of the subsequent etched pattern, thereby improving the boundary definition of the etched pattern and reducing pattern defects.

[0030] The second aspect of the present application provides a silicon direct bonding chip resist strip structure, which is suitable for the dry etching method of the silicon direct bonding chip resist strip structure of the first aspect, the resist strip structure comprising a top silicon layer;

[0031] The thickness of the top silicon layer is in a predetermined thickness range, and the thickness uniformity is less than a predetermined low deviation value;

[0032] The sidewall angle of the barrier structure is in a predetermined steep angle range, and the surface roughness is less than a predetermined nanoscale surface roughness threshold value;

[0033] The top silicon layer of the barrier structure is formed by a dry etching process, which includes three-stage etching control and optical emission spectroscopy end-point detection; the three stages include a start-up stage, a main etching stage, and an end-point control stage.

[0034] The silicon direct bonding chip barrier structure has a top silicon layer with high thickness uniformity, a steep sidewall angle, and low surface roughness. These structural characteristics are achieved through a dry etching process that includes three-stage etching control and optical emission spectroscopy end-point detection, which helps to improve the geometric precision of the device structure and reduce surface topography defects, thereby solving the problems of large thickness deviation and insufficient sidewall angle in silicon direct bonding chip etching.

[0035] Optionally, the predetermined thickness range is 3150 angstroms to 3250 angstroms;

[0036] The predetermined low deviation value is a thickness uniformity of less than ±1.3%.

[0037] The thickness of the top silicon layer of the barrier structure is controlled in the range of 3150 angstroms to 3250 angstroms, and the thickness uniformity is less than ±1.3%. This precise thickness control is achieved through a three-stage etching process, which helps to improve the size consistency of the device structure and reduce thickness fluctuations.

[0038] Optionally, the predetermined steep sidewall angle range is 89 degrees ±1 degree;

[0039] The predetermined nanoscale surface roughness threshold value is less than 2 nanometers;

[0040] The thickness deviation of the barrier structure in the thermal cycle test is less than ±30 angstroms, and the electromigration failure time of the barrier structure is greater than 2800 hours.

[0041] The barrier structure has a steep sidewall angle of 89 degrees ±1 degree and a surface roughness of less than 2 nanometers, a thickness deviation of less than ±30 angstroms in the thermal cycle test, and an electromigration failure time of greater than 2800 hours. These structural characteristics indicate that it can maintain good size stability under thermal stress and has high electromigration resistance, thereby improving the reliability of the device in long-term operation.

[0042] According to the technical scheme, the application provides a silicon direct bonding chip resistor structure and a dry etching method. The method sets a target thickness of a top silicon layer of a silicon direct bonding chip as a predetermined thickness range. A three-stage etching process is used to etch the top silicon layer. The three stages include a start-up stage, a main etching stage and an endpoint control stage. In the main etching stage and the endpoint control stage, an optical emission spectrum monitoring system is used to monitor the intensity change of a silicon fluoride compound characteristic peak in real time. When the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold value, the endpoint control stage is triggered. In the endpoint control stage, a pulse process of a fluorocarbon-containing gas is introduced, and the etching power is gradually reduced to realize the gradient reduction of the etching rate, so as to solve the problems of large thickness deviation and insufficient sidewall angle in the etching of the silicon direct bonding chip. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical scheme of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, other drawings can also be obtained by those skilled in the art without creative labor.

[0044] Figure 1 The flowchart of the dry etching method of the silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure.

[0045] Figure 2 The OES signal monitoring curve of the dry etching method of the silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure.

[0046] Figure 3 The cross-sectional structure of the chip after pretreatment in the dry etching method of the silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure.

[0047] Figure 4 The cross-sectional structure of the chip during the photoetch process in the dry etching method of the silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure.

[0048] Figure 5 The cross-sectional structure of the chip after etching in the dry etching method of the silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure.

[0049] Figure 6 The batch thickness distribution of the resistor structure of Example 1 in the dry etching method of the silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure. DETAILED DESCRIPTION

[0050] Embodiments will be described in detail below with reference to examples illustrated in the accompanying drawings. Descriptions of the embodiments described in the following examples do not represent all embodiments consistent with the present application. Rather, they are merely examples of systems and methods consistent with some aspects of the present application.

[0051] To solve the problem of large thickness deviation and insufficient sidewall angle in the etching of a silicon direct bonding chip, see Figure 1 Some embodiments of the present application provide a dry etching method for a silicon direct bonding chip barrier structure, which comprises:

[0052] S100: Set the target thickness of the top silicon layer of the silicon direct bonding chip to a predetermined thickness range.

[0053] It should be understood that, see Figures 3-5 The silicon direct bonding chip can include, from top to bottom, a top silicon layer Si (S2), a middle silicon dioxide layer SiO2 (S3), a middle silicon layer Si (S4), and a bottom silicon dioxide layer SiO2 (S3). The predetermined thickness range is 3150 angstroms to 3250 angstroms, and the target thickness of the top silicon layer of the silicon direct bonding chip is preferably 3200 angstroms.

[0054] S200: Etching the top silicon layer using a three-stage etching process, which includes a start-up stage, a main etching stage, and an endpoint control stage.

[0055] S210: In the main etching stage and the endpoint control stage, the intensity change of the characteristic peak of silicon fluoride is monitored in real time by an optical emission spectrum monitoring system.

[0056] S220: When the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold value, the endpoint control stage is triggered.

[0057] In some embodiments, the characteristic peak monitored by the optical emission spectrum monitoring system is the emission peak of silicon fluoride at a wavelength of 440 nanometers; and the set threshold value is 0.5.

[0058] It should be understood that when the absolute value of the second derivative of the intensity change of the characteristic peak is greater than 0.5, the endpoint control stage is triggered.

[0059] By setting the characteristic peak of the optical emission spectrum monitoring system to the emission peak of silicon fluoride at a wavelength of 440 nanometers and setting the determination threshold value to 0.5, this specific monitoring condition improves the signal specificity and response sensitivity of the endpoint detection, thereby helping to reduce the risk of misjudgment of the etching endpoint and improving the accuracy of controlling the timing of stopping the etching process.

[0060] It should be understood that the intensity change of the characteristic peak can specifically establish an OES (optical emission spectrum) signal second derivative model capture. The OES signal second derivative model is:

[0061] d 2 I / dt 2 = -0.02 I 0 e -t / τ ;

[0062] Wherein, d 2 I / dt 2 represents the second derivative of light intensity I with respect to time t, reflecting the change in signal curvature; -0.02 I 0 is a proportional coefficient, I 0 represents the initial light intensity reference value; e -t / τ is an exponential decay term, and τ is a time constant.

[0063] The model captures the second derivative extreme point of the light intensity of a specific wavelength in real time during the etching process, and accurately determines the etching endpoint. When d 2 I / dt 2 reaches the negative peak value, it indicates that the fluorocarbon passivation layer is completely penetrated, at which time the system automatically terminates etching, and the chip structure is as shown in S7.

[0064] The thickness control accuracy of 3200±50 angstroms is achieved.

[0065] When |d 2 I / dt 2 |>0.5, the thickness inversion formula is calculated in real time at the same time, and the thickness inversion formula is:

[0066] ;

[0067] Wherein, d(t) represents the remaining thickness of the silicon layer at time t, d 0 is the initial thickness; the integral term represents the cumulative etching depth from 0 to t.

[0068] In the OES real-time monitoring curve, the corresponding relationship between the intensity change inflection point of the 440nm peak S8 of the carbon tetrafluoride gas and the etching endpoint is as shown in Figure 2 .

[0069] In some embodiments, the etching rate of the endpoint control stage has an exponential decay trend over time, and the etching rate of the endpoint control stage is:

[0070] ;

[0071] Wherein, is the etching rate; is the etching time; A is the initial etching rate, which can be 900 angstroms / minute; B is the decay amplitude parameter of the etching rate in the time dimension, which can be 900 angstroms / minute; τ is a time constant, and τ can be 180s.

[0072] The etching rate of the endpoint control stage follows an exponential decay model, achieving precise and gradual regulation of the etching rate. This controlled rate decay helps to reduce the likelihood of over-etching and improves the control accuracy of etching depth and morphology.

[0073] S230: In the endpoint control stage, a pulse process of fluorocarbon-containing gas is introduced, and the etching power is gradually reduced to achieve a gradient decrease in etching rate.

[0074] The above dry etching method uses a three-stage etching process and an optical emission spectrum monitoring system to monitor the intensity change of the silicon fluoride compound characteristic peak in real time. When the absolute value of the second derivative exceeds the set threshold, the endpoint control stage is triggered. In this stage, a pulse process of fluorocarbon-containing gas is introduced, and the etching power is gradually reduced to achieve a gradient decrease in etching rate, thereby reducing the top silicon layer thickness deviation and improving the sidewall angle, to solve the problems of large thickness deviation and insufficient sidewall angle in silicon direct bonding chip etching.

[0075] In some embodiments, the start-up stage uses a first mixed gas comprising carbon tetrafluoride, oxygen, and argon.

[0076] Specifically, the steps of the start-up stage can be: first, place the silicon direct bonding chip in the reaction chamber of the etching equipment. Then, configure the mixed gas according to the ratio of carbon tetrafluoride:oxygen:argon = 5:1:4 (vol%), and introduce it into the reaction chamber, while setting the chamber pressure to 3 mTorr. Next, turn on the source power and set it to 450 W. Under this condition, the mixed gas reacts under the action of the electric field, quickly removing the oxide layer on the surface of the top silicon layer of the chip. During the entire start-up stage, the etching rate is monitored in real time to ensure that it is stable at 1200 angstroms per minute, until the surface oxide layer is completely removed, preparing for the subsequent main etching stage.

[0077] The main etching stage uses a second mixed gas comprising carbon tetrafluoride, oxygen, and argon.

[0078] Specifically, the steps of the main etching stage can be: first, configure the second mixed gas according to the ratio of carbon tetrafluoride:oxygen:argon = 3:2:5 (vol%), and continuously introduce it into the reaction chamber, while precisely controlling the chamber pressure at 5 mTorr. Next, adjust the source power to 600 W. Under this condition, the second mixed gas reacts under the action of the electric field, forming a stable fluorocarbon passivation layer that can effectively control the anisotropy of etching, achieving an anisotropy ratio of 1:50. During the etching process, when the etching depth reaches 3500 angstroms, immediately start the OES (optical emission spectrum) monitoring system to monitor the intensity change of the specific wavelength light generated during etching in real time, to accurately determine the etching endpoint and ensure the accuracy and consistency of the etching process.

[0079] It should be understood that, in the main etching stage, gas dynamics is applied for optimization, specifically, the fluorine atom radicals F * The relationship with the oxygen content is:

[0080] F * cm -3 ;

[0081] Wherein, F * represents the concentration of fluorine atom radicals, with the unit of particle number per cubic centimeter (cm -3 ); is a proportional constant; CF4 represents the concentration of carbon tetrafluoride; O2 represents the concentration of oxygen; the index 0.3 indicates the degree of influence of the oxygen content on the concentration of fluorine atom radicals. This means that when the ratio of carbon tetrafluoride to oxygen changes, the concentration of fluorine atom radicals will change, thereby affecting the etching rate and selectivity. At the same time, the energy distribution of argon ions under a 90V bias shows that 85% of the energy is concentrated in the range of 50-80eV, which exactly matches the sputtering threshold of the Si(100) surface.

[0082] The end-point control stage introduces a third gas, which is octafluorocyclobutane.

[0083] Specifically, the steps of the end-point control stage can be: first, when the etching depth approaches the preset end-point, accurately introduce the octafluorocyclobutane gas, and at the same time start the octafluorocyclobutane pulse supply system, set the pulse period to 3-5 seconds, and control the duty cycle in the range of 30-40%. Then, according to the real-time OES monitoring feedback, gradually adjust the source power, implement the power gradient reduction strategy, i.e. reduce the source power by 50 watts every 30 seconds, until the etching rate is stably reduced to 300 angstroms per minute. In this process, the optical emission spectrum signal is continuously monitored to ensure the accuracy of the etching end-point judgment and to avoid over-etching or under-etching, thereby ensuring the integrity and performance consistency of the chip resistor structure.

[0084] The three stages use a mixed gas containing carbon tetrafluoride, oxygen and argon in the start-up stage and the main etching stage, and introduce octafluorocyclobutane as the third gas in the end-point control stage. This combination of gas and process stages helps to maintain the stability of the etching process and adjust the etching characteristics at key stages, thereby positively affecting the improvement of etching uniformity and sidewall morphology.

[0085] In some embodiments, the volume ratio of the first mixed gas is: 40% to 60% of carbon tetrafluoride, 5% to 15% of oxygen, and 30% to 50% of argon;

[0086] The third gas is introduced in a pulse mode, the pulse period is 2-5 seconds, and the duty cycle is 30-40%.

[0087] By controlling the volume ratio of the first mixed gas in the range of 40-60% of carbon tetrafluoride, 5-15% of oxygen, and 30-50% of argon, and introducing the third gas in a pulse period of 2-5 seconds and a duty cycle of 30-40%, the optimized gas ratio combined with the pulse parameters helps to improve the process controllability, thereby positively affecting the improvement of etching uniformity and control of etching profile.

[0088] In some embodiments, in the endpoint control stage, the etching power is reduced once every predetermined time, and each time the power value is reduced by 50 watts until the etching rate is reduced to below the target value.

[0089] By gradually reducing the etching power at a predetermined time interval in the endpoint control stage, and reducing the power value by a fixed 50 watts each time until the etching rate is reduced to below the target value, this gradual power regulation helps to achieve a smooth transition of the etching rate, thereby reducing process fluctuations and improving control of the final etching depth consistency.

[0090] In some embodiments, the method further comprises: pretreating the silicon direct bonding chip before etching, the pretreatment comprising coating photoresist, exposure, development and hardening steps to form a mask layer and a resist strip pattern.

[0091] Specifically, the SDB wafer is first placed on a spin coater, and spin coating is performed at a set speed of 5000 r / min for 30 S, so that the photoresist AZ4620 uniformly covers the top silicon surface of the wafer to form a mask layer with a thickness of 1 μm (S1). After spin coating, the wafer is immediately transferred to a hardening device for hardening at a temperature of 150°C for 60 S to enhance the adhesion and stability of the mask layer. At this time, the chip structure is as shown in Figure 3

[0092] Then, the wafer after hardening is manually exposed using an exposure device SUSS MABA6 (numerical aperture NA=0.75), and the exposure time is 30 S to form an 8 μm resist strip device (S6) pattern on the wafer.

[0093] After exposure, the chip is developed. The chip is placed in a developing solution, and the developing time is controlled to be 160 S to accurately remove the photoresist in the exposed part. After development, the chip is spun dry using a spin dryer at a speed of 7000 r / min to remove the residual developing solution on the surface.

[0094] Finally, the chip is placed on a hot plate again, and is hardened at a temperature of 150°C for 60 S to make the pattern formed after development more stable. The pattern formed after development is as shown in​Figure 4 as shown.

[0095] By implementing a pre-treatment step including coating photoresist, exposure, development and hardening before etching, a mask layer with a barrier pattern is formed, which helps to improve the accuracy of subsequent etching pattern transfer, thus improving the boundary definition of etching pattern and reducing pattern defects.

[0096] After pre-treatment, the chip is placed in the etching equipment, and the parameters are edited as follows:

[0097] First, in the control interface of the etching equipment, find the gas flow setting option. Set the flow rate of carbon tetrafluoride gas to 50 sccm, the flow rate of oxygen gas to 8 sccm, the flow rate of argon gas to 40 sccm, and the flow rate of octafluorocyclobutane gas to 0 sccm in the start-up stage. Then, set the pulse frequency to 0 Hz, the power to 450 W, and the time to 1.25 minutes to complete the parameter setting of the start-up stage.

[0098] Subsequently, the main etching stage parameter setting is entered. Adjust the flow rate of carbon tetrafluoride gas to 45 sccm, the flow rate of oxygen gas to 10 sccm, the flow rate of argon gas to 35 sccm, and the flow rate of octafluorocyclobutane gas to 0 sccm. Keep the pulse frequency at 0 Hz, the power at 450 W, and the time at 2.22 minutes.

[0099] Next is the parameter setting of the transition stage. Set the flow rate of carbon tetrafluoride gas to 30 sccm, the flow rate of oxygen gas to 0, the flow rate of argon gas to 40 sccm, and the flow rate of octafluorocyclobutane gas to 25 sccm. Adjust the pulse frequency to 0.2 Hz, the power to 200 W, and the time to 0.83 minutes.

[0100] Finally, the parameter setting of the end point stage is performed. Set the flow rate of carbon tetrafluoride gas to 15 sccm, the flow rate of oxygen gas to 0, the flow rate of argon gas to 30 sccm, and the flow rate of octafluorocyclobutane gas to 30 sccm. Adjust the pulse frequency to 0.3 Hz, the power to 150 W, and the time to 0.33 minutes.

[0101] After completing all the parameter settings above, start the etching equipment and perform dry etching according to the set menu.

[0102] It should be noted that at the beginning of the transition stage, the introduction of octafluorocyclobutane gas is first suspended, while the octafluorocyclobutane gas pulse supply system is maintained running, but the pulse period is adjusted to 2-4 seconds, and the duty cycle is adjusted to the range of 25%-35% to adapt to the change of etching rate. Then, according to the change rate of the 440 nm peak intensity of carbon tetrafluoride gas monitored by OES, when the 440 nm peak intensity change rate is stable in the interval of 3% / s to 4% / s, gradually adjust the source power to 80% of the initial value, and keep the etching chamber pressure stable in the preset range. In this process, the 440 nm peak intensity of carbon tetrafluoride gas in the optical emission spectrum signal and its change rate are continuously monitored to ensure smooth transition and lay a foundation for accurate control of the etching endpoint.

[0103] In some embodiments, before pretreatment, an appropriate amount of silicon direct bonding chip can be taken out from the storage container and placed on the slide stage of the dedicated HMDS processing equipment to ensure that the silicon direct bonding chip is placed flat and without overlap. Then, start the HMDS processing equipment, and according to the equipment operation manual, accurately set the temperature to 150°C. This temperature has been verified by previous experiments to effectively promote the good chemical adsorption reaction of HMDS and the surface of the silicon direct bonding chip, providing a stable basis for subsequent processes. Then, set the processing time to 60 minutes. During the processing, the HMDS vapor in the equipment will uniformly cover the surface of the silicon direct bonding chip, forming a dense chemical adsorption layer. This adsorption layer can enhance the adhesion of the photoresist to the surface of the silicon direct bonding chip, reducing problems such as delamination and pattern distortion in subsequent photoresist coating, exposure, development, and other processes. After 60 minutes of processing time, turn off the HMDS processing equipment, and after the temperature in the equipment drops to a safe range, take out the HMDS-processed silicon direct bonding chip. At this time, the silicon direct bonding chip has better surface properties and can enter the subsequent pretreatment process.

[0104] It should be understood that HMDS processing refers to the process of using hexamethyldisilazane (HMDS) vapor to pretreat the surface of the silicon direct bonding chip. By accurately controlling the processing temperature and time, the HMDS vapor forms a uniform and dense chemical adsorption layer on the surface of the silicon direct bonding chip. This processing method not only improves the wettability of the surface of the silicon direct bonding chip, but also effectively removes water and organic contaminants adsorbed on the surface, creating ideal surface conditions for subsequent photolithography processes. Experimental data show that the surface contact angle of the silicon direct bonding chip after HMDS processing can be reduced from more than 70° to less than 30°, significantly improving the uniformity of photoresist adhesion.

[0105] Some embodiments of the present application also provide a silicon direct bonding chip barrier structure suitable for the dry etching method of the silicon direct bonding chip barrier structure described in the above embodiments. The barrier structure comprises a top silicon layer;

[0106] the thickness of the top silicon layer is in a predetermined thickness range, and the thickness uniformity is less than a predetermined low deviation value;

[0107] the sidewall angle of the barrier structure is in a predetermined steep angle range, and the surface roughness is less than a predetermined nanoscale surface roughness threshold;

[0108] the top silicon layer of the barrier structure is formed by a dry etching process, and the dry etching process includes three-stage etching control and optical emission spectroscopy end-point detection; the three stages include a start-up stage, a main etching stage, and an end-point control stage.

[0109] It should be understood that the optical emission spectroscopy end-point detection refers to a detection technology that determines in real time whether the etching reaction has reached the preset end point by monitoring the plasma emission spectrum characteristic signal generated during the dry etching process. This technology uses the characteristic spectrum intensity changes generated in different etching stages, combined with a pre-established end-point determination model, to accurately identify the moment when the top silicon layer etching is completed, so as to timely terminate the etching process, effectively avoid over-etching or under-etching phenomenon, and ensure that the sidewall angle and surface roughness of the barrier structure meet the design requirements.

[0110] The silicon direct bonding chip barrier structure has a top silicon layer with high thickness uniformity, a steep sidewall angle, and low surface roughness. These structural characteristics are achieved through a dry etching process that includes three-stage etching control and optical emission spectroscopy end-point detection, which helps to improve the geometric accuracy of the device structure and reduce surface topography defects, thereby solving the problems of large thickness deviation and insufficient sidewall angle in the etching of silicon direct bonding chips.

[0111] In some embodiments, the predetermined thickness range is 3150 angstroms to 3250 angstroms;

[0112] The predetermined low deviation value is that the thickness uniformity is less than ±1.3%.

[0113] The thickness of the top silicon layer of the barrier structure is controlled in the range of 3150 angstroms to 3250 angstroms, and the thickness uniformity is less than ±1.3%. This precise thickness control is achieved through a three-stage etching process, which helps to improve the size consistency of the device structure and reduce thickness fluctuations.

[0114] In some embodiments, the predetermined steep sidewall angle range is 89 degrees ±1 degree;

[0115] The predetermined nanoscale surface roughness threshold is less than 2 nanometers;

[0116] The thickness deviation of the barrier structure in the thermal cycle test is less than ±30 angstroms, and the electromigration failure time of the barrier structure is greater than 2800 hours.

[0117] The barrier structure has an abrupt sidewall angle of 89 degrees ± 1 degree and a surface roughness of less than 2 nanometers, a thickness deviation of less than ± 30 angstroms and an electromigration failure time of greater than 2800 hours in a thermal cycle test, which indicates that the structure has good size stability and high electromigration resistance in a thermal stress environment, thereby improving the reliability of long-term operation of a device.

[0118] The following comparative experiments were performed on an SDB wafer with a top silicon thickness of 1800 angstroms:

[0119] Example 1 used a three-stage etching process in combination with octafluorocyclobutane pulse gas, and achieved 1800 ± 50 angstroms thickness control by precisely adjusting the gas ratio of carbon tetrafluoride gas / oxygen / argon = 3:1:6 and 350 W source power, combined with double-wavelength OES (silicon tetrafluoride 440 nm + silicon 700 nm) end-point detection, a sidewall angle of 89.2° ± 0.3°, and an etching rate of 920 angstroms / minute. Thickness distribution statistics (see Table 1) show that the accuracy requirements are met. Figure 6

[0120] Comparative Example 1 cancelled the octafluorocyclobutane pulse under the same gas ratio, resulting in a thickness mean value of 3120 angstroms and a 3σ deviation of ± 180 angstroms, a sidewall angle of 86.3° ± 1.2°, and an etching rate of 850 angstroms / minute, indicating that the octafluorocyclobutane pulse has a significant optimization effect on thickness uniformity and sidewall perpendicularity.

[0121] Comparative Example 2 changed the OES detection wavelength to 511 nm, although the etching rate was increased to 900 angstroms / minute, the thickness mean value was shifted to 3350 angstroms and the 3σ deviation was ± 220 angstroms, and the sidewall angle was 87.5° ± 0.8°, which was also worse than that of Example 1, indicating that the combination of double wavelengths (440 nm + 700 nm) is more conducive to precise control of the etching end point.

[0122] According to the above technical solution, the embodiment of the present application provides a silicon direct bonding chip barrier structure and a dry etching method. The method first sets the target thickness of the top silicon layer of the silicon direct bonding chip to a predetermined thickness range; then a three-stage etching process is used to etch the top silicon layer, the three stages including a start-up stage, a main etching stage and an end-point control stage; in the main etching stage and the end-point control stage, the intensity change of the silicon fluoride compound characteristic peak is monitored in real time by an optical emission spectrum monitoring system; when the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold, the end-point control stage is triggered; in the end-point control stage, a pulse process of fluorine-containing carbon gas is introduced, and the etching power is gradually reduced to realize the gradient reduction of the etching rate, thereby solving the problems of large thickness deviation and insufficient sidewall angle in the etching of the silicon direct bonding chip. ​

[0123] The similar parts among the embodiments provided in the present application can be referred to each other, the specific embodiments provided above are only several examples under the general concept of the present application, and do not constitute the limitation of the protection scope of the present application. Any other embodiments extended according to the present application scheme without creative labor for the person skilled in the art shall fall within the protection scope of the present application.

Claims

1. A dry etching method for a silicon direct bonded chip resistor strip structure, characterized by, The method comprises: Setting a target thickness of a top silicon layer of a silicon direct bonding chip to a predetermined thickness range; Using a three-stage etching process to etch the top silicon layer, the three stages including a start-up stage, a main etching stage and an endpoint control stage; the start-up stage uses a first mixed gas, the first mixed gas including carbon tetrafluoride; the main etching stage uses a second mixed gas, the second mixed gas including carbon tetrafluoride; In the main etching stage and the endpoint control stage, the intensity change of a characteristic peak of a silicon fluoride compound is monitored in real time by an optical emission spectrum monitoring system; the characteristic peak monitored by the optical emission spectrum monitoring system is an emission peak of the silicon fluoride compound at a wavelength of 440 nanometers; When the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold value, the endpoint control stage is triggered; In the endpoint control stage, a pulse process of a third gas is introduced, the third gas being octafluorocyclobutane; and the etching power is gradually reduced to achieve a gradient decline of the etching rate.

2. The dry etching method of a silicon direct bonded chip resistor structure according to claim 1, wherein, The first mixed gas used in the start-up stage further includes oxygen and argon; the second mixed gas used in the main etching stage further includes oxygen and argon.

3. The dry etching method of a silicon direct bonded chip resistor structure according to claim 2, wherein, The volume ratio of the first mixed gas is: 40% to 60% of carbon tetrafluoride, 5% to 15% of oxygen and 30% to 50% of argon; The third gas is introduced in a pulse manner, the pulse period being 2 seconds to 5 seconds, and the duty cycle being 30% to 40%.

4. The dry etching method of a silicon direct bonded chip resistor structure according to claim 1, wherein, The etching rate of the endpoint control stage presents an exponential decay trend with time, and the etching rate of the endpoint control stage is: ； wherein, is the etching rate; is the etching time, A is the initial etching rate; B is the decay amplitude parameter of the etching rate in the time dimension; is the time constant.

5. The dry etching method of a silicon direct bonded chip resistor structure according to claim 1, wherein, The set threshold value is 0.

5.

6. The dry etching method of a silicon direct bonded chip resistor structure according to claim 1, wherein, In the endpoint control stage, the etching power is reduced once every predetermined time, and the power value of each reduction is 50 watts, until the etching rate is reduced to below the target value.

7. The dry etching method of a silicon direct bonded chip resistor structure according to claim 1, wherein, The method further comprises: Before etching, the silicon direct bonding chip is pretreated, the pretreatment including the steps of coating photoresist, exposure, development and hardening to form a mask layer and a resist strip pattern.

8. A silicon direct bonded chip resistor structure, characterized by, The resist strip structure includes a top silicon layer, which is etched by the dry etching method of the silicon direct bonding chip resist strip structure according to any one of claims 1-7. The thickness of the top silicon layer is in a predetermined thickness range, and the thickness uniformity is less than a predetermined low deviation value; The sidewall angle of the resist strip structure is in a predetermined steep angle range, and the surface roughness is less than a predetermined nanoscale surface roughness threshold value; The top silicon layer is formed by a dry etching process, and the dry etching process includes three-stage etching control and optical emission spectrum endpoint detection; the three stages include a start-up stage, a main etching stage and an endpoint control stage.

9. The silicon direct bonded chip resistor structure of claim 8, wherein, The predetermined thickness range is 3150 angstroms to 3250 angstroms; The predetermined low deviation value is that the thickness uniformity is less than ±1.3%.

10. The silicon direct bonding chip resist strip structure according to claim 8, characterized in that, The predetermined steep sidewall angle range is 89 degrees ±1 degree; The predetermined nanoscale surface roughness threshold value is less than 2 nanometers; The thickness deviation of the resist strip structure in the thermal cycle test is less than ±30 angstroms, and the electromigration failure time of the resist strip structure is greater than 2800 hours.

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