Substrate interconnect packaging methods and substrate interconnect packaging structures

Abstract

This invention provides a substrate interconnect packaging method and a substrate interconnect packaging structure, relating to the field of chip packaging technology. The method involves forming a photosensitive layer on a substrate circuit layer, then removing a portion of the photosensitive layer to form a first opening. A stacked circuit layer is then formed within the first opening, and the remaining photosensitive layer is removed to form a second opening. A first chip is mounted within the second opening to form a first encapsulation layer. A second chip is then mounted to form a second encapsulation layer. After a stripper, the chip is cut along a dicing kerf. The dicing kerf can be along the centerline and / or edge of the stacked circuit layer, or along the centerline and / or edge of the first encapsulation layer. Compared to existing technologies, this invention forms different types of packaging structures within the first and second openings, enabling the creation of different types of packaged products. Furthermore, during dicing, the dicing kerf can be cut at different positions, allowing for the production of different types of packaged products through different cutting methods, thus enhancing versatility.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a substrate interconnect packaging method and a substrate interconnect packaging structure. Background Technology

[0002] Wafer-level packaging (WLP) is widely used in the semiconductor industry. It typically involves cutting individual chips from a wafer, packaging them onto a carrier wafer, reconstructing the wafer using a dielectric encapsulation layer, and then rewiring the chip pins to change the chip's position. Its main advantages include high-density integration, small package size, superior product performance, and high signal transmission frequency.

[0003] As product designs iterate, existing wafer packaging typically only meets the requirements of a single type of packaging structure (e.g., single / multi-chip integrated packaging, stacked integrated packaging). In other words, current wafer-level packaging processes usually only produce a single type of packaged product, and different production lines are needed for different types of packaged products. This undoubtedly increases wafer processing costs and reduces production efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a substrate interconnect packaging method and a substrate interconnect packaging structure that can set different types of packaging products in the same reconstructed wafer, thereby enabling different types of packaging products to be produced through different dicing methods, thus improving the diversity of packaging products.

[0005] In a first aspect, the present invention provides a substrate interconnect packaging method, comprising:

[0006] Provide a first carrier coated with an adhesive layer;

[0007] A base circuit layer is formed on the first carrier;

[0008] A photosensitive layer is formed on the substrate circuit layer;

[0009] The photosensitive layer is partially removed to form a first opening, wherein the first opening exposes the substrate circuit layer;

[0010] A stacked circuit layer is formed on the base circuit layer within the first opening;

[0011] Remove the remaining photosensitive layer to form a second opening, wherein the second opening exposes the substrate circuit layer;

[0012] A first chip is mounted on the substrate circuit layer within the second opening;

[0013] A first encapsulation layer is formed on the substrate circuit layer, wherein the first encapsulation layer fills the second opening and at least covers the first chip;

[0014] While stripping the first carrier, a second chip is mounted on the base circuit layer or the stacked circuit layer, and a second encapsulation layer is formed covering the second chip;

[0015] Cut the substrate circuit layer along the cutting path;

[0016] The cutting path is along the centerline and / or edge of the stacked circuit layer, or the cutting path is along the centerline and / or edge of the first encapsulation layer.

[0017] In an optional embodiment, the step of simultaneously peeling off the first carrier, mounting the second chip on the stacked circuit layer, and forming a second encapsulation layer covering the second chip includes:

[0018] A second chip is mounted on the side of the stacked circuit layer away from the base circuit layer;

[0019] A second encapsulation layer is formed on the first encapsulation layer, and the second encapsulation layer covers the second chip;

[0020] The first carrier is stripped away to expose the base circuit layer;

[0021] A soldering circuit layer is formed on the side of the base circuit layer away from the second encapsulation layer.

[0022] In an optional embodiment, the step of simultaneously peeling off the first carrier, mounting the second chip on the substrate circuit layer, and forming a second encapsulation layer covering the second chip includes:

[0023] The first carrier is stripped off, and a second carrier is attached to the side of the stacked circuit layer away from the base circuit layer;

[0024] A second chip is mounted on the side of the substrate circuit layer away from the second encapsulation layer;

[0025] A second encapsulation layer is formed on the substrate circuit layer, and the second encapsulation layer covers the second chip;

[0026] Strip the second vehicle.

[0027] In an optional embodiment, the step of forming a first encapsulation layer on the substrate circuit layer includes:

[0028] A first encapsulation layer is formed on the base circuit layer and the stacked circuit layer within the first opening, wherein the first encapsulation layer simultaneously encapsulates the first chip and the stacked circuit layer.

[0029] In an optional embodiment, the step of forming a first encapsulation layer on the substrate circuit layer includes:

[0030] A first encapsulation layer is formed on the base circuit layer within the first opening, wherein the first encapsulation layer covers the first chip, and the side of the first encapsulation layer away from the base circuit layer is flush with the stacked circuit layer.

[0031] In an optional implementation, prior to the step of mounting the second chip on the side of the stacked circuit layer away from the substrate circuit layer, the method further includes:

[0032] An interconnect layer is formed on the first encapsulation layer and the stacked circuit layer, wherein the interconnect layer is electrically connected to the stacked circuit layer.

[0033] In an optional implementation, the step of mounting a second chip on the side of the stacked circuit layer away from the substrate circuit layer includes:

[0034] A second chip is mounted on the interconnect layer at the positions corresponding to the stacked circuit layer and the first chip.

[0035] In an optional embodiment, prior to the step of mounting the first chip on the substrate circuit layer within the second opening, the method further includes:

[0036] A first conductive pillar is formed on the substrate circuit layer within the second opening, wherein the end of the first conductive pillar away from the substrate circuit layer is flush with the stacked circuit layer, and the first conductive pillar is located on both sides of the first chip.

[0037] In an optional implementation, the step of mounting the first chip on the substrate circuit layer within the second opening includes:

[0038] Multiple first chips are mounted on the front side of the substrate circuit layer within the second opening, wherein at least some of the first chips are bridge chips. The front side of the bridge chip is provided with a connecting conductive post electrically connected to the substrate circuit layer, and the back side of the bridge chip is provided with a second conductive post for electrically connecting to the interconnect circuit layer. The first conductive post is provided on both sides of the first chips and both sides of the bridge chips.

[0039] Secondly, embodiments of the present invention provide a substrate interconnect packaging structure, fabricated using the aforementioned substrate interconnect packaging method, wherein the substrate interconnect packaging structure includes:

[0040] Base circuit layer;

[0041] The first chip has its front side attached to the substrate circuit layer and electrically connected to the substrate circuit layer.

[0042] The first encapsulation layer is disposed on the substrate circuit layer and covers the outside of the first chip;

[0043] A second encapsulation layer is disposed on top of the first encapsulation layer.

[0044] Thirdly, embodiments of the present invention provide a substrate interconnect packaging structure, fabricated using the aforementioned substrate interconnect packaging method, wherein the substrate interconnect packaging structure includes:

[0045] Base circuit layer;

[0046] A stacked circuit layer, wherein the stacked circuit layer is disposed on the base circuit layer and electrically connected to the base circuit layer;

[0047] The second chip is attached to the stacked circuit layer;

[0048] The second encapsulation layer is disposed on the stacked circuit layer and covers the second chip, and the sidewalls of the second encapsulation layer are aligned with the edge of the stacked circuit layer.

[0049] Fourthly, embodiments of the present invention provide a substrate interconnect packaging structure, fabricated using the aforementioned substrate interconnect packaging method, wherein the substrate interconnect packaging structure includes:

[0050] Base circuit layer;

[0051] A stacked circuit layer, wherein the stacked circuit layer is disposed in a local area of ​​the base circuit layer and is electrically connected to the base circuit layer accordingly;

[0052] The first chip is attached to the substrate circuit layer and located on one side of the stacked circuit layer;

[0053] A first encapsulation layer is disposed on the substrate circuit layer and at least covers the first chip;

[0054] The second chip is mounted on the stacked circuit layer;

[0055] The second encapsulation layer is disposed on the stacked circuit layer and the first encapsulation layer, and covers the second chip.

[0056] Fifthly, embodiments of the present invention provide a substrate interconnect packaging structure, fabricated using the aforementioned substrate interconnect packaging method, wherein the substrate interconnect packaging structure includes:

[0057] Base circuit layer;

[0058] A stacked circuit layer, wherein the stacked circuit layer is disposed in a local area of ​​the base circuit layer and is electrically connected to the base circuit layer;

[0059] The first chip is disposed on the substrate circuit layer;

[0060] The first conductive pillar is disposed on the substrate circuit layer and located on both sides of the first chip;

[0061] A first encapsulation layer is disposed on the substrate circuit layer and covers the first chip and the first conductive pillar, and the side of the first encapsulation layer away from the substrate circuit layer is flush with the stacked circuit layer.

[0062] An interconnection layer is disposed on the stacked circuit layer and the first encapsulation layer and is electrically connected to the stacked circuit layer, and the interconnection layer is electrically connected to the substrate circuit layer through the first conductive post;

[0063] The second chip is mounted on the interconnect layer and corresponds to the stacked circuit layer and the first chip, respectively.

[0064] The second encapsulation layer is disposed on the interconnect layer and covers the second chip.

[0065] Sixthly, embodiments of the present invention provide a substrate interconnect packaging structure, fabricated using the aforementioned substrate interconnect packaging method, wherein the substrate interconnect packaging structure includes:

[0066] Base circuit layer;

[0067] The first chip is disposed on the substrate circuit layer;

[0068] The first conductive pillar is disposed on the substrate circuit layer and located on both sides of the first chip;

[0069] A first encapsulation layer is disposed on the substrate circuit layer and covers the first chip and the first conductive pillar, and the side of the first encapsulation layer away from the substrate circuit layer is flush with the stacked circuit layer.

[0070] An interconnection layer is disposed on the stacked circuit layer and the first encapsulation layer and is electrically connected to the stacked circuit layer, and the interconnection layer is electrically connected to the substrate circuit layer through the first conductive post;

[0071] The second chip is mounted on the interconnect layer and corresponds to the first chip respectively;

[0072] The second encapsulation layer is disposed on the interconnect layer and covers the second chip.

[0073] In a seventh aspect, embodiments of the present invention provide a substrate interconnect packaging structure, fabricated using the aforementioned substrate interconnect packaging method, wherein the substrate interconnect packaging structure includes:

[0074] Base circuit layer;

[0075] A stacked circuit layer, wherein the stacked circuit layer is disposed in a local area of ​​the base circuit layer and is electrically connected to the base circuit layer;

[0076] The first chip is disposed on the substrate circuit layer;

[0077] The first conductive pillar is disposed on the substrate circuit layer and located on both sides of the first chip;

[0078] A first encapsulation layer is disposed on the substrate circuit layer and covers the first chip and the first conductive pillar, and the side of the first encapsulation layer away from the substrate circuit layer is flush with the stacked circuit layer.

[0079] An interconnection layer is disposed on the stacked circuit layer and the first encapsulation layer and is electrically connected to the stacked circuit layer, and the interconnection layer is electrically connected to the substrate circuit layer through the first conductive post;

[0080] The second chip is mounted on the side of the base circuit layer away from the interconnect circuit layer and corresponds to the stacked circuit layer and the first chip, respectively.

[0081] The second encapsulation layer is disposed on the side of the base circuit layer away from the interconnect circuit layer and covers the second chip.

[0082] Eighthly, embodiments of the present invention provide a substrate interconnect packaging structure, fabricated using the aforementioned substrate interconnect packaging method, the substrate interconnect packaging structure comprising:

[0083] Base circuit layer;

[0084] The first chip is disposed on the substrate circuit layer;

[0085] The first conductive pillar is disposed on the substrate circuit layer and located on both sides of the first chip;

[0086] A first encapsulation layer is disposed on the substrate circuit layer and covers the first chip and the first conductive pillar;

[0087] An interconnection layer is disposed on the first encapsulation layer and electrically connected to the substrate circuit layer through the first conductive post;

[0088] The second chip is mounted on the side of the substrate circuit layer away from the interconnect circuit layer and corresponds to the first chip.

[0089] The second encapsulation layer is disposed on the side of the base circuit layer away from the interconnect circuit layer and covers the second chip;

[0090] The first chip is a bridge chip. The front side of the bridge chip is provided with a connecting conductive post that is electrically connected to the base circuit layer. The back side of the bridge chip is provided with a second conductive post for electrically connecting to the interconnect circuit layer. The first conductive post is provided on both sides of the bridge chip.

[0091] Ninthly, embodiments of the present invention provide a substrate interconnect packaging structure, fabricated using the aforementioned substrate interconnect packaging method, the substrate interconnect packaging structure comprising:

[0092] Base circuit layer;

[0093] The first chip, the front side of the first chip is mounted on the substrate circuit layer;

[0094] The first conductive pillar is disposed on the substrate circuit layer and located on both sides of the first chip;

[0095] A first encapsulation layer is disposed on the substrate circuit layer and covers the first chip and the first conductive pillar;

[0096] An interconnection layer is disposed on the first encapsulation layer and electrically connected to the substrate circuit layer through the first conductive post;

[0097] The second chip is mounted on the side of the substrate circuit layer away from the interconnect circuit layer and corresponds to the first chip.

[0098] The second encapsulation layer is disposed on the side of the base circuit layer away from the interconnect circuit layer and covers the second chip.

[0099] The beneficial effects of the embodiments of the present invention include:

[0100] The substrate interconnect packaging method and structure provided in this invention first provide a carrier coated with an adhesive layer, on which a base circuit layer is formed. Then, a photosensitive layer is formed on the base circuit layer. After partially removing the photosensitive layer, a first opening is formed, exposing the base circuit layer. Next, a stacked circuit layer is formed on the base circuit layer within the first opening. The remaining photosensitive layer is then removed, forming a second opening that exposes the base circuit layer. A first chip is mounted on the base circuit layer within the second opening, and a first encapsulation layer is formed, filling the second opening and at least covering the first chip. Then, while peeling off the first carrier, a second chip is mounted on the base circuit layer or the stacked circuit layer, forming a second encapsulation layer covering the second chip. Finally, the base circuit layer is cut along a dicing track, wherein the dicing track is along the centerline and / or edge of the stacked circuit layer, or along the centerline and / or edge of the first encapsulation layer.

[0101] Compared to existing technologies, the embodiments of the present invention remove the photosensitive layer by partitioning, thereby forming different types of packaging structures within the first and second openings. This allows for the creation of different types of packaging products within the same reconstructed wafer. During dicing, the dicing path can be along the centerline and / or edge of the stacked circuit layer, or along the centerline and / or edge of the first encapsulation layer. Depending on the location of the dicing path, different types of packaging products can be cut, enabling the generation of different types of packaging products through different dicing methods, thus enhancing the diversity of packaging products. Attached Figure Description

[0102] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0103] Figure 1 This is a flowchart illustrating the steps of the substrate interconnect packaging method provided in the first embodiment of the present invention;

[0104] Figure 2 This is a schematic diagram of the structure corresponding to step S1 in the substrate interconnect packaging method provided in the first embodiment of the present invention;

[0105] Figure 3 This is a schematic diagram of the structure corresponding to step S2 in the substrate interconnect packaging method provided in the first embodiment of the present invention;

[0106] Figure 4 This is a schematic diagram of the structure corresponding to step S3 in the substrate interconnect packaging method provided in the first embodiment of the present invention;

[0107] Figure 5 This is a schematic diagram of the structure corresponding to step S4 in the substrate interconnect packaging method provided in the first embodiment of the present invention;

[0108] Figure 6 This is a schematic diagram of the structure corresponding to step S5 in the substrate interconnect packaging method provided in the first embodiment of the present invention;

[0109] Figure 7 This is a schematic diagram of the structure corresponding to step S6 in the substrate interconnect packaging method provided in the first embodiment of the present invention;

[0110] Figure 8 This is a schematic diagram of the structure corresponding to step S7 in the substrate interconnect packaging method provided in the first embodiment of the present invention;

[0111] Figure 9 This is a schematic diagram of the structure corresponding to step S8 in the substrate interconnect packaging method provided in the first embodiment of the present invention;

[0112] Figure 10 This is a schematic diagram of the structure corresponding to step S9 in the substrate interconnect packaging method provided in the first embodiment of the present invention;

[0113] Figure 11 This is a schematic diagram of the structure corresponding to step S10 in the substrate interconnect packaging method provided in the first embodiment of the present invention;

[0114] Figure 12 This is a schematic diagram of a first substrate interconnect packaging structure provided in the first embodiment of the present invention;

[0115] Figure 13 This is a schematic diagram of the second substrate interconnect packaging structure provided in the first embodiment of the present invention;

[0116] Figure 14 This is a schematic diagram of the third substrate interconnect packaging structure provided in the first embodiment of the present invention;

[0117] Figure 15 This is a schematic diagram of the structure corresponding to step S4 in the substrate interconnect packaging method provided in the second embodiment of the present invention;

[0118] Figure 16 This is a schematic diagram of the structure corresponding to step S5 in the substrate interconnect packaging method provided in the second embodiment of the present invention;

[0119] Figure 17 This is a schematic diagram of the structure corresponding to step S6 in the substrate interconnect packaging method provided in the second embodiment of the present invention;

[0120] Figure 18 This is a schematic diagram of the structure corresponding to step S7 in the substrate interconnect packaging method provided in the second embodiment of the present invention;

[0121] Figure 19 This is a schematic diagram of the structure corresponding to step S8 in the substrate interconnect packaging method provided in the second embodiment of the present invention;

[0122] Figure 20 This is a schematic diagram of the structure corresponding to step S9 in the substrate interconnect packaging method provided in the second embodiment of the present invention;

[0123] Figure 21 This is a schematic diagram of the structure corresponding to step S10 in the substrate interconnect packaging method provided in the second embodiment of the present invention;

[0124] Figure 22 This is a schematic diagram of the structure corresponding to step S11 in the substrate interconnect packaging method provided in the second embodiment of the present invention;

[0125] Figure 23 This is a schematic diagram of the structure corresponding to step S12 in the substrate interconnect packaging method provided in the second embodiment of the present invention;

[0126] Figure 24 This is a schematic diagram of the fourth substrate interconnect packaging structure provided in the second embodiment of the present invention;

[0127] Figure 25 This is a schematic diagram of the fifth substrate interconnect packaging structure provided in the second embodiment of the present invention;

[0128] Figure 26 This is a schematic diagram of the sixth substrate interconnect packaging structure provided in the second embodiment of the present invention;

[0129] Figure 27 This is a schematic diagram of the structure corresponding to step S8 in the substrate interconnect packaging method provided in the third embodiment of the present invention;

[0130] Figure 28 This is a schematic diagram of the structure corresponding to step S9 in the substrate interconnect packaging method provided in the third embodiment of the present invention;

[0131] Figure 29 This is a schematic diagram of the structure corresponding to step S10 in the substrate interconnect packaging method provided in the third embodiment of the present invention;

[0132] Figure 30 This is a schematic diagram of the structure corresponding to step S11 in the substrate interconnect packaging method provided in the third embodiment of the present invention;

[0133] Figure 31 This is a schematic diagram of the structure corresponding to step S12 in the substrate interconnect packaging method provided in the third embodiment of the present invention;

[0134] Figure 32 This is a schematic diagram of the seventh substrate interconnect packaging structure provided in the third embodiment of the present invention;

[0135] Figure 33 This is a schematic diagram of the eighth substrate interconnect packaging structure provided in the third embodiment of the present invention;

[0136] Figure 34 This is a schematic diagram of the ninth substrate interconnect packaging structure provided in the third embodiment of the present invention;

[0137] Figure 35 This is a schematic diagram of the tenth substrate interconnect packaging structure provided in the second embodiment of the present invention.

[0138] Icons: 100 - Substrate interconnect package structure; 110 - Base circuit layer; 111 - Solder circuit layer; 113 - Solder ball; 120 - Stacked circuit layer; 130 - First chip; 131 - First conductive pillar; 133 - Bridge chip; 135 - Connecting conductive pillar; 137 - Second conductive pillar; 139 - Active wiring layer; 140 - First encapsulation layer; 150 - Interconnect layer; 160 - Second chip; 170 - Second encapsulation layer; 200 - First carrier; 300 - Photosensitive layer; 310 - First opening; 320 - Second opening; 400 - Second carrier. Detailed Implementation

[0139] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0140] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0141] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0142] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0143] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0144] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0145] First Embodiment

[0146] See Figure 1 This invention provides a substrate interconnect packaging method that can set different types of packaging products in the same reconstructed wafer, thereby enabling different types of packaging products to be produced through different dicing methods, thus improving the diversity of packaging products.

[0147] The substrate interconnect packaging method provided in this embodiment of the invention includes the following steps:

[0148] S1: Provide a first carrier 200 coated with an adhesive layer.

[0149] See Figure 2 Specifically, a carrier is provided, and a UV adhesive layer is coated on the surface of the carrier to facilitate subsequent peeling. The carrier can be a substrate or a base plate. The liquid adhesive layer is applied to the surface of the carrier using a spin coater, and then the coating is set by a hot plate. The UV adhesive layer can be separated by irradiation with UV light. Materials include epoxy resin, polyimide, benzocyclobutene, and other polymer composite materials.

[0150] S2: A base circuit layer 110 is formed on the first carrier 200.

[0151] See Figure 3 Specifically, the substrate circuit layer 110 can be a combination of multiple wiring layers and multiple dielectric layers. In actual fabrication, a dielectric material can be coated first, then exposed and developed to form patterned layer openings, followed by electroplating to form wiring layers, and then spin coating to form dielectric material again. After multiple coatings and electroplating, the substrate circuit layer 110 is formed. It should be noted that the fabrication process of the substrate circuit layer 110 here can refer to the fabrication process of redistribution layers in the prior art.

[0152] S3: A photosensitive layer 300 is formed on the substrate circuit layer 110.

[0153] See Figure 4 Specifically, a photosensitive layer 300, which is a photosensitive material, can be coated on the surface of the substrate circuit layer 110 again using a spin coating process.

[0154] S4: Partially remove the photosensitive layer 300 to form the first opening 310.

[0155] See Figure 5 The first opening 310 exposes the substrate circuit layer 110. Specifically, the first opening 310 can be formed on the photosensitive layer 300 using an exposure and development process.

[0156] S5: A stacked circuit layer 120 is formed on the base circuit layer 110 within the first opening 310.

[0157] See Figure 6 Specifically, a first dielectric layer can be formed using a spin-coating process, followed by an exposure and development process to form patterned openings on the first dielectric layer, and then electroplating to form a first wiring layer. A second dielectric layer can then be formed by spin-coating again, followed by an exposure and development process to form patterned openings on the second dielectric layer, and then electroplating to form a second wiring layer. This process can form multiple dielectric layers and multiple wiring layers, thus forming a stacked circuit layer 120. The fabrication process of the stacked circuit layer 120 can also refer to the fabrication process of multi-layer redistribution layers in the prior art.

[0158] It should be noted that a dielectric material can be formed on the top layer of the stacked circuit layer 120. This can serve a protective function, protecting the stacked circuit layer 120 when the second opening 320 is formed, and also ensuring that the stacked circuit layer 120 is flush with the photosensitive layer 300.

[0159] S6: Remove the remaining photosensitive layer 300 to form the second opening 320.

[0160] See Figure 7 The second opening 320 exposes the substrate circuit layer 110. Specifically, after the fabrication of the stacked circuit layer 120 is completed, a photosensitive layer 300 can be applied using an exposure and development process, and then the photosensitive layer 300 can be decomposed using ultraviolet light. Finally, the remaining photosensitive layer 300 is cleaned using chemical agents, thereby removing the remaining photosensitive layer 300 and forming the second opening 320 between or on both sides of the stacked circuit layers 120. The second opening 320 exposes the substrate circuit layer 110.

[0161] After forming the second opening 320, a dielectric material can be coated on the substrate circuit layer 110 within the second opening 320. Then, a patterned opening is formed on the dielectric material on the top side by an exposure and development process. That is, the dielectric material on the top side of the stacked circuit layer 120 and the dielectric material within the second opening 320 are simultaneously opened. Then, a metal material is electroplated to complete the electrical connection metal layer between the stacked circuit layer 120 and the substrate circuit layer 110.

[0162] S7: The first chip 130 is mounted on the base circuit layer 110 within the second opening 320.

[0163] See Figure 8 Specifically, the first chip 130 can be flip-chip bonded to the substrate circuit layer 110 inside the second opening 320. Multiple first chips 130 can be disposed in each second opening 320, and each first chip 130 is electrically connected to the substrate circuit layer 110.

[0164] S8: A first encapsulation layer 140 is formed on the base circuit layer 110.

[0165] See Figure 9 The first encapsulation layer 140 fills the second opening 320 and at least covers the first chip 130. Specifically, the first encapsulation layer 140 is formed on the base circuit layer 110 and the stacked circuit layer 120 within the first opening 310, and the first encapsulation layer 140 covers both the first chip 130 and the stacked circuit layer 120. That is, the thickness of the first encapsulation layer 140 is greater than the depth of the second opening 320, so that the first encapsulation layer 140 can cover both the first chip 130 and the stacked circuit layer 120. After the first chip 130 is mounted, a molding process can be used to form the first encapsulation layer 140 within the second opening 320. The first encapsulation layer 140 covers the first chip 130 and the stacked circuit layer 120, resulting in a planar structure that facilitates subsequent wiring.

[0166] S9: While stripping the first carrier 200, the second chip 160 is mounted on the stacked circuit layer 120 and a second encapsulation layer 170 is formed covering the second chip 160.

[0167] See Figure 10 Specifically, in step S9, firstly, a second chip 160 is mounted on the side of the stacked circuit layer 120 away from the base circuit layer 110; then, a second encapsulation layer 170 is formed on the first encapsulation layer 140, and the second encapsulation layer 170 covers the second chip 160; then, the first carrier 200 is peeled off, exposing the base circuit layer 110; finally, a soldering circuit layer 111 is formed on the side of the base circuit layer 110 away from the second encapsulation layer 170.

[0168] It should be noted that the first encapsulation layer 140 can be a dielectric material, and the second encapsulation layer 170 can be a molding compound, such as epoxy-based resin or silicone-based resin with added high thermal conductivity materials and silicon micropowder. The high thermal conductivity materials include, but are not limited to, alumina thermal conductive powder or nano-alumina. By setting the second encapsulation layer 170, heat dissipation performance can be improved, while reducing product warpage. An opening can be made in the first encapsulation layer 140 and an electroplated metal layer can be formed to create pads that connect to the stacked circuit layer 120. Then, the second chip 160 is flip-chip bonded onto these pads, and the second encapsulation layer 170 is formed through a molding process. The second encapsulation layer 170 covers the entire first encapsulation layer 140, providing excellent protection for the second chip 160.

[0169] It is worth noting that the second chip 160 here is a flip chip and corresponds to the stacked circuit layer 120, and multiple second chips 160 are correspondingly mounted on the stacked circuit layer 120. When peeling off the first carrier 200, the first carrier 200 can be peeled off by irradiating with UV light, so that the substrate circuit layer 110 is exposed.

[0170] S10: Cut the base circuit layer 110 along the cutting path.

[0171] See Figure 11 Specifically, solder balls 113 may be formed on the soldering circuit layer 111 prior to cutting, and these solder balls 113 are electrically connected to the base circuit layer 110 through the soldering circuit layer 111. Cutting is then performed along a cut track, wherein the cut track is along the centerline and / or edge of the stacked circuit layer 120.

[0172] In actual cutting, cutting can be performed along the center line and both sides of the stacked circuit layer 120 to form the first substrate interconnect package structure 100 and the second substrate interconnect package structure 100; cutting can also be performed along the center line of the stacked circuit layer 120 to obtain the third substrate interconnect package structure 100.

[0173] It should be noted that the center line of the stacked circuit layer 120 mentioned in the embodiments of the present invention refers to the center line that can divide the stacked circuit layer 120 equally from the two side edges, and the stacked circuit layer 120 can be equally divided into two parts along the center line.

[0174] See Figure 12This invention also provides a first substrate interconnect packaging structure 100, fabricated using the substrate interconnect packaging method described above. The substrate interconnect packaging structure 100 includes a substrate circuit layer 110, a first chip 130, a first encapsulation layer 140, and a second encapsulation layer 170. The front side of the first chip 130 is bonded to and electrically connected to the substrate circuit layer 110, i.e., the first chip 130 is flip-chip disposed on the substrate circuit layer 110. The first encapsulation layer 140 is disposed on the substrate circuit layer 110 and covers the first chip 130. The second encapsulation layer 170 is disposed on the first encapsulation layer 140.

[0175] It should be noted that solder balls 113 are also provided on the side of the base circuit layer 110 away from the second encapsulation layer 170. The first encapsulation layer 140 can be a dielectric material, and the second encapsulation layer 170 can be a molding compound, such as epoxy-based resin or silicone-based resin with added high thermal conductivity materials and silicon micropowder. The high thermal conductivity materials include, but are not limited to, alumina thermal conductive powder or nano-alumina. By providing the second encapsulation layer 170, heat dissipation performance can be improved, while reducing product warpage.

[0176] See Figure 13 The present invention also provides a second substrate interconnect packaging structure 100, which is prepared by the substrate interconnect packaging method described above. The substrate interconnect packaging structure 100 includes a base circuit layer 110, a stacked circuit layer 120, a second chip 160, and a second encapsulation layer 170. The stacked circuit layer 120 is disposed on the base circuit layer 110 and electrically connected to the base circuit layer 110. The second chip 160 is attached to the stacked circuit layer 120. The first encapsulation layer 140 is disposed on the stacked circuit layer 120 and covers the second chip 160. The sidewalls of the second encapsulation layer 170 are aligned with the edges of the stacked circuit layer 120.

[0177] It should be noted that solder balls 113 are also provided on the side of the substrate circuit layer 110 away from the second encapsulation layer 170. The multi-layered stacked circuit layer 120 can increase circuit density and improve product performance. Furthermore, the first substrate interconnect package structure 100 and the second substrate interconnect package structure 100 can be obtained by cutting along the centerline and both sides of the stacked circuit layer 120 during dicing.

[0178] See Figure 14This invention also provides a third substrate interconnect packaging structure 100, which is fabricated using the substrate interconnect packaging method described above. The substrate interconnect packaging structure 100 includes a base circuit layer 110, a stacked circuit layer 120, a first chip 130, a first encapsulation layer 140, a second chip 160, and a second encapsulation layer 170. The stacked circuit layer 120 is disposed in a local area of ​​the base circuit layer 110 and is electrically connected to the base circuit layer 110. The first chip 130 is attached to the base circuit layer 110 and located on one side of the stacked circuit layer 120. The first encapsulation layer 140 is disposed on the base circuit layer 110 and at least covers the first chip 130. The second chip 160 is mounted on the stacked circuit layer 120. The second encapsulation layer 170 is disposed on the stacked circuit layer 120 and the first encapsulation layer 140 and covers the second chip 160.

[0179] It should be noted that solder balls 113 are also provided on the side of the base circuit layer 110 away from the second encapsulation layer 170. Furthermore, the first encapsulation layer 140 can cover the first chip 130 and cover the side of the stacked circuit cutoff layer away from the base circuit layer 110, and the second encapsulation layer 170 can cover the first encapsulation layer 140, which can reduce warpage and improve heat dissipation performance. Moreover, the third substrate interconnect package structure 100 can be obtained by cutting along the centerline of the stacked circuit layer 120 during dicing.

[0180] In summary, the substrate interconnect packaging method and structure provided in this embodiment of the invention first provides a carrier coated with an adhesive layer, on which a base circuit layer 110 is formed. Then, a photosensitive layer 300 is formed on the base circuit layer 110. After removing a portion of the photosensitive layer 300, a first opening 310 is formed, exposing the base circuit layer 110. Next, a stacked circuit layer 120 is formed on the base circuit layer 110 within the first opening 310. The remaining photosensitive layer 300 is then removed, forming a second opening 320, which exposes the base circuit layer 110. A first chip 130 is mounted on the base circuit layer 110 within the second opening 320, and a first encapsulation layer 140 is formed. The first encapsulation layer 140 fills the second opening 320 and at least covers the first chip 130. Then, while peeling off the first carrier 200, a second chip 160 is mounted on the stacked circuit layer 120, and a second encapsulation layer 170 is formed covering the second chip 160. Finally, the substrate circuit layer 110 is cut along the dicing path, wherein the dicing path is along the centerline and / or edge of the stacked circuit layer 120. Compared with the prior art, the embodiments of the present invention remove the photosensitive layer 300 by partitioning, thereby forming different types of packaging structures within the first opening 310 and the second opening 320. Different types of packaging products can be set in the same reconstructed wafer. During dicing, the dicing path can be along the centerline and / or edge of the stacked circuit layer 120. Depending on the position of the dicing path, different types of packaging products can be cut out, so that different types of packaging products can be produced by different dicing methods, thereby improving the diversity of packaging products.

[0181] Second Embodiment

[0182] This invention provides a substrate interconnect packaging method, whose basic steps, principles, and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0183] The substrate interconnect packaging method provided in this embodiment of the invention includes the following steps:

[0184] S1: Provide a first carrier 200 coated with an adhesive layer.

[0185] S2: A base circuit layer 110 is formed on the first carrier 200.

[0186] S3: A photosensitive layer 300 is formed on the substrate circuit layer 110.

[0187] Steps S1 to S3 are the same as in the first embodiment.

[0188] S4: Partially remove the photosensitive layer 300 to form the first opening 310.

[0189] See Figure 15The photosensitive layers 300 on both sides of the local structure shown in the figure can be removed to form the first opening 310.

[0190] S5: A stacked circuit layer 120 is formed on the base circuit layer 110 within the first opening 310.

[0191] See Figure 16 Specifically, a first dielectric layer can be formed using a spin-coating process, followed by an exposure and development process to form patterned openings on the first dielectric layer, and then electroplating to form a first wiring layer. A second dielectric layer is then formed by spin-coating again, followed by an exposure and development process to form patterned openings on the second dielectric layer, and then electroplating to form a second wiring layer. This process can form multiple dielectric layers and multiple wiring layers, thus forming a stacked circuit layer 120. The fabrication process of the stacked circuit layer 120 can also refer to the fabrication process of multi-layer redistribution layers in the prior art. Furthermore, the side of the stacked circuit layer 120 furthest from the substrate circuit layer 110 is flush with the photosensitive layer 300.

[0192] S6: Remove the remaining photosensitive layer 300 to form the second opening 320.

[0193] See Figure 17 Compared to the first embodiment, in this embodiment, the second opening 320 is located in the middle of the illustrated structure, that is, formed between two adjacent stacked circuit layers 120. Specifically, the second opening 320 exposes the substrate circuit layer 110. After the stacked circuit layers 120 are prepared, a photosensitive layer 300 can be applied using an exposure and development process, and the photosensitive layer 300 can be decomposed using ultraviolet light. Finally, the remaining photosensitive layer 300 is cleaned using chemical agents, thereby removing the remaining photosensitive layer 300 and forming the second opening 320 between the stacked circuit layers 120. The second opening 320 exposes the substrate circuit layer 110.

[0194] S7: A first conductive pillar 131 is formed on the substrate circuit layer 110 within the second opening 320.

[0195] See Figure 18 The first conductive post 131, located away from the substrate circuit layer 110, is flush with the stacked circuit layer at one end, and is situated on both sides of the first chip 130. Specifically, a dielectric material can be first coated onto the substrate circuit layer 110 within the second opening 320, followed by exposure and development to form the opening. Then, pads are formed by electroplating within the opening, and the first conductive posts 131 are further grown by electroplating on some of these pads. Multiple first conductive posts 131 are formed within the second opening 320.

[0196] It should be noted that the end of the first conductive post 131 away from the base circuit layer 110 is flush with the stacked circuit layer 120.

[0197] S8: The first chip 130 is mounted on the base circuit layer 110 within the second opening 320.

[0198] See Figure 19 Specifically, multiple first chips 130 can be flip-chip bonded to the substrate circuit layer 110 within the second opening 320, and the first chips 130 can also be bonded between two first conductive pillars 131, so that the first conductive pillars 131 are provided on both sides of the first chip 130.

[0199] S9: A first encapsulation layer 140 is formed on the base circuit layer 110.

[0200] See Figure 20 Specifically, a first encapsulation layer 140 is formed on the base circuit layer 110 within the first opening 310, wherein the first encapsulation layer 140 covers the first chip 130, and the side of the first encapsulation layer 140 away from the base circuit layer 110 is flush with the stacked circuit layer 120.

[0201] S10: An interconnect layer 150 is formed on the first encapsulation layer 140 and the stacked line layer 120.

[0202] See Figure 21 The interconnect layer 150 is electrically connected to the stacked redistribution layer 120. Specifically, a dielectric material can be coated on the surface of the first encapsulation layer 140 and the stacked redistribution layer 120, then the opening is exposed and developed, followed by electroplating to form a metal layer. Then, the dielectric layer and the metal layer are prepared to complete the preparation of the interconnect layer 150. The preparation of the interconnect layer 150 can refer to the preparation process of multilayer redistribution layers in the prior art.

[0203] S11: While stripping the first carrier 200, the second chip 160 is mounted on the stacked circuit layer 120 and a second encapsulation layer 170 is formed covering the second chip 160.

[0204] See Figure 22 Specifically, firstly, a second chip 160 is mounted on the side of the stacked circuit layer 120 away from the base circuit layer 110; then, a second encapsulation layer 170 is formed on the first encapsulation layer 140, and the second encapsulation layer 170 covers the second chip 160; then, the first carrier 200 is peeled off, exposing the base circuit layer 110; finally, a soldering circuit layer 111 is formed on the side of the base circuit layer 110 away from the second encapsulation layer 170.

[0205] Specifically, when mounting the second chip 160, the second chip 160 can be mounted at positions on the interconnect layer 150 corresponding to the stacked circuit layer 120 and the first chip 130. That is, some of the second chips 160 correspond to the stacked circuit layer 120, and other parts of the second chips 160 are distributed corresponding to the first chip 130.

[0206] S12: Cut the base circuit layer 110 along the cutting path.

[0207] See Figure 23 Specifically, solder balls 113 may be formed on the soldering circuit layer 111 prior to cutting. These solder balls 113 are electrically connected to the base circuit layer 110 via the soldering circuit layer 111. Cutting is then performed along a cutting path, wherein the cutting path is along the centerline and / or edge of the first encapsulation layer 140.

[0208] In actual cutting, the first encapsulation layer 140 can be cut along the centerline alone to form the fourth substrate interconnect package structure 100; or the first encapsulation layer 140 can be cut along the centerline and both sides simultaneously to obtain the fifth and sixth substrate interconnect package structures 100.

[0209] It should be noted that the center line of the first packaging layer 140 mentioned in the embodiments of the present invention refers to the center line that can divide the first packaging layer 140 into two equal parts along the center line that is equidistant from both sides of the edge.

[0210] See Figure 24This invention also provides a fourth substrate interconnect packaging structure 100, which is fabricated using the substrate interconnect packaging method described above. The substrate interconnect packaging structure 100 includes a base circuit layer 110, a stacked circuit layer 120, a first chip 130, a first conductive pillar 131, a first encapsulation layer 140, an interconnect circuit layer 150, a second chip 160, and a second encapsulation layer 170. The stacked circuit layer 120 is disposed in a local area of ​​the base circuit layer 110 and is electrically connected to the base circuit layer 110. The first chip 130 is disposed on the base circuit layer 110 and located on one side of the stacked circuit layer 120. The first conductive pillar 131 is disposed on the base circuit layer 110 and located on the first chip 130. On both sides of 0; a first encapsulation layer 140 is disposed on the base circuit layer 110 and covers the first chip 130 and the first conductive post 131, and the side of the first encapsulation layer 140 away from the base circuit layer 110 is flush with the stacked circuit layer 120; an interconnect circuit layer 150 is disposed on the stacked circuit layer 120 and the first encapsulation layer 140 and is electrically connected to the stacked circuit layer 120, and the interconnect circuit layer 150 is electrically connected to the base circuit layer 110 through the first conductive post 131; a second chip 160 is mounted on the interconnect circuit layer 150 and corresponds to the stacked circuit layer 120 and the first chip 130 respectively; a second encapsulation layer 170 is disposed on the interconnect circuit layer 150 and covers the second chip 160.

[0211] It should be noted that the first chip 130 is mounted on the substrate circuit layer 110, and the second chip 160 is mounted on the interconnect circuit layer 150. Both the first chip 130 and the second chip 160 are flip chips. This fourth substrate interconnect package structure 100 can be obtained by cutting along the centerline of the first encapsulation layer 140 during dicing.

[0212] See Figure 25This invention also provides a fifth substrate interconnect packaging structure 100, fabricated using the substrate interconnect packaging method described above. The substrate interconnect packaging structure 100 includes a substrate circuit layer 110, a first chip 130, a first conductive pillar 131, a first encapsulation layer 140, an interconnect circuit layer 150, a second chip 160, and a second encapsulation dielectric layer. The first chip 130 is disposed on the substrate circuit layer 110. The first conductive pillar 131 is disposed on the substrate circuit layer 110 and located on both sides of the first chip 130. The first encapsulation layer 140 is disposed on the substrate circuit layer 110 and covers the first chip 130 and the first conductive pillar 131, with the side of the first encapsulation layer 140 away from the substrate circuit layer 110 flush with the stacked circuit layer 120. The interconnect circuit layer 150 is disposed on the stacked circuit layer 120 and the first encapsulation layer 140, and is electrically connected to the stacked circuit layer 120. The interconnect circuit layer is electrically connected to the substrate circuit layer 110 through the first conductive pillar 131. The second chip 160 is mounted on the interconnect layer 150 and corresponds to the first chip 130. The second encapsulation layer 170 is disposed on the interconnect layer 150 and covers the second chip 160.

[0213] It should be noted that the first chip 130 is flip-chip mounted on the substrate circuit layer 110, and the second chip 160 is flip-chip mounted on the interconnect circuit layer 150.

[0214] See Figure 26 This invention also provides a sixth substrate interconnect packaging structure 100, fabricated using the substrate interconnect packaging method described above. The substrate interconnect packaging structure 100 includes a base circuit layer 110, a stacked circuit layer 120, an interconnect circuit layer 150, a second chip 160, and a second encapsulation layer 170. The stacked circuit layer 120 is disposed on and electrically connected to the base circuit layer 110. The interconnect circuit layer 150 is disposed on and electrically connected to the stacked circuit layer 120. The second chip 160 is disposed on and electrically connected to the interconnect circuit layer 150. The second encapsulation layer 170 is disposed on the interconnect circuit layer 150 and encapsulates the second chip 160.

[0215] It should be noted that the fifth and sixth interconnect packaging structures here can be obtained by cutting along the center line and both sides of the first encapsulation layer 140 simultaneously during the cutting process.

[0216] Third Embodiment

[0217] This invention provides a substrate interconnect packaging method, whose basic steps, principles, and resulting technical effects are the same as those of the second embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the second embodiment.

[0218] The substrate interconnect packaging method provided in this embodiment of the invention includes the following steps:

[0219] S1: Provide a first carrier 200 coated with an adhesive layer.

[0220] S2: A base circuit layer 110 is formed on the first carrier 200.

[0221] S3: A photosensitive layer 300 is formed on the substrate circuit layer 110.

[0222] S4: Partially remove the photosensitive layer 300 to form the first opening 310.

[0223] Compared with the first embodiment, the first opening 310 in this embodiment is located on both sides of the illustrated structure, and the opening width is slightly smaller than that of the first opening 310 in the first embodiment.

[0224] S5: A stacked circuit layer 120 is formed on the base circuit layer 110 within the first opening 310.

[0225] S6: Remove the remaining photosensitive layer 300 to form the second opening 320.

[0226] S7: A first conductive pillar 131 is formed on the substrate circuit layer 110 within the second opening 320.

[0227] Steps S1-S7 are the same as in the second embodiment.

[0228] S8: The first chip 130 is mounted on the base circuit layer 110 within the second opening 320.

[0229] See Figure 27 Specifically, multiple first chips 130 are mounted on the substrate circuit layer 110 within the second opening 320, with at least a portion of the first chips 130 serving as bridge chips 133. The bridge chips 133 are spaced apart from the two memory chips, and two first conductive posts 131 are disposed on both sides of the bridge chips 133. The front side of the bridge chips 133 has connecting conductive posts 135 electrically connected to the substrate circuit layer 110 (see...). Figure 33 The back of the bridge chip 133 has a second conductive post 137 for electrical connection with the interconnect layer 150 (see...). Figure 33 Furthermore, the first chip 130 has first conductive posts 131 on both sides.

[0230] The bridge chip 133 can be an inductor, voltage regulator, resistor, capacitor, transistor, or diode, etc. The bridge chip 133 can be an active chip or a passive chip. An active wiring layer 139 is provided in the middle of the bridge chip 133 (see...). Figure 33The front and back sides have interconnect wiring layers that connect to the active wiring layers. The front interconnect wiring layer is connected to the pads on the substrate circuit layer 110 via conductive posts 135 using hot-press copper-copper soldering. The back interconnect wiring layer is electrically connected to the interconnect circuit layer 150 via second conductive posts 137. Alternatively, the active wiring layer 139 can be omitted in the middle of the bridging chip 133, and electrical connection and signal transmission can be achieved directly through wiring layers and copper posts.

[0231] Of course, the bridge chip 133 here can also be an integrated circuit (IC) package, which includes a package substrate and one or more IC chips or other electronic modules mounted on the package substrate to provide electrical connections to the IC chips. For example, the IC chip in the IC package can be a system-on-a-chip (SoC). The IC chip is electrically coupled to other IC chips and / or other components in the IC package via metal lines electrically coupled to the package substrate wiring layer 110. The IC chip can also be electrically coupled to other circuits outside the IC package via electrical connections of external metal interconnects. For example, one or more embedded capacitors can provide decoupling capacitance for the power distribution network (PDN) in the IC package to reduce current resistance (IR) drop. Furthermore, the active wiring layer of the embedded capacitor is disposed between the IC chip and the substrate wiring layer 110 to minimize the distance between the embedded capacitor and the IC chip. This can reduce parasitic inductance in the power distribution lines between the embedded capacitor and the IC chip, thereby reducing IR drop in the PDN and also helping to reduce PDN noise.

[0232] S9: A first encapsulation layer 140 is formed on the base circuit layer 110.

[0233] See Figure 28 Specifically, a first encapsulation layer 140 is formed on the base circuit layer 110 within the first opening 310, wherein the first encapsulation layer 140 covers the first chip 130, and the side of the first encapsulation layer 140 away from the base circuit layer 110 is flush with the stacked circuit layer 120.

[0234] S10: An interconnect layer 150 is formed on the first encapsulation layer 140 and the stacked line layer 120.

[0235] See Figure 29 The interconnect layer 150 is electrically connected to the stacked redistribution layer 120. Specifically, a dielectric material can be coated on the surface of the first encapsulation layer 140 and the stacked redistribution layer 120, then the opening is exposed and developed, followed by electroplating to form a metal layer. Then, the dielectric layer and the metal layer are prepared to complete the preparation of the interconnect layer 150. The preparation of the interconnect layer 150 can refer to the preparation process of multilayer redistribution layers in the prior art.

[0236] S11: While stripping the first carrier 200, the second chip 160 is mounted on the base circuit layer 110 and a second encapsulation layer 170 is formed covering the second chip 160.

[0237] See Figure 30 Specifically, the first carrier 200 can be peeled off first, and the second carrier 400 can be mounted on the side of the stacked circuit layer away from the base circuit layer. Then, the second chip 160 can be mounted on the side of the base circuit layer 110 away from the second encapsulation layer 170. The second encapsulation layer 170 is then formed on the base circuit layer 110, and the second encapsulation layer 170 covers the second chip 160. Finally, the second carrier 400 can be peeled off.

[0238] It should be noted that after the first carrier 200 is peeled off, the second carrier 400 needs to be mounted on the stacked circuit layer. The surface of the second carrier 400 can also be coated with a UV adhesive layer to facilitate subsequent peeling. In some other preferred embodiments, the second carrier 400 may not be mounted, and subsequent operations can be completed directly on the reconstructed wafer structure.

[0239] It is worth noting that before mounting the second chip 160, a dielectric material needs to be coated on the substrate circuit layer, and after exposure and development to form an opening, a metal material is electroplated to form a pad structure. This pad structure can be connected to the substrate circuit layer 110. Then, the second chip 160 is mounted on the pad structure. The second chip 160 is a flip chip and can be electrically connected to the substrate circuit layer 110.

[0240] S12: Cut the base circuit layer 110 along the cutting path.

[0241] See Figure 31 Specifically, solder balls 113 may be formed on interconnect layer 150 prior to dicing. Dicing is then performed along a dicing kerf, which runs along the centerline and / or edge of the first encapsulation layer 140.

[0242] See Figure 32This invention also provides a seventh substrate interconnect packaging structure 100, which is fabricated using the aforementioned substrate interconnect packaging method. The substrate interconnect packaging structure 100 includes a base circuit layer 110, a stacked circuit layer 120, a first chip 130, a first conductive pillar 131, a first encapsulation layer 140, an interconnect circuit layer 150, a second chip 160, and a second encapsulation layer 170. The stacked circuit layer 120 is disposed in a local area of ​​the base circuit layer 110 and is electrically connected to the base circuit layer 110. The first chip 130 is disposed on the base circuit layer 110. The first conductive pillar 131 is disposed on the base circuit layer 110 and located on both sides of the first chip 130. The first encapsulation layer 140 is disposed on the base circuit layer 110 and covers the first chip 130 and the first conductive pillar 131, with the side of the first encapsulation layer 140 away from the base circuit layer 110 flush with the stacked circuit layer 120. An interconnect layer 150 is disposed on the stacked circuit layer 120 and the first encapsulation layer 140, and is electrically connected to the stacked circuit layer 120. The interconnect layer 150 is also electrically connected to the base circuit layer 110 via a first conductive post 131. A second chip 160 is mounted on the side of the base circuit layer 110 away from the interconnect layer 150, and corresponds to both the stacked circuit layer 120 and the first chip 130. A second encapsulation layer 170 is disposed on the side of the base circuit layer 110 away from the interconnect layer 150 and encapsulates the second chip 160. Solder balls 113 are provided on the side of the interconnect layer 150 away from the base circuit layer 110.

[0243] It should be noted that the seventh type of substrate interconnect packaging structure 100 can be obtained by cutting along the centerline of the first encapsulation dielectric layer during the cutting process.

[0244] See Figure 33This invention also provides an eighth substrate interconnect packaging structure 100, which is fabricated using the aforementioned substrate interconnect packaging method. The substrate interconnect packaging structure 100 includes a substrate circuit layer 110, a first chip 130, a first conductive pillar 131, a first encapsulation layer 140, an interconnect circuit layer 150, a second chip 160, and a second encapsulation layer 170. The first chip 130 is disposed on the substrate circuit layer 110; the first conductive pillar 131 is disposed on the substrate circuit layer 110 and located on both sides of the first chip 130; the first encapsulation layer 140 is disposed on the substrate circuit layer 110 and covers the first chip 130 and the first conductive pillar 131; the interconnect circuit layer 150 is disposed on the first encapsulation layer. On chip 140, a second chip 160 is mounted on the side of the base circuit layer 110 away from the interconnect circuit layer 150 and corresponds to the first chip 130. A second encapsulation layer 170 is disposed on the side of the base circuit layer 110 away from the interconnect circuit layer 150 and covers the second chip 160. The first chip 130 is a bridge chip 133. The front side of the bridge chip 133 is provided with a connecting conductive post 135 that is electrically connected to the base circuit layer 110. The back side of the bridge chip 133 is provided with a second conductive post 137 for electrically connecting to the interconnect circuit layer 150. The bridge chip 133 is provided with first conductive posts 131 on both sides.

[0245] Furthermore, an active wiring layer 139 is provided in the middle of the bridging chip 133, and wiring layers are provided on both the front and back sides of the bridging chip 133. A connecting conductive post 135 is provided on the front side of the bridging chip 133, which is connected to the active wiring layer 139. A second conductive post 137 is also provided on the back side of the bridging chip 133. The second conductive post 137 can be a TSV conductive post and is connected to the active wiring layer 139. In actual chip mounting, the front side of the bridging chip 133 can be connected to the substrate circuit layer 110 by hot-pressing copper-copper soldering, while the other first chips 130 can be connected by conventional flip-chip reflow soldering.

[0246] See Figure 34This invention also provides a ninth substrate interconnect packaging structure 100, which is fabricated using the aforementioned substrate interconnect packaging method. The substrate interconnect packaging structure 100 includes a substrate circuit layer 110, a first chip 130, a first conductive pillar 131, a first encapsulation layer 140, an interconnect circuit layer 150, a second chip 160, and a second encapsulation layer 170. The first chip 130 is front-mounted on the substrate circuit layer 110, i.e., flip-chip mounted on the substrate circuit layer 110. The first conductive pillar 131 is disposed on the substrate circuit layer 110 and located at the... A first encapsulation layer 140 is disposed on the substrate circuit layer 110 and covers the first chip 130 and the first conductive post 131. An interconnect circuit layer 150 is disposed on the first encapsulation layer 140 and electrically connected to the substrate circuit layer 110 through the first conductive post 131. A second chip 160 is mounted on the side of the substrate circuit layer 110 away from the interconnect circuit layer 150 and corresponds to the first chip 130. A second encapsulation layer 170 is disposed on the side of the substrate circuit layer 110 away from the interconnect circuit layer 150 and covers the second chip 160. Multiple first chips 130 may be present, and all multiple first chips 130 are flip-chip bonded to the substrate circuit layer 110.

[0247] See Figure 35 The present invention also provides a tenth substrate interconnect packaging structure 100, which is prepared by the aforementioned substrate interconnect packaging method. The substrate interconnect packaging structure 100 includes a base circuit layer 110, a stacked circuit layer 120, an interconnect circuit layer 150, a second chip 160, and a second encapsulation layer 170. The stacked circuit layer 120 is disposed on the base circuit layer 110, the interconnect circuit layer 150 is disposed on the stacked circuit layer 120, the second chip 160 is mounted on the side of the base circuit layer 110 away from the interconnect circuit layer 150, and the second encapsulation layer 170 is disposed on the side of the base circuit layer 110 away from the interconnect circuit layer 150 and covers the second chip 160.

[0248] It should be noted that the eighth, ninth and tenth substrate interconnect packaging structures 100 here can be obtained by cutting along the center line and both sides of the first encapsulation dielectric layer simultaneously during the cutting process.

[0249] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for substrate interconnection packaging, characterized by, The method comprises: providing a first carrier coated with an adhesive layer; forming a base circuit layer on the first carrier; forming a photosensitive layer on the base circuit layer; partially removing the photosensitive layer to form a first opening, wherein the first opening exposes the base circuit layer; forming a stacked circuit layer on the base circuit layer in the first opening; removing the remaining photosensitive layer to form a second opening, wherein the second opening exposes the base circuit layer; mounting a first chip on the base circuit layer in the second opening; forming a first encapsulation layer on the base circuit layer in the first opening, wherein the first encapsulation layer fills the second opening and at least covers the first chip; peeling off the first carrier while mounting a second chip on the base circuit layer or the stacked circuit layer and forming a second encapsulation layer covering the second chip; cutting the base circuit layer along a cutting path; wherein the first encapsulation layer covers the first chip and the stacked circuit layer, and the cutting path extends along the center line and / or edge of the stacked circuit layer; or, the side of the first encapsulation layer away from the base circuit layer is flush with the stacked circuit layer, and the cutting path extends along the center line and / or edge of the first encapsulation layer.

2. The method of claim 1, wherein, The step of peeling off the first carrier while mounting a second chip on the stacked circuit layer and forming a second encapsulation layer covering the second chip comprises: mounting a second chip on the side of the stacked circuit layer away from the base circuit layer; forming a second encapsulation layer on the first encapsulation layer, which covers the second chip; peeling off the first carrier and exposing the base circuit layer; forming a solder circuit layer on the side of the base circuit layer away from the second encapsulation layer.

3. The method of claim 1, wherein The step of peeling off the first carrier while mounting a second chip on the base circuit layer and forming a second encapsulation layer covering the second chip comprises: peeling off the first carrier and mounting a second carrier on the side of the stacked circuit layer away from the base circuit layer; mounting a second chip on the side of the base circuit layer away from the second encapsulation layer; forming a second encapsulation layer on the base circuit layer, which covers the second chip; peeling off the second carrier.

4. The method of claim 2 or 3, wherein Before the step of mounting a second chip on the side of the stacked circuit layer away from the base circuit layer, the method further comprises: forming an interconnection circuit layer on the first encapsulation layer and the stacked circuit layer, wherein the interconnection circuit layer is electrically connected to the stacked circuit layer.

5. The method of claim 4, wherein, The step of mounting a second chip on the side of the stacked circuit layer away from the base circuit layer comprises: mounting a second chip on the interconnection circuit layer corresponding to the stacked circuit layer and the first chip.

6. The method of claim 4, wherein, Before the step of mounting a first chip on the base circuit layer in the second opening, the method further comprises: forming a first conductive pillar on the base circuit layer in the second opening, wherein one end of the first conductive pillar away from the base circuit layer is flush with the stacked circuit layer, and the first conductive pillar is located on both sides of the first chip.

7. The method of claim 6, wherein, attaching a first chip on the substrate circuit layer in the second opening, comprising: attaching a plurality of first chips on the substrate circuit layer in the second opening, wherein at least part of the first chips are bridge chips, the front surface of the bridge chip is provided with a connecting conductive pillar electrically connected to the substrate circuit layer, the back surface of the bridge chip is provided with a second conductive pillar for electrically connecting with the interconnection circuit layer, and the two sides of the first chip are provided with the first conductive pillar.

8. A substrate interconnect package structure, comprising: The substrate interconnection packaging structure prepared by the substrate interconnection packaging method of any one of claims 1-7, comprising: a substrate circuit layer; a first chip, the front surface of the first chip is attached on the substrate circuit layer and electrically connected to the substrate circuit layer; a first encapsulation layer, the first encapsulation layer is arranged on the substrate circuit layer and encapsulates the first chip; a second encapsulation layer, the second encapsulation layer is arranged on the first encapsulation layer.

9. A substrate interconnect package structure, comprising: The substrate interconnection packaging structure prepared by the substrate interconnection packaging method of any one of claims 1-7, comprising: a substrate circuit layer; a stacked circuit layer, the stacked circuit layer is arranged on the substrate circuit layer and electrically connected to the substrate circuit layer; a second chip, the second chip is attached on the stacked circuit layer; a second encapsulation layer, the first encapsulation layer is arranged on the stacked circuit layer and encapsulates the second chip, and the sidewall of the second encapsulation layer is aligned with the edge of the stacked circuit layer.

10. A substrate interconnect package structure, comprising: The substrate interconnection packaging structure prepared by the substrate interconnection packaging method of any one of claims 1-7, comprising: a substrate circuit layer; a stacked circuit layer, the stacked circuit layer is arranged on a partial area of the substrate circuit layer and correspondingly electrically connected to the substrate circuit layer; a first chip, the first chip is attached on the substrate circuit layer and located on one side of the stacked circuit layer; a first encapsulation layer, the first encapsulation layer is arranged on the substrate circuit layer and encapsulates at least the first chip; a second chip, the second chip is attached on the stacked circuit layer; a second encapsulation layer, the second encapsulation layer is arranged on the stacked circuit layer and the first encapsulation layer and encapsulates the second chip.

11. A substrate interconnect package structure, comprising: The substrate interconnection packaging structure prepared by the substrate interconnection packaging method of any one of claims 1-7, comprising: a substrate circuit layer; a stacked circuit layer, the stacked circuit layer is arranged on a partial area of the substrate circuit layer and electrically connected to the substrate circuit layer; a first chip, the first chip is arranged on the substrate circuit layer; a first conductive pillar, the first conductive pillar is arranged on the substrate circuit layer and located on the two sides of the first chip; a first encapsulation layer, the first encapsulation layer is arranged on the substrate circuit layer and encapsulates the first chip and the first conductive pillar, and the side of the first encapsulation layer away from the substrate circuit layer is flush with the stacked circuit layer. an interconnection circuit layer disposed on the stacked circuit layer and the first encapsulation layer and electrically connected with the stacked circuit layer, and the interconnection circuit layer is electrically connected with the base circuit layer through the first conductive column; a second chip mounted on the interconnection circuit layer and corresponding to the stacked circuit layer and the first chip respectively; a second encapsulation layer disposed on the interconnection circuit layer and encapsulating the second chip.

12. A substrate interconnect package structure, comprising: The substrate interconnection packaging structure prepared by the substrate interconnection packaging method of any one of claims 1-7 comprises: a base circuit layer; a first chip disposed on the base circuit layer; a first conductive column disposed on the base circuit layer and located on both sides of the first chip; a first encapsulation layer disposed on the base circuit layer and encapsulating the first chip and the first conductive column, and a side of the first encapsulation layer away from the base circuit layer is flush with the stacked circuit layer; an interconnection circuit layer disposed on the stacked circuit layer and the first encapsulation layer and electrically connected with the stacked circuit layer, and the interconnection circuit layer is electrically connected with the base circuit layer through the first conductive column; a second chip mounted on the interconnection circuit layer and corresponding to the first chip respectively; a second encapsulation layer disposed on the interconnection circuit layer and encapsulating the second chip.

13. A substrate interconnect package structure, comprising: The substrate interconnection packaging structure prepared by the substrate interconnection packaging method of any one of claims 1-7 comprises: a base circuit layer; a stacked circuit layer disposed on a partial area of the base circuit layer and electrically connected with the base circuit layer; a first chip disposed on the base circuit layer; a first conductive column disposed on the base circuit layer and located on both sides of the first chip; a first encapsulation layer disposed on the base circuit layer and encapsulating the first chip and the first conductive column, and a side of the first encapsulation layer away from the base circuit layer is flush with the stacked circuit layer; an interconnection circuit layer disposed on the stacked circuit layer and the first encapsulation layer and electrically connected with the stacked circuit layer, and the interconnection circuit layer is electrically connected with the base circuit layer through the first conductive column; a second chip mounted on a side of the base circuit layer away from the interconnection circuit layer and corresponding to the stacked circuit layer and the first chip respectively; a second encapsulation layer disposed on a side of the base circuit layer away from the interconnection circuit layer and encapsulating the second chip.

14. A substrate interconnect package structure, comprising: The substrate interconnection packaging structure prepared by the substrate interconnection packaging method of any one of claims 1-7 comprises: a base circuit layer; a first chip disposed on the base circuit layer; a first conductive column disposed on the base circuit layer and located on both sides of the first chip; a first encapsulation layer disposed on the base circuit layer and covering the first chip and the first conductive column; an interconnection circuit layer disposed on the first encapsulation layer and electrically connected to the base circuit layer through the first conductive column; a second chip attached to the side of the base circuit layer away from the interconnection circuit layer and corresponding to the first chip; a second encapsulation layer disposed on the side of the base circuit layer away from the interconnection circuit layer and covering the second chip. The first chip is a bridge chip, the front surface of the bridge chip is provided with a connecting conductive column electrically connected to the base circuit layer, the back surface of the bridge chip is provided with a second conductive column for electrical connection with the interconnection circuit layer, and the two sides of the bridge chip are both provided with the first conductive column.

15. A substrate interconnect package structure, comprising: The substrate interconnection packaging structure is prepared by the substrate interconnection packaging method according to any one of claims 1-7, and the substrate interconnection packaging structure comprises: a base circuit layer; a first chip, the front surface of the first chip being attached to the base circuit layer; a first conductive column disposed on the base circuit layer and located on the two sides of the first chip; a first encapsulation layer disposed on the base circuit layer and covering the first chip and the first conductive column; an interconnection circuit layer disposed on the first encapsulation layer and electrically connected to the base circuit layer through the first conductive column; a second chip attached to the side of the base circuit layer away from the interconnection circuit layer and corresponding to the first chip; a second encapsulation layer disposed on the side of the base circuit layer away from the interconnection circuit layer and covering the second chip.

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