Semiconductor device and manufacturing method thereof
By using a specially designed mask to form patterns in semiconductor device manufacturing, the problem of uneven pattern density at the corners of adjacent chip areas in the edge region is solved, achieving uniform filling of conductive materials and improving electrical connections and product yield.
Patent Information
- Application Number
- CN202511073679.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-07
AI Technical Summary
When filling conductive materials, the pattern at the corner of the edge region of a semiconductor device adjacent to the chip region is prone to premature sealing, leading to the formation of voids, which affects electrical connections and product yield.
First and second patterns are formed in a substrate using first and second masks. The second portion of the mask extends along a specific direction to control the pattern density and avoid the pattern density being too low at the corners. The pattern density consistency is controlled by splicing the masks.
This effectively avoids premature sealing of the pattern when filling it with conductive material, thus improving the reliability and yield of the product's electrical connection.
Smart Images
Figure CN120914166A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and its manufacturing method. Background Technology
[0002] like Figure 1 As shown, each region in the chip region A1 of the substrate has multiple patterns (e.g., through-silicon vias, TSVs), while the edge region A2 of the substrate does not have patterns. This results in the corners of the chip region A1 adjacent to the edge region A2 (e.g., Figure 1 The density of the pattern at the corners of areas marked with ★ (1, 8, 28, 29, and 32) is much lower than that of the patterns in other areas of chip area A1. This means that when conductive material is filled into the pattern, the pattern at the corner of chip area A1 adjacent to edge area A2 is easily sealed prematurely. As a result, voids are easily formed in the pattern at the corner of chip area A1 adjacent to edge area A2 after the conductive material is filled. When these voids expand due to heat, they can easily cause cracks in the sidewall structure of the pattern, thus affecting the electrical connection and reliability of the product, and consequently affecting the product yield.
[0003] Therefore, how to prevent the pattern at the corner of the chip area adjacent to the edge area from being prematurely sealed when filling conductive material is an urgent problem to be solved. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which enables the pattern at the corner of the chip area adjacent to the edge area to be sealed prematurely when filling the conductive material.
[0005] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising:
[0006] A substrate is provided, the substrate including a chip region and an edge region, the edge region surrounding the chip region, the chip region including a first region and a second region, the edge region including a third region and a fourth region, the first region and the fourth region being separated from the third region by the second region, the second region being adjacent to the third region;
[0007] A first pattern and a second pattern are formed in the substrate using a first mask, wherein the first pattern is located in the substrate in the first region and the second region, and the second pattern is located in the substrate in the third region;
[0008] The first mask plate includes a first portion and a second portion, the second portion surrounds the first portion, the first portion is used to form the first pattern, the second portion is used to form the second pattern, and the part of the second portion used to form the second pattern is located at a first side and a second side of the first portion, the first side and the second side are connected and extend along a first direction and a second direction respectively.
[0009] Optionally, the method for manufacturing the semiconductor device further comprises:
[0010] providing a second mask plate, the second mask plate is symmetrical to the first mask plate;
[0011] splicing the first mask plate and the second mask plate, and shielding the second portion of the first mask plate and / or the second mask plate in the first direction and / or the second direction at the same time, to form the first pattern in the substrate of the second region.
[0012] Optionally, the method for manufacturing the semiconductor device further comprises:
[0013] splicing the first mask plate and the second mask plate, and shielding the second portion of the first mask plate and the second portion of the second mask plate at the same time, to form the first pattern in the substrate of the first region.
[0014] Optionally, the steps of forming the first pattern and forming the second pattern comprise:
[0015] forming a mask layer on the substrate;
[0016] patterning the mask layer to form a patterned mask layer;
[0017] etching the substrate of the chip region and the third region with the patterned mask layer as a mask, to form a first pattern in the substrate of the chip region and a second pattern in the substrate of the third region.
[0018] Optionally, the mask layer is a photoresist layer, and an exposure and development process is performed on the photoresist layer on the chip region and the third region with the first portion and the second portion to form the patterned mask layer.
[0019] Optionally, the density of the second pattern of the third region is the same as or within a predetermined range of the density of the first pattern of the chip region.
[0020] Optionally, the first pattern and the second pattern are both vias.
[0021] Optionally, the method for manufacturing the semiconductor device further comprises:
[0022] filling conductive material in the first pattern and the second pattern.
[0023] Optionally, the method for manufacturing the semiconductor device further comprises:
[0024] forming an insulating medium layer on the substrate, the insulating medium layer covering the conductive material;
[0025] forming a rewiring conductive structure in the insulating medium layer, the rewiring conductive structure being electrically connected with the conductive material in the first pattern.
[0026] The application further provides a semiconductor device manufactured by the method for manufacturing the semiconductor device.
[0027] Compared with the prior art, the technical scheme of the application has the following beneficial effects:
[0028] 1. The method for manufacturing the semiconductor device comprises: providing a substrate, the substrate comprising a chip area and an edge area, the edge area surrounding the chip area, the chip area comprising a first region and a second region, the edge area comprising a third region and a fourth region, the first region being separated from the fourth region by the second region and the third region, the second region being adjacent to the third region; forming a first pattern and a second pattern in the substrate by using a first mask, the first pattern being located in the substrate in the first region and the second region, the second pattern being located in the substrate in the third region; wherein the first mask comprises a first part and a second part, the second part surrounding the first part, the first part being used for forming the first pattern, the second part being used for forming the second pattern, the part of the second part for forming the second pattern being located at a first side edge and a second side edge of the first part, the first side edge and the second side edge being connected and extending along a first direction and a second direction respectively. This makes it possible to avoid the pattern at the corner of the chip area adjacent to the edge area being sealed in advance when filling the conductive material.
[0029] 2. The semiconductor device is manufactured by the method for manufacturing the semiconductor device, which makes it possible to avoid the pattern at the corner of the chip area adjacent to the edge area being sealed in advance when filling the conductive material. BRIEF DESCRIPTION OF DRAWINGS
[0030] Figure 1 is a top view of a substrate;
[0031] Figure 2 is a flow chart of the method for manufacturing the semiconductor device according to an embodiment of the application.
[0032] Figure 3 is a top view of a substrate of an embodiment of the present application;
[0033] Figures 4a-4b is a top view of a mask plate of an embodiment of the present application.
[0034] wherein, the Figures 1-4b The reference signs in the drawings are explained as follows:
[0035] A1-chip region; A2-edge region; B1-chip region; B2-edge region; B3-third region; 11-first part; 12-second part; 121-second light-transmitting part; 122-second light-blocking part. DETAILED DESCRIPTION
[0036] In order to make the objects, advantages and features of the present application clearer, the semiconductor device and the manufacturing method thereof according to the present application will be further described in detail below with reference to the drawings. It should be noted that all the drawings are very simplified and all use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.
[0037] An embodiment of the present application provides a manufacturing method of a semiconductor device, referring to Figure 2 , Figure 2 is a flow chart of a manufacturing method of a semiconductor device of an embodiment of the present application, the manufacturing method of the semiconductor device comprising:
[0038] Step S1, providing a substrate, the substrate comprising a chip region and an edge region, the edge region surrounding the chip region, the chip region comprising a first region and a second region, the edge region comprising a third region and a fourth region, the first region being separated from the fourth region by the second region and the third region, the second region being adjacent to the third region;
[0039] Step S2, forming a first pattern and a second pattern in the substrate by using a first mask plate, the first pattern being in the substrate in the first region and the second region, the second pattern being in the substrate in the third region; wherein the first mask plate comprises a first part and a second part, the second part surrounding the first part, the first part being used for forming the first pattern, the second part being used for forming the second pattern, the part of the second part for forming the second pattern being located at a first side and a second side of the first part, the first side and the second side being connected and extending along a first direction and a second direction respectively.
[0040] The following refers to Figure 3 and Figures 4a-4bA method for manufacturing a semiconductor device is provided.
[0041] According to step S1, a substrate (not shown) is provided, the substrate comprising a chip region B1 and an edge region B2, the edge region B2 surrounding the chip region B1, the chip region B1 comprising a first region and a second region, the edge region B2 comprising a third region and a fourth region, the first region being separated from the fourth region by the second region and the third region, the second region being adjacent to the third region. Figure 3 In the embodiment shown, the regions labeled 1-32 constitute the chip region B1, the chip region B1 being surrounded by the edge region B2, wherein the regions labeled 5-7, 10-12, 15-17, 20-22, 25-27, 30 are located in the first region of the chip region B1, the regions labeled 1-4, 8-9, 13-14, 18-19, 23-24, 28-29, 31-32 are located in the second region of the chip region B1, the region of the edge region B2 adjacent to the second region is the third region B3, the second region shares a side with the third region B3, and the region of the edge region B2 away from the chip region B1 is the fourth region. It should be understood that the regions labeled 1-32 are only shown by way of example, and the application is not limited thereto.
[0042] The substrate can be made of semiconductor materials such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors, and can also include layered substrates such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator, and can also include other materials other than semiconductor materials, such as glass, etc.
[0043] According to step S2, a first mask is used to form a first pattern (not shown) and a second pattern (not shown) in the substrate, the first pattern being located in the substrate in the first region and the second region, and the second pattern being located in the substrate in the third region.
[0044] In an embodiment, the first pattern and the second pattern are both vias, and in other embodiments, the first pattern and the second pattern can also be other patterns other than vias. Figure 3 In the embodiment shown, a plurality of interconnection vias are formed in the substrate of the chip region B1, and a plurality of dummy vias are formed in the substrate of the third region B3. In other embodiments, the first pattern and the second pattern can also be other patterns other than vias.
[0045] The density of the second pattern of the third region is the same as or within a predetermined range of the density of the first pattern of the chip region. In an embodiment, the density of the dummy via of the third region B3 is the same as or within a predetermined range of the density of the interconnection via of the chip region B1.
[0046] In an embodiment, the steps of forming the first pattern and forming the second pattern can comprise: forming a mask layer on the substrate; patterning the mask layer to form a patterned mask layer; etching the substrate of the chip region B1 and the third region B3 with the patterned mask layer as a mask to form a first pattern in the substrate of the chip region B1 and a second pattern in the substrate of the third region B3.
[0047] The mask layer can be a material well known in the art, including but not limited to an oxide layer, a nitride layer, a photoresist layer.
[0048] The patterning of the mask layer to form a patterned mask layer can be performed in a manner well known in the art. In an embodiment, the mask layer is a photoresist layer, and a mask plate is used to perform an exposure and development process on the photoresist layer on the third region B3 and the chip region B1 to form the patterned mask layer.
[0049] As shown in Figure 4a , 4b , Figure 4a a first mask plate is shown, Figure 4b a second mask plate is shown. For a single chip with a larger size, the first mask plate and the second mask plate can be spliced, and the first mask plate shown in Figure 4a is used to expose the photoresist layer on the left half of a single chip in the chip region B1, and the second mask plate shown in Figure 4b is used to expose the photoresist layer on the right half of the aforementioned single chip in the chip region B1. In other embodiments, for a single chip with a smaller size, a mask plate (i.e. the first mask plate or the second mask plate) can also be used to expose the entire region of a single chip in the chip region B1.
[0050] In an embodiment, the first mask plate comprises a first part 11 and a second part 12, the second part 12 surrounds the first part 11, the first part 11 is used to form the first pattern, and the second part 12 is used to form the second pattern. The first part 11 is used to expose the photoresist layer on the chip region B1 (the first region or the second region), and the second part 12 is used to expose the photoresist layer on the third region B3.
[0051] The first portion 11 comprises a first light-transmitting part and a first light-blocking part, and the second portion 12 comprises a second light-transmitting part 121 and a second light-blocking part 122; after performing an exposure and development process on the photoresist layer, the first light-transmitting part and the second light-transmitting part 121 correspond to the photoresist layer thereunder being completely removed, and the first light-blocking part and the second light-blocking part 122 correspond to the photoresist layer thereunder being completely reserved; and after etching the substrate with the patterned photoresist layer as a mask, the first pattern is formed in the substrate under the first light-transmitting part, and the second pattern is formed in the substrate under the second light-transmitting part 121.
[0052] The portion in the second portion 12 for forming the second pattern is located between a first side edge and a second side edge of the first portion 11, the first side edge and the second side edge are connected and respectively extend along a first direction and a second direction.
[0053] In an embodiment, the first direction is perpendicular to the second direction.
[0054] In Figure 4aIn the shown embodiment, preferably, the width W1 of the second portion 12 at the first side of the first portion 11 is greater than the width W2 of the second portion 12 at the third side of the first portion 11, and the width W3 of the second portion 12 at the second side of the first portion 11 is greater than the width W4 of the second portion 12 at the fourth side of the first portion 11, the first side and the third side being opposite sides, and the second side and the fourth side being opposite sides, the second portion 12 at the first side and the second side of the first portion 11 is used for exposing the photoresist layer on the third region B3, i.e. the second portion 12 at the first side and the second side of the first portion 11 is provided with the second light-transmissive portions 121 for forming the second pattern, the second portion 12 at the third side and the fourth side of the first portion 11 can be used as an edge support structure for support, can not be provided with the second light-transmissive portions 121 for forming the second pattern, or the second portion 12 can not be provided at the third side and the fourth side of the first portion 11. The second light-transmissive portions 121 are provided in the second portion 12 at the side with greater width, and the second light-transmissive portions 121 are not provided in the second portion 12 at the opposite side with smaller width, so that more second light-transmissive portions 121 can be provided in the second portion 12 at the side with greater width, and thus more second patterns (e.g. virtual vias) can be formed in the third region B3, so as to ensure that the density of the second patterns in the third region B3 is equal to or close to the density of the first patterns (e.g. interconnection vias) in the second region. Further, positioning marks can be provided in the second portion 12 at the third side and the fourth side of the first portion 11.
[0055] In Figure 4bIn the shown embodiment, the second mask is symmetrical to the first mask, which can be axial symmetry or point symmetry, and the present application does not limit this. The width W2' of the second part 12 located at the third side of the first part 11 is greater than the width W1' of the second part 12 located at the first side of the first part 11, the width W3' of the second part 12 located at the second side of the first part 11 is greater than the width W4' of the second part 12 located at the fourth side of the first part 11, the second part 12 located at the third side and the second side of the first part 11 is used to expose the photoresist layer on the third region B3, that is, the second part 12 located at the third side and the second side of the first part 11 is provided with the second light-transmitting part 121 for forming the second pattern, the second part 12 located at the first side and the fourth side of the first part 11 can be used as an edge support structure to support, can not be provided with the second light-transmitting part 121 for forming the second pattern, or the second part 12 can also not be provided at the first side and the fourth side of the first part 11. In other embodiments, the pattern formed by the first part 11 of the second mask on the substrate can be different from the pattern formed by the first part 11 of the first mask, and the pattern formed by the second part 12 of the second mask on the substrate can also be different from the pattern formed by the second part 12 of the first mask.
[0056] When the first mask and the second mask are spliced to expose the photoresist layer located in the first region by using the first part 11, a baffle (not shown) is used to shield the second part 12 of the first mask and the second mask, so that the photoresist layer corresponding to the first light-transmitting part below is exposed while avoiding the photoresist layer corresponding to the second light-transmitting part 121 below being exposed, thereby forming the first pattern in the substrate located in the first region while avoiding forming the second pattern in the substrate of the chip region B1.
[0057] When the first mask and the second mask are spliced to expose the photoresist layer located in the second region by using the first part 11, the second part 12 of the first mask and / or the second mask in the first direction and / or the second direction is shielded at the same time, so as to form the first pattern in the substrate of the second region while avoiding forming the second pattern in the substrate of the chip region B1. Wherein, the second pattern can also be formed in the substrate of the third region B3.
[0058] When the first mask and the second mask are spliced to expose the photoresist layer located in the second region by using the first part 11, the second part 12 of the first mask and / or the second mask in the first direction and / or the second direction is shielded at the same time, so as to form the first pattern in the substrate of the second region while avoiding forming the second pattern in the substrate of the chip region B1. Wherein, the second pattern can also be formed in the substrate of the third region B3. Figure 4a The first mask shown in the figure and Figure 4b The second mask shown in the figure is used to Figure 3Exposure of the photoresist layer on the chip area B1 and the edge area B2 shown is taken as an example for illustration.
[0059] When exposing the photoresist layer of the second area (for example, the area marked 1, 8) in which the third area B3 is formed on the first side edge, the second part 12 of the first mask in the second direction and the second part 12 of the second mask in the first direction and the second direction are shielded to simultaneously expose the photoresist layer of the second area and the third area B3 on the first side edge of the second area; and the first part and the second part 12 in the first direction of the first mask and the first part and the second part 12 in the first direction of the second mask are shielded to expose the photoresist layer of the third area B3 on the fourth side edge of the second area.
[0060] When exposing the photoresist layer of the second area (for example, the area marked 2) in which the third area B3 is formed on the fourth side edge, the second part 12 of the first mask in the first direction and the second direction and the second part 12 of the second mask in the first direction and the second direction are shielded to expose the second area; and the first part and the second part 12 in the first direction of the first mask and the first part and the second part 12 in the first direction of the second mask are shielded to expose the photoresist layer of the third area B3 on the fourth side edge of the second area.
[0061] When exposing the photoresist layer of the second area (for example, the area marked 9, 18, 19) in which the third area B3 is formed on the first side edge, the second part 12 of the first mask in the second direction and the second part 12 of the second mask in the first direction and the second direction are shielded to simultaneously expose the photoresist layer of the second area and the third area B3 on the first side edge of the second area.
[0062] When exposing the photoresist layer of the second area (for example, the area marked 28, 29) in which the third area B3 is formed on the first side edge and the second side edge, the second part 12 of the second mask in the first direction is shielded to simultaneously expose the photoresist layer of the second area and the third area B3 on the first side edge and the second side edge of the second area.
[0063] When the photoresist layer of the second region (for example, the region of mark 32) in which the first side edge, the second side edge and the third side edge of the third region B3 are formed is exposed, the photoresist layer of the second region and the photoresist layer of the third region B3 in the first side edge, the second side edge and the third side edge of the second region can be exposed simultaneously without shielding the second part 12.
[0064] When the photoresist layer of the regions of marks 3, 4, 13, 14, 23, 24, 31 and the third region B3 which is co-located with the regions is exposed, reference is made to the exposure steps of the photoresist layer of the regions of marks 1, 8, 9, 18, 19, 28, 29 and the third region B3 which is co-located with the regions, and adjustment is made according to the symmetry of the first mask shown in Figure 4a Figure 4b and the second mask shown in
[0065] When the photoresist layer of the first region (for example, the regions of marks 5-7, 10-12, 15-17, 20-22, 25-27, 30) is exposed, the second part 12 of the first mask in the first direction and the second direction and the second part 12 of the second mask in the first direction and the second direction are shielded to expose the first region.
[0066] It should be noted that when the regions are exposed as described above, the exposure of the first mask and the exposure of the second mask can be completed in different regions first, or the exposure of the first mask and the exposure of the second mask can be completed in the same region first, and then the exposure of the first mask and the exposure of the second mask can be completed in the next region.
[0067] The method for manufacturing the semiconductor device further includes filling a conductive material in the first pattern and the second pattern.
[0068] The conductive material fills the first pattern and the second pattern.
[0069] In an embodiment, the method for manufacturing the semiconductor device further includes:
[0070] forming an insulating medium layer (not shown) on the substrate, the insulating medium layer covering the conductive material;
[0071] forming a rewiring conductive structure (not shown) in the insulating medium layer, the rewiring conductive structure being electrically connected to the conductive material in the first pattern, the rewiring conductive structure not being electrically connected to the conductive material in the second pattern.
[0072] The insulating medium layer can include at least one insulating layer.
[0073] The re-wiring conductive structure can include at least one metal layer; when the re-wiring conductive structure includes at least two metal layers, the adjacent metal layers are electrically connected through a plug structure.
[0074] In an embodiment, the method for manufacturing the semiconductor device further includes: soldering the substrate to a packaging substrate (not shown) through an external solder ball (not shown) away from the surface of the insulating medium layer, the conductive material in the first pattern being electrically connected with the external solder ball.
[0075] In addition, the method for manufacturing the semiconductor device further includes: attaching a chip (not shown) to the side of the insulating medium layer away from the substrate, the chip being electrically connected with the re-wiring conductive structure. The chip can be electrically connected with the re-wiring conductive structure through a hybrid bonding structure or a micro bump (not shown), and the type of the chip is not limited.
[0076] After the desired structure is made on the substrate, the substrate is cut, and the chip area B1 after cutting is reserved as an effective chip, and the edge area B2 after cutting is an ineffective chip.
[0077] In an embodiment, the semiconductor device is a 2.5D interposer.
[0078] As can be seen from the above, in the method for manufacturing the semiconductor device, the first pattern is formed in the substrate of the chip area B1, and the second pattern is formed in the substrate of the third area B3 surrounding the chip area B1, so that the density of the second pattern in the edge area B2 adjacent to the chip area B1 is the same as or within a predetermined range of the density of the first pattern in the chip area B1, that is, the pattern density (for example, the density of through silicon vias) at the corner of the chip area B1 adjacent to the third area B3 is improved, and thus when the conductive material is filled in the first pattern and the second pattern, the supply of the conductive material is avoided to be greater than the demand due to the too low pattern density at the corner of the chip area B1 adjacent to the third area B3, and thus the pattern at the corner of the chip area B1 adjacent to the third area B3 is avoided to be sealed in advance (if the number of patterns is too small, the amount of conductive material entering the pattern per unit time is more, that is, the filling speed is faster, which leads to early sealing), so as to avoid the pattern at the corner of the chip area B1 adjacent to the third area B3 to form a cavity after the conductive material is filled, thereby avoiding affecting the electrical connection and reliability of the product.
[0079] An embodiment of the present application provides a semiconductor device manufactured by the method for manufacturing the semiconductor device.
[0080] The manufacturing method of the semiconductor device is described above, and will not be repeated here.
[0081] Since the semiconductor device is manufactured by the manufacturing method of the semiconductor device, when filling the conductive material in the first pattern and the second pattern, the supply of the conductive material can be avoided to be greater than the demand due to the too low pattern density at the corner of the chip area adjacent to the edge area, and the pattern at the corner of the chip area adjacent to the edge area can be avoided to be sealed in advance (if the number of the pattern is too small, the amount of the conductive material entering the pattern per unit time is more, i.e. the filling speed is faster, and the pattern is sealed in advance), to avoid the pattern at the corner of the chip area adjacent to the edge area to form a cavity after filling the conductive material, so as to avoid affecting the electrical connection and reliability of the product, and further avoid affecting the yield of the product.
[0082] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or change made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.
Claims
1. A method of manufacturing a semiconductor device, characterized by, The semiconductor device manufacturing method comprises: providing a substrate, the substrate comprising a chip region and an edge region, the edge region surrounding the chip region, the chip region comprising a first region and a second region, the edge region comprising a third region and a fourth region, the first region being separated from the fourth region by the second region and the third region, the second region being contiguous with the third region; forming a first pattern and a second pattern in the substrate using a first mask, the first pattern being formed in the substrate in the first region and the second region, the second pattern being formed in the substrate in the third region; wherein the first mask comprises a first portion and a second portion, the second portion surrounding the first portion, the first portion being used to form the first pattern, the second portion being used to form the second pattern, the second portion used to form the second pattern being located at a first side and a second side of the first portion, the first side and the second side being connected and extending along a first direction and a second direction respectively.
2. The method of manufacturing a semiconductor device according to Claim 1, wherein The semiconductor device manufacturing method further comprises: providing a second mask, the second mask being symmetrical to the first mask; splicing the first mask and the second mask, and simultaneously shielding the second portion of the first mask and / or the second mask in the first direction and / or the second direction to form the first pattern in the substrate in the second region.
3. The method of manufacturing a semiconductor device according to Claim 2, wherein The semiconductor device manufacturing method further comprises: splicing the first mask and the second mask, and simultaneously shielding the second portion of the first mask and the second portion of the second mask to form the first pattern in the substrate in the first region.
4. The method of manufacturing a semiconductor device according to Claim 1, wherein The steps of forming the first pattern and forming the second pattern comprise: forming a mask layer on the substrate; patterning the mask layer to form a patterned mask layer; etching the substrate in the chip region and the third region using the patterned mask layer as a mask to form a first pattern in the substrate in the chip region and a second pattern in the substrate in the third region.
5. The method of manufacturing a semiconductor device according to Claim 4, wherein The mask layer is a photoresist layer, and the photoresist layer on the chip region and the third region is exposed and developed using the first portion and the second portion to form the patterned mask layer.
6. The method of manufacturing a semiconductor device according to Claim 1, wherein The density of the second pattern in the third region is the same as or within a predetermined range of the density of the first pattern in the chip region.
7. The method of manufacturing a semiconductor device according to Claim 1, wherein The first pattern and the second pattern are both vias.
8. The method of manufacturing a semiconductor device according to Claim 1, wherein The semiconductor device manufacturing method further comprises: filling a conductive material in the first pattern and the second pattern.
9. The method of manufacturing a semiconductor device according to Claim 8, wherein The semiconductor device manufacturing method further comprises: forming an insulating dielectric layer on the substrate, the insulating dielectric layer covering the conductive material; forming a rewiring conductive structure in the insulating dielectric layer, the rewiring conductive structure being electrically connected to the conductive material in the first pattern.
10. A semiconductor device, characterized by comprising: The semiconductor device is manufactured using the semiconductor device manufacturing method of any one of claims 1-9.