Power control circuit and chip

Abstract

The application provides a power supply control circuit and a chip. A dynamic latch is added in the front stage of a comparator. The power consumption of the dynamic latch (nA level) is much lower than the power consumption of the comparator (μA level). The internal power supply voltage output by a power supply system is quickly detected, and the comparator is enabled or disabled according to the detection result. Especially when the internal power supply voltage is relatively high, the comparator is not turned on, and the power consumption is further reduced, so that the product demand of lower standby power consumption can be met.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a power control circuit and chip. Background Technology

[0002] Low-power design is particularly important in the fields of information technology and electronic devices, as it can significantly extend the lifespan of devices. A common low-power design approach in the prior art is to put the device or chip into standby mode (also known as "low-power mode") when the device or chip is not in use, thereby reducing the device's power consumption to an extremely low operating state. In standby mode, the device or chip enters a dormant state, but still maintains the normal operation of some functions (such as clock or wake-up mechanism).

[0003] To reduce the standby power consumption of a device or chip, the standby power consumption of the device or chip's power system can be reduced. Generally, the following approach is adopted: the power system is set to operate in an intermittent mode, that is, the power system operates for a period of time and then shuts down for a period of time. During the period when the power system is off, the internal capacitor provides the internal power supply voltage to the internal circuit, thereby reducing standby power consumption. However, during this period, the internal power supply voltage will decrease due to leakage. Therefore, after a period of time, the power system is restarted to restore the internal power supply voltage to the target potential.

[0004] The above-mentioned solution typically uses a voltage detection circuit with a comparator to detect changes in the internal power supply voltage to determine whether to start the power system. This solution is simple and easy to implement, but the comparator will work continuously, generating power consumption, which makes it difficult to meet the product requirements for lower standby power consumption. Summary of the Invention

[0005] The purpose of this invention is to provide a power control circuit and chip that can detect the internal power supply voltage output by the power system more frequently with lower power consumption, thereby achieving a more stable internal power supply voltage.

[0006] To achieve the above objectives, the present invention provides a power control circuit for providing an internal power supply voltage to a chip, comprising a dynamic latch and a comparator coupled in sequence, wherein the power consumption of the comparator during operation is greater than the power consumption of the dynamic latch during operation, and:

[0007] The dynamic latch is coupled to the corresponding power system and is periodically enabled after the power system enters the intermittent operating mode. After being enabled, it detects whether the internal power supply voltage output by the power system is lower than the corresponding reference voltage. If it is, the comparator is enabled; otherwise, the comparator is disabled.

[0008] The comparator is used to compare the magnitude of the internal power supply voltage and the reference voltage after being enabled, so as to enable the power system to operate when the internal power supply voltage is lower than the reference voltage, until the power system pulls the internal power supply voltage up to be equal to or higher than the reference voltage.

[0009] Optionally, the power control circuit further includes a disable logic circuit coupled between the dynamic latch and the comparator, configured to, when the internal power supply voltage is lower than the reference voltage, delay the output of the dynamic latch before providing it to the comparator to delay enabling the comparator; and, after the power system pulls the internal power supply voltage up to equal to or higher than the reference voltage, the disable logic circuit disables the comparator and / or resets the dynamic latch based on the flipped output of the comparator.

[0010] Optionally, the enable / disable logic circuit includes:

[0011] The first delay logic circuit has its input terminal coupled to the output terminal of the dynamic latch and is used to perform delay logic processing on the output of the dynamic latch.

[0012] The second delay logic circuit has its input terminal coupled to the output terminal of the comparator and is used to perform delay logic processing on the output of the comparator.

[0013] Wherein, the delay time of the output of the first delay logic circuit to the dynamic latch is longer than the delay time of the output of the second delay logic circuit to the comparator.

[0014] Optionally, the disable logic circuit further includes:

[0015] The NAND logic circuit has one input terminal coupled to the output terminal of the first delay logic circuit and the other input terminal coupled to the output terminal of the second delay logic circuit, and is used to perform NAND logic operations on the output of the first delay logic circuit and the output of the second delay logic circuit.

[0016] The flip-flop has one input terminal coupled to the output terminal of the NAND logic circuit and the other input terminal coupled to the output terminal of the first delay logic circuit, and is used to enable or disable the comparator based on the output of the NAND logic circuit and the output of the first delay logic circuit.

[0017] Optionally, the first delay logic circuit includes a first inverter, a second inverter, a first NAND gate, and a first delay circuit. The input terminal of the first inverter is coupled to the output terminal of the dynamic latch. The output terminal of the first inverter is coupled to the input terminal of the second inverter and the input terminal of the first delay circuit. The output terminal of the second inverter is coupled to the first input terminal of the first NAND gate. The output terminal of the first delay circuit is coupled to the second input terminal of the first NAND gate. The output terminal of the first NAND gate is coupled to the first input terminal of the NAND logic circuit.

[0018] And / or, the second delay logic circuit includes a third inverter, a fourth inverter, a fifth inverter, a second NAND gate, and a second delay circuit. The input of the third inverter is coupled to the output of the comparator. The output of the third inverter is coupled to the input of the fourth inverter and the input of the second delay circuit. The output of the fourth inverter is coupled to the first input of the second NAND gate. The output of the second delay circuit is coupled to the second input of the second NAND gate. The output of the second NAND gate is coupled to the input of the fifth inverter. The output of the fifth inverter is coupled to the second input of the NOT logic circuit.

[0019] Optionally, the dynamic latch includes a first input transistor, a second input transistor, and a pair of back-to-back cascaded inverters. The drain of the first input transistor is coupled to the reference voltage, the drain of the second input transistor is coupled to the internal power supply voltage, the gates of the first and second input transistors are both coupled to the inverted signals of corresponding periodic enable signals, and the sources of the first and second input transistors are both coupled to the back-to-back cascaded inverters.

[0020] Optionally, the dynamic latch further includes at least one of the following (1) to (4):

[0021] (1) A wake tube, wherein the drain of the wake tube is coupled to the back-to-back cascaded inverter, the source of the wake tube is grounded, and the gate of the wake tube is coupled to the periodic enable signal.

[0022] (2) A switching transistor, wherein the drain of the switching transistor is coupled to the back-to-back cascaded inverter, the source of the switching transistor is connected to the power supply, and the gate of the switching transistor is coupled to the inverted signal of the periodic enable signal.

[0023] (3) A first buffer, wherein the input terminal of the first buffer is coupled to the source of the back-to-back cascaded inverter and the first input transistor;

[0024] (4) Second buffer, the input terminal of the second buffer is coupled to the source of the back-to-back cascaded inverter and the second input tube, and the output terminal of the second buffer is coupled to the enable terminal of the comparator.

[0025] Optionally, the second buffer includes a zeroth inverter and an OR gate, the input of the zeroth inverter being coupled to the periodic enable signal, the output of the zeroth inverter being coupled to the first input of the OR gate, the second input of the OR gate being coupled to the back-to-back cascaded inverters, and the output of the OR gate being coupled to the comparator.

[0026] Optionally, the power supply system has a power switch transistor, the gate of which is coupled to the output of the comparator, and the drain of which is coupled to or outputs the internal power supply voltage.

[0027] Alternatively, the power supply system includes a linear regulator, the enable terminal of which is coupled to the output terminal of the comparator, and the output terminal of which is coupled to or outputs the internal power supply voltage.

[0028] Alternatively, the power supply system includes a charge pump, the control terminal of which is coupled to the output terminal of the comparator, and the output terminal of which is coupled to or outputs the internal power supply voltage.

[0029] Alternatively, the power supply system includes a DC-DC converter, the control terminal of which is coupled to the output terminal of the comparator, and the output terminal of the DC-DC converter is coupled to or outputs the internal power supply voltage.

[0030] Optionally, the power control circuit further includes a pulse generator coupled to the dynamic latch and used to generate periodic enable signals to periodically enable the dynamic latch.

[0031] Optionally, the power control circuit further includes an oscillator coupled to the pulse generator and used to provide a corresponding frequency signal to the pulse generator; the pulse generator is used to count the frequency signal, and generates a pulse and restarts counting each time the count reaches a set value, so as to generate the periodic enable signal.

[0032] Optionally, the pulse generator and the oscillator are enabled when the power system enters an intermittent operating mode.

[0033] Based on the same inventive concept, the present invention also provides a chip, which includes a power system, a power consumption circuit coupled to the output terminal of the power system to receive the internal power supply voltage, and a power control circuit as described in the present invention. When the chip receives a low-power mode entry instruction and some or all of the devices in the power consumption circuit enter the corresponding low-power mode, the power system enters an intermittent operating mode.

[0034] Optionally, the chip is a memory chip, and the low-power mode is a semi-sleep mode, a deep sleep mode, or a hybrid sleep mode of the memory chip.

[0035] Compared with the prior art, the technical solution of the present invention adds a dynamic latch in the front stage of the comparator. Taking advantage of the fact that the power consumption of the dynamic latch (in the nA range) is much lower than that of the comparator (in the μA range), the power supply voltage output by the power supply system is quickly detected, and the comparator is enabled or disabled according to the detection result. In particular, when the internal power supply voltage is relatively high, the comparator can be kept off, thereby further reducing power consumption. Attached Figure Description

[0036] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0037] Figure 1 This is a schematic diagram of a voltage detection circuit with a comparator.

[0038] Figure 2 This is a schematic diagram of the power control circuit architecture according to an embodiment of the present invention.

[0039] Figure 3 yes Figure 1 and Figure 2 The circuit shown is a schematic diagram comparing the signal timing.

[0040] Figure 4 This is a schematic diagram illustrating an application example of a power control circuit according to an embodiment of the present invention.

[0041] Figure 5 This is a schematic diagram illustrating another application example of the power control circuit according to an embodiment of the present invention.

[0042] Figure 6 This is a schematic diagram illustrating another application example of the power control circuit according to an embodiment of the present invention.

[0043] Figure 7 This is a schematic diagram illustrating another application example of the power control circuit according to an embodiment of the present invention.

[0044] Figure 8 This is a schematic diagram of an example structure of a dynamic latch in a power control circuit according to an embodiment of the present invention.

[0045] Figure 9 This is a schematic diagram of another example structure of a dynamic latch in a power control circuit according to an embodiment of the present invention.

[0046] Figure 10 This is a schematic diagram of an example structure of a comparator in a power control circuit according to an embodiment of the present invention.

[0047] Figure 11 This is a schematic diagram of the power control circuit architecture according to another embodiment of the present invention.

[0048] Figure 12 yes Figure 11 The diagram shows an example structure of the enable / disable logic circuit in the power control circuit.

[0049] Figure 13 yes Figure 11 The diagram shows the signal timing of the power control circuit.

[0050] Figure 14 This is a schematic diagram of the chip architecture according to an embodiment of the present invention. Detailed Implementation

[0051] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0052] Please refer to Figure 1 A voltage detection circuit with a comparator generally consists of an oscillator 10, a pulse generator 11, and a comparator 12 coupled in sequence.

[0053] Among them, the oscillator 10 is used to generate an internal frequency signal f. The pulse generator 11 counts the internal frequency signal f and generates a pulse as an enable signal EN1 at regular intervals (i.e., when the count reaches a set value) to enable the comparator 12 to detect the state of the internal power supply voltage V_int output by the power supply system 13. The comparator 12 has two functions: ① comparing the magnitudes of the internal power supply voltage V_int and the reference voltage Vref; ② enabling or disabling the operation of the power supply system 13.

[0054] Please combine Figure 1 and Figure 3 , after receiving the corresponding low-power entry instruction, the system (or chip) where the voltage detection circuit and the power supply system 13 are located will enter the low-power mode (the internal power-consuming circuits are silent), and then generate a low-power mode signal PDEN (power done) (it can also be said to "pull up" or "enable" PDEN), which in turn allows the power supply system 13 to enter the intermittent operation mode. Initially, the intermittent operation mode will temporarily turn off the power supply system 13. In a further embodiment, the oscillator 10 and the pulse generator 11 in the voltage detection circuit will also start working according to the low-power mode signal PDEN. In other embodiments, the oscillator 10 and the pulse generator 11 in the voltage detection circuit can also work continuously without being enabled by the low-power mode signal PDEN. When the pulse generator 11 periodically generates a pulse EN1, and then based on the EN1 signal and in combination with the required comparator operating state, generates an enable signal EN1 for the comparator to enable the comparator 12. After the comparator 12 is enabled, it will compare the magnitudes of the internal power supply voltage V_int and the reference voltage Vref. If V_int < Vref, it means that V_int is pulled down below Vref by internal leakage in the system, and the enable signal EN2 output by the comparator 12 is valid (for example, it is a low level), starting the operation of the power supply system 13 to charge and raise V_int to Vref or above Vref; if V_int > Vref, the enable signal EN2 output by the comparator 12 is invalid (for example, EN2 changes from a low level to a high level), and the power supply system 13 remains off and silent.

[0055] The disadvantage of this voltage detection circuit is that when V_int is relatively high, the comparator 12 still operates at a relatively high frequency, but the power supply system 13 does not need to charge V_int, which will result in additional power consumption and it is difficult to further reduce the system power consumption.

[0056] Based on this, in the technical solution of the present invention, a dynamic latch is added in the front stage of the comparator. By utilizing the characteristics that the power consumption of the dynamic latch (in the nA level) is much lower than that of the comparator (in the μA level), the internal power supply voltage output by the power supply system is quickly detected, and the comparator is enabled or disabled according to the detection result. When the internal power supply voltage is relatively high, the comparator is not opened, thereby further reducing the power consumption.

[0057] The following will combine the attached Figures 2 to 14 to detail the technical solution of the present invention.

[0058] Please refer to Figure 2 In an embodiment of the present invention, a power supply control circuit is provided for supplying an internal power supply voltage V_int to a chip, which includes a dynamically coupled latch 14 and a comparator 12 in sequence. Among them, the dynamically coupled latch 14 is coupled to the corresponding power supply system 13 and is used to be periodically enabled after the power supply system 13 enters the intermittent working mode. After being enabled, it detects whether the internal power supply voltage V_int output by the power supply system 13 is lower than the corresponding reference voltage Vref. If so, the comparator 12 is enabled; if not, the comparator 12 is disabled. The comparator 12 is used to compare the magnitudes of the internal power supply voltage V_int and the reference voltage Vref after being enabled, so that when the internal power supply voltage V_int is lower than the reference voltage Vref (i.e., V_int < Vref), the power supply system 13 is enabled to work (i.e., the power supply system 13 is started and charges V_int) until the power supply system 13 raises the internal power supply voltage V_int to be equal to or higher than the reference voltage Vref.

[0059] The dynamically coupled latch 14 has the characteristics of low power consumption (such as in the nA level), high precision, and fast response. And only when V_int < Vref, the comparator 12 will be enabled, and then the comparator 12 will enable the power supply system 13 to charge V_int. After V_int reaches the standard (i.e., V_int ≥ Vref), the output EN4 of the comparator 12 will flip, and the power supply system 13 will be disabled (i.e., the power supply system 13 is turned off). Thus, compared with Figure 1 the voltage detection circuit shown, when the internal power supply voltage V_int ≥ Vref, the comparator 12 can be disabled, thereby reducing the power consumption generated by the comparator 12 during this period (where the power consumption of the comparator 12 is generally in the μA level), and the power consumption can be greatly saved.

[0060] It should be understood that in this invention, the power supply system 13 can enter an intermittent operating mode (i.e., the power supply system 13 can operate for a period of time and then be turned off for a period of time) due to any suitable reason such as the system entering a low-power mode. After the power supply system 13 enters the intermittent operating mode, the power control circuit can periodically enable the dynamic latch 14 in any suitable manner. Moreover, the power supply system 13, the dynamic latch 14, and the comparator 12 can each be implemented using any suitable circuit design.

[0061] In one example, please refer to Figure 2 The power control circuit also includes a pulse generator 11, which is a pre-amplifier of the dynamic latch 14. The output of the pulse generator 11 is coupled to the dynamic latch 14 and is used to generate a periodic enable signal EN (which can be connected to...). Figure 1 (The same as EN1 in the original text) to periodically enable dynamic latch 14.

[0062] Alternatively, please refer to Figure 2 The power control circuit also includes an oscillator 10, which is a pre-amplifier of the pulse generator 11. The output of the oscillator 10 is coupled to the input of the pulse generator 11 and provides a corresponding frequency signal f to the pulse generator 11. This frequency signal f is the internal timing unit of the power control circuit. The pulse generator 11 counts the period of the frequency signal f, and generates a pulse each time the count reaches a set value and restarts the counting to generate a periodic enable signal EN. When EN is high, the dynamic latch 14 is enabled; when EN is low, the dynamic latch 14 is disabled.

[0063] Please combine Figure 2 and Figure 3 , Figure 14 In one example, the power control circuit and the system (or chip) containing power system 13 enter a low-power mode after receiving the corresponding low-power entry command Standby. The power-consuming circuit 2 within this system enters a silent state (i.e., a state with very low power consumption) and generates a low-power mode signal PDEN (e.g., PDEN "pull high" or "enable") to provide to power system 13. This low-power mode signal PDEN can cause power system 13 to enter an intermittent operating mode, temporarily shutting it down. The specific timing sequence of the power control circuit in this example is as follows:

[0064] The oscillator 10 and the pulse generator 11 operate. The oscillator 10 outputs a frequency signal f, and the pulse generator 11 counts the frequency signal f output by the oscillator 10. Each time the count of the frequency signal f output by the oscillator 10 by the pulse generator 11 reaches a set value, a pulse is generated and the counting restarts. Thus, the pulse generator 11 can generate a periodic enable signal EN according to the frequency signal f to periodically enable the dynamic latch 14. In one embodiment, the low-power mode signal PDEN is provided not only to the power supply system 13 but also to the oscillator 10 and the pulse generator 11 in the power supply control circuit. Therefore, the low-power mode signal PDEN can not only cause the power supply system 13 to enter the discontinuous operation mode but also enable the pulse generator 11 and the oscillator 10 to start operating. That is to say, when the power supply system 13 is controlled by PDEN to enter the discontinuous operation mode, the pulse generator 11 and the oscillator 10 are also synchronously enabled by PDEN to operate. At this time, the chip is in the low-power mode, and the pulse generator 11 and the oscillator 10 keep operating in the low-power mode of the chip. In another embodiment, the pulse generator 11 and the oscillator 10 may not be coupled to the PDEN, and thus keep operating in both the normal operation mode and the low-power mode of the chip.

[0065] The dynamic latch 14 is periodically enabled by the periodic enable signal EN output by the pulse generator 11, and only when it detects that V_int < Vref, it will output a valid enable signal EN3 (for example, EN3 changes from low level to high level), and then enable the comparator 12;

[0066] After being enabled, when the comparator 12 compares and finds that V_int < Vref, it will output a valid enable signal EN4 (for example, EN4 changes from high level to low level) to enable the power supply system 13 to charge V_int until V_int ≥ Vref, at which time EN4 flips to disable the power supply system 13 and turn off the power supply system 13.

[0067] Comparing Figure 3 the enable signals EN1 and EN3 shown in [reference] which are both used to enable the comparator 12 to operate, it can be found that EN3 is low during V_int ≥ Vref, thus making the comparator 12 not operate, while EN1 flips multiple times during V_int ≥ Vref, and the comparator 12 will operate intermittently. Therefore, the technical solution of this example can save the power consumption of the comparator 12 during V_int ≥ Vref.

[0068] In one example, please refer to Figure 4, the power supply system 13 has a power switch transistor Power mos. The gate of the power switch transistor Power mos is coupled to the output terminal of the comparator 12. The drain of the power switch transistor Power mos outputs an internal power supply voltage V_int, and the source is coupled to the corresponding power supply vdd. When the comparator 12 compares that V_int < Vref, the enable signal EN4 output by the comparator 12 is valid, and the power switch transistor Power mos will be turned on, and the power supply vdd charges V_int.

[0069] In one example, please refer to Figure 5 , the power supply system 13 includes a linear voltage regulator LDO. The enable terminal of the linear voltage regulator LDO is coupled to the output terminal of the comparator 12. The output terminal of the linear voltage regulator LDO outputs an internal power supply voltage V_int. When the comparator 12 compares that V_int < Vref, the enable signal EN4 output by the comparator 12 is valid, and the linear voltage regulator LDO will be enabled to work, and the linear voltage regulator LDO charges V_int.

[0070] In one example, please refer to Figure 6 , the power supply system 13 includes a DC converter (i.e., Figure 6 the "DC-DC converter" in). The control terminal of the DC converter is coupled to the output terminal of the comparator 12. The output terminal of the DC converter outputs an internal power supply voltage V_int. When the comparator 12 compares that V_int < Vref, the enable signal EN4 output by the comparator 12 is valid, and the DC converter will be enabled to work, and the DC converter charges V_int.

[0071] In one example, please refer to Figure 7 , the power supply system 13 includes a charge pump. The control terminal of the charge pump is coupled to the output terminal of the comparator 12. The output terminal of the charge pump outputs an internal power supply voltage V_int. When the comparator 12 compares that V_int < Vref, the enable signal EN4 output by the comparator 12 is valid, and the charge pump will be enabled to work, and the charge pump charges V_int.

[0072] In one example, please refer to Figure 8 , the dynamic latch 14 includes a first input transistor N3, a second input transistor N4, and a pair of back-to-back cascaded inverters. The pair of back-to-back cascaded inverters includes PMOS transistors P1, P2 and NMOS transistors N1, N2.

[0073] In this back-to-back cascaded inverter, P1 and N1 constitute one inverter, and P2 and N2 constitute the other inverter. The drains of P1 and N1, the gates of P2 and N2, and the source of N3 are coupled together to form output node a of the back-to-back cascaded inverter. The drains of P2 and N2, the gates of P1 and N1, and the source of N4 are coupled together to form output node b of the back-to-back cascaded inverter. The sources of P1 and P2 are coupled together, and the sources of N1 and N2 are coupled together. The drain of N3 is coupled to the reference voltage Vref, and the drain of N4 is coupled to the internal power supply voltage V_int. The gates of N3 and N4 are both coupled to the inverted signal ENB of the periodic enable signal EN.

[0074] Optionally, the dynamic latch 14 further includes at least one of the following (1) to (4):

[0075] (1) The tail tube N0 has its drain coupled to the source of N1 and the source of N2, the source of N0 is grounded, and the gate of N0 is coupled to the periodic enable signal EN.

[0076] (2) Switch P0, the drain of P0 is coupled to the source of P1 and the source of P2, the source of P0 is connected to the power supply vdd, and the gate of P0 is coupled to the inverted signal ENB of the periodic enable signal EN.

[0077] (3) First buffer buffer1, the input terminal of the first buffer buffer1 is coupled to the output node a of the back-to-back cascaded inverter, and the output terminal of the first buffer buffer1 is Out-. The first buffer buffer1 can buffer the signal of the output node a, reduce the internal offset of the dynamic latch 14, and improve the performance of the dynamic latch 14.

[0078] (4) The second buffer 2 is coupled to the output node b of the back-to-back cascaded inverter. The output terminal Out+ of the second buffer 2 is used to output the enable signal EN3 and is coupled to the enable terminal of the comparator 12. The second buffer 2 can buffer the signal of the output node b, reduce the internal offset of the dynamic latch 14, and improve the performance of the dynamic latch 14.

[0079] The first buffer (buffer1) and the second buffer (buffer2) can be implemented using any suitable circuit design. For example, please refer to... Figure 9The second buffer 2 includes a zero-th inverter INV0 and an OR gate OR0. The input of the zero-th inverter INV0 is coupled to a periodic enable signal EN. The output of the zero-th inverter INV0 is coupled to the first input of the OR gate OR0. The second input of the OR gate OR0 is coupled to the output node b of the back-to-back cascaded inverters. The output of the OR gate OR0 is the output of the second buffer 2 and is coupled to the enable terminal of comparator 12.

[0080] In one example, please refer to Figure 10 The comparator 12 includes a tail current bias circuit 121, a differential input circuit 122, and a load circuit 123. The differential input circuit 122 is used to input and compare V_int and Vref. The tail current bias circuit 121 is coupled to the dynamic latch 14 and the differential input circuit 122, and provides a tail current to the differential input circuit 122 after the dynamic latch 14 is enabled. The load circuit 123 is coupled to the differential input circuit 122 and is used to convert and output the output of the differential input circuit 122. The tail current bias circuit 121, the differential input circuit 122, and the load circuit 123 can employ any suitable circuit design.

[0081] For example, the tail current bias circuit 121 includes tail current transistors T3 and T4 connected in series. The gate of tail current transistor T3 is coupled to the output of dynamic latch 14, the source of tail current transistor T3 is coupled to the drain of tail current transistor T4, and the drain of tail current transistor T3 is coupled to differential input circuit 122. Tail current transistor T3 is turned on or off under the control of the enable signal EN3 output by dynamic latch 14. The gate of tail current transistor T4 is coupled to the bias signal bias, and the source of tail current transistor T4 is grounded. When tail current transistor T3 is turned on, tail current transistor T4 converts the bias signal bias into tail current and provides it to differential input circuit 122. Both T3 and T4 can be NMOS.

[0082] For example, the differential input circuit 122 includes differential input transistors T1 and T2. Both T1 and T2 can be PMOS transistors. The gate of T1 is coupled to the reference voltage Vref. The gate of T2 is coupled to the output of the power supply system 13 to receive the internal power supply voltage V_int output by the power supply system 13. The drains of T1 and T2 are coupled to the drain of T3, and the sources of T1 and T2 are both coupled to the load circuit 123.

[0083] For example, the load circuit 123 includes cross-coupled transistors Q3 and Q4, a current mirror circuit, and a buffer 3. The current mirror circuit includes switching transistors Q1, Q2, Q6, Q5, and T5-T8. Q1-Q6 can all be PMOS, and T5-T8 can be NMOS. The gates of Q1, Q2, Q3, and Q4 are mutually coupled and connected to the differential input circuit 122 (e.g., the source of T1). The gates of Q6, Q5, Q4, and Q3 are mutually coupled and connected to the differential input circuit 122 (e.g., the source of T2). The sources of Q1-Q6 are all coupled to the power supply Vdd. The drain of Q1 is coupled to the drain and gate of T5 and the gate of T7. The source of T5 is coupled to the drain and gate of T6 and the gate of T8. The sources of T6 and T8 are both grounded. The drain of T8 is coupled to the source of T7. The drain of T7 is coupled to the drain of Q6 and the input of buffer3. The output of buffer3 is coupled to the control or enable terminal of power supply system 13.

[0084] Please refer to Figure 11 Another embodiment of the present invention also provides a power control circuit, which in Figure 2 Based on the illustrated embodiment, a further enable / disable logic circuit 15 is added. This enable / disable logic circuit 15 is coupled between the dynamic latch 14 and the comparator 12. When the internal power supply voltage V_int output by the power system 13 is lower than the reference voltage Vref, it delays the output of the dynamic latch 14 and provides it to the comparator 12 to delay enabling the comparator 12. After the power system 13 pulls the internal power supply voltage V_int high to be equal to or higher than the reference voltage Vref, it disables the comparator 12 according to the flipped output DISEN of the comparator 12 (which is a flipped EN4, indicating that the power is in place), so as to shut down the charging activity of V_int by the power system 13 and prepare for the next detection of V_int.

[0085] This enables the disabled logic circuit 15 to be implemented using any suitable circuit design.

[0086] Please refer to Figure 12 In one example, the enable / disable logic circuit 15 includes a first delay logic circuit 151 and a second delay logic circuit 152. In another example, the enable / disable logic circuit 15 includes a first delay logic circuit 151, a second delay logic circuit 152, a NAND logic circuit NAND0, and a flip-flop 153.

[0087] The input terminal of the first delay logic circuit 151 is coupled to the output terminal Out+ of the dynamic latch 14 to receive the enable signal EN3 and perform delay logic processing on the enable signal EN3 output by the dynamic latch 14.

[0088] The input terminal of the second delay logic circuit 152 is coupled to the output terminal of the comparator 12 to access the output DISEN of the comparator 12 (i.e., the inverted enable signal EN4 output by the comparator 12), and perform delay logic processing on the output DISEN of the comparator 12.

[0089] Among them, the delay time of the first delay logic circuit 151 for the output EN3 of the dynamic latch 14 is longer than the delay time of the second delay logic circuit 152 for the output DISEN of the comparator 12, thereby ensuring the establishment of the comparator 12 to avoid the problem that the comparator 12 may be accidentally turned off during the establishment of the comparator 12.

[0090] One input terminal of the NAND logic circuit NAND0 is coupled to the output terminal of the first delay logic circuit 151, and the other input terminal is coupled to the output terminal of the second delay logic circuit 152, and is used to perform NAND logic operation on the output of the first delay logic circuit 151 and the output of the second delay logic circuit 152.

[0091] One input terminal of the flip-flop 153 is coupled to the output terminal of the NAND logic circuit NAND0, and the other input terminal is coupled to the output terminal of the first delay logic circuit 151, and is used to enable or disable the comparator 12 according to the output of the NAND logic circuit NAND0 and the output of the first delay logic circuit 151.

[0092] Figure 13 It is a schematic diagram of the working timing of the power control circuit of this embodiment. Please refer to Figure 9 and Figure 12 and Figure 13 As shown in, the working timing of the power control circuit of this embodiment is specifically as follows:

[0093] When the enable signal EN changes from low to high, after the dynamic latch 14 is enabled by EN, it starts to detect whether V_int is less than Vref;

[0094] When the dynamic latch 14 detects that V_int < Vref, the EN3 output by the dynamic latch 14 changes from low to high;

[0095] The first delay logic circuit 151 delays EN3 by Delay1, and outputs the delayed enable signal EN3' through the NAND logic circuit NAND0 and the flip-flop 153;

[0096] The comparator 12 is enabled when EN3' changes from low to high (i.e., enabled by the rising edge of EN3'), and outputs a valid enable signal EN4 to enable the power supply system 13 to charge V_int;

[0097] After V_int reaches the target potential (which can be any suitable value greater than or equal to Vref, and at this time the power supply system 13 charges V_int to the appropriate level), the output EN4 of the comparator 12 will flip (at this time, the output EN4 of the comparator 12 is denoted as DISEN);

[0098] The second delay logic circuit 152 delays this DISEN (i.e., the flipped EN4) by Delay2 (where Delay2 < Delay1), and provides it to the input terminal of the comparator 12 through the NAND logic circuit NAND0 and the flip-flop 153, causing EN3' to be pulled low (i.e., from high to low), thereby disabling the comparator 12.

[0099] Among them, the first delay logic circuit 151, the second delay logic circuit 152, the NAND logic circuit NAND0, and the flip-flop 153 can all adopt any suitable specific circuit design.

[0100] As an example, please refer to Figure 12 , the first delay logic circuit 151 includes a first inverter INV1, a second inverter INV2, a first NAND gate NAND1, and a first delay circuit (for the sake of easy understanding, it is marked with its delay Delay1). The input terminal of the first inverter INV1 is coupled to the output terminal Out+ of the dynamic latch 14. The output terminal of the first inverter INV1 is coupled to the input terminal of the second inverter INV2 and the input terminal of the first delay circuit Delay1. The output terminal of the second inverter INV2 is coupled to the first input terminal of the first NAND gate NAND1. The output terminal of the first delay circuit Delay1 is coupled to the second input terminal of the first NAND gate NAND1. The output terminal of the first NAND gate NAND1 is coupled to the first input terminal of the NAND logic circuit NAND0.

[0101] As an example, please refer to Figure 12 , the second delay logic circuit 152 includes a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a second NAND gate NAND2, and a second delay circuit (for the sake of easy understanding, it is marked with its delay Delay2). The input terminal of the third inverter INV3 is coupled to the output terminal of the comparator 12. The output terminal of the third inverter INV3 is coupled to the input terminal of the fourth inverter INV4 and the input terminal of the second delay circuit Delay2. The output terminal of the fourth inverter INV4 is coupled to the first input terminal of the second NAND gate NAND2. The output terminal of the second delay circuit Delay2 is coupled to the second input terminal of the second NAND gate NAND2. The output terminal of the second NAND gate NAND2 is coupled to the input terminal of the fifth inverter INV5. The output terminal of the fifth inverter INV5 is coupled to the second input terminal of the NAND logic circuit NAND0.

[0102] As an example, please refer to Figure 12 The flip-flop 153 includes a third NAND gate NAND3 and a fourth NAND gate NAND4. The first input of the third NAND gate NAND3 is coupled to the output of the NAND logic circuit NAND0. The second input of the third NAND gate NAND3 is coupled to the output of the fourth NAND gate NAND4 and the enable terminal of the comparator 12. The output of the third NAND gate NAND3 is coupled to the first input of the fourth NAND gate NAND4. The second input of the fourth NAND gate NAND4 is coupled to the output of the first delay logic circuit 151.

[0103] In one example, EN3' can be further provided to the reset terminal of dynamic latch 14. When EN3' goes from high to low, dynamic latch 14 can be reset by the falling edge of EN3', preparing for the next detection of V_int.

[0104] In another example, a corresponding OR logic circuit (not shown) can be added between the pulse generator 11 and the dynamic latch 14. The DISEN (i.e., the toggled EN4) is coupled to one input of the OR logic circuit, the EN output of the pulse generator 11 is coupled to the other input, and the output of the OR logic circuit is coupled to the dynamic latch 14. This further provides the DISEN (i.e., the toggled EN4) to the dynamic latch 14. When the power system 13 is fully charged (i.e., EN4 changes from high to low), the dynamic latch 14 is reset via the toggled EN4 (i.e., DISEN), preparing for the next detection of V_int. In this example, the falling edge of EN3' can be aligned with the reset time of the dynamic latch 14.

[0105] It should be understood that the dynamic latch 14 can also be reset in any other suitable manner, and the present invention does not specifically limit this.

[0106] The power control circuit of this invention can be applied to chips inside any suitable electronic device such as mobile phones, smart voice devices, GPS receivers, and wearable devices to reduce their power consumption.

[0107] Based on this, please refer to Figure 14 An embodiment of the present invention also provides a chip, which includes a power supply system 13, a power supply circuit 2 coupled to the output terminal of the power supply system 13, and a power control circuit 1 as described in the present invention (which can employ...). Figure 2 or Figure 11The illustrated embodiment architecture design shows that when the chip receives the corresponding low-power entry instruction Standby, the chip will enter a low-power mode. Some or all of the devices in the power-consuming circuit 2 (which may include the chip's internal control logic) inside the chip will enter a silent state (i.e., a state with very low power consumption) and generate a low-power mode signal PDEN, causing the power system 13 to enter an intermittent working mode.

[0108] Optionally, the chip is a PSRAM (Pseudo Static Random Access Memory) chip, a DRAM (Dynamic Random Access Memory) chip, or a Flash memory chip, etc. When the memory chip receives a low-power entry command Standby (such as a half-sleep mode entry command, hybrid sleep entry command, deep power-down (DPD) entry command, etc., which can be sent to the memory chip by the corresponding memory control module), after the read and write operations are completed, it will enter a low-power (Standby) mode according to the low-power entry command, and put most of its internal circuits (such as power circuit 2) into a silent state to reduce unnecessary power consumption and increase the usage time of electronic devices using the memory chip. The low-power mode can be the half-sleep mode of the memory chip (a low-power mode in which part of the power is turned off), or it can be the hybrid sleep mode, or it can be the deep power down mode (which consumes less power than the half-sleep mode). When most of the circuits of the memory chip (such as the power circuit 2) enter the low-power mode, the low-power mode signal PDEN is enabled to the power system 13.

[0109] In summary, the power control circuit of this invention adds a dynamic latch before the comparator. Utilizing the fact that the power consumption of the dynamic latch (in the nA range) is much lower than that of the comparator (in the μA range), it quickly detects the magnitude of the internal power supply voltage output by the power system. Based on the detection result, it enables or disables the comparator, especially when the internal power supply voltage is relatively high, preventing the comparator from turning on, thereby further reducing power consumption. The method is simple and easy to implement. Because the chip of this invention uses the power control circuit of this invention, it can achieve even lower standby power consumption.

[0110] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A power control circuit for providing an internal power supply voltage to a chip, characterized by The power consumption of the comparator in operation is greater than the power consumption of the dynamic latch in operation, and The dynamic latch is coupled to a corresponding power supply system and is periodically enabled after the chip enters a low power consumption mode and the power supply system enters a discontinuous operation mode, and detects whether the internal power supply voltage output by the power supply system is lower than a corresponding reference voltage after being enabled, and if so, enables the comparator, and if not, disables the comparator; The comparator is used to compare the sizes of the internal power supply voltage and the reference voltage after being enabled, to enable the power supply system to work when the internal power supply voltage is lower than the reference voltage, until the power supply system pulls up the internal power supply voltage to be equal to or higher than the reference voltage.

2. The power control circuit of claim 1, wherein, The power control circuit further includes a disable logic circuit coupled between the dynamic latch and the comparator, and is used to provide the output of the dynamic latch to the comparator after being delayed when the internal power supply voltage is lower than the reference voltage, to delay the enablement of the comparator, and after the power supply system pulls up the internal power supply voltage to be equal to or higher than the reference voltage, the disable logic circuit disables the comparator and / or resets the dynamic latch according to the output of the comparator that occurs.

3. The power control circuit of claim 2, wherein, The disable logic circuit includes: A first delay logic circuit, the input end of which is coupled to the output end of the dynamic latch, and is used to perform delay logic processing on the output of the dynamic latch; A second delay logic circuit, the input end of which is coupled to the output end of the comparator, and is used to perform delay logic processing on the output of the comparator; The delay time of the first delay logic circuit on the output of the dynamic latch is longer than the delay time of the second delay logic circuit on the output of the comparator.

4. The power control circuit of claim 3, wherein, The disable logic circuit further includes: A NAND logic circuit, one input end of which is coupled to the output end of the first delay logic circuit, and the other input end of which is coupled to the output end of the second delay logic circuit, and is used to perform NAND logic operation on the output of the first delay logic circuit and the output of the second delay logic circuit; A flip-flop, one input end of which is coupled to the output end of the NAND logic circuit, and the other input end of which is coupled to the output end of the first delay logic circuit, and is used to enable or disable the comparator according to the output of the NAND logic circuit and the output of the first delay logic circuit.

5. The power control circuit of claim 4, wherein, The first delay logic circuit includes a first inverter, a second inverter, a first NAND gate and a first delay circuit, the input end of the first inverter is coupled to the output end of the dynamic latch, the output end of the first inverter is coupled to the input end of the second inverter and the input end of the first delay circuit, the output end of the second inverter is coupled to the first input end of the first NAND gate, the output end of the first delay circuit is coupled to the second input end of the first NAND gate, and the output end of the first NAND gate is coupled to the first input end of the NAND logic circuit. And / or, the second delay logic circuit comprises a third inverter, a fourth inverter, a fifth inverter, a second NAND gate and a second delay circuit, the input end of the third inverter is coupled to the output end of the comparator, the output end of the third inverter is coupled to the input end of the fourth inverter and the input end of the second delay circuit, the output end of the fourth inverter is coupled to the first input end of the second NAND gate, the output end of the second delay circuit is coupled to the second input end of the second NAND gate, the output end of the second NAND gate is coupled to the input end of the fifth inverter, and the output end of the fifth inverter is coupled to the second input end of the non-logic circuit.

6. The power control circuit of claim 1, wherein, The dynamic latch comprises a first input tube, a second input tube and a pair of back-to-back cascade inverters, the drain of the first input tube is coupled to the reference voltage, the drain of the second input tube is coupled to the internal power supply voltage, the gate of the first input tube and the gate of the second input tube are both coupled to the inverted signal of the corresponding periodic enable signal, and the source of the first input tube and the source of the second input tube are both coupled to the back-to-back cascade inverters.

7. The power control circuit of claim 6, wherein, The dynamic latch further comprises at least one of the following (1)~(4): (1) a tail current tube, the drain of the tail current tube is coupled to the back-to-back cascade inverters, the source of the tail current tube is grounded, and the gate of the tail current tube is coupled to the periodic enable signal; (2) a switch tube, the drain of the switch tube is coupled to the back-to-back cascade inverters, the source of the switch tube is coupled to the power supply, and the gate of the switch tube is coupled to the inverted signal of the periodic enable signal; (3) a first buffer, the input end of the first buffer is coupled to the back-to-back cascade inverters and the source of the first input tube; (4) a second buffer, the input end of the second buffer is coupled to the back-to-back cascade inverters and the source of the second input tube, and the output end of the second buffer is coupled to the enable end of the comparator.

8. The power control circuit of claim 7, wherein, The second buffer comprises a zeroth inverter and an OR gate, the input end of the zeroth inverter is coupled to the periodic enable signal, the output end of the zeroth inverter is coupled to the first input end of the OR gate, the second input end of the OR gate is coupled to the back-to-back cascade inverters, and the output end of the OR gate is coupled to the comparator.

9. The power control circuit of claim 1, wherein, The power supply system has a power switch tube, the gate of the power switch tube is coupled to the output end of the comparator, and the drain of the power switch tube outputs or is coupled to the internal power supply voltage; Or, the power supply system comprises a linear voltage regulator, the enable end of the linear voltage regulator is coupled to the output end of the comparator, and the output end of the linear voltage regulator outputs or is coupled to the internal power supply voltage; Or, the power supply system comprises a charge pump, the control end of the charge pump is coupled to the output end of the comparator, and the output end of the charge pump is coupled to or outputs the internal power supply voltage; Or, the power supply system comprises a DC converter, the control end of the DC converter is coupled to the output end of the comparator, and the output end of the DC converter is coupled to or outputs the internal power supply voltage.

10. The power control circuit of any one of claims 1-9, wherein, The power supply control circuit further comprises a pulse generator coupled to the dynamic latch and configured to generate a periodic enable signal to periodically enable the dynamic latch.

11. The power control circuit of claim 10, wherein, The power supply control circuit further comprises an oscillator coupled to the pulse generator and configured to provide a corresponding frequency signal to the pulse generator; the pulse generator is configured to count the frequency signal and generate a pulse and restart counting each time the count reaches a set value to generate the periodic enable signal.

12. The power control circuit of claim 11, wherein, The pulse generator and the oscillator are enabled when the power supply system enters the intermittent operation mode.

13. A chip, characterized by The chip is a memory chip, and the low-power consumption mode is a semi-sleep mode, a deep sleep mode, or a hybrid sleep mode of the memory chip.

14. The chip of claim 13, wherein, The chip is a memory chip, and the low-power consumption mode is a semi-sleep mode, a deep sleep mode, or a hybrid sleep mode of the memory chip.

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