A bipolar half-bridge dc-dc converter with fault topology reconfiguration and a control method thereof

Abstract

The application discloses a bipolar half-bridge DC converter for fault topology reconfiguration and a control method thereof. T r Two input ends of an inverter circuit are connected with positive and negative poles of an input voltage respectively, two output ends of the inverter circuit are connected with two ends of a primary winding of a high-frequency transformer T r , and the two ends of the primary winding are connected with a first excitation inductor in parallel; same-named ends of a secondary winding of the high-frequency transformer L k are connected with a midpoint of a first bridge arm of a half-bridge three-level bipolar output circuit through a leakage inductor T r , and different-named ends of the secondary winding are connected with a midpoint of a second bridge arm of the half-bridge three-level bipolar output circuit through a clamping capacitor C s , and two ends of the secondary winding are connected with a second excitation inductor in parallel. The application can realize bidirectional power flow and improve power supply reliability without increasing the number of switch tubes.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of bipolar DC converters, and more particularly relates to a bipolar half-bridge DC converter with fault topology reconfiguration and a control method thereof. BACKGROUND

[0002] In a bipolar DC distribution network, the two common fault types are open-circuit fault or short-circuit fault of one pole of the bipolar port. Among them, the single-pole open-circuit fault, i.e. the unbalanced power of the port, can be solved by appropriate voltage balancing measures. However, how to continue to ensure the stable operation of the other pole port under single-pole short-circuit fault is an important research point. At present, the traditional method to isolate single-pole short-circuit fault is to use a DC circuit breaker, and two diodes are connected in parallel with the bipolar DC bus to prevent the reverse charging of the DC bus capacitor by the line inductance during short-circuit fault. This scheme requires additional circuit, which increases the total cost of the system and reduces the power density of the system. Therefore, researchers try to integrate the single-pole short-circuit fault isolation function into the bipolar DC converter itself. The structures of various bipolar DC converters suitable for low-voltage DC distribution networks can be mainly divided into two types: independent type and multiplex type. The independent type of positive and negative pole ports has an inherent advantage in dealing with single-pole short-circuit fault, as the outputs of the positive and negative pole ports can be independently controlled, and the pulse blocking protection method can be used for the switch tube of the fault port to isolate the single-pole short-circuit fault. However, the existing independent type of positive and negative pole ports has a large number of switch tube devices and high cost. Professor Zhu Miao's team from Shanghai Jiaotong University proposed a bipolar half-bridge DC converter to solve this problem (Ma J, Zhu M, Li Y, et al. Monopolar fault reconfiguration of bipolar half bridge converter for reliable load supply in dc distribution system [J]. IEEE Transactions on Power Electronics, 2022, 37(9): 11305-11318), but due to the use of diodes in the rectifier circuit, the problem of bidirectional power flow cannot be solved. SUMMARY

[0003] To solve the problems in the prior art, the application provides a bipolar half-bridge DC converter with fault topology reconfiguration and a control method thereof.

[0004] The application adopts the following technical solutions.

[0005] The bipolar half-bridge DC converter of the fault topology reconfiguration comprises an inverter circuit, a high-frequency transformer T r , a leakage inductor L k , a clamping capacitor C s and a half-bridge three-level bipolar output circuit, specifically:

[0006] The two input ends of the inverter circuit are connected with the positive and negative poles of the input voltage respectively, the two output ends of the inverter circuit are connected with the two ends of the primary winding of the high-frequency transformer T r , and the two ends of the primary winding are connected in parallel with the first excitation inductor; the same-named ends of the secondary winding of the high-frequency transformer T r are connected with the midpoint of the first bridge arm of the half-bridge three-level bipolar output circuit through the leakage inductor L k , and the different-named ends of the secondary winding of the high-frequency transformer T r are connected with the midpoint of the second bridge arm of the half-bridge three-level bipolar output circuit through the clamping capacitor C s , and the two ends of the secondary winding are connected in parallel with the second excitation inductor; the neutral line of the half-bridge three-level bipolar output circuit, one end of the first load and one end of the second load are connected, the positive output end of the half-bridge three-level bipolar output circuit is connected with the other end of the first load, and the negative output end is connected with the other end of the second load.

[0007] Preferably, the half-bridge three-level bipolar output circuit is composed of a fifth switch tube Q 5, a sixth switch tube Q 6, a seventh switch tube Q 7 and an eighth switch tube Q 8 connected in series. Q 5 and the sixth switch tube Q 6 constitute the first bridge arm, the sixth switch tube Q 6 and the seventh switch tube Q 7 constitute the second bridge arm, the drain of the fifth switch tube Q 5 is the positive output end of the half-bridge three-level bipolar output circuit, and the drain of the eighth switch tube Q 5 is the negative output end of the half-bridge three-level bipolar output circuit.

[0008] Preferably, the bipolar half-bridge DC converter further comprises an input capacitor C in , a first output capacitor C o1 and a second output capacitor Co2 input capacitor C in first output capacitor C o1 second output capacitor R o1 C o2 R o2

[0009] Preferably, the inverter circuit is a full-bridge circuit, which consists of a leading bridge arm and a lagging bridge arm, the leading bridge arm consists of a first switch tube Q 1 and a second switch tube Q 2 connected in series, the connecting point of the two switch tubes is connected to the same terminal of the primary winding of the high-frequency transformer T r as an output terminal of the full-bridge circuit.

[0010] The lagging bridge arm consists of a third switch tube Q 3 and a fourth switch tube Q 4 connected in series, the connecting point of the two switch tubes is connected to the opposite terminal of the primary winding of the high-frequency transformer T r as another output terminal of the full-bridge circuit.

[0011] Preferably, the clamping capacitor C s 、 input capacitor C in first output capacitor C o1 and second output capacitor C o2 are all leakage inductance L k is the turns ratio of the high-frequency transformer is 2, and the switching frequency of all switch tubes is 10 kHz.

[0012] The second aspect of the present application provides a control method of a bipolar half-bridge DC converter applied to the fault topology reconfiguration of the first aspect of the present application, comprising:

[0013] controlling the full-bridge circuit to operate under fixed phase shift and fixed duty cycle;

[0014] When no fault occurs, all switch tubes operate normally, the duty cycle of the fifth switch tube Q 5 is d , and the duty cycle of the sixth switch tube Q ​​​6, seventh switch tube Q 7, eighth switch tube Q 8, duty cycle of 1- d , 0.5+ d , 0.5- d , fifth switch tube Q 5 and sixth switch tube Q 6, a dead zone is set between the two t d , and the phase shift time of the two is (0.5- dT s , wherein T s is the switching period of all switch tubes; seventh switch tube Q 7 and eighth switch tube Q 8, a dead zone is set between the two t d , and the phase shift time of the two is (0.5+ d ) T s ; the length of time that the drive of the fifth switch tube Q 5 lags behind the drive of the first switch tube Q 1 is φT s ; the length of time that the drive of the seventh switch tube Q 7 lags behind the drive of the second switch tube Q 2 is also φT s , φ is the phase shift ratio, the bipolar port voltage balance control is performed by adjusting the duty cycle d , and the voltage regulation control is performed by adjusting φT s ;

[0015] When a unipolar short circuit fault occurs, the switch tube directly connected in series with the output end corresponding to the fault side is locked, and the duty cycle and the phase shift time of the switch tube directly connected in series with the switch tube that is locked are adjusted.

[0016] Preferably, the bipolar port voltage balance control is performed by adjusting the duty cycle d , and the voltage regulation control is performed by adjusting φT s ;

[0017] The bipolar port voltage balance control is to sample the difference between the output voltages of the positive output end and the negative output end of the half-bridge three-level bipolar output circuit, and to close-loop control the duty cycle d so that the difference between the output voltages is 0;

[0018] The voltage regulation control is to sample the sum of the output voltages of the positive output end and the negative output end of the half-bridge three-level bipolar output circuit, and to close-loop control the phase shift ratio φ The sum of the output voltages is set to be the phase shift ratio value.

[0019] Preferably, the control full-bridge circuit operates at a fixed phase shift and a fixed duty cycle, in particular:

[0020] The first switch tube Q 1, Q 2, Q 3 and the fourth switch tube Q 4 have equal duty cycles and are constant values, the first switch tube Q 1 and the second switch tube Q 2 are provided with a dead zone t d and the phase shift time of both is 0.5 T s The third switch tube Q 3 and the fourth switch tube Q 4 are provided with a dead zone t d and the phase shift time of both is also 0.5 T s The first switch tube Q 1 and the fourth switch tube Q 4 have a phase shift time of 0, the second switch tube Q 2 and the third switch tube Q 3 have a phase shift time of 0.

[0021] Preferably, when a unipolar short circuit fault occurs, the switch tube directly connected in series with the corresponding output end on the fault side is controlled to be locked, and the duty cycle and the phase shift time of the switch tube directly connected in series with the switch tube of the lock are adjusted.

[0022] When a short circuit fault occurs in the positive output end of the half-bridge three-level bipolar output circuit, the duty cycle of the fifth switch tube Q 5 is 0, the duty cycle of the sixth switch tube Q 6 is 1; the duty cycle of the seventh switch tube Q 7 is 0.5+ d , the duty cycle of the eighth switch tube Q 8 is 0.5- d ; the seventh switch tube Q 7 and the eighth switch tube Q 8 are provided with a dead zone t d and the phase shift time of both is (0.5+ d ) T s ; control the phase shift ratioφ is 0, the seventh switch tube Q 7 and the second switch tube Q 2 is 0; and the duty cycle is closed-loop controlled by sampling the output voltage of the negative output end of the half-bridge three-level bipolar output circuit d to make the output voltage of the negative output end of the half-bridge three-level bipolar output circuit be a set negative port output voltage

[0023] when a short circuit fault occurs at the negative output end of the half-bridge three-level bipolar output circuit, the duty cycle of the fifth switch tube Q 5 is controlled to be d , the duty cycle of the sixth switch tube Q 6 is controlled to be 1- d , the duty cycle of the seventh switch tube Q 7 is controlled to be 1, and the duty cycle of the eighth switch tube Q 8 is controlled to be 0; and the phase shift ratio φ is controlled to be 0.5 Q , the phase shift time of the fifth switch tube Q 5 and the first switch tube T 1 is controlled to be 0.5 s . The phase shift time of the fifth switch tube Q 5 and the sixth switch tube Q 6 is controlled to be t d ; and the phase shift time of the fifth switch tube dT s ; the phase shift ratio φ is controlled to be 0.5 Q , the phase shift time of the fifth switch tube Q 5 and the first switch tube T 1 is controlled to be 0.5 s ; the duty cycle is closed-loop controlled by sampling the output voltage of the negative output end of the half-bridge three-level bipolar output circuit d to make the output voltage of the negative output end of the half-bridge three-level bipolar output circuit be a set negative port output voltage.

[0024] Compared with the prior art, the present application has the following advantages: 1. The half-bridge three-level bipolar output circuit of the present application includes four switch tubes, which avoids increasing the number of switch tubes while realizing bidirectional power flow. 2. The control method of the half-bridge three-level bipolar output circuit of the present application realizes output port voltage balancing under normal working conditions and topology reconstruction under single-pole short circuit fault conditions, thereby improving power supply reliability. 3. The present application generates a phase shift between the full-bridge circuit and the half-bridge three-level bipolar output circuit, and realizes closed-loop control of the bipolar port output total voltage by controlling the phase shift ratio, thereby having a voltage regulation function. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 This is a circuit diagram of the converter of the present invention;

[0026] Figure 2 The waveforms of the primary voltage and current under fault-free conditions are shown.

[0027] Figure 3 The waveforms of the two loads under asymmetrical load conditions when no faults occur;

[0028] Figure 4 The waveforms of the drive signals of each switch transistor in the converter when no fault occurs;

[0029] Figure 5 These are the two load voltage waveforms when a short circuit fault occurs at the positive output terminal.

[0030] Figure 6 This is a waveform diagram of the drive signals of each switch in the converter when a short circuit fault occurs at the positive output terminal. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0032] The present invention adopts the following technical solution.

[0033] like Figure 1 As shown, Embodiment 1 of the present invention proposes a bipolar half-bridge DC-DC converter for fault topology reconfiguration, including an inverter circuit and a high-frequency transformer. T r Leakage L k Clamping capacitors C s The half-bridge three-level bipolar output circuit is as follows:

[0034] The two input terminals of the inverter circuit are connected to the positive and negative terminals of the input voltage, respectively, and the two output terminals of the inverter circuit are connected to the high-frequency transformer, respectively. T r The two ends of the primary winding are connected, and the two ends of the primary winding are connected in parallel with the first magnetizing inductor; high-frequency transformer T r The secondary winding's corresponding terminal passes through leakage inductance. L k It is then connected to the midpoint of the first bridge arm of the half-bridge three-level bipolar output circuit, and the high-frequency transformer. Tr The opposite end of the secondary winding is connected to the clamping capacitor C s The midpoint of the second bridge arm of the half-bridge three-level bipolar output circuit is connected to the output end of the auxiliary winding, and the two ends of the auxiliary winding are connected in parallel with the second excitation inductor; the neutral line of the half-bridge three-level bipolar output circuit, one end of the first load and one end of the second load are all connected, the positive output end of the half-bridge three-level bipolar output circuit is connected to the other end of the first load, and the negative output end is connected to the other end of the second load.

[0035] In this embodiment, the half-bridge three-level bipolar output circuit is preferably composed of a fifth switch tube Q 5, a sixth switch tube Q 6, a seventh switch tube Q 7 and an eighth switch tube Q 8 connected in series. Q 5 and the sixth switch tube Q 6 constitute a first bridge arm, the sixth switch tube Q 6 and the seventh switch tube Q 7 constitute a second bridge arm, the drain of the fifth switch tube Q 5 serves as the positive output end of the half-bridge three-level bipolar output circuit, and the drain of the eighth switch tube Q 5 serves as the negative output end of the half-bridge three-level bipolar output circuit.

[0036] In this embodiment, the bipolar half-bridge direct current converter further comprises an input capacitor C in , a first output capacitor C o1 and a second output capacitor C o2 The input capacitor C in is connected between the two input ends of the full-bridge circuit, the first output capacitor C o1 is connected between the two ends of the first load R o1 , and the second output capacitor C o2 is connected between the two ends of the second load R o2 .

[0037] In this embodiment, the inverter circuit is a full-bridge circuit composed of a leading bridge arm and a lagging bridge arm, the leading bridge arm is composed of a first switch tube Q 1 and a second switch tube Q 2 connected in series, and the connection point of the two switch tubes serves as an output end of the full-bridge circuit and is connected to the high-frequency transformer Tr the same name end of the primary winding of the high-frequency transformer

[0038] The lagging bridge arm is composed of the third switch tube Q 3 and the fourth switch tube Q 4 in series, and the connection point of the two switch tubes is connected to the other output end of the full-bridge circuit and the primary winding of the high-frequency transformer T r the different name end of the primary winding of the high-frequency transformer

[0039] In this embodiment, the input voltage is 150V, the output voltage to the two loads is ±375V, the maximum output power is 12.5kW, the clamping capacitance C s 、 the input capacitance C in , the first output capacitance C o1 and the second output capacitance C o2 are all , the leakage inductance L k is , the transformation ratio of the high-frequency transformer is 2, and the switching frequency of all the switch tubes is 10kHz.

[0040] Embodiment 2 of the present application provides a control method of a bipolar half-bridge DC converter based on the fault topology reconstruction of embodiment 1 of the present application, comprising:

[0041] controlling the full-bridge circuit to operate under fixed phase shift and fixed duty cycle;

[0042] In this embodiment, the control of the full-bridge circuit operating under fixed phase shift and fixed duty cycle is specifically as follows:

[0043] the duty cycles of the first switch tube Q 1, the second switch tube Q 2, the third switch tube Q 3 and the fourth switch tube Q 4 are equal and are a constant value, a dead zone is set between the first switch tube Q 1 and the second switch tube Q 2 t d , and the phase shift time of the two is 0.5 T s , a dead zone is set between the third switch tube Q 3 and the fourth switch tube Q 4 t d , and the phase shift time of the two is also 0.5 T s , a dead zone is set between the first switch tubeQ 1 and the fourth switch tube Q 4 whose phase shift time is 0, the second switch tube Q 2 and the third switch tube Q 3 whose phase shift time is 0.

[0044] When no fault occurs, all the switch tubes operate normally, the fifth switch tube Q 5 whose duty ratio is d , the sixth switch tube Q 6, the seventh switch tube Q 7 and the eighth switch tube Q 8 whose duty ratios are respectively 1- d , 0.5+ d , 0.5- d ; the fifth switch tube Q 5 and the sixth switch tube Q 6 are provided with a dead zone t d and the phase shift time of the two is dT s , wherein T s is the switching period of all the switch tubes; the seventh switch tube Q 7 and the eighth switch tube Q 8 are provided with a dead zone t d and the phase shift time of the two is (0.5+ d ) T s ; the driving of the fifth switch tube Q 5 lags behind the driving of the first switch tube Q 1 by a time length of φT s ; the driving of the seventh switch tube Q 7 lags behind the driving of the second switch tube Q 2 by a time length of φT s , φ is the phase shift ratio, the bipolar port voltage balance control is performed by adjusting the duty ratio d , and the voltage regulation control is performed by adjusting φT s ;

[0045] Preferably, the bipolar port voltage balance control is performed by adjusting the duty ratio d , the voltage regulation control is performed by adjusting φT s , and specifically, the bipolar port voltage balance control is performed by adjusting the duty ratio of the first switch tube 1 and the fourth switch tube

[0046] The bipolar port voltage equalization control is to sample the difference between the output voltages of the positive output end and the negative output end of the half-bridge three-level bipolar output circuit, and to close-loop control the duty cycle d The difference between the output voltages is 0.

[0047] The voltage regulation control is to sample the sum of the output voltages of the positive output end and the negative output end of the half-bridge three-level bipolar output circuit, and to close-loop control the phase shift ratio φ The sum of the output voltages is set to be the phase shift ratio value.

[0048] It should be noted that when the first load R o1 and the second load R o2 are equal, the time length for which the secondary winding of the high-frequency transformer T r supplies power to the first load R o1 is dT s and the time length for which the secondary winding of the high-frequency transformer R o2 supplies power to the second load d T s When the first load R o1 is greater than the second load R o2 , the time length for which the secondary winding of the high-frequency transformer T r supplies power to R o1 is reduced, and the time length for which the secondary winding of the high-frequency transformer T r supplies power to the load R o2 is increased; when the first load R o1 is less than the second load R o2 , the time length for which the secondary winding of the high-frequency transformer T r supplies power to R o1 is increased, and the time length for which the secondary winding of the high-frequency transformer T r supplies power to the load R o2 is reduced.

[0049] When a unipolar short-circuit fault occurs, the switch tube directly connected in series with the output end on the fault side is locked, and the duty cycle and the phase shift time of the switch tube directly connected in series with the switch tube are adjusted. ​

[0050] Specifically, the first switching transistor Q 1. Second switching transistor Q 2. Third switching transistor Q 3 and the fourth switching transistor Q The duty cycle of 4 is set to 0.5.

[0051] In this preferred embodiment, when a unipolar short-circuit fault occurs, the switch directly connected in series with the output terminal corresponding to the fault side is locked out, and the duty cycle and phase shift time of the switch directly connected in series with the locked-out switch are adjusted accordingly. Specifically:

[0052] When a short circuit fault occurs at the positive output terminal, the fifth switching transistor is controlled. Q The duty cycle of switch 5 is 0, and the sixth switch is active. Q The duty cycle of switch 6 is 1, and the seventh switch is... Q 7 and second switching transistor Q The phase shift time of switch 2 becomes 0; the other switches remain unchanged, and the seventh switch... Q The duty cycle of 7 remains at 0.5+. d Eighth switch tube Q The duty cycle for 8 remains at 0.5- d The seventh switch Q 7 and 8 switch transistors Q 8. A dead zone is still set between the two. t d And the phase shift time of both is (0.5+ d ) T s Within one cycle, the high-frequency transformer T r The secondary winding supplies power to the second load. R o2 The power supply duration is (0.5+) d ) T s Second output capacitor C o2 To the second load R o2 The power supply duration is (0.5-d). T s .

[0053] When a short circuit fault occurs at the negative output terminal, the phase shift ratio is controlled. φ The value remains unchanged at 0.5, and the seventh switch is... Q The duty cycle of switch 7 is 1, and the eighth switch is... Q The duty cycle of switch 8 is 0; the fifth switch transistor Q 5 and the first switching transistor Q The phase shift time of switch 1 is 0; other switches remain unchanged, and the fifth switch... QThe duty cycle of 5 is still 5 d The sixth switch Q The duty cycle of 6 is still 1- d Fifth switch tube Q 5 and the sixth switching transistor Q 6. A dead zone is still set between the two. t d And the phase shift time of both dT s Within one cycle, the high-frequency transformer T r The secondary winding supplies power to the load. R o1 The duration of power supply is dT s Output capacitor C o1 The duration of power supply to the load is (1- d ) T s .

[0054] Simulations were performed based on the above parameters, and the simulation results are as follows: Figures 2 to 6 As shown. Figure 2 The figure shows the primary voltage and current when no fault occurs. Figure 3 Two load voltage waveforms under asymmetrical load conditions in a fault-free state are presented. It can be seen that the converter disclosed in this invention effectively achieves output port voltage balancing under asymmetrical load conditions through the aforementioned control method. The switching transistors of the converter in a fault-free state (…) Q 1 ~Q 8) The drive signal waveform is as follows Figure 4 As shown. Figure 5 Two load voltage waveforms are given when a short circuit fault occurs at the positive output terminal. Figure 6 The following are the conditions for a short circuit fault at the positive output terminal of the converter's switching transistors ( Q 1 ~Q From the drive signal waveform of 8), it can be seen that the fifth switch transistor is at this time. Q The duty cycle of switch 5 is 0, and the sixth switch is active. Q The duty cycle of switch 6 is 1, and the switch connected in series with the positive output terminal on the fault side is blocked; the seventh switch... Q The duty cycle of switch 7 is 0.5+d, and the eighth switch is... Q With the duty cycle of 8 open, the output terminal operates normally with power supplied. Within one cycle, the secondary winding supplies power to the second load. R o2 The power supply duration is (0.5+d). T s The second output capacitor C o2 To the second loadR o2 the length of time for which power is supplied is (0.5 - d) T s .

[0055] The disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0056] Finally, it should be noted that the above-mentioned embodiments are merely used to illustrate the technical solutions of the present application, rather than limit the present application. Although the present application has been described in detail with reference to the above-mentioned embodiments, it should be understood by those skilled in the art that the specific embodiments of the present application can be modified or equivalent replaced without departing from the spirit and scope of the present application, and any modification or equivalent replacement without departing from the spirit and scope of the present application should be covered in the protection scope of the claims of the present application.

Claims

1. A bipolar half-bridge DC-DC converter for fault topology reconfiguration, comprising an inverter circuit and a high-frequency transformer. T r Leakage L k Clamping capacitors C s The half-bridge three-level bipolar output circuit is characterized by: The two input terminals of the inverter circuit are connected to the positive and negative terminals of the input voltage, respectively, and the two output terminals of the inverter circuit are connected to the high-frequency transformer, respectively. T r The two ends of the primary winding are connected, and the two ends of the primary winding are connected in parallel with the first magnetizing inductor; high-frequency transformer T r The secondary winding's corresponding terminal passes through leakage inductance. L k It is then connected to the midpoint of the first bridge arm of the half-bridge three-level bipolar output circuit, and the high-frequency transformer. T r The opposite terminals of the secondary winding are connected via clamping capacitors. C s It is then connected to the midpoint of the second bridge arm of the half-bridge three-level bipolar output circuit, and the two ends of the secondary winding are connected in parallel with the second magnetizing inductor; the neutral line of the half-bridge three-level bipolar output circuit, one end of the first load, and one end of the second load are all connected; the positive output terminal of the half-bridge three-level bipolar output circuit is connected to the other end of the first load, and the negative output terminal is connected to the other end of the second load. The half-bridge three-level bipolar output circuit consists of a fifth switching transistor. Q 5. Sixth switching transistor Q 6. Seventh switching transistor Q 7. Eighth switching transistor Q The 8 transistors are connected in series, with the fifth switch being the most important. Q 5 and the sixth switching transistor Q The first bridge arm consists of 6 components, and the sixth switch is... Q 6 and 7 switch transistors Q 7 form the second bridge arm, and the fifth switching transistor. Q The drain of transistor 5 serves as the positive output terminal of the half-bridge three-level bipolar output circuit, and the eighth switching transistor... Q The drain of 5 is used as the negative output terminal of the half-bridge three-level bipolar output circuit; When a unipolar short-circuit fault occurs, the switch directly connected in series with the output terminal corresponding to the fault side is blocked, and the duty cycle and phase shift time of the switch directly connected in series with the blocked switch are adjusted accordingly, specifically: When a short circuit fault occurs at the positive output terminal of the half-bridge three-level bipolar output circuit, the fifth switching transistor is controlled. Q The duty cycle of switch 5 is 0, and the sixth switch is active. Q The duty cycle of switch 6 is 1; the seventh switch transistor Q The duty cycle of 7 is 0.5+ d Eighth switch tube Q The duty cycle of 8 is 0.5- d ; Seventh switch Q 7 and 8 switch transistors Q 8. Set a dead zone between the two. t d And the phase shift time of both is (0.5+ d ) T s Controlling the phase shift ratio φ The value remains unchanged at 0; the seventh switch transistor... Q 7 and second switching transistor Q The phase shift time of 2 is 0; and the duty cycle is controlled by sampling the output voltage at the negative output terminal of the half-bridge three-level bipolar output circuit. d Make the output voltage of the negative output terminal of the half-bridge three-level bipolar output circuit the set negative port output voltage; When a short circuit fault occurs at the negative output terminal of the half-bridge three-level bipolar output circuit, the fifth switching transistor is controlled. Q The duty cycle of 5 is d The sixth switch Q The duty cycle of 6 is 1- d ; Seventh switch Q The duty cycle of switch 7 is 1, and the eighth switch is... Q The duty cycle of 8 is 0; control phase shift ratio φ The value remains unchanged at 0.5, and the fifth switch transistor... Q 5 and the first switching transistor Q The phase shift time of 1 is 0.

5. T s Fifth switching transistor Q 5 and the sixth switching transistor Q 6. Set a dead zone between the two t d And the phase shift time of both is dT s Controlling the phase shift ratio φ The value remains unchanged at 0.5, and the fifth switch transistor... Q 5 and the first switching transistor Q The phase shift time of 1 is 0.

5. T s The duty cycle is controlled in a closed loop by sampling the output voltage at the negative output terminal of the half-bridge three-level bipolar output circuit. d Make the output voltage of the negative output terminal of the half-bridge three-level bipolar output circuit the set negative port output voltage.

2. The bipolar half-bridge DC-DC converter for fault topology reconfiguration according to claim 1, characterized in that: The bipolar half-bridge DC-DC converter also includes an input capacitor. C in First output capacitor C o1 Second output capacitor C o2 Input capacitor C in The first output capacitor is connected between the two input terminals of the full-bridge circuit. C o1 Connected to the first load R o1 Between the two ends, the second output capacitor C o2 Connected to the second load R o2 Between the two ends.

3. The bipolar half-bridge DC-DC converter for fault topology reconfiguration according to claim 1, characterized in that: The inverter circuit is a full-bridge circuit, consisting of a leading arm and a lagging arm. The leading arm is composed of a first switching transistor. Q 1 and second switching transistors Q The circuit consists of two series-connected transistors, and the connection point of these two transistors serves as one output terminal of the full-bridge circuit, connected to the high-frequency transformer. T r The primary windings are connected to the same-named terminals; The lagging bridge arm is controlled by the third switch. Q 3 and the fourth switching transistor Q The circuit consists of four series-connected transistors, with the connection point of the two switching transistors serving as the other output terminal of the full-bridge circuit, connected to the high-frequency transformer. T r The opposite terminals of the primary winding are connected.

4. A bipolar half-bridge DC-DC converter for fault topology reconfiguration according to claim 1, characterized in that: Clamping capacitor C s 、 Input capacitor C in First output capacitor C o1 Second output capacitor C o2 All Leakage L k for The high-frequency transformer has a turns ratio of 2, and all switching transistors have a switching frequency of 10kHz.

5. A control method for a bipolar half-bridge DC-DC converter applied to fault topology reconfiguration as described in claim 4, characterized in that, include: Control the full-bridge circuit to operate under fixed phase shift and fixed duty cycle; When no fault occurs, all switches operate normally, except for the fifth switch. Q The duty cycle of 5 is d The sixth switch Q 6. Seventh switching transistor Q 7. Eighth switching transistor Q The duty cycles of 8 are 1- d 0.5+ d 0.5- d Fifth switching transistor Q 5 and the sixth switching transistor Q 6. Set a dead zone between the two t d And the phase shift time of both is dT s ,in T s For the switching cycles of all switching transistors; seventh switching transistor Q 7 and 8 switch transistors Q 8. Set a dead zone between the two. t d And the phase shift time of both is (0.5+ d ) T s Fifth switching transistor Q The drive lags behind the first switching transistor by 5. Q The duration of the drive for 1 is φT s ; Seventh switch Q The drive lags behind the second switching transistor 7 Q The duration of the drive for 2 is also... φT s , φ To achieve phase shift ratio, the duty cycle is adjusted. d Perform bipolar port voltage equalization control by adjusting φT s Perform voltage regulation control; When a single-pole short-circuit fault occurs, the switch directly connected in series with the output terminal corresponding to the fault side is blocked, and the duty cycle and phase shift time of the switch directly connected in series with the blocked switch are adjusted accordingly.

6. The control method according to claim 5, characterized in that: The method of adjusting the duty cycle d Perform bipolar port voltage equalization control by adjusting φT s Voltage regulation control is performed, specifically as follows: The bipolar port voltage equalization control is achieved by sampling the difference between the positive and negative output voltages of the half-bridge three-level bipolar output circuit and then controlling the duty cycle in a closed loop. d Make the difference in output voltage zero; The voltage regulation control is achieved by sampling the sum of the output voltages at the positive and negative output terminals of the half-bridge three-level bipolar output circuit, and then using closed-loop control to adjust the phase shift ratio. φ Make the sum of the output voltages equal to the set phase shift ratio value.

7. The control method according to claim 5, characterized in that: The control full-bridge circuit operates under fixed phase shift and fixed duty cycle, specifically as follows: First switching transistor Q 1. Second switching transistor Q 2. Third switching transistor Q 3 and the fourth switching transistor Q The duty cycles of the four transistors are equal and constant, and the first switching transistor... Q 1 and second switching transistors Q 2. Set a dead zone between the two. t d Furthermore, the phase shift time for both is 0.5 seconds. T s Third switching transistor Q 3 and the fourth switching transistor Q 4. Set a dead zone between the two t d Furthermore, the phase shift time for both is 0.

5. T s First switching transistor Q 1 and the fourth switching transistor Q 4. Phase shift time is 0, second switching transistor Q 2 and the third switching transistor Q 3. The phase shift time is 0.

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