A resonator having an inductive charge-trapping defect structure and a method of fabrication

Abstract

The application discloses a resonator with an induced charge trapping defect structure and a preparation method, and particularly relates to the fields of third-generation semiconductor technology and radio frequency front-end device technology, wherein a multi-step cleaning is adopted to remove contamination and an oxide layer, a multi-layer defect gradient structure is deposited to control charge migration, a sacrifice layer is constructed to form a cavity foundation, a support layer is deposited to improve structural stability, a high-conductivity electrode and a high-quality piezoelectric layer are superposed, and a cavity structure is precisely etched and released; the application removes organic matter and oxidation residues through high-purity pretreatment, enhances the combination of a deposited layer and a substrate, constructs a multi-layer defect gradient silicon structure to inhibit induced charge migration, introduces a stable support layer to prevent structure collapse, deposits a high-conductivity and high-voltage composite layer to improve excitation efficiency and frequency response, cooperatively matches layer thickness and defect density to enhance energy conversion efficiency, and adopts a high-selectivity etching system to release a cavity, so that loss inhibition and quality factor improvement under high frequency are realized.

Description

Technical Field

[0001] This invention relates to the fields of third-generation semiconductor technology and radio frequency front-end device technology, and in particular to a resonator with an induced charge trapping defect structure and its fabrication method. Background Technology

[0002] With the extension of 5G mobile communication technology to higher frequency bands, the evolution of intelligent radar systems towards high-precision detection, and the large-scale deployment of IoT terminal devices, radio frequency (RF) front-end devices are facing unprecedented performance challenges. High-frequency signal transmission places almost stringent requirements on the energy conversion efficiency of devices. Maintaining high-frequency stability while effectively controlling energy loss has become a key bottleneck restricting the industry's development. Especially in emerging application scenarios such as millimeter-wave communication and vehicle-to-everything (V2X) sensing, devices need to simultaneously achieve low insertion loss, high power handling capacity, and excellent thermal stability in complex electromagnetic environments, which places higher-dimensional technical requirements on materials interface engineering.

[0003] Current mainstream thin-film bulk acoustic resonators exhibit significant physical limitations under high-frequency conditions, with the core issue being the interface defect effect between the piezoelectric layer and the substrate. Due to the inherent lattice mismatch between heterogeneous materials, the dislocation network formed during epitaxial growth becomes an active channel for parasitic charges. These defect states trigger multiple energy dissipation mechanisms under the influence of high-frequency alternating electric fields. More seriously, existing defect control techniques often fall into a performance trade-off: while using a buffer layer structure can improve interface quality, it introduces additional dielectric loss paths; surface passivation can suppress charge migration, but it leads to nonlinear degradation of the piezoelectric response. This technological paradox severely limits the feasibility of extending next-generation communication systems to higher frequency bands.

[0004] In existing technologies, substrate cleaning can easily leave residual contaminants that induce interface defects, uncontrolled charge migration paths, increased induced losses leading to insertion loss and Q-value deterioration, difficulty in controlling the thickness of support and sacrificial layers, easy damage to release cavity boundaries, poor electrode conductivity and insufficient piezoelectric response, severe high-frequency signal distortion, poor selectivity of etching schemes and high microstructure damage rate, affecting device consistency and packaging stability, significant frequency drift, increased energy loss, and shortened lifespan, limiting high-frequency applications. Summary of the Invention

[0005] The main objective of this invention is to provide a resonator with an induced charge trapping defect structure and a method for its fabrication, which can effectively solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A method for fabricating a resonator with an induced charge trapping defect structure, wherein the thin film is applied to an acoustic resonator or filter, includes the following steps:

[0008] S1. Substrate cleaning: Select a silicon wafer as the silicon substrate. First, use acetone to clean the silicon substrate to remove organic contaminants on the surface. Then, use isopropanol or deionized water to rinse. Next, use hydrofluoric acid solution to remove the natural oxide layer on the surface. After washing, rinse thoroughly with deionized water and dry with nitrogen.

[0009] S2. Deposition of multi-layer defect structures: Multi-layer defect structures are sequentially deposited on the silicon substrate after cleaning in step S1. The defect densities of the multi-layer defect structures are different, so that the defect densities of the multi-layer defect structures form a gradient distribution.

[0010] S3, Sacrificial layer deposition: Depositing a sacrificial layer on the surface of a multi-layer defect structure;

[0011] S4. Cavity etching release: Dry and wet etching methods are used to remove the sacrificial layer to form a cavity structure. The etching gas is a chlorine or fluorine halide.

[0012] S5. Support layer deposition: Deposit a support layer on the surface of the sacrificial layer;

[0013] S6. Electrode and piezoelectric material deposition: The bottom electrode, piezoelectric material layer and top electrode are deposited sequentially on the support layer.

[0014] Preferably, the multilayer defect structure comprises 3 to 5 silicon-based thin films, and the total thickness of the multilayer defect structure is 0.1 μm to 2 μm.

[0015] Preferably, in the defect structure, the first layer located near the silicon substrate has the lowest defect density, and the uppermost layer located near the device active region has the highest defect density, and the thickness of each defect structure is 50 nm to 300 nm.

[0016] Preferably, the support layer is used to prevent the structure above the cavity from collapsing due to external forces and stress, and the thickness of the support layer is 0.05μm to 3μm.

[0017] Preferably, the sacrificial layer is formed by low-temperature deposition, including LPCVD, PECVD and PVD deposition processes, and the thickness of the sacrificial layer is 0.5 μm to 4 μm.

[0018] Preferably, the etching method is gas phase HF dry etching and Cl2 / Ar plasma etching.

[0019] Preferably, the top electrode and bottom electrode are made of Mo, the piezoelectric material is AlN, the thickness of the bottom electrode and the top electrode is 0.05 μm to 0.5 μm, and the thickness of the piezoelectric material is 0.5 μm to 2 μm.

[0020] Preferably, the defect structure is formed by ion implantation, doping control, or polycrystalline or amorphous silicon deposition.

[0021] Preferably, the ions used for ion implantation of the defect structure are phosphorus, boron, and argon.

[0022] In addition, the present invention also provides a resonator with an induced charge trapping defect structure, comprising: a silicon substrate, a gradient defect structure layer, a support layer, a bottom electrode, an AlN piezoelectric layer and a top electrode arranged sequentially from bottom to top, wherein a cavity structure formed between the support layer and the gradient defect structure layer by etching a sacrificial layer is formed, and the gradient defect structure layer comprises 3-5 silicon-based thin films with a gradient defect density distribution.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] In this invention, high-purity pretreatment is used to remove organic matter and oxidation residues, enhancing the bonding between the deposited layer and the substrate. A multi-layer defect gradient silicon structure is constructed to suppress induced charge migration. A stable support layer is introduced to prevent structural collapse. A composite layer of high conductivity and high voltage is deposited to improve excitation efficiency and frequency response. The layer thickness and defect density are synergistically matched to enhance energy conversion efficiency. A highly selective etching system is used to release cavities, ensuring boundary integrity and tension balance, thereby achieving loss suppression and quality factor improvement at high frequencies. Attached Figure Description

[0025] Figure 1 This is a flowchart illustrating the preparation process of the present invention;

[0026] Figure 2 This is a flowchart of the substrate cleaning process of the present invention;

[0027] Figure 3 This is a flowchart of the multilayer defect structure deposition process of the present invention;

[0028] Figure 4 This is a flowchart of the sacrificial layer deposition process of the present invention;

[0029] Figure 5 This is a flowchart of the cavity etching release process of the present invention;

[0030] Figure 6 This is a flowchart of the support layer deposition process of the present invention;

[0031] Figure 7 This is a flowchart illustrating the electrode and piezoelectric material deposition process of the present invention;

[0032] Figure 8 This is a schematic diagram of the resonator structure of the present invention;

[0033] Figure 9 This is a schematic diagram of the preparation process of the present invention.

[0034] In the figure: 101, silicon wafer substrate; 102, defect structure; 103, cavity structure; 104, support layer; 105, bottom electrode; 106, piezoelectric material; 107, top electrode; 108, sacrificial layer SiO2. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below in conjunction with the embodiments of this invention. Those skilled in the art should understand that the embodiments are merely illustrative of the invention and should not be considered as specific limitations thereof. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention. Process parameters not specifically specified in the following embodiments are generally performed under conventional conditions.

[0036] Example 1: Fabrication of a Standard Thin-Film Bulk Acoustic Resonator

[0037] S1. Substrate cleaning: Select silicon wafer substrate 101. First, clean the substrate surface with acetone to remove organic matter. Then, use hydrofluoric acid solution to remove the surface silicon oxide layer. Next, use deionized water (DIwater) for thorough cleaning. Finally, blow the substrate dry to ensure that there is no moisture residue on the surface and that the substrate cleanliness meets the requirements of subsequent processes.

[0038] S2. Deposition of multilayer defect structure 102: Chemical vapor deposition (CVD) is used to sequentially deposit three silicon-based thin films on a silicon wafer substrate 101. The first layer is a 100 nm thick low-doped silicon film, the second layer is a 100 nm thick medium-doped silicon film, and the third layer is a 100 nm thick high-doped silicon film. The defect density gradually increases from the bottom layer to the top layer to ensure effective capture of induced charges. The deposition temperature is 550°C, and the gas flow rate is controlled within the standard CVD process range to ensure the quality and uniformity of each film layer.

[0039] S3. Sacrificial layer deposition and planarization: A sacrificial layer of SiO2108 with a thickness of 1 μm was deposited on the surface of the multilayer defect structure 102 using PECVD technology. The PECVD deposition temperature was 300°C and the deposition rate was controlled at 5 nm / min to ensure the surface of the sacrificial layer was planar. After completion, chemical mechanical polishing (CMP) was used to planarize the surface and remove the non-uniform layer generated during the deposition process to ensure the planarity of the subsequent structure.

[0040] S4. Cavity etching release: The sacrificial layer is removed by gas phase HF dry etching technology to form cavity structure 103. The etching gas is chlorine gas, and the etching time is controlled within 30 minutes to ensure complete removal of the sacrificial layer and clear cavity structure 103. During the etching process, a mixture of gas phase HF and oxygen is used to reduce the etching rate and improve the etching accuracy.

[0041] S5. Deposition of support layer 104: A 0.2 μm thick Si3N4 support layer 104 is deposited on the surface of the sacrificial layer using the LPCVD method. The LPCVD deposition temperature is 800°C, the deposition gases are SiH4 and NH3, and the deposition rate is controlled at 15 nm / min. The Si3N4 support layer 104 has good mechanical strength, which can effectively prevent the collapse of the cavity structure 103 and improve the structural stability of the resonator.

[0042] S6. Electrode and piezoelectric layer deposition: Using PVD technology, a bottom electrode 105, a 1 μm thick AlN piezoelectric material layer 106, and a top electrode 107 are sequentially deposited on the support layer 104. Both the bottom electrode 105 and the top electrode 107 are made of molybdenum (Mo) material with a deposition thickness of 0.3 μm, which is completed by magnetron sputtering. The piezoelectric material 106 is AlN, which is deposited by reactive sputtering (RF sputtering). The deposition temperature is controlled at 300°C, the nitrogen flow rate is 20 sccm, and the deposition rate is 0.5 μm / h.

[0043] A three-layer gradient-doped defect structure 102 was constructed using standard CVD and PECVD processes, and a sacrificial layer SiO2 108 and a Si3N4 support layer 104 were adopted. This structure has good process compatibility and manufacturing stability, is suitable for the manufacture of conventional communication devices, and is easy to mass-produce.

[0044] Example 2: High-frequency optimized fabrication of a thin-film bulk acoustic resonator

[0045] S1. Substrate cleaning: Select the silicon wafer substrate 101, clean it multiple times with pure water and deionized water, and then use UV-ozone treatment to remove surface organic matter and residual contaminants to ensure that the surface of the silicon wafer substrate 101 is clean and free of contamination.

[0046] S2. Deposition of multilayer defect structure 102: Chemical vapor deposition (CVD) is used to deposit three silicon thin films with different doping concentrations on a silicon substrate. The thickness of each layer is 80 nm, 120 nm and 200 nm respectively, with the doping concentration increasing sequentially to form a gradient structure with increasing defect density. The doping element used is boron (B). The doping concentration is adjusted by ion implantation. The deposition temperature is controlled at 550°C and the doping gas flow rate is 10 sccm.

[0047] S3. Sacrificial layer deposition and leveling: A 2μm thick Si3N4 sacrificial layer was deposited using PECVD at a temperature of 350°C. The deposition gases were SiH4 and N2O, and the deposition rate was 3nm / min. After completion, CMP was used to level the surface to ensure uniformity and good contact of the subsequent structure.

[0048] S4. Cavity etching release: The sacrificial layer is removed by etching with Cl2 / Ar plasma. The etching gas is a mixture of hydrogen chloride (Cl2) and argon (Ar). The etching time is 20 minutes. By precisely controlling the etching time and gas ratio, the fine control and stability of the cavity structure 103 are ensured.

[0049] S5. Deposition of support layer 104: A 0.5 μm thick Si3N4 support layer 104 is deposited using LPCVD process with a gas flow rate controlled at 5 sccm and a deposition temperature of 800°C. The Si3N4 layer has high mechanical strength and is suitable for high-frequency applications that require structural stability.

[0050] S6. Electrode and piezoelectric layer deposition: Gold (Au) bottom electrode 105 and top electrode 107 are sequentially deposited on the support layer 104 using PVD technology. The thickness of each is 0.5 μm. Bottom electrode 105 and top electrode 107 are deposited by magnetron sputtering. The intermediate piezoelectric layer is AlN with a thickness of 1 μm, which is deposited by RF sputtering technology at a deposition temperature of 300°C, a nitrogen flow rate of 15 sccm, and a sputtering power of 200 W.

[0051] By further refining the doping concentration and layer thickness on the defect structure 102, and using Au electrodes and high-quality AlN piezoelectric material 106, the high-frequency response performance is greatly optimized and the in-band insertion loss is reduced. It is particularly suitable for 5G communication and high-speed radio frequency applications, demonstrating the high sensitivity and high Q value characteristics of the device.

[0052] Example 3: High-Reliability Fabrication of Thin-Film Bulk Acoustic Resonators

[0053] S1. Substrate cleaning: Select the silicon wafer substrate 101, use acetone, isopropanol and hydrofluoric acid to clean and remove organic matter and oxides, then thoroughly clean with deionized water, and finally use nitrogen gas flow to dry the surface of the silicon wafer substrate 101.

[0054] S2. Multilayer defect structure 102 deposition: Four silicon thin films are deposited using CVD technology, each with a thickness of 50nm, for a total thickness of 200nm. The doping concentration of each layer increases sequentially, from the lowest doping concentration on the substrate side to the highest doping concentration near the active region of the device. The boron doping concentration is controlled by ion implantation to ensure a defect density increasing structure.

[0055] S3. Sacrificial layer deposition and leveling: A 1μm thick sacrificial layer of SiO2108 is deposited using PECVD at a deposition temperature of 250°C. After deposition, the surface is leveled using CMP to ensure the uniformity of subsequent layers.

[0056] S4. Cavity etching release: The sacrificial layer is removed by hydrogen fluoride gas phase etching (HFdryetching) with an etching time of 35 minutes and a fluorine concentration of 60%, ensuring high etching precision and stability of the cavity structure 103.

[0057] S5. SiC support layer 104 deposition: The SiC support layer 104 is deposited using LPCVD process, with a thickness of 0.3 μm. SiC material has high hardness and temperature resistance, which can ensure the long-term stability of the device in harsh environments.

[0058] S6. Electrode and piezoelectric layer deposition: The bottom electrode 105 is made of platinum (Pt) and the top electrode 107 is made of aluminum (Al). They are deposited using PVD technology, and both have a thickness of 0.3 μm. The piezoelectric material 106 is made of AlxGa1₋xN with a thickness of 1.5 μm. It is deposited using reactive sputtering at a temperature of 350°C, a nitrogen flow rate of 20 sccm, and a sputtering power of 250 W.

[0059] By emphasizing reliability in material selection and structural strength, a four-layer boron-doped silicon defect structure 102 and a SiC support layer 104 are adopted, which have excellent structural stability and long-term reliability in high temperature or harsh environments.

[0060] Based on the above three embodiments, a detailed comparative analysis was conducted. Each embodiment differs in material selection, structural design, and manufacturing process, resulting in differences in their performance. The following table summarizes the key technical parameters and characteristics of each embodiment and compares and analyzes them to facilitate the selection of the best embodiment. The results are shown in Table 1.

[0061] Table 1: Comparison of Examples

[0062] Example Number of thin film layers Thickness of each layer Sacrificial layer material Support layer material piezoelectric materials Electrode materials Main features Example 1 3 floors 100nm <![CDATA[SiO2]]> <![CDATA[Si3N4]]> AlN Mo Standard process, suitable for basic applications Example 2 3 floors 80-200nm <![CDATA[Si3N4]]> <![CDATA[Si3N4]]> AlN Au High-frequency optimization, suitable for 5G communication Example 3 4 floors 50nm <![CDATA[SiO2]]> SiC <![CDATA[AlxGa1₋xN]]> Pt / Al High reliability, suitable for high temperature environments

[0063] According to the table above, Embodiment 2 has the following advantages over other embodiments:

[0064] I. High-frequency performance optimization

[0065] The core advantage of Example 2 lies in its optimized high-frequency performance of the device. It uses gold (Au) as the electrode material. Compared with the molybdenum electrode used in Example 1, the gold electrode has lower resistance and better conductivity, which results in lower insertion loss in high-frequency operation and enables the transmission of high-speed signals such as 5G.

[0066] AlN (aluminum nitride) is used as the piezoelectric material 106. Compared with the AlN material in Example 1, it has better piezoelectric performance and can maintain a higher resonant frequency and Q value at higher frequencies. Therefore, Example 2 is particularly suitable for applications such as 5G and Wi-Fi that require high frequency and low insertion loss.

[0067] II. Optimization of Materials and Structures

[0068] The silicon film in Example 2 adopts a gradient defect structure 102 (boron-doped silicon), in which the defect density of each layer gradually increases, and the control of defect density can effectively capture induced charges, thereby suppressing induced losses. This enables the device to maintain low power loss and high operating efficiency under high frequency signal operation.

[0069] By using this defect density gradient control method, Example 2 can effectively reduce insertion loss caused by charge migration at high frequencies compared to the standard silicon film structure in Example 1.

[0070] III. High adaptability

[0071] The choice of materials and layer structure in Embodiment 2 makes it highly adaptable to high-frequency, low-power, and high-efficiency applications, especially suitable for modern communication fields such as 5G communication and radar systems. These applications require accurate frequency response, low insertion loss, and good stability, and Embodiment 2 meets these requirements.

[0072] Compared to Example 1, Example 2 provides higher operating frequency support and better stability in high-frequency applications.

[0073] IV. Process Optimization:

[0074] The sacrificial layer used in Example 2 is Si3N4, which further optimizes the overall structure of the device and provides strong mechanical stability.

[0075] The selection of Au electrodes is crucial for improving the high-frequency performance of the device, a point that is less discussed in Example 1 (molybdenum electrode) and Example 3 (platinum electrode).

[0076] IV. Comparison with other embodiments:

[0077] In Example 1, although its basic processes and materials are relatively common, the conductivity of the molybdenum electrode is not as good as that of the gold electrode in high-frequency applications, and the piezoelectric material 106 and the defect structure 102 are not optimized for high frequencies. Therefore, it is not suitable for providing the best performance in 5G and higher frequency applications.

[0078] In Example 3, although the SiC support layer 104 provides strong high-temperature resistance and good reliability in high-temperature environments, the high-frequency optimized design of Example 2 (such as the AlN piezoelectric layer and Au electrode) makes it more advantageous in terms of high-frequency performance and low insertion loss in the field of high-frequency communication.

[0079] Example 2, through careful optimization of electrode materials, piezoelectric material 106 and defect structure 102, is particularly suitable for high-frequency communication applications, especially in the fields of 5G and other high-speed signal transmission. Its performance is significantly better than that of Example 1 and Example 3. Therefore, Example 2 is the most recommended example of the present invention.

[0080] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A method for fabricating a resonator with an induced charge trapping cavity structure, characterized in that, Includes the following steps: S1. Substrate cleaning: Select a silicon wafer as the silicon substrate. First, use acetone to clean the silicon substrate to remove organic contaminants on the surface. Then, use isopropanol or deionized water to rinse. Next, use hydrofluoric acid solution to remove the natural oxide layer on the surface. After washing, rinse thoroughly with deionized water and dry with nitrogen. S2. Deposition of multilayer cavity structures: Multilayer cavity structures are sequentially deposited on the silicon substrate cleaned in step S1. The defect densities of the multilayer cavity structures are different, forming a gradient distribution of defect densities. The multilayer cavity structure includes 3 to 5 silicon-based thin films, and the total thickness of the multilayer cavity structure is 0.1 μm to 2 μm. In the cavity structure, the first layer located near the silicon substrate has the lowest defect density, and the topmost layer located near the device active region has the highest defect density. The thickness of each cavity structure is 50 nm to 300 nm. The cavity structure is formed by ion implantation, doping control, and polycrystalline silicon or amorphous silicon deposition. The ions used for ion implantation are phosphorus, boron, and argon. S3. Sacrificial layer deposition: A sacrificial layer is deposited on the surface of a multi-layer cavity structure. The sacrificial layer is formed by low-temperature deposition, including LPCVD, PECVD and PVD deposition processes. The thickness of the sacrificial layer is 0.5 μm to 4 μm. S4. Cavity etching release: The sacrificial layer is removed to form a defect structure using dry and wet etching methods. The etching gas is a chlorine or fluorine halide. The etching method is gas phase HF dry etching and Cl2 / Ar plasma etching. S5. Deposition of support layer: A support layer is deposited on the surface of the sacrificial layer. The support layer is used to prevent the structure above the cavity from collapsing due to external forces and stress. The thickness of the support layer is 0.05 μm to 3 μm. S6. Electrode and piezoelectric material deposition: A bottom electrode, a piezoelectric material layer and a top electrode are sequentially deposited on a support layer. The top electrode and bottom electrode are made of Mo, and the piezoelectric material is AlN. The thicknesses of the bottom electrode and top electrode are 0.05 μm to 0.5 μm, respectively; the thickness of the piezoelectric material is 0.5 μm to 2 μm.

2. A resonator with an induced charge trapping cavity structure, fabricated using the fabrication method of the resonator with an induced charge trapping cavity structure as described in claim 1, characterized in that, include: The following components are arranged sequentially from bottom to top: a silicon wafer substrate (101), a cavity structure (102), a support layer (104), a bottom electrode (105), a piezoelectric material (106), and a top electrode (107). A defect structure (103) formed between the support layer (104) and the cavity structure (102) by etching a sacrificial layer SiO2 (108) is formed. The cavity structure (102) contains 3-5 silicon-based thin films with a defect density gradient distribution.

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