LDPC (Low Density Parity Check) check belief propagation decoding method based on improved minimum sum

Abstract

The invention relates to an LDPC (Low Density Parity Check) check confidence propagation decoding method based on an improved minimum sum. According to the method, variable node external information is introduced to participate in calculation of verification confidence to variable node (B2V) information, and a four-step processing mechanism of numerical value selection, numerical value offset, numerical value scaling and symbol calculation is combined, so that the decoding performance is improved, and the algorithm convergence is enhanced. The hardware device comprises a storage module, a verification confidence coefficient cyclic shift module, a three-information parallel computing module, an update information cyclic shift module, a verification confidence coefficient update information parallel computing module, a verification equation verification module and a global control module, and all the modules work cooperatively in a pipeline mode to achieve efficient parallel processing of the decoding process. The device adopts technologies such as compression storage, forward forwarding path, dynamic merging shift control, specific storage and calculation sequence control and the like, so that the hardware resource consumption is reduced, and the throughput rate is improved. According to the invention, the accuracy and efficiency of LDPC decoding can be effectively improved, and the method has good practicability and expandability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computer communication, and in particular to an LDPC check confidence propagation decoding method based on improved minimum sum. BACKGROUND

[0002] As a key error correction coding technology approaching the Shannon limit in modern communication systems, low-density parity-check codes (LDPC codes) are widely used in high-speed data transmission scenarios such as 5G new radio (NR). In related technologies, through the cooperation of the minimum sum (MS) method and the check confidence propagation (CBP) mechanism, a new iteration decoding technology system is constructed. Specifically, this decoding system covers the whole process from message passing to check equation verification, including key links such as check confidence to variable node information update, posteriori information update, extrinsic information update, and check confidence information update. Among them, the check confidence propagation algorithm has good hardware implementation potential because it does not need to accumulate calculation, and especially shows high parallel efficiency and scalability in the block parallel structure.

[0003] However, in the existing MS-CBP method, the minimum value and the second minimum value of the check confidence are directly used for B2V information calculation, and the key role of the variable node extrinsic information is not considered, which may cause the reliability of the B2V information to be greatly reduced, especially in the presence of a large number of degree 1 variable nodes in the check matrix, which is easy to cause decoding non-convergence problem, thereby significantly affecting the decoding performance. In addition, the non-cumulative calculation characteristics of the CBP algorithm and the compatibility problem of the traditional decoding architecture exist, which causes the existing hardware implementation to be difficult to directly reuse, limiting its application in low power, low area, and high throughput scenarios. Based on this, it is necessary to optimize the B2V information calculation mechanism and redesign an efficient hardware architecture suitable for the CBP algorithm to achieve a balance between performance and implementation complexity. SUMMARY

[0004] The present application aims to at least partially solve one of the technical problems in the related art.

[0005] The present application proposes an LDPC check confidence propagation decoding method based on improved minimum sum, aiming to solve the problem that the existing minimum sum check confidence propagation (MS-CBP) decoding algorithm maintains high decoding performance under low hardware implementation complexity.

[0006] Another purpose of the present application is to propose an LDPC check confidence propagation decoding hardware implementation device based on improved minimum sum.

[0007] To achieve the above purpose, the present application proposes, in one aspect, an LDPC check confidence propagation decoding method based on improved minimum sum, comprising:

[0008] In response to the decoding request, obtaining a check belief information block, an extrinsic information block and a check belief to variable node information block of a current decoding block;

[0009] Performing cyclic shift processing on the check belief information block to match the order of all variable nodes in the same decoding block;

[0010] Based on the cyclically shifted check belief information block, the extrinsic information block and the check belief to variable node information block, performing parallel calculation to generate a check node to variable node update information block, a posteriori information update information block and an extrinsic information update information block;

[0011] Merging the posteriori information update information block and the extrinsic information update information block, and performing cyclic shift processing and splitting to match the order of all check nodes in the same decoding block;

[0012] Based on the split information block, performing parallel calculation to generate a check belief update information block, and writing the check belief update information block back to the storage module;

[0013] In response to the check equation verification result of the current decoding block, if the partial check results of all layer blocks are correct, it is determined that the decoding is successful and the decoding result is output; if there is an error and the current iteration number is less than the maximum iteration number, the next iteration decoding is performed; if there is an error and the current iteration number is equal to the maximum iteration number, it is determined that the decoding fails and the decoding is terminated.

[0014] The improved min-sum based LDPC check belief propagation decoding method of the embodiment of the application can also have the following additional technical features:

[0015] In an embodiment of the application, the four steps of value selection, value offset, value scaling and sign calculation are as follows:

[0016] In the value selection step, a value is selected from the minimum value of the check belief of the check node, the second minimum value and the absolute value of the extrinsic information of the corresponding variable node, if the minimum value is equal to the absolute value, the second minimum value is selected, otherwise the smaller one of the minimum value and the absolute value is selected;

[0017] In the value offset step, if the selected value is the second minimum value and is equal to the minimum value, a first conditional offset factor is subtracted; if the selected value is the minimum value and is equal to the second minimum value, a second conditional offset factor is subtracted; otherwise, no value offset is performed;

[0018] In the value scaling step, the value after the value offset processing is multiplied by a scaling factor;

[0019] In the sign calculation step, the numerical value after the numerical scaling processing is multiplied by the sign of the check confidence and the sign of the extrinsic information to obtain the update information from the check node to the variable node.

[0020] To achieve the above object, the application further provides a hardware implementation device for LDPC check confidence propagation decoding based on improved minimum sum, comprising:

[0021] A storage module is configured to store the check confidence information block in ascending order of the check node, store the extrinsic information block, the check confidence to variable node information block and the posterior information block in ascending order of the variable node, and realize block reading and writing and initialization of the information block under the control of the global control module;

[0022] A check confidence cyclic shift module is configured to perform cyclic right shift processing on the read check confidence information block to match the order of all variable nodes in the same decoding block;

[0023] A three-information parallel calculation module is configured to perform parallel calculation to generate the update information block from the check node to the variable node, the posterior information update information block and the extrinsic information update information block;

[0024] An updated posterior information and extrinsic information cyclic shift module is configured to combine the posterior information update information block and the extrinsic information update information block, perform cyclic shift processing on the combined information block, and split the processed information block to match the order of all check nodes in the same decoding block;

[0025] A check confidence update information parallel calculation module is configured to perform parallel calculation on the minimum value and the second minimum value of the check confidence of all check nodes in the current decoding block based on the split information block, and output the check confidence update information block in compressed storage form;

[0026] A check equation verification module is configured to verify the check equation after the decoding of the current decoding block is completed, generate partial check results, and determine whether the decoding is successful according to the partial check results of all layer blocks;

[0027] A global control module is configured to control the operation of each module in a pipeline manner, and provide check matrix related signals, scaling factor parameters, conditional offset factor selection parameters, storage module reading and writing addresses, shift module shift bit numbers, iteration start and termination signals, and module enable signals.

[0028] Further, the three-information parallel calculation module comprises a check confidence to variable node information update sub-module, a posterior information update sub-module and an extrinsic information update sub-module,

[0029] The calculation sub-modules in the three-information parallel calculation module perform numerical selection, numerical offset, numerical scaling and sign calculation operations, wherein:

[0030] In the numerical selection operation, a numerical value is selected from the minimum value of the check belief, the second minimum value and the absolute value of the extrinsic information of the corresponding variable node, if the minimum value is equal to the absolute value, the second minimum value is selected, otherwise the smaller one of the minimum value and the absolute value is selected;

[0031] In the numerical offset operation, if the selected numerical value is the second minimum value and is equal to the minimum value, a first conditional offset factor is subtracted; if the selected numerical value is the minimum value and is equal to the second minimum value, a second conditional offset factor is subtracted; otherwise, no numerical offset is performed;

[0032] In the numerical scaling operation, the numerical value after the numerical offset processing is multiplied by a scaling factor;

[0033] In the sign calculation operation, the numerical value after the numerical scaling processing is multiplied by the sign of the check belief and the sign of the extrinsic information to obtain the update information from the check node to the variable node.

[0034] Further, the storage module compressively stores the check belief information block, only retains a single sign bit for the minimum value and the second minimum value, and prevents memory read-write conflict through a forward forwarding path to improve the pipeline efficiency.

[0035] Further, the check belief cyclic shift module dynamically adjusts the cyclic right shift number according to the structure of the check matrix to perform cyclic shift processing, so as to ensure that the information blocks are input into the calculation module in the order of the variable nodes from small to large.

[0036] Further, each sub-module in the three information parallel calculation modules processes the information blocks in the order of the variable nodes from small to large in parallel, so as to improve the decoding throughput.

[0037] Further, the updated posterior information and extrinsic information cyclic shift module, after merging the posterior information and extrinsic information blocks, dynamically adjusts the cyclic right shift number according to the structure of the check matrix to perform cyclic shift processing, and inputs the check belief update information parallel calculation module and the check equation verification module in the order of the check nodes from small to large after splitting.

[0038] Further, the check belief update information parallel calculation module, after completing the calculation of the minimum value and the second minimum value of the check belief of the current decoding block, outputs the check belief update information block in the form of compressive storage, and writes back to the storage module.

[0039] The improved minimum-sum based LDPC check confidence propagation decoding method and device can realize high decoding performance under low complexity, and the block parallel hardware implementation device of the decoding algorithm can realize high throughput under low area and power consumption.

[0040] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0041] The above and / or additional aspects and advantages of the present application will become apparent and be more readily understood from the following description, taken in conjunction with the accompanying drawings, in which:

[0042] Figure 1 is a flow chart of the improved minimum-sum based LDPC check confidence propagation decoding method according to the embodiment of the present application;

[0043] Figure 2 is a structural diagram of the improved minimum-sum based LDPC check confidence propagation decoding hardware implementation device according to the embodiment of the present application;

[0044] Figure 3 is another structural diagram of the improved minimum-sum based LDPC check confidence propagation decoding hardware implementation device according to the embodiment of the present application;

[0045] Figure 4 is an information block merging and splitting schematic diagram of the updated a posteriori information and updated extrinsic information cyclic shift module of the improved minimum-sum based LDPC check confidence propagation decoding hardware implementation device according to the embodiment of the present application;

[0046] Figure 5 is a decoding flow chart of aligning the last non-negative element in the last row of the circulant base matrix of the improved minimum-sum based LDPC check confidence propagation decoding hardware implementation device according to the embodiment of the present application. DETAILED DESCRIPTION

[0047] It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0048] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the present application.

[0049] The improved min-sum based LDPC check node belief propagation decoding method and device proposed according to the embodiments of the present application are described below with reference to the drawings.

[0050] Figure 1 The flow chart of the improved min-sum based LDPC check node belief propagation decoding method according to the embodiments of the present application is shown in FIG. 1, which includes: Figure 1

[0051] S1, in response to a decoding request, acquiring a check node belief information block, an extrinsic information block and a check node to variable node information block of a current decoding block;

[0052] S2, performing cyclic shift processing on the check node belief information block to match the order of all variable nodes in the same decoding block;

[0053] S3, based on the check node belief information block after the cyclic shift, the extrinsic information block and the check node to variable node information block, performing parallel calculation to generate a check node to variable node update information block, a posteriori information update information block and an extrinsic information update information block;

[0054] S4, merging the posteriori information update information block and the extrinsic information update information block, and performing cyclic shift processing and splitting to match the order of all check nodes in the same decoding block;

[0055] S5, based on the split information block, performing parallel calculation to generate a check node belief update information block, and writing the check node belief update information block back to a storage module;

[0056] S6, in response to the check equation verification result of the current decoding block, if the partial check results of all layer blocks are correct, determining that the decoding is successful and outputting the decoding result; if there is an error and the current iteration number is less than the maximum iteration number, performing the next iteration decoding; if there is an error and the current iteration number is equal to the maximum iteration number, determining that the decoding fails and terminating the decoding.

[0057] The four steps of the value selection, the value offset, the value scaling and the sign calculation, wherein:

[0058] ​In the numerical selection step, a numerical value is selected from the minimum and second minimum values ​​of the verification confidence of the verification node and the absolute value of the extrinsic information of the corresponding variable node. If the minimum value is equal to the absolute value, the second minimum value is selected; otherwise, the smaller value between the minimum value and the absolute value is selected.

[0059] In the numerical offset step, if the selected value is the second minimum value and is equal to the minimum value, then the first conditional offset factor is subtracted; if the selected value is the minimum value and is equal to the second minimum value, then the second conditional offset factor is subtracted; otherwise, no numerical offset is performed.

[0060] In the numerical scaling step, the numerically offset value is multiplied by a scaling factor.

[0061] In the symbolic computation step, the numerical value after numerical scaling is multiplied by the symbol of the verification confidence and the symbol of the external information to obtain the update information from the verification node to the variable node.

[0062] Understandably, the low accuracy of B2V messages in the MS-CBP algorithm leads to severe performance degradation, and there is a lack of high-performance hardware implementations suitable for CBP-type decoding algorithms. To address these issues, we first propose an IMS-CBP algorithm. This method eliminates computational errors caused by ignoring external information of variable nodes in B2V message calculation and introduces scaling and conditional offset factors. It significantly improves the accuracy of B2V information with a slight increase in computational complexity, thereby enhancing decoding performance. Secondly, we propose a block-parallel hardware implementation of the IMS-CBP algorithm. This device achieves high throughput while reducing area and power consumption through a series of optimizations, including compressed storage, increased forwarding paths, optimized data storage order, optimized computation order, and dynamic merging and shifting.

[0063] This application aims to address, to some extent, the problem of severe performance degradation in the MS-CBP algorithm and the lack of high-performance hardware implementation devices suitable for CBP-type decoding algorithms.

[0064] Therefore, this application first proposes an improved MS-CBP decoding algorithm, IMS-CBP. The improvement of IMS-CBP over MS-CBP lies in the B2V information computation, which divides the B2V information computation into four steps: value selection, value offset, value scaling, and symbol computation. The detailed steps are explained below:

[0065] Step 1: Numerical selection. The j-th check node c in the check matrix... j Minimum confidence level of the test and second minimum value The a-th variable node v in the verification matrix a absolute value of external information The smaller one of and is selected if is equal to , and the larger one of and is selected if

[0066] is not equal to . Step two: numerical offset. If the value selected in step one is and is equal to , the value selected in step one is reduced by a conditional offset factor γ1; if the value selected in step one is and is equal to

[0067] , the value selected in step one is reduced by a conditional offset factor γ2; otherwise, no numerical offset is performed.

[0068] Step three: numerical scaling. The value processed in step two is multiplied by a suitable scaling factor in the range of (0, 1) for calculation. Step four: sign calculation. The value processed in step three is multiplied by the sign of the check belief of the check node c j and the sign of the extrinsic information of the variable node v a to obtain the updated information from the check node c j to the variable node v a .

[0069] The four steps can be combined and represented as:

[0070]

[0071] wherein α is a scaling factor; γ1 and γ2 respectively represent the conditional offset factors used in step two after the selection of and in step one, and γ1 and γ2 are respectively related to λ1 and λ2 and λ1 and λ2 are both selected to be two numbers of 0 or 1 for independent adjustment.

[0072] The present application improves the calculation method of B2V information, introduces the extrinsic information of the variable node, the scaling factor and the conditional offset factor, effectively improves the accuracy of the B2V information, and thus significantly improves the decoding performance, especially in the check matrix with a large number of degree-1 variable nodes, effectively alleviates the problem of decoding non-convergence, and improves the decoding stability.

[0073] To implement the above-mentioned embodiments, as shown in Figure 2 , the present embodiment further provides an improved min-sum based LDPC check belief propagation decoding hardware implementation device 10, comprising:

[0074] a storage module 100, configured to store the check confidence information block in ascending order of the check nodes, store the extrinsic information block, the check confidence to variable node information block and the posterior information block in ascending order of the variable nodes, and realize block reading and writing and initialization of the information blocks under control of the global control module;

[0075] a check confidence cyclic shift module 200, configured to perform cyclic right shift processing on the read check confidence information block to match the order of all the variable nodes in the same decoding block;

[0076] a three-information parallel computation module 300, configured to perform parallel computation to generate the check node to variable node update information block, the posterior information update information block and the extrinsic information update information block;

[0077] an updated posterior information and extrinsic information cyclic shift module 400, configured to combine the posterior information update information block and the extrinsic information update information block, perform cyclic shift processing on the combined information block, and split the processed information block to match the order of all the check nodes in the same decoding block;

[0078] a check confidence update information parallel computation module 500, configured to perform parallel computation on the minimum value and the second minimum value of the check confidence of all the check nodes in the current decoding block based on the split information block, and output the check confidence update information block in compressed storage form;

[0079] a check equation verification module 600, configured to verify the check equation after decoding of the current decoding block is completed, generate partial check results, and determine whether the decoding is successful according to the partial check results of all the layer blocks;

[0080] a global control module 700, configured to control the modules to run in a pipeline manner, and provide check matrix related signals, scaling factor parameters, conditional offset factor selection parameters, storage module reading and writing addresses, shift module shift bit numbers, iteration start and termination signals, and module enable signals.

[0081] Further, the three-information parallel computation module includes a check confidence to variable node information update sub-module, a posterior information update sub-module and an extrinsic information update sub-module,

[0082] The computation sub-modules in the three-information parallel computation module perform numerical selection, numerical offset, numerical scaling and sign computation, wherein:

[0083] In the numerical selection operation, a numerical value is selected from the minimum value, the second minimum value of the check confidence of the check node and the absolute value of the extrinsic information of the corresponding variable node, if the minimum value is equal to the absolute value, the second minimum value is selected, otherwise the smaller one of the minimum value and the absolute value is selected;

[0084] In the numerical offset operation, if the selected value is the second minimum value and is equal to the minimum value, a first conditional offset factor is subtracted; if the selected value is the minimum value and is equal to the second minimum value, a second conditional offset factor is subtracted; otherwise, no numerical offset is performed.

[0085] In the numerical scaling operation, the value after the numerical offset processing is multiplied by a scaling factor.

[0086] In the sign calculation operation, the value after the numerical scaling processing is multiplied by the sign of the check confidence and the extrinsic information.

[0087] Further, the storage module compressively stores the check confidence information block, retains only a single sign bit for the minimum value and the second minimum value, and prevents memory read-write conflict through a forward forwarding path to improve pipeline efficiency.

[0088] Further, the check confidence cyclic shift module dynamically adjusts the cyclic right shift number according to the structure of the check matrix to perform cyclic shift processing, so as to ensure that the information block is input into the calculation module in the order of variable nodes from small to large.

[0089] Further, each submodule in the three information parallel calculation modules processes the information block in the order of variable nodes from small to large in parallel, so as to improve the decoding throughput rate.

[0090] Further, the updated a posteriori information and extrinsic information cyclic shift module, after merging the a posteriori information and extrinsic information blocks, dynamically adjusts the cyclic right shift number according to the structure of the check matrix to perform cyclic shift processing, and then splits and inputs the check confidence update information and the check equation verification module in the order of check nodes from small to large.

[0091] Further, the check confidence update information parallel calculation module, after completing the calculation of the minimum value and the second minimum value of the check confidence of the current decoding block, outputs the check confidence update information block in the form of compressed storage, and writes back to the storage module.

[0092] Specifically, the application provides a block parallel hardware implementation device based on an IMS-CBP algorithm. As shown in the figure, the device connects each module in a pipeline form for operation, and each module is described in detail as follows: Figure 3

[0093] The storage module: store the check confidence Ω in the order of check nodes from small to large, store the extrinsic information Q, the check confidence to variable node information R and the a posteriori information Λ in the order of variable nodes from small to large, and realize the block reading and writing and initialization of related information under the control of the global control module. Especially, the design of the check confidence storage is as follows: ​

[0094] (1) The check confidence of a single check node is compressed and stored after retaining only a single symbol bit for the minimum and second minimum values.

[0095] (2) A forward transmission path is implemented for the check confidence storage module to prevent pipeline stoppage caused by simultaneous memory read and write conflicts and to improve throughput.

[0096] The check confidence cyclic shift module cyclically shifts the check confidence information block read out from the storage module, so that the shifted information block can be input to the variable node information update R new , the a posteriori information update Λ new , and the extrinsic information update Q new in parallel according to the order of all variable nodes in the same decoding block from small to large.

[0097] The check confidence to variable node information update R new , the a posteriori information update Λ new , and the extrinsic information update Q new is calculated in parallel according to the order of all variable nodes in the same decoding block from small to large.

[0098] The a posteriori information Λ new and the extrinsic information Q new are updated. Figure 4 The cyclic shift module combines the a posteriori information update block and the extrinsic information update block calculated by the R new , Λ new , and Q new calculation modules, cyclically shifts the combined information block, and then splits the shifted information block, so that the split information block can be input to the check confidence update information calculation module and the check equation verification module in parallel according to the order of all check nodes in the same decoding block from small to large.

[0099] The check confidence update information Ω new calculation module calculates the temporary minimum and second minimum values of the check confidence of all check nodes in the current decoding block in parallel and synchronously according to the order of all check nodes in the same decoding block from small to large. When the decoding traverses all variable nodes in the check matrix layer block involved in the current decoding block, the compressed and stored check confidence update information block is output, and the information block is written back to the corresponding storage module under the global control module.

[0100] The check equation verification module: each layer block in the check matrix, which is composed of multiple continuous layers, will generate a set of parity check results when the decoding of the layer block is completed. The set of results is regarded as a partial check. If all the partial checks of all the layer blocks in the check matrix are correct, the decoding is successful, and the decoding is stopped and the decoding result is output. If there is an error in the partial check of all the layer blocks in the check matrix and the iteration number is less than the maximum iteration number, the next iteration decoding is started. Otherwise, if there is an error in the partial check of all the layer blocks in the check matrix and the iteration number is equal to the maximum iteration number, the decoding fails and the decoding is stopped.

[0101] The global control module: controls the modules in the device to run in a pipeline manner, stores and provides the related signals of the consistent check matrix, the scaling factor parameters, the conditional offset factor selection parameters, the storage module read-write address, the shift module shift bit number, the iteration start and termination signal, the maximum iteration number parameter, and the module enable signal.

[0102] The following is an example supplement to the technical method of the embodiment of the application. The block parallel hardware implementation device based on the IMS-CBP algorithm is used to decode a quasi-cyclic code. The quasi-cyclic code expands the elements in the base graph into a 4*4-dimensional matrix, and the device performs parallel decoding with a single element in the base graph as a decoding block. For convenience, a certain element C X The first variable / check node, the second variable / check node, the first variable / check node, the third variable / check node, and the fourth variable / check node in the decoding block in the order from small to large are represented as

[0103] When the device decodes the last non-negative element C I in the last row of the base graph and the most adjacent non-negative element C I in the previous layer of the same column is C J , the device performs the specific decoding process as shown in the following table. I When the matrix cyclic right shift number is 2 bits, C Figure 5 When the matrix cyclic right shift number is 1 bit, the specific decoding process of the device is as shown in the following table.

[0104] Step 1: data reading. The C J representing the check confidence information block vector of the decoding block C I representing the extrinsic information block vector of the decoding block and the check confidence to the variable node information block vector

[0105] Step 2: cyclic shift of the check confidence information block. After the vector is cyclically right shifted by 2 bits, it becomes the shifted check confidence information block vector

[0106] Step 3: Verify confidence level to update variable node information blocks, posterior information blocks, and extrinsic information blocks, calculate and write back. Transfer the information block vector... Divided into The same parallel computation operation is performed in four parts to obtain C. I The outer information update information block vector represents the decoded block. Update the information block vector with posterior information C J This represents the update of the information block vector from the confidence level of the decoded block to the variable node information. Then, these information blocks are written back to the corresponding locations in the storage module. The above parallel computing operations include four sequential operations from verifying confidence level to updating variable node information. For example, some are as follows:

[0107] Operation 1: Value Selection. Select the verification node. Confidence level verification Restored to the minimum confidence level of the test and second minimum value Then at the verification node Minimum confidence level of the test and second minimum value Variable Node absolute value of external information Choose a value from the three options, if and If they are equal, then choose Conversely, choose and The smaller value in the range.

[0108] Operation 2: Numerical Offset. If the value selected in Operation 1 is... and and If they are equal, subtract the conditional offset factor γ1 from the value selected in operation one; if the value selected in operation one is... and and If they are equal, the value selected in Operation 1 will be subtracted from the conditional offset factor γ2; otherwise, no numerical offset will be performed.

[0109] Operation 3: Numerical scaling. The numerical value processed in Operation 2 is multiplied by a suitable scaling factor within the range of (0,1) for calculation.

[0110] Operation 4: Symbolic Calculation. Multiply the value processed in Operation 3 by the check node. The sign of the confidence level of the test and variable nodes the extrinsic information of the check node obtaining the update information of the check node to the variable node the update information of the check node

[0111] The four operations can be combined as follows:

[0112]

[0113] wherein a is a scaling factor; and γ1 and γ2 represent the conditional offset factors used in step one and step two respectively, and γ1 and γ2 are related to λ1 and λ2 respectively and λ1 and λ2 are independently adjusted to be either 0 or 1. and The conditional offset factors used in step one and step two respectively, and γ1 and γ2 are related to λ1 and λ2 respectively and λ1 and λ2 are independently adjusted to be either 0 or 1.

[0114] Step four: cyclic shift of the extrinsic information update information block and the a posteriori information update information block. It contains three sequential operations:

[0115] Operation one: merge the information block vector and the information block vector to become the vector wherein {} represents a concatenation operation.

[0116] Operation two: cyclically right shift the vector Mer by 3 bits to become the shifted vector Mer wherein {} represents a concatenation operation.

[0117] Operation three: split the vector Mer Shifted to become the cyclically shifted information blocks of the vector and , which are denoted as the vectors

[0118] Step five: perform the check confidence update information block calculation and write back and the check equation verification and decoding subsequent process decision in parallel.

[0119] (1) check confidence update information block calculation and write back: use the information block vector to calculate the check confidence update information block, and write the check confidence update information block in compressed storage form back to the corresponding position of the storage module after the calculation is completed.

[0120] (2) check equation verification and decoding subsequent process decision: use the information block vector The partial check results of the decoded layer blocks are obtained by performing check equation verification. At this time, if the partial checks of all the layer blocks in the check matrix are correct, the decoding succeeds, the decoding is stopped and the decoding result is output; if the partial checks of all the layer blocks in the check matrix are incorrect and the iteration number of decoding is less than the maximum iteration number, the next iteration decoding is started; otherwise, if the partial checks of all the layer blocks in the check matrix are incorrect and the iteration number of decoding is equal to the maximum iteration number, the decoding fails and the decoding is stopped.

[0121] It can be understood that, by improving the B2V message computer mechanism and optimizing the block parallel hardware structure, the decoding performance, hardware area, power consumption and throughput are all superior to those of the prior art.

[0122] According to the hardware implementation device for the improved min-sum based LDPC check confidence propagation decoding of the embodiment of the present application, by introducing the variable node outer information, the scaling factor and the conditional offset factor, the B2V information calculation is more accurate while the low decoding complexity of the IMS-CBP algorithm is maintained, the non-convergence problem caused by the degree 1 variable node can be effectively alleviated, the decoding success rate is improved and the decoding performance of the IMS-CBP algorithm approaches the CBP algorithm; by the compression storage for reducing the storage overhead, the dynamic merging shift control for reducing the shift overhead, the specific storage and calculation sequence control for avoiding the pipeline pause and the forward forwarding, the hardware area and the power consumption are significantly reduced; the block parallel structure and the pipeline parallel operation design enable multiple decoding blocks to be processed at the same time, the overall throughput is improved and the global control module can dynamically adjust the iteration number and the module enable according to the check result, the system robustness is improved.

[0123] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the different embodiments or examples described in the present specification and the features of the different embodiments or examples can be combined and combined by those skilled in the art without contradiction.

[0124] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

Claims

1. An improved min-sum based LDPC check confidence propagation decoding method, characterized in that, The method comprises the following steps: In response to a decoding request, obtaining a check confidence information block, extrinsic information block and check confidence to variable node information block of a current decoding block; Performing cyclic shift processing on the check confidence information block to match the order of all variable nodes in the same decoding block; Based on the cyclically shifted check confidence information block, extrinsic information block and check confidence to variable node information block, performing parallel computation to generate a check node to variable node update information block, a posteriori information update information block and an extrinsic information update information block; Merging the posteriori information update information block and the extrinsic information update information block, and performing cyclic shift processing and splitting to match the order of all check nodes in the same decoding block; Based on the split information block, performing parallel computation to generate a check confidence update information block, and writing the check confidence update information block back to the storage module; In response to a check equation verification result of the current decoding block, if the partial check results of all layer blocks are correct, it is determined that the decoding is successful and the decoding result is output; If there is an error and the current iteration number is less than the maximum iteration number, the next iteration decoding is performed; If there is an error and the current iteration number is equal to the maximum iteration number, it is determined that the decoding fails and the decoding is terminated.

2. The method of claim 1, wherein, The four steps of value selection, value offset, value scaling and sign calculation, wherein: In the value selection step, a value is selected from the minimum value, the second minimum value of the check confidence of the check node and the absolute value of the extrinsic information of the corresponding variable node, if the minimum value is equal to the absolute value, the second minimum value is selected, otherwise the smaller one of the minimum value and the absolute value is selected; In the value offset step, if the selected value is the second minimum value and is equal to the minimum value, a first conditional offset factor is subtracted; if the selected value is the minimum value and is equal to the second minimum value, a second conditional offset factor is subtracted; otherwise, no value offset is performed; In the value scaling step, the value after the value offset processing is multiplied by a scaling factor; In the sign calculation step, the value after the value scaling processing is multiplied by the sign of the check confidence and the sign of the extrinsic information to obtain the check node to variable node update information.

3. An improved min-sum based LDPC check confidence propagation decoding hardware implementation apparatus, comprising: It comprises: A storage module for storing the check confidence information block in the order of check nodes from small to large, storing the extrinsic information block, check confidence to variable node information block and posteriori information block in the order of variable nodes from small to large, and realizing block reading and writing and initialization of the information block under the control of the global control module; A check confidence cyclic shift module for performing cyclic right shift processing on the read check confidence information block to match the order of all variable nodes in the same decoding block; Three kinds of information parallel computation modules for performing parallel computation to generate a check node to variable node update information block, a posteriori information update information block and an extrinsic information update information block; The updating extrinsic information and extrinsic information cyclic shift module is used for combining the extrinsic information updating information block and the extrinsic information updating information block, and performing cyclic shift processing on the combined information block and then splitting the information block to match the order of all check nodes in the same decoding block. The check confidence updating information parallel computing module is used for parallel computing the minimum value and the second minimum value of the check confidence of all check nodes in the current decoding block based on the split information block, and outputting the check confidence updating information block in compressed storage form. The check equation verification module is used for verifying the check equation after the current decoding block is decoded, generating partial check results, and judging whether the decoding is successful according to the partial check results of all layer blocks. The global control module is used for controlling the modules to run in a pipeline mode, and providing check matrix related signals, scaling factor parameters, conditional offset factor selection parameters, storage module read-write addresses, shift module shift bit numbers, iteration start and termination signals, and module enable signals.

4. The decoding device of claim 3, wherein, The three information parallel computing modules include a check confidence to variable node information updating submodule, an a posteriori information updating submodule and an extrinsic information updating submodule, The computing submodules in the three information parallel computing modules perform numerical selection, numerical offset, numerical scaling and sign calculation operations, in which: In the numerical selection operation, a value is selected from the minimum value, the second minimum value of the check confidence of the check node and the absolute value of the extrinsic information of the corresponding variable node, if the minimum value is equal to the absolute value, the second minimum value is selected, otherwise, the smaller one of the minimum value and the absolute value is selected; In the numerical offset operation, if the selected value is the second minimum value and is equal to the minimum value, a first conditional offset factor is subtracted, if the selected value is the minimum value and is equal to the second minimum value, a second conditional offset factor is subtracted, and no numerical offset is performed in other cases; In the numerical scaling operation, the value after the numerical offset processing is multiplied by a scaling factor; In the sign calculation operation, the value after the numerical scaling processing is multiplied by the sign of the check confidence and the sign of the extrinsic information to obtain the updating information from the check node to the variable node.

5. The decoding device of claim 4, wherein, The storage module compressively stores the check confidence information block, only retains a single sign bit for the minimum value and the second minimum value, and prevents memory read-write conflict through a forward forwarding path to improve pipeline efficiency.

6. The decoding device of claim 4, wherein, The check confidence cyclic shift module dynamically adjusts the cyclic right shift number according to the structure of the check matrix to perform cyclic shift processing, so as to ensure that the information block is input into the computing module in the order of variable nodes from small to large.

7. The decoding device of claim 4, wherein, Each submodule in the three information parallel computing modules parallel processes the information block in the order of variable nodes from small to large, so as to improve decoding throughput.

8. The decoding device of claim 4, wherein, The updating extrinsic information and extrinsic information cyclic shift module dynamically adjusts the cyclic right shift number according to the structure of the check matrix to perform cyclic shift processing after combining the a posteriori information and the extrinsic information block, and inputs the split information block into the check confidence updating information parallel computing module and the check equation verification module in the order of check nodes from small to large.

9. The decoding device of claim 4, wherein, The check confidence update information parallel computing module outputs the check confidence update information block in compressed storage form after completing the check confidence minimum value and sub-minimum value calculation of the current decoding block, and writes back to the storage module.

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