Power system data processing method and device based on cryptographic algorithm, equipment, storage medium and program product

Abstract

The invention relates to a power system data processing method and device based on a cryptographic algorithm, equipment, a storage medium and a program product. The method comprises the following steps: acquiring power system data and service parameters of a power terminal, and screening a target cryptographic algorithm from a plurality of candidate encryption algorithms according to the service parameters; performing operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm, and processing the fused cryptographic algorithm according to a multi-emission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence; the out-of-order cryptographic algorithm sequence comprises a plurality of microinstruction packets; and adjusting the window depth of each microinstruction packet according to the power consumption time delay parameter of each microinstruction packet, and encrypting the power system data according to the adjusted microinstruction packet. According to the method, the target cryptographic algorithm is determined by collecting different service parameters of the power terminal, encryption processing can be flexibly performed on the power data according to different scenes and security levels, and the security of the power system in the data encryption processing process is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power systems, in particular to a power system data processing method and device based on a cryptographic algorithm, equipment, a storage medium and a program product. BACKGROUND

[0002] With the continuous improvement of informatization, the power terminal equipment in the power system as an important infrastructure carries a large amount of sensitive data and business operations. In order to ensure the security of the power system data, a post-quantum cryptographic algorithm is usually used to encrypt the power system data.

[0003] However, the security of the power system data encrypted by the traditional post-quantum cryptographic algorithm is low. SUMMARY

[0004] Therefore, it is necessary to provide a power system data processing method and device based on a cryptographic algorithm capable of improving the security of power system data.

[0005] In a first aspect, the present application provides a power system data processing method based on a cryptographic algorithm, comprising:

[0006] obtaining power system data and business parameters of a power terminal, and screening a target cryptographic algorithm from a plurality of candidate encryption algorithms according to the business parameters;

[0007] performing operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm, and processing the fused cryptographic algorithm according to a multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence; the out-of-order cryptographic algorithm sequence comprises a plurality of micro-instruction packets;

[0008] adjusting the window depth of each micro-instruction packet according to the power consumption and delay parameters of each micro-instruction packet, and performing encryption processing on the power system data according to the adjusted micro-instruction packets.

[0009] In one embodiment, the encryption processing on the power system data according to the adjusted micro-instruction packets comprises:

[0010] allocating a corresponding target time window for the power system data;

[0011] grouping a plurality of adjusted micro-instruction packets to obtain a plurality of groups of micro-instruction packets, and matching each group of micro-instruction packets with a corresponding operator domain and time window;

[0012] determining a target operator domain corresponding to the target time window according to the correspondence between each operator domain and each time window;

[0013] The power system data is encrypted in the target time window by using the microinstruction package in the target operator domain.

[0014] In one of the embodiments, the method further comprises:

[0015] Monitoring the load state of each operator domain and the state of the corresponding time window, and adjusting the operator domain and the time window according to a preset adjustment rule to obtain a new corresponding relationship between each operator domain and each time window;

[0016] The target operator domain corresponding to the target time window is determined according to the corresponding relationship between each operator domain and each time window, and the target time window corresponds to the target operator domain.

[0017] The target operator domain corresponding to the target time window is determined according to the new corresponding relationship between each operator domain and each time window.

[0018] In one of the embodiments, the operator-level fusion of the target cryptographic algorithm to obtain a fused cryptographic algorithm comprises:

[0019] If the type of the target cryptographic algorithm is lattice algorithm, the first target operator in the target cryptographic algorithm is integrated into a butterfly array, and a bypass register is arranged between any adjacent levels in the butterfly array to obtain the fused cryptographic algorithm; the first target operator includes a polynomial transformation operator, a coefficient multiplication operator and an inverse transformation operator.

[0020] If the type of the target cryptographic algorithm is encoding algorithm, the second target operator in the target cryptographic algorithm is integrated into a composite operator, and the composite operator is operated by time division multiplexing to obtain the fused cryptographic algorithm; the second target operator includes a companion calculation operator, a key equation solving operator and an error positioning polynomial root solving operator.

[0021] If the type of the target cryptographic algorithm is hash signature algorithm, the third target operator in the target cryptographic algorithm is integrated into a hash operator, and the hash operator is operated by two levels to obtain the fused cryptographic algorithm; the third target operator includes a tree node operator and a signature chain operator.

[0022] In one of the embodiments, the processing of the fused cryptographic algorithm according to the multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence comprises:

[0023] The fused cryptographic algorithm is decomposed into a plurality of initial microinstruction packages based on a preset decomposition rule.

[0024] The plurality of microinstruction packages are reordered by a multi-issue out-of-order pipeline to obtain the plurality of microinstruction packages, and a reordered cryptographic algorithm sequence is generated according to the plurality of microinstruction packages.

[0025] In one of the embodiments, the adjusting the window depth of each microinstruction package according to the power consumption and latency parameter of the microinstruction package comprises:

[0026] The power consumption and latency product of each microinstruction package is determined according to the power consumption and latency parameter of the microinstruction package.

[0027] The window depth of the microinstruction package with the power consumption and latency product greater than a preset threshold is reduced to obtain a reduced window depth; the power consumption and latency product of the microinstruction package corresponding to the reduced window depth is less than or equal to the preset threshold.

[0028] In one of the embodiments, the selecting the target cryptographic algorithm from the plurality of candidate cryptographic algorithms according to the service parameter comprises:

[0029] The service parameter is matched with the preset algorithm matrix to obtain the plurality of candidate cryptographic algorithms.

[0030] The priority of each candidate cryptographic algorithm is determined according to a preset priority factor; the preset priority factor comprises security strength, calculation period, energy consumption and error correction bit number.

[0031] The candidate cryptographic algorithm corresponding to the highest priority is determined as the target cryptographic algorithm.

[0032] In a second aspect, the present application further provides a power system data processing device based on a cryptographic algorithm, comprising:

[0033] A screening module is configured to obtain power system data and a service parameter of a power terminal, and select a target cryptographic algorithm from a plurality of candidate cryptographic algorithms according to the service parameter.

[0034] A fusion module is configured to perform operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm, and process the fused cryptographic algorithm according to a multi-issue out-of-order pipeline to generate a reordered cryptographic algorithm sequence; the reordered cryptographic algorithm sequence comprises a plurality of microinstruction packages.

[0035] An adjusting module is configured to adjust the window depth of each microinstruction package according to the power consumption and latency parameter of the microinstruction package, and perform encryption processing on the power system data according to the adjusted microinstruction package.

[0036] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0037] obtain power system data and service parameters of the power terminal, and select a target cryptographic algorithm from a plurality of candidate cryptographic algorithms according to the service parameters;

[0038] perform operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm, and process the fused cryptographic algorithm according to a multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence; the out-of-order cryptographic algorithm sequence comprises a plurality of micro-instruction packets;

[0039] adjust window depths of the micro-instruction packets according to power consumption and delay parameters of the micro-instruction packets, and perform encryption processing on the power system data according to the adjusted micro-instruction packets.

[0040] In a fourth aspect, the present application further provides a computer readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the following steps:

[0041] obtain power system data and service parameters of the power terminal, and select a target cryptographic algorithm from a plurality of candidate cryptographic algorithms according to the service parameters;

[0042] perform operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm, and process the fused cryptographic algorithm according to a multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence; the out-of-order cryptographic algorithm sequence comprises a plurality of micro-instruction packets;

[0043] adjust window depths of the micro-instruction packets according to power consumption and delay parameters of the micro-instruction packets, and perform encryption processing on the power system data according to the adjusted micro-instruction packets.

[0044] In a fifth aspect, the present application further provides a computer program product comprising a computer program, the computer program being executed by a processor to implement the following steps:

[0045] obtain power system data and service parameters of the power terminal, and select a target cryptographic algorithm from a plurality of candidate cryptographic algorithms according to the service parameters;

[0046] perform operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm, and process the fused cryptographic algorithm according to a multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence; the out-of-order cryptographic algorithm sequence comprises a plurality of micro-instruction packets;

[0047] adjust window depths of the micro-instruction packets according to power consumption and delay parameters of the micro-instruction packets, and perform encryption processing on the power system data according to the adjusted micro-instruction packets.

[0048] The power system data processing method and device based on a cryptographic algorithm, the computer device, the computer readable storage medium and the computer program product, first acquire power system data and service parameters of a power terminal, and filter a target cryptographic algorithm from a plurality of candidate cryptographic algorithms according to the service parameters; then perform operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm, and process the fused cryptographic algorithm according to a multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence; finally, adjust the window depth of each micro instruction packet according to the power consumption and delay parameters of each micro instruction packet, and encrypt the power system data according to the adjusted micro instruction packet. By collecting different service parameters of the power terminal, the target cryptographic algorithm is determined, which ensures that the power terminal can flexibly encrypt the power data according to different scenes and security levels, improves the security in the power system data encryption process; at the same time, based on the operator-level fusion and the window depth adjustment of the algorithm instruction, the optimal configuration for the target cryptographic algorithm is generated, which improves the operation efficiency of the power terminal and reduces unnecessary cost and energy consumption caused by resource waste. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other related drawings can be obtained by those skilled in the art without creative labor.

[0050] Figure 1 An application environment diagram of the power system data processing method based on a cryptographic algorithm in an embodiment;

[0051] Figure 2 A flowchart of the power system data processing method based on a cryptographic algorithm in an embodiment;

[0052] Figure 3 A flowchart of the power system data encryption processing in an embodiment;

[0053] Figure 4 A flowchart of the power system data encryption processing in another embodiment;

[0054] Figure 5 A flowchart of the operator-level fusion in an embodiment;

[0055] Figure 6 A flowchart of the out-of-order processing in an embodiment;

[0056] Figure 7 A flowchart of the window depth adjustment in an embodiment;

[0057] Figure 8 Flowchart of a process for screening a target cryptographic algorithm in an embodiment;

[0058] Figure 9 Flowchart of a process for power consumption and latency adjustment in an embodiment;

[0059] Figure 10 Flowchart of a process for fault self-recovery in an embodiment;

[0060] Figure 11 Flowchart of a process for generating a remote attestation token in an embodiment;

[0061] Figure 12 Flowchart of a process for a power system data processing method based on a cryptographic algorithm in another embodiment;

[0062] Figure 13 Block diagram of a structure of a power system data processing apparatus based on a cryptographic algorithm in an embodiment;

[0063] Figure 14 Internal structure diagram of a computer device in an embodiment. DETAILED DESCRIPTION

[0064] In order to make the purposes, technical solutions and advantages of the present application clearer, further detailed description will be given below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0065] It should be noted that the terms "first", "second", etc. used in the present application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "include" and "have" and any variations thereof used in the present application are intended to cover non-exclusive inclusion. The term "a plurality of" used in the present application means two or more. The term "and / or" used in the present application means one of the options or any combination of multiple options.

[0066] With the continuous improvement of informatization, power terminal devices in the power system as important infrastructure, carry a large amount of sensitive data and business operations. In order to ensure the security of power system data, the post-quantum cryptographic algorithm is usually used to encrypt the power system data. At present, in the power system, the traditional cryptographic algorithm is a general algorithm, and the data processing security is low for the special requirements of the power terminal device. In addition, the traditional cryptographic algorithm does not fully adapt to the hardware resource limitation of the power terminal device, resulting in waste of computing resources and latency.

[0067] In view of the above technical problems, the application embodiment provides a power system data processing method based on a cryptographic algorithm, which can improve the security of power system data.

[0068] The power system data processing method based on the cryptographic algorithm provided by the application embodiment can be applied to an application environment as shown in Figure 1 The processing device 102 is connected to the power system 104 by wire, and the processing device 102 is configured to perform encryption processing on power system data transmitted by the power system 104. In a specific application, when the power system 104 is running, the power system data to be processed is transmitted to the processing device 102 for encryption processing. The processing device 102 can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, Internet of Things devices, and portable wearable devices. The Internet of Things device can be a smart speaker, a smart television, a smart air conditioner, a smart vehicle device, a projection device, etc. The portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, etc. The head-mounted device can be a virtual reality (VR) device, an augmented reality (AR) device, smart glasses, etc.

[0069] In an exemplary embodiment, as shown in Figure 2 A power system data processing method based on a cryptographic algorithm is provided, and the embodiment takes the method applied to a processing device as an example. In the embodiment, the method includes the following steps.

[0070] S201, obtaining power system data and service parameters of a power terminal, and screening a target cryptographic algorithm from a plurality of candidate cryptographic algorithms according to the service parameters;

[0071] The power system data is parallel task data required to be processed by the power terminal, and the service parameters include at least any one of the following: a service type identifier, a real-time level field, a security level field, a service message length field, a chip temperature sampling value, and a channel error rate indication value. The service type identifier is used to distinguish between power distribution automation, distributed energy grid connection, load control, or fault recording service. The real-time level field indicates the upper limit of the end-to-end delay allowed by the service. The security level field indicates the required quantum security strength. The service message length field is used to evaluate the data volume of a single operation. The chip temperature sampling value is used for thermal constraint evaluation. The residual energy budget value is used for power consumption constraint evaluation. The channel error rate indication value is used for error correction capability requirement evaluation.

[0072] The types of the candidate encryption algorithms include lattice algorithms, encoding algorithms and hash signature algorithms, and can also include other data encryption algorithm types, which are not limited herein. The candidate encryption algorithms are represented in the form of a decision matrix. The target cryptographic algorithm is an algorithm for encrypting power system data.

[0073] In this embodiment, when the processing device acquires the power system data and the service parameters of the power terminal, the acquired data is written into the on-chip algorithm decision register group for storage, and the collected service parameters are matched with the plurality of candidate encryption algorithms in the decision matrix. The target cryptographic algorithm is selected from the plurality of candidate encryption algorithms that pass the matching.

[0074] By collecting multi-dimensional parameters such as the service type, real-time level, security level, message length, chip temperature, residual energy budget and channel bit error rate of the power system, accurate matching in terms of security strength, real-time performance, power consumption and error correction capability can be achieved when determining the target cryptographic algorithm, so as to ensure that the optimal configuration of area-power-time delay is dynamically achieved under the premise of quantum security, and the robustness and reliability of the power terminal under complex working conditions are improved.

[0075] S202, performing operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm, and processing the fused cryptographic algorithm according to a multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence; the out-of-order cryptographic algorithm sequence includes a plurality of micro-instruction packets;

[0076] The types of the target cryptographic algorithm include lattice algorithms, encoding algorithms and hash signature algorithms, and can also include other data encryption algorithm types, which are not limited herein. The fused cryptographic algorithm is an encryption algorithm composed of complex operators fused from basic operators in the target cryptographic algorithm. The multi-transmission out-of-order pipeline is an algorithm for out-of-order processing of instructions of the fused cryptographic algorithm. The plurality of micro-instruction packets in the out-of-order cryptographic algorithm sequence are not arranged according to the original time sequence.

[0077] In this embodiment, different target cryptographic algorithms have different basic operators, and the fusion of the basic operators reduces the data volume and improves the efficiency of power system data processing based on the cryptographic algorithm. However, different types of target cryptographic algorithms have different fusion methods. After the processing device acquires the target cryptographic algorithm, the type of the target cryptographic algorithm is determined, and the target cryptographic algorithm is processed according to the type to obtain a fused cryptographic algorithm. The fused cryptographic algorithm is processed in an out-of-order manner by a multi-transmission out-of-order pipeline, and each instruction in the fused cryptographic algorithm is rearranged in an out-of-order manner to obtain an out-of-order cryptographic algorithm sequence.

[0078] S203, adjusting the window depth of each micro-instruction packet according to the power consumption and delay parameters of each micro-instruction packet, and encrypting the power system data according to the adjusted micro-instruction packets.

[0079] The power consumption time delay parameter can be a power consumption time delay product. In particular, the power consumption time delay parameter is set by the control code generated by the power consumption time delay monitoring unit.

[0080] In this embodiment, after obtaining the out-of-order password algorithm sequence generated based on S204, the processing device compares the power consumption time delay product of each instruction package with a preset threshold, reduces the window depth of the micro instruction package and closes the non-critical clock tree branch when the power consumption time delay product is higher than the preset threshold, and encrypts the power system data by the adjusted micro instruction package to obtain a data processing result.

[0081] The power system data processing method based on a password algorithm in this embodiment first acquires power system data and service parameters of a power terminal, and selects a target password algorithm from a plurality of candidate encryption algorithms according to the service parameters; then performs operator-level fusion on the target password algorithm to obtain a fused password algorithm, and processes the fused password algorithm according to a multi-transmit out-of-order pipeline to generate an out-of-order password algorithm sequence; finally adjusts the window depth of each micro instruction package according to the power consumption time delay parameter of each micro instruction package, and encrypts the power system data according to the adjusted micro instruction package. By collecting different service parameters of the power terminal, the target password algorithm is determined to ensure that the power terminal can flexibly encrypt the power data according to different scenarios and security levels, improving the security during the power system data encryption process. At the same time, based on the operator-level fusion and the adjustment of the window depth of the algorithm instruction, the optimal configuration for the target password algorithm is generated, improving the operation efficiency of the power terminal and reducing unnecessary costs and energy consumption caused by resource waste.

[0082] In one exemplary embodiment, as shown in Figure 3 encrypting the power system data according to the adjusted micro instruction package includes:

[0083] S301, allocating a corresponding target time window for the power system data;

[0084] Each power system data is a concurrent task, and each concurrent task is allocated an independent target time window. In this embodiment, the processing device dynamically allocates an independent time window, i.e., a target time window, for each power system data based on the task priority and real-time demand for the obtained power system data. Alternatively, a corresponding target time window is allocated for each power system data at the same time.

[0085] Optionally, the second way is to sequentially assign each power system data with a corresponding target time window according to the time identifier of the power system data. For example, each power system data is assigned with a corresponding target time window according to the time sequence of the power system data.

[0086] Optionally, the third way is to assign each power system data with a corresponding target time window in a random order. For example, one or a group of data can be randomly selected from the power system data to assign a corresponding time window, and then one or a group of data can be randomly selected from the remaining power system data to assign a corresponding time window, until all the power system data have been assigned to a time window.

[0087] S302, grouping the plurality of adjusted micro-instruction packets to obtain a plurality of groups of micro-instruction packets, and matching each group of micro-instruction packets with a corresponding operation sub-domain and time window;

[0088] Each group of instruction packets is located in an operation sub-domain, each operation sub-domain has independent registers, caches and address spaces, and data of any operation sub-domain must be reviewed by an on-chip security unit when cross-domain access.

[0089] In this embodiment, the correspondence between the operation sub-domain and the time window is established, each operation sub-domain corresponds to a time window, that is, a time window exclusively occupies the operation resources of an operation sub-domain, and each operation sub-domain processes the power system data in the corresponding time window. When establishing the correspondence between the operation sub-domain and the time window, it is randomly set according to the actual scene requirements, which is not limited here.

[0090] In this embodiment, the plurality of adjusted micro-instruction packets are grouped, that is, the micro-instruction packets are divided into a plurality of physically isolated operation sub-domains, and the correspondence between the operation sub-domain and the time window is established to ensure that the power system data in each time window is processed quickly and specifically.

[0091] S303, determining a target operation sub-domain corresponding to the target time window according to the correspondence between each operation sub-domain and each time window;

[0092] In this embodiment, by traversing the correspondence between each operation sub-domain and each time window, the target time window is matched with the time window in the correspondence, and the operation resources corresponding to the matched time window are determined as the target operation sub-domain corresponding to the target time window.

[0093] S304, using the micro-instruction packet under the target operation sub-domain to perform encryption processing on the power system data in the target time window.

[0094] In the embodiment, after determining the target operator domain corresponding to the target time window, the processing device performs encryption processing on the power system data of the target time window based on the microinstruction package under the target operator domain.

[0095] By setting the target time window and the target operator domain for the power system data, an optimal hardware configuration of the target cryptographic algorithm is formed, the hardware execution efficiency in the power system data processing process is improved, the occupation of the computing resources, the power consumption and the time delay are minimized while ensuring the security of the power system data.

[0096] In an exemplary embodiment, as shown in Figure 4 The method further includes:

[0097] S401, monitoring the load state of each operator domain and the state of the corresponding time window, and adjusting the operator domain and the time window according to a preset adjustment rule to obtain a new corresponding relationship between each operator domain and each time window;

[0098] The preset adjustment rule can include any one or a combination of the following:

[0099] The priority preemption rule shortens the time window depth corresponding to the operator domain and switches the current processed power system data of the operator domain to a high-priority task when a new high-priority task arrives or the current task times out, and postpones the current processed power system data to after the high-priority task.

[0100] The load balancing rule migrates part of the tasks (with the lowest type proportion) of the operator domain to the operator domain with the lowest utilization rate if the instantaneous utilization rate of the operator domain is higher than the set upper limit.

[0101] The time delay convergence rule takes end-to-end time delay closed-loop feedback as input, increases or decreases the length of each time window by a certain proportion in each scheduling period until the time delay falls within a target interval, wherein the target interval is set according to actual scene requirements and is not limited herein.

[0102] The power consumption-aware rule forcibly reduces the depth of all time windows and closes the clock network of the idle operator domain when the overall power consumption of the chip exceeds a set threshold.

[0103] In the embodiment, the load state of each operator domain and the time window state are monitored in real time, the operator domain and the time window are adjusted by the preset adjustment rule, the corresponding relationship between the original operator domain and the time window changes, and a new corresponding relationship between each operator domain and each time window is obtained.

[0104] S402, determine a target operator domain corresponding to the target time window according to the correspondence between the new operator domains and the time windows.

[0105] In this embodiment, the correspondence between the new operator domains and the time windows is traversed, the target time window is matched with the time windows in the new correspondence, and the operator domain corresponding to the time window that is successfully matched is taken as the target operator domain corresponding to the target time window.

[0106] By adjusting the time window length and the allocation of the operator domain in real time through the preset adjustment rule, the end-to-end delay can be kept below the set threshold, thereby minimizing the occupation of computing resources, power consumption and delay, and improving the efficiency of power system data processing based on the cryptographic algorithm.

[0107] In one exemplary embodiment, as shown in Figure 5 The target cryptographic algorithm is integrated at the operator level to obtain a fused cryptographic algorithm, including:

[0108] S501, if the type of the target cryptographic algorithm is lattice algorithm, integrate a first target operator in the target cryptographic algorithm into a butterfly array, and set a bypass register between any adjacent levels in the butterfly array to obtain the fused cryptographic algorithm; the first target operator includes a polynomial transformation operator, a coefficient multiplication operator and an inverse transformation operator;

[0109] In this embodiment, when the type of the target cryptographic algorithm is lattice algorithm, the polynomial transformation, the coefficient multiplication and the inverse transformation are integrated into a single reconfigurable butterfly array, and an inter-stage bypass register is set inside the array, so that the intermediate results generated by the non-last level can be transmitted in zero waiting period.

[0110] S502, if the type of the target cryptographic algorithm is encoding algorithm, integrate a second target operator in the target cryptographic algorithm into a composite operator, and perform multi-stage operation on the composite operator through time division multiplexing to obtain the fused cryptographic algorithm; the second target operator includes a companion calculation operator, a key equation solving operator and an error positioning polynomial root finding operator;

[0111] The composite operator is a shared Galois field operation unit.

[0112] In this embodiment, when the type of the target cryptographic algorithm is encoding algorithm, the companion calculation, the key equation solving and the error positioning polynomial root finding are integrated into the composite operator of the shared Galois field operation unit, and multi-stage operation is completed through time division multiplexing of the same operation unit, thereby improving the efficiency of power system data processing based on the cryptographic algorithm.

[0113] S503, if the type of the target cryptographic algorithm is a hash signature algorithm, integrating a third target operator in the target cryptographic algorithm into a hash operator, performing two-level operation by multiplexing the hash operator, and obtaining a fused cryptographic algorithm; the third target operator includes a tree node operator and a signature chain operator.

[0114] The hash operator is a single-cycle multi-port composite operator. The signature chain operator is a one-time signature chain.

[0115] In this embodiment, when the type of the target cryptographic algorithm is a hash signature algorithm, the tree node and the one-time signature chain are compressed and integrated into a single-cycle multi-port hash operator, two-level operation is achieved by multiplexing the hash, the combination logic area is reduced, the occupation of computing resources and energy consumption are reduced, and the data processing efficiency of the power system based on the cryptographic algorithm is improved. In addition, in the tree construction process of the hash signature algorithm, a mixed traversal strategy of depth-first and breadth-first is adopted, and an on-chip loop buffer is combined to realize instant multiplexing of the tree node, so as to reduce the peak storage occupation on the chip.

[0116] In one exemplary embodiment, as shown in Figure 6 the fused cryptographic algorithm is processed according to a multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence, including:

[0117] S601, decomposing the fused cryptographic algorithm into a plurality of initial micro-instruction packages based on a preset decomposition rule;

[0118] The preset decomposition rule can be to decompose the fused cryptographic algorithm by using a micro-instruction scheduler of a token ring.

[0119] S602, performing out-of-order processing on the plurality of micro-instruction packages by the multi-transmission out-of-order pipeline to obtain a plurality of micro-instruction packages, and generating an out-of-order cryptographic algorithm sequence according to the plurality of micro-instruction packages.

[0120] The out-of-order processing includes executing parallel transmission matrix multiplication, sampling, hash and compression instructions on each micro-instruction package.

[0121] In this embodiment, by decomposing and out-of-order processing the fused cryptographic algorithm, the algorithm execution efficiency is improved, and the efficiency of the power system data is improved.

[0122] In one exemplary embodiment, as shown in Figure 7 the window depth of each micro-instruction package is adjusted according to the power consumption and delay parameters of each micro-instruction package, including:

[0123] S701, determining the power consumption and delay product of each micro-instruction package according to the power consumption and delay parameters of each micro-instruction package;

[0124] In this embodiment, the power consumption and delay product of the micro-instruction package is obtained by analyzing the power consumption and delay parameters.

[0125] S702, the window depth of the microinstruction package with the power consumption delay product greater than the preset threshold is reduced to obtain a reduced window depth; the power consumption delay product of the microinstruction package corresponding to the reduced window depth is less than or equal to the preset threshold.

[0126] In the embodiment, when the power consumption delay product is higher than the preset threshold, the time window depth of the microinstruction package is reduced. Optionally, the first way is to reduce the time window depth to a first value, at this time, it is checked whether the power consumption delay product of the microinstruction package is greater than the preset threshold. If the power consumption delay product is still greater than the preset threshold, the time window depth of the microinstruction package is continuously reduced until the power consumption delay product is equal to the preset threshold, the reduction operation is ended, and the non-critical clock tree branch is closed.

[0127] Optionally, the second way is to reduce the time window depth to a second value, the second value is less than the first value, at this time, it is checked whether the power consumption delay product of the microinstruction package is greater than the preset threshold. If the power consumption delay product is less than the preset threshold, the time window depth of the microinstruction package is continuously reduced until the power consumption delay product reaches a first preset threshold, the first preset threshold is less than the first preset threshold, the reduction operation is ended, and the non-critical clock tree branch is closed.

[0128] The time window depth of the microinstruction package is dynamically adjusted by the power consumption delay product, and the dynamic power consumption in the algorithm resource execution process is reduced.

[0129] In an exemplary embodiment, as shown in FIG. 1, a target cryptographic algorithm is selected from a plurality of candidate cryptographic algorithms according to service parameters, comprising: Figure 8

[0130] S801, the service parameters are matched with a preset algorithm matrix to obtain a plurality of candidate cryptographic algorithms;

[0131] The preset algorithm matrix is a decision matrix fixed in the chip. The preset algorithm matrix type includes lattice, coding, hash signature, and can also be other types of decision matrix, which is not limited herein. Each row of the preset algorithm matrix corresponds to an encryption algorithm, and each column corresponds to a parameter threshold interval.

[0132] In the embodiment, the column data of the preset algorithm matrix is taken as the matching object, and the service parameters are matched with the column data of the preset algorithm matrix respectively. If the parameter group falls into all threshold intervals of a column, the row data corresponding to the column data is marked as a candidate encryption algorithm.

[0133] S802, the priority of each candidate encryption algorithm is determined according to a preset priority factor; the preset priority factor includes security strength, calculation period, energy consumption and error correction bit number; ​

[0134] In the embodiment, preset priority factors are extracted from each candidate encryption algorithm, and a weighted sum is performed based on the preset weight factors and the preset priority factors, and the weighted sum result is determined as the priority of each candidate encryption algorithm. In actual execution, the preset weight factors corresponding to the security strength, the calculation period, the energy consumption and the number of error correction bits are adjusted in real time by the microcode according to the current security policy register, which is not limited herein.

[0135] S803, the candidate encryption algorithm corresponding to the highest priority is determined as the target cryptographic algorithm.

[0136] In the embodiment, the priorities of each candidate encryption algorithm are sorted in descending order, and the candidate encryption algorithm corresponding to the highest priority is determined as the target cryptographic algorithm. The target cryptographic algorithm identifier is written into the target algorithm latch, and if there is no encryption algorithm that can meet all the thresholds, the default fallback algorithm Kyber-768 is triggered.

[0137] By determining the target cryptographic algorithm, the targeted processing of different business scenarios of power system data can be realized, and the security of the power system data encryption process is improved.

[0138] In one exemplary embodiment, as shown in Figure 9 the method further comprises:

[0139] S901, in each operation sub-domain microinstruction packet scheduling period, the current power consumption value collected by the on-chip power consumption monitoring unit and the current end-to-end time delay value collected by the time delay monitoring unit are obtained;

[0140] S902, the power consumption value and the time delay value are input into the closed loop control logic, and the frequency adjustment signal, the voltage adjustment signal and the operation sub-domain enable or shutdown signal are output according to the preset power consumption time delay weight mapping relationship;

[0141] S903, according to the frequency adjustment signal, the voltage adjustment signal and the operation sub-domain enable or shutdown signal, the clock network, the power management unit and the operation sub-domain are adjusted in real time.

[0142] In the embodiment, the current power consumption value P and the task remaining time (current end-to-end latency value) T are monitored in real time, and the collected current power consumption value and current end-to-end latency value are input into the PID controller. The working voltage and frequency are dynamically adjusted by using the PID controller, and the product of P and T2 after each adjustment operation is calculated. When the product of P and T2 is the smallest, the frequency adjustment signal, the voltage adjustment signal, and the operation sub-domain enable / disable signal are output to obtain the adjustment instruction, and the clock network, the power management unit, and the operation sub-domain are adjusted based on the adjustment instruction. In particular, when T is lower than 200 µs and P is higher than 150 mW, the near-threshold voltage mode is automatically triggered, and the non-critical clock tree branch is turned off.

[0143] By adjusting the clock network, the power management unit, and the operation sub-domain in real time, the occupation of computing resources, power consumption, and latency are maximally reduced.

[0144] In an exemplary embodiment, as shown in Figure 10 the method further includes:

[0145] S1001, after the target cryptographic algorithm completes processing of the power system data, performing consistency verification on the calculation result;

[0146] S1002, if the verification fails for multiple times in succession, marking the target cryptographic algorithm as invalid, and triggering a context migration request;

[0147] S1003, migrating the context information of the invalid target cryptographic algorithm to a backup algorithm library, and restoring the execution of the target cryptographic algorithm, to complete fault self-recovery without stopping.

[0148] In the embodiment, the processing device performs consistency verification on the calculation result by the hardware self-checking unit after the execution of each instance of the target cryptographic algorithm is completed. If the verification fails for multiple times in succession, the instance of the target cryptographic algorithm is marked as invalid by the fault management unit, and a context migration request is triggered. The context information of the invalid instance of the target cryptographic algorithm is migrated to the backup algorithm library by using the multi-channel parallel arbitrator, and the execution of the target cryptographic algorithm is restored, to complete fault self-recovery without stopping. In specific execution, if the signature verification of any algorithm instance fails more than 3 times in succession, the instance is marked as “invalid”. The heterogeneous algorithm is immediately loaded from the backup algorithm area, and the session context is migrated by using the on-chip state synchronization register, and the migration time is ≤50 µs.

[0149] In an exemplary embodiment, as shown in Figure 11 the method further includes:

[0150] S1101, based on the execution result of the power system data and the chip internal metric information, jointly signing the metric digest, device identity and timestamp according to the post-quantum signature algorithm to form a remote attestation token;

[0151] S1102, encapsulating the remote attestation token into a standardized message and outputting it to the power master station through a secure channel for trusted verification.

[0152] In the embodiment, the remote attestation message can use Dilithium-based zero-knowledge range proof to ensure that the firmware version number and configuration parameters are verified without exposing the plaintext; the chip manufacturing batch ID, current temperature and cumulative power-on time are embedded in the remote attestation message to support device health assessment by the power master station. At the same time, the root key in the quantum secure non-volatile memory is used for signing to prevent key rollback under quantum attack.

[0153] By generating a remote attestation report, the entire process is ensured to be trusted and auditable.

[0154] The method of all the above embodiments also provides a power system data processing method based on a cryptographic algorithm, as shown in Figure 12 The method comprises:

[0155] S1201, obtaining power system data and service parameters of a power terminal, performing matching operation on the service parameters and a preset algorithm matrix to obtain a plurality of candidate encryption algorithms, and screening a target cryptographic algorithm from the plurality of candidate encryption algorithms.

[0156] S1202, performing operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm.

[0157] S1203, decomposing the fused cryptographic algorithm into a plurality of initial micro-instruction packets based on a preset decomposition rule; performing out-of-order processing on the plurality of micro-instruction packets through a multi-transmission out-of-order pipeline to obtain a plurality of micro-instruction packets, and generating an out-of-order cryptographic algorithm sequence according to the plurality of micro-instruction packets.

[0158] S1204, determining the power consumption and delay product of each micro-instruction packet according to the power consumption and delay parameters of each micro-instruction packet; reducing the window depth of the micro-instruction packet whose power consumption and delay product is greater than a preset threshold to obtain a reduced window depth.

[0159] S1205, a corresponding target time window is allocated for the power system data; a plurality of adjusted micro-instruction packages are grouped to obtain a plurality of groups of micro-instruction packages, and a corresponding operation sub-domain and a time window are matched for each group of micro-instruction packages; a target operation sub-domain corresponding to the target time window is determined according to the corresponding relationship between each operation sub-domain and each time window; and the micro-instruction packages under the target operation sub-domain are used to perform encryption processing on the power system data within the target time window.

[0160] S1206, the load state of each operation sub-domain and the state of the corresponding time window are monitored, and the operation sub-domain and the time window are adjusted according to a preset adjustment rule to obtain a new corresponding relationship between each operation sub-domain and each time window; and a target operation sub-domain corresponding to the target time window is determined according to the new corresponding relationship between each operation sub-domain and each time window.

[0161] The above steps are described in the foregoing embodiments, and the details are described in the foregoing content, which will not be repeated here.

[0162] In some embodiments, an anti-quantum attack power security chip for implementing the above technical solutions is also provided, which includes: an on-chip heterogeneous security infrastructure, the on-chip heterogeneous security infrastructure including a control area, an algorithm area and a storage area, each area being connected through a physically isolated bus interface;

[0163] A post-quantum cryptographic algorithm hardware acceleration engine is arranged in the algorithm area and is used to perform operator-level fusion and instruction-level scheduling.

[0164] A multi-channel parallel arbitrator is arranged in the control area and is used to realize the time domain-space domain double isolation scheduling.

[0165] A quantum security trusted root module is arranged in the control area and is used to generate and output the remote attestation report.

[0166] A quantum security non-volatile memory is arranged in the storage area, supports one-time writing and multiple reading, and is used to store a root key and a signature verification public key.

[0167] It should be understood that although each step in the flowchart involved in the above embodiments is shown in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in the above embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or steps or stages in other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and various non-contradictory schemes formed by the combination all belong to the scope of protection of the present application.

[0168] Based on the same inventive concept, the embodiments of the present application also provide a motor rotor broken bar fault detection device for implementing the above-mentioned motor rotor broken bar fault detection method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more motor rotor broken bar fault detection device embodiments provided below can refer to the limitations of the motor rotor broken bar fault detection method in the above text, which will not be repeated here.

[0169] In one exemplary embodiment, as shown in Figure 13 A motor rotor broken bar fault detection device is provided, comprising: a screening module 131, a fusion module 132, and an adjustment module 133, wherein:

[0170] The screening module 131 is configured to obtain power system data and service parameters of a power terminal, and screen a target cryptographic algorithm from a plurality of candidate cryptographic algorithms according to the service parameters;

[0171] The fusion module 132 is configured to perform operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm, and process the fused cryptographic algorithm according to a multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence; the out-of-order cryptographic algorithm sequence includes a plurality of micro-instruction packets;

[0172] The adjustment module 133 is configured to adjust the window depth of each micro-instruction packet according to the power consumption and delay parameters of each micro-instruction packet, and perform encryption processing on the power system data according to the adjusted micro-instruction packet.

[0173] In one exemplary embodiment, the above-mentioned adjustment module 133 comprises:

[0174] The allocation unit is configured to allocate a corresponding target time window for the power system data;

[0175] a grouping unit configured to group the plurality of adjusted micro-instruction packets to obtain a plurality of groups of micro-instruction packets, and match each group of micro-instruction packets with a corresponding operation sub-domain and time window;

[0176] a first determination unit configured to determine, according to a correspondence between each operation sub-domain and each time window, a target operation sub-domain corresponding to the target time window;

[0177] an encryption unit configured to perform encryption processing on the power system data within the target time window by using the micro-instruction packet under the target operation sub-domain.

[0178] In an exemplary embodiment, the adjusting module 133 further includes:

[0179] a monitoring unit configured to monitor a load state of each operation sub-domain and a state of the corresponding time window, and adjust the operation sub-domain and the time window according to a preset adjustment rule to obtain a new correspondence between each operation sub-domain and each time window;

[0180] a second determination unit configured to determine, according to the new correspondence between each operation sub-domain and each time window, a target operation sub-domain corresponding to the target time window.

[0181] In an exemplary embodiment, the fusion module 132 includes:

[0182] a first fusion module configured to, when the type of the target cryptographic algorithm is lattice algorithm, integrate a first target operator in the target cryptographic algorithm into a butterfly array, and set a bypass register between any adjacent levels in the butterfly array to obtain the fusion cryptographic algorithm; the first target operator includes a polynomial transformation operator, a coefficient multiplication operator, and an inverse transformation operator;

[0183] a second fusion module configured to, when the type of the target cryptographic algorithm is encoding algorithm, integrate a second target operator in the target cryptographic algorithm into a composite operator, and perform multi-stage operation on the composite operator through time division multiplexing to obtain the fusion cryptographic algorithm; the second target operator includes a companion calculation operator, a key equation solving operator, and an error positioning polynomial root finding operator;

[0184] a second fusion module configured to, when the type of the target cryptographic algorithm is hash signature algorithm, integrate a third target operator in the target cryptographic algorithm into a hash operator, and perform two-stage operation on the hash operator through multiplexing to obtain the fusion cryptographic algorithm; the third target operator includes a tree node operator and a signature chain operator.

[0185] In an exemplary embodiment, the fusion module 132 includes:

[0186] a decomposition unit, configured to decompose the fusion cryptographic algorithm into a plurality of initial micro-instruction packages based on a preset decomposition rule;

[0187] an out-of-order processing unit, configured to perform out-of-order processing on the plurality of micro-instruction packages through a multi-issue out-of-order pipeline to obtain a plurality of micro-instruction packages, and generate a sequence of out-of-order cryptographic algorithms according to the plurality of micro-instruction packages.

[0188] In an exemplary embodiment, the adjusting module 133 comprises:

[0189] a third determining unit, configured to determine a power consumption and latency product of each micro-instruction package according to a power consumption and latency parameter of the micro-instruction package;

[0190] a reducing unit, configured to reduce a window depth of the micro-instruction package whose power consumption and latency product is greater than a preset threshold to obtain a reduced window depth; the power consumption and latency product of the micro-instruction package corresponding to the reduced window depth is less than or equal to the preset threshold.

[0191] In an exemplary embodiment, the screening module 131 comprises:

[0192] performing matching operation on the service parameter and the preset algorithm matrix to obtain a plurality of candidate encryption algorithms;

[0193] determining a priority of each candidate encryption algorithm according to a preset priority factor; the preset priority factor comprises security strength, calculation period, energy consumption and error correction bit number;

[0194] determining the candidate encryption algorithm corresponding to the highest priority as the target cryptographic algorithm.

[0195] Each module in the power system data processing apparatus based on a cryptographic algorithm can be realized by software, hardware and a combination thereof in whole or in part. Each module can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a memory in a computer device in software form, so as to be called and executed by a processor to perform the operations corresponding to each module.

[0196] In an exemplary embodiment, a computer device is provided, which can be a server, and an internal structure diagram of the computer device can be as shown in Figure 14As shown in the figure. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through the system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capability. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store power system data. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with the terminal outside through network connection. The computer program is executed by the processor to realize a motor rotor broken bar fault detection method.

[0197] Those skilled in the art can understand that, Figure 14 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0198] In one exemplary embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the following steps:

[0199] Obtain power system data and service parameters of a power terminal, and select a target cryptographic algorithm from a plurality of candidate cryptographic algorithms according to the service parameters;

[0200] Fuse the target cryptographic algorithm at the operator level to obtain a fused cryptographic algorithm, and process the fused cryptographic algorithm according to a multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence; the out-of-order cryptographic algorithm sequence includes a plurality of micro-instruction packets;

[0201] Adjust the window depth of each micro-instruction packet according to the power consumption delay parameter of each micro-instruction packet, and encrypt the power system data according to the adjusted micro-instruction packet.

[0202] In one embodiment, the processor executing the computer program further implements the following steps:

[0203] Assign a corresponding target time window to the power system data;

[0204] The plurality of adjusted micro-instruction packages are grouped to obtain a plurality of groups of micro-instruction packages, and each group of micro-instruction packages is matched with a corresponding operator domain and a time window;

[0205] According to the correspondence between each of the operator domains and each of the time windows, a target operator domain corresponding to the target time window is determined;

[0206] The micro-instruction package under the target operator domain is used to perform encryption processing on the power system data within the target time window.

[0207] In one embodiment, the processor executing the computer program also implements the following steps:

[0208] The load state of each of the operator domains and the state of the corresponding time window are monitored, and the operator domains and the time windows are adjusted according to a preset adjustment rule to obtain a new correspondence between each of the operator domains and each of the time windows;

[0209] According to the correspondence between each of the operator domains and each of the time windows, a target operator domain corresponding to the target time window is determined.

[0210] In one embodiment, the processor executing the computer program also implements the following steps:

[0211] If the type of the target cryptographic algorithm is lattice algorithm, a first target operator in the target cryptographic algorithm is integrated into a butterfly array, and a bypass register is arranged between any adjacent levels in the butterfly array to obtain the fused cryptographic algorithm; the first target operator includes a polynomial transformation operator, a coefficient multiplication operator, and an inverse transformation operator;

[0212] If the type of the target cryptographic algorithm is encoding algorithm, a second target operator in the target cryptographic algorithm is integrated into a composite operator, and the composite operator is operated in multiple stages through time division multiplexing to obtain the fused cryptographic algorithm; the second target operator includes a companion calculation operator, a key equation solving operator, and an error positioning polynomial root solving operator;

[0213] If the type of the target cryptographic algorithm is hash signature algorithm, a third target operator in the target cryptographic algorithm is integrated into a hash operator, and two-level operation is performed through multiplexing of the hash operator to obtain the fused cryptographic algorithm; the third target operator includes a tree node operator and a signature chain operator.

[0214] In one embodiment, the processor executing the computer program also implements the following steps:

[0215] The fused cryptographic algorithm is decomposed into a plurality of initial micro-instruction packages based on a preset decomposition rule;

[0216] The plurality of micro-instruction packages are reordered by a multi-issue reorder pipeline to obtain the plurality of micro-instruction packages, and a reordered cryptographic algorithm sequence is generated according to the plurality of micro-instruction packages.

[0217] In one embodiment, the processor, when executing the computer program, also implements the following steps:

[0218] A power consumption and latency product of each micro-instruction package is determined according to a power consumption and latency parameter of the micro-instruction package;

[0219] The window depth of the micro-instruction package whose power consumption and latency product is greater than a preset threshold is reduced to obtain a reduced window depth; the power consumption and latency product of the micro-instruction package corresponding to the reduced window depth is less than or equal to the preset threshold.

[0220] In one embodiment, the processor, when executing the computer program, also implements the following steps:

[0221] The service parameter is matched with the preset algorithm matrix to obtain the plurality of candidate encryption algorithms;

[0222] A priority of each candidate encryption algorithm is determined according to a preset priority factor; the preset priority factor includes security strength, calculation period, energy consumption, and error correction bit number;

[0223] The candidate encryption algorithm corresponding to the highest priority is determined as the target cryptographic algorithm.

[0224] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, which, when executed by a processor, implements the steps in each method embodiment described above.

[0225] In one embodiment, a computer program product is provided, and the computer program product includes a computer program, which, when executed by a processor, implements the steps in each method embodiment described above.

[0226] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0227] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0228] The above-described embodiments are merely illustrative of several embodiments of the present application, which are described in more detail and in a specific manner, but should not be construed as limiting the scope of the patent of the present application. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A power system data processing method based on a cryptographic algorithm, characterized by, The method comprises: acquiring power system data and service parameters of a power terminal, and screening a target cryptographic algorithm from a plurality of candidate cryptographic algorithms according to the service parameters; performing operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm, and processing the fused cryptographic algorithm according to a multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence; the out-of-order cryptographic algorithm sequence comprises a plurality of micro-instruction packets; adjusting the window depth of each micro-instruction packet according to the power consumption and delay parameters of each micro-instruction packet, and performing encryption processing on the power system data according to the adjusted micro-instruction packets.

2. The method of claim 1, wherein, The encryption processing on the power system data according to the adjusted micro-instruction packets comprises: allocating a corresponding target time window for the power system data; grouping a plurality of adjusted micro-instruction packets to obtain a plurality of groups of micro-instruction packets, and matching each group of micro-instruction packets with a corresponding operator domain and time window; determining a target operator domain corresponding to the target time window according to the correspondence between each operator domain and each time window; performing encryption processing on the power system data in the target time window by using the micro-instruction packets in the target operator domain.

3. The method of claim 2, wherein, The method further comprises: monitoring the load state of each operator domain and the state of the corresponding time window, and adjusting the operator domains and the time windows according to a preset adjustment rule to obtain a new correspondence between each operator domain and each time window; The determination of the target operator domain corresponding to the target time window according to the correspondence between each operator domain and each time window comprises: determining the target operator domain corresponding to the target time window according to the new correspondence between each operator domain and each time window.

4. The method of claim 1, wherein, The operator-level fusion on the target cryptographic algorithm to obtain a fused cryptographic algorithm comprises: if the type of the target cryptographic algorithm is lattice algorithm, integrating a first target operator in the target cryptographic algorithm into a butterfly array, and setting a bypass register between any adjacent levels in the butterfly array to obtain the fused cryptographic algorithm; the first target operator comprises a polynomial transformation operator, a coefficient multiplication operator and an inverse transformation operator; if the type of the target cryptographic algorithm is encoding algorithm, integrating a second target operator in the target cryptographic algorithm into a composite operator, and performing multi-level operation on the composite operator through time division multiplexing to obtain the fused cryptographic algorithm; the second target operator comprises a companion calculation operator, a key equation solving operator and an error positioning polynomial root solving operator; if the type of the target cryptographic algorithm is hash signature algorithm, integrating a third target operator in the target cryptographic algorithm into a hash operator, and performing two-level operation on the hash operator through multiplexing to obtain the fused cryptographic algorithm; the third target operator comprises a tree node operator and a signature chain operator.

5. The method of claim 1, wherein, The processing of the fused cryptographic algorithm according to the multi-transmission out-of-order pipeline to generate an out-of-order cryptographic algorithm sequence comprises: decomposing the fused cryptographic algorithm into a plurality of initial micro-instruction packets based on a preset decomposition rule; The multiple microinstruction packages are reordered by a multiple emission reorder pipeline to obtain the multiple microinstruction packages, and a reorder cipher algorithm sequence is generated according to the multiple microinstruction packages.

6. The method of claim 1, wherein, The window depth of each microinstruction package is adjusted according to the power consumption and time delay parameter of each microinstruction package, including: The power consumption and time delay product of each microinstruction package is determined according to the power consumption and time delay parameter of each microinstruction package; The window depth of the microinstruction package with the power consumption and time delay product greater than a preset threshold is reduced to obtain a reduced window depth; the power consumption and time delay product of the microinstruction package corresponding to the reduced window depth is less than or equal to the preset threshold.

7. The method according to any one of claims 1 to 5, characterized in that, The target cipher algorithm is selected from multiple candidate cipher algorithms according to the service parameter, including: The service parameter is matched with the preset algorithm matrix to obtain the multiple candidate cipher algorithms; The priority of each candidate cipher algorithm is determined according to a preset priority factor; the preset priority factor includes security strength, calculation period, energy consumption and error correction bit number; The candidate cipher algorithm corresponding to the highest priority is determined as the target cipher algorithm.

8. A power system data processing apparatus based on a cryptographic algorithm, characterized by, The device includes: The screening module is configured to obtain power system data and a service parameter of a power terminal, and select a target cipher algorithm from multiple candidate cipher algorithms according to the service parameter; The fusion module is configured to perform operator-level fusion on the target cipher algorithm to obtain a fusion cipher algorithm, and process the fusion cipher algorithm according to a multiple emission reorder pipeline to generate a reorder cipher algorithm sequence; the reorder cipher algorithm sequence includes multiple microinstruction packages; The adjustment module is configured to adjust the window depth of each microinstruction package according to the power consumption and time delay parameter of each microinstruction package, and perform encryption processing on the power system data according to the adjusted microinstruction package. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8 when the computer program is executed by the processor. The processor executes the computer program to implement the steps of the method in any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 7.

Images