Semiconductor device and preparation method thereof, memory and memory system

Abstract

The invention provides a semiconductor device and a preparation method thereof, a memory and a storage system, the semiconductor device comprises a stacking structure and a channel structure, the stacking structure comprises gate layers and interlayer insulating layers which are alternately stacked, and the channel structure penetrates through the stacking structure along the stacking direction of the stacking structure. Wherein the channel structure comprises a first end, a second end and a turning part located between the first end and the second end in the stacking direction; the maximum size of the first end in the first direction is larger than the maximum size of the turning part in the first direction, the maximum size of the second end in the first direction is larger than or equal to the maximum size of the turning part in the first direction, and the first direction is perpendicular to the stacking direction. Therefore, the maximum size of the end parts (including the first end and the second end) of the channel structure is greater than or equal to the maximum size of the middle turning part, namely, the size of the end parts is increased, so that the performance of the semiconductor device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic devices, and more particularly, to a semiconductor device and a preparation method thereof, a memory and a storage system. BACKGROUND

[0002] NAND memory devices are non-volatile storage products with low power consumption, light weight and good performance, and have been widely used in electronic products. The planar structure of NAND devices has reached the limit of practical expansion. In order to further improve the storage capacity and reduce the storage cost per bit, 3D NAND memory is proposed. In the structure of 3D NAND memory, a vertical stacked multi-layer data storage unit is used to realize a stacked memory structure.

[0003] 3D NAND has become an inevitable trend to achieve higher storage density by thickening the stacked film layer. However, the decrease of the size of the channel hole or the bottom of the channel structure is strongly related to the increase of the aspect ratio, that is, as the aspect ratio increases, the size of the channel structure gradually decreases, and the bottom size is the smallest. This will result in too small size of the end of the channel structure, and ultimately affect the performance of the device. SUMMARY

[0004] The purpose of the present application is to provide a semiconductor device and a preparation method thereof, a memory and a storage system, which aims to increase the size of the end of the channel structure, thereby improving the performance of the device.

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] a stacked structure comprising gate layers and interlayer insulating layers alternately stacked;

[0007] a channel structure penetrating through the stacked structure along a stacking direction of the stacked structure;

[0008] wherein the channel structure comprises a first end, a second end and a turning portion between the first end and the second end along the stacking direction; the maximum size of the first end along a first direction is greater than the maximum size of the turning portion along the first direction, and the maximum size of the second end along the first direction is greater than or equal to the maximum size of the turning portion along the first direction, and the first direction is perpendicular to the stacking direction.

[0009] In some embodiments, the size of the first end to the turning portion along the stacking direction is greater than or equal to the size of the second end to the turning portion along the stacking direction.

[0010] In some embodiments, a maximum dimension of the channel structure along the first direction gradually decreases from the first end to the turn, and a maximum dimension of the channel structure along the first direction gradually decreases from the second end to the turn.

[0011] In some embodiments, a maximum dimension of the first end along the first direction is equal to a maximum dimension of the second end along the first direction.

[0012] In some embodiments, the gate layer comprises a bottom select gate layer and a control gate layer stacked along the stacking direction, the second end is located on a side of the bottom select gate layer away from the control gate layer, or the second end is located on a side of the control gate layer away from the bottom select gate layer.

[0013] In some embodiments, the channel structure comprises:

[0014] a first insulating layer extending along the stacking direction;

[0015] a channel layer surrounding the first insulating layer;

[0016] a storage layer surrounding the channel layer and located between the stack structure and the channel layer.

[0017] In a second aspect, the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0018] forming a stack layer comprising interlayer dielectric layers and interlayer insulating layers stacked alternately, the stack layer comprising a first side and a second side opposite to each other in a stacking direction of the stack structure;

[0019] performing an etching process from the first side to form an initial channel hole penetrating through the stack layer along the stacking direction;

[0020] performing a hole expanding process on an end of the initial channel hole close to the second side to form a channel hole, the channel hole comprising a first end close to the first side, a second end away from the first side, and a turn between the first end and the second end, a maximum dimension of the first end along a first direction is greater than a maximum dimension of the turn along the first direction, a maximum dimension of the second end along the first direction is greater than or equal to a maximum dimension of the turn along the first direction, and the first direction is perpendicular to the stacking direction.

[0021] In some embodiments, the step of forming the stack layer and the step of forming the initial channel hole comprise:

[0022] providing a first substrate;

[0023] forming a first stack layer and a second stack layer on the first substrate in sequence;

[0024] forming an initial trench hole by etching the second stack layer and the first stack layer in sequence, the initial trench hole comprising a first end close to the second stack layer and a second initial end away from the second stack layer, and the maximum dimension of the initial trench hole along the first direction gradually decreases from the first end to the second initial end.

[0025] In some embodiments, the step of forming a trench hole by enlarging one end of the initial trench hole close to the second side comprises:

[0026] filling a sacrificial layer in the initial trench hole;

[0027] forming a second substrate on a side of the second stack layer away from the first substrate;

[0028] removing the first substrate;

[0029] forming a trench hole by enlarging the second initial end of the initial trench hole, the trench hole comprising the first end, a second end, and a turning portion between the first end and the second end, the maximum dimension of the trench hole along the first direction gradually decreases from the first end to the turning portion, and the maximum dimension of the trench hole along the first direction gradually decreases or remains unchanged from the second end to the turning portion.

[0030] In some embodiments, the step of forming an initial trench hole by etching the second stack layer and the first stack layer in sequence comprises:

[0031] forming a first hard mask pattern layer on the second stack layer using a first mask plate;

[0032] performing a first etching on the second stack layer and the first stack layer in sequence using the first hard mask pattern layer.

[0033] In some embodiments, the step of forming a trench hole by enlarging the second initial end of the initial trench hole comprises:

[0034] forming a second hard mask pattern layer on a side of the stack layer close to the second initial end using a second mask plate;

[0035] performing a second etching on the sacrificial layer and the stack layer around the initial trench hole using the second hard mask pattern layer to remove part of the sacrificial layer and enlarge the size of the initial trench hole around the part of the sacrificial layer.

[0036] In some embodiments, the second mask and the first mask are the same mask, and a thickness of the second hard mask pattern layer along the stacking direction is less than a thickness of the first hard mask pattern layer along the stacking direction, and a depth of the second etching is less than a depth of the first etching.

[0037] In some embodiments, the step of forming the stack layer and the step of forming the initial trench hole comprise:

[0038] providing a first substrate;

[0039] forming a second stack layer and a first stack layer on the first substrate in sequence;

[0040] performing etching on the first stack layer and the second stack layer in sequence to form an initial trench hole, the initial trench hole comprising a first end close to the first stack layer and a second initial end away from the first stack layer, and a maximum dimension of the initial trench hole along the first direction gradually decreases from the first end to the second initial end.

[0041] In some embodiments, the step of performing a hole expansion process on an end of the initial trench hole close to the second side to form a trench hole comprises:

[0042] forming a second substrate on a side of the first stack layer away from the first substrate;

[0043] removing the first substrate;

[0044] performing a hole expansion process on the second initial end of the initial trench hole to form a trench hole, the trench hole comprising the first end, a second end, and a turning portion between the first end and the second end, a maximum dimension of the trench hole along the first direction gradually decreases from the first end to the turning portion, and a maximum dimension of the trench hole along the first direction gradually decreases or remains unchanged from the second end to the turning portion;

[0045] removing the second substrate;

[0046] forming a third substrate on a side of the second stack layer away from the first stack layer.

[0047] In a third aspect, the present application provides a memory, comprising:

[0048] the semiconductor device in any of the above embodiments;

[0049] a peripheral circuit connected with the semiconductor device.

[0050] In a fourth aspect, the present application provides a memory system, comprising:

[0051] The memory of the third aspect;

[0052] A controller connected with the memory, configured to control the memory to store data.

[0053] The application provides a semiconductor device and a preparation method thereof, a memory and a storage system. The semiconductor device comprises a stack structure and a channel structure. The stack structure comprises gate layers and interlayer insulating layers which are alternately stacked. The channel structure penetrates the stack structure along a stacking direction of the stack structure. The channel structure comprises a first end, a second end and a turning portion between the first end and the second end along the stacking direction. The maximum dimension of the first end along a first direction is greater than the maximum dimension of the turning portion along the first direction. The maximum dimension of the second end along the first direction is greater than or equal to the maximum dimension of the turning portion along the first direction. The first direction is perpendicular to the stacking direction. Therefore, the maximum dimension of the end portion (including the first end and the second end) of the channel structure is greater than or equal to the maximum dimension of the intermediate turning portion, that is, the size of the end portion is increased, so that the performance of the semiconductor device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0054] The technical solutions and other beneficial effects of the application will become apparent from the following detailed description of the application, taken in conjunction with the accompanying drawings.

[0055] Figure 1 is a structural schematic diagram of a semiconductor device provided by some embodiments of the application;

[0056] Figure 2 is a structural schematic diagram of a semiconductor device provided by some embodiments of the application; Figure 1 is a sectional structural schematic diagram of a semiconductor device in a planar direction perpendicular to the stacking direction;

[0057] Figure 3 is a flowchart of a preparation method of a semiconductor device provided by some embodiments of the application;

[0058] Figures 4a-4l is a structural schematic diagram of a semiconductor device in a preparation process provided by some embodiments of the application;

[0059] Figures 5a-5e is a structural schematic diagram of a semiconductor device in a preparation process provided by some embodiments of the application;

[0060] Figure 6 is a structural schematic diagram of a memory provided by some embodiments of the application;

[0061] Figure 7 is a structural schematic diagram of a storage system provided by some embodiments of the application. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0063] It should be understood that although the terms first, second, etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of the present application.

[0064] It should be understood that when one component is referred to as being "on" or "connected to" another component, it can be directly on or connected to the other component, or there can be an intervening component present. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0065] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have a thickness that is less than the thickness of the underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any set of horizontal planes between and at the top and bottom surfaces of a continuous structure. Layers can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and contact layers (in which contacts, interconnect lines, and / or vertical interconnect accesses (VIA) are formed) and one or more dielectric layers.

[0066] It should be noted that the diagrams in the embodiments of the present application only schematically illustrate the basic concept of the present application, and although only the components related to the present application are shown in the diagrams, the actual implementation is not drawn according to the number, shape and size of the components, and the actual implementation of each component can be arbitrarily changed in shape, number and proportion, and the layout pattern of the components can be more complex.

[0067] The directions are represented by Cartesian coordinates herein, in which "X" represents the stacking direction, "Y" represents the first direction, and "Z" represents the direction intersecting with "X" and "Y".

[0068] The semiconductor device in the present application can be a wafer or a three-dimensional memory, or a part of a three-dimensional memory. The three-dimensional memory can be applied to communication products, consumer electronics products, automotive products, aerospace products, artificial intelligence products, big data, etc. Among them, the consumer electronics products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses, game products, etc.

[0069] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of a semiconductor device provided by some embodiments of the present application. Please also refer to Figure 2 , Figure 2 is a structural schematic diagram of a semiconductor device provided by some embodiments of the present application Figure 1 is a cross-sectional structural schematic diagram of the semiconductor device in the vertical direction perpendicular to the stacking direction.

[0070] The semiconductor device 100 includes a stacking structure 10 and a channel structure 20, the stacking structure 10 includes gate layers 11 and interlayer insulating layers 12 stacked alternately, and the channel structure 20 penetrates the stacking structure 10 along a stacking direction (X) of the stacking structure 10. Among them, the channel structure 20 includes a first end 21, a second end 22 and a turning portion 23 between the first end 21 and the second end 22 along the stacking direction (X); the maximum dimension W1 of the first end 21 along a first direction (Y) is greater than the maximum dimension W2 of the turning portion 23 along the first direction (Y), and the maximum dimension W3 of the second end 22 along the first direction (Y) is greater than or equal to the maximum dimension W2 of the turning portion 23 along the first direction (Y), and the first direction (Y) is perpendicular to the stacking direction (X).

[0071] It should be noted that the "stacking direction (X)" refers to the stacking direction (X) of the gate layers 11 and the interlayer insulating layers 12, that is, the gate layers 11 and the interlayer insulating layers 12 are alternately stacked along the stacking direction (X). As shown in Figure 2 , the cross-sectional shape of the channel structure 20 can be circular or elliptical, and the maximum dimensions of different parts of the channel structure 20 (including the first end 21, the second end 22 and the turning portion 23) along the first direction (Y) can be compared to reflect the overall size of the channel structure 20 at this part.

[0072] In some embodiments, the material of the interlayer insulating layer 12 includes but is not limited to any one or a combination of silicon oxide, silicon nitride and silicon oxynitride. The gate layer 11 can include a conductive layer and a dielectric layer surrounding the conductive layer, the conductive layer can include metal (such as tungsten), and the dielectric layer can include a high-K dielectric layer (such as aluminum oxide).

[0073] The number of layers of the stack structure 10 determines the number of memory cells included in the first direction (Y). For example, the number of layers of the stack structure 10 can be 32 layers, 64 layers, 96 layers, 128 layers, etc., and the more the number of layers of the stack structure 10, the higher the integration of the corresponding three-dimensional memory. In the prior art, the size of the channel structure 20 along the first direction (Y) gradually decreases from top to bottom, so the more the number of layers of the stack structure 10, the smaller the size of the bottom of the channel structure 20, thereby affecting the performance of the channel structure 20. The semiconductor device 100 in the present application sets a turning portion 23 between the first end 21 and the second end 22, and sets the size of the first end 21 and the second end 22 to be greater than or equal to the size of the turning portion 23 between them, so that the size of the end portion can be increased, thereby improving the performance of the channel structure 20.

[0074] In some embodiments, the channel structure 20 includes a first insulating layer 201, a channel layer 202, and a storage layer 203. The first insulating layer 201 extends along the stacking direction (X), the channel layer 202 surrounds the first insulating layer 201, and the storage layer 203 surrounds the channel layer 202 and is located between the stack structure 10 and the channel layer 202. The storage layer 203 includes a tunnel insulating layer 2031 surrounding the channel layer 202, a charge trapping layer 2032 surrounding the tunnel insulating layer 2031, and a blocking insulating layer 2033 surrounding the charge trapping layer 2032. The exemplary materials of the blocking insulating layer 2033 and the tunnel insulating layer 2031 are silicon oxide, the exemplary material of the charge trapping layer 2032 is silicon nitride, forming an oxide-nitride-oxide (ONO) structure, and the exemplary structure of the channel layer 202 is polysilicon, but it can be understood that these layers can be selected from other materials.

[0075] In some embodiments, the size of the first end 21 to the turning portion 23 along the stacking direction (X) is greater than or equal to the size of the second end 22 to the turning portion 23 along the stacking direction (X). When the size of the first end 21 to the turning portion 23 along the stacking direction (X) is equal to the size of the second end 22 to the turning portion 23 along the stacking direction (X), the turning portion 23 is located at the center of the channel structure 20; when the size of the first end 21 to the turning portion 23 along the stacking direction (X) is greater than the size of the second end 22 to the turning portion 23 along the stacking direction (X), the position of the turning portion 23 relative to the first end 21 and the second end 22 is closer to the second end 22, i.e. the second end 22 is closer to the turning portion 23 than the first end 21.

[0076] In some embodiments, the maximum dimension of the channel structure 20 gradually decreases from the first end 21 to the turning portion 23 along the first direction (Y), and the maximum dimension of the channel structure 20 gradually decreases from the second end 22 to the turning portion 23 along the first direction (Y). That is, the dimension of the turning portion 23 along the first direction (Y) is the smallest. Therefore, in the fabrication process (see below), the channel structure 20 can be formed by two etching processes, one forward and one reverse, with the turning portion 23 being the endpoint of the second etching.

[0077] In some embodiments, the maximum dimension of the first end 21 along the first direction (Y) is equal to the maximum dimension of the second end 22 along the first direction (Y). Thus, the same mask can be used for etching in both etching processes described above.

[0078] In some embodiments, the gate layer 11 includes a bottom select gate layer 111 and a control gate layer 112 stacked along the stacking direction (X), with the second end 22 located on the side of the bottom select gate layer 111 away from the control gate layer 112; or the second end 22 is located on the side of the control gate layer 112 away from the bottom select gate layer 111.

[0079] like Figure 1 As shown, the gate layer 11 can be divided into a bottom select gate layer 111 and a control gate layer 112. For example, two gate layers 11 can be used as the bottom select gate layer 111, and the other gate layers 11 can be used as the control gate layer 112. Furthermore, the bottom select gate layer 111 can be located below the control gate layer 112 (near the first end 21) or above the control gate layer 112 (near the second end 22).

[0080] In some embodiments, the gate layer 11 may further include a top select gate layer (not shown) stacked with the control gate layer 112, that is, the top select gate layer and the bottom select gate layer 111 may be located on opposite sides of the control gate layer, and the bottom select gate layer 111 may be close to the first end 21, and the top select gate layer may be close to the second end 22.

[0081] In other embodiments, the top select gate layer may be close to the first end 21, and the bottom select gate layer 111 may be close to the second end 22.

[0082] The semiconductor device 100 provided by the embodiments of the present application comprises a stack structure 10 and a channel structure 20, the stack structure 10 comprises gate layers 11 and interlayer insulating layers 12 which are alternately stacked, and the channel structure 20 penetrates the stack structure 10 along a stacking direction (X) of the stack structure 10. The channel structure 20 comprises a first end 21, a second end 22 and a turning portion 23 between the first end 21 and the second end 22 along the stacking direction (X), the maximum dimension of the first end 21 along a first direction (Y) is greater than the maximum dimension of the turning portion 23 along the first direction (Y), and the maximum dimension of the second end 22 along the first direction (Y) is greater than or equal to the maximum dimension of the turning portion 23 along the first direction (Y), and the first direction (Y) is perpendicular to the stacking direction (X). Therefore, the turning portion 23 is arranged between the first end 21 and the second end 22 of the channel structure 20, and the maximum dimension of the end portion (including the first end 21 and the second end 22) of the channel structure 20 is greater than or equal to the maximum dimension of the turning portion 23, that is, the dimension of the end portion is increased, so that the performance of the semiconductor device 100 can be improved.

[0083] Please refer to Figure 3 , Figure 3 is a flowchart of a method for manufacturing a semiconductor device provided by some embodiments of the present application. Please refer to Figures 4a-4l , Figures 4a-4l is a structural diagram of a semiconductor device in a manufacturing process provided by some embodiments of the present application. The embodiments take the manufacturing of the semiconductor device 100 described above as an example to describe the manufacturing method of the semiconductor device 100, so please combine Figure 1 and Figure 2 , the manufacturing method of the semiconductor device 100 comprises the following steps S1-S3.

[0084] Step S1: forming a stack layer 10a, the stack layer 10a comprises interlayer dielectric layers 13 and interlayer insulating layers 12 which are alternately stacked, and the stack layer 10a comprises a first side 101 and a second side 102 which are opposite in the stacking direction (X) of the stack structure 10.

[0085] Step S2: performing etching process from the first side 101 to form an initial channel hole 30 which penetrates the stack layer 10a along the stacking direction (X).

[0086] Please refer to Figures 4a-4d , the steps S1 and S2 can comprise: 1) as shown in Figure 4a , first providing a first substrate 41; 2) as shown in Figure 4b , sequentially forming a first stack layer 110a and a second stack layer 120a on the first substrate 41; 3) as shown in Figures 4c-4dAs shown, the second stack layer 120a and the first stack layer 110a are sequentially etched to form an initial channel hole 30, the initial channel hole 30 includes a first end 21 close to the second stack layer 120a and a second initial end 22a away from the second stack layer 120a, and the maximum dimension of the initial channel hole 30 along the first direction (Y) gradually decreases from the first end 21 to the second initial end 22a.

[0087] For example, as shown in FIG. 1, a first hard mask layer M1 is first formed on the second stack layer 120a. Figure 4c As shown, a first hard mask layer M1 is first formed on the second stack layer 120a. Figure 4d As shown, a first hard mask layer M1 is first formed on the second stack layer 120a.

[0088] In some embodiments, the initial channel hole 30 can extend into part of the first substrate 41.

[0089] It should be noted that the medium layer 13 will be replaced by a gate layer in subsequent processes (after the formation of the channel structure), and the medium layer 13 in the first stack layer 110a becomes a control gate layer, and the medium layer 13 in the second stack layer 120a becomes a bottom selection gate layer.

[0090] Step S3: A hole expansion process is performed on an end of the initial channel hole 30 close to the second side 102 to form a channel hole 31, the channel hole 31 includes a first end 21 close to the first side 101, a second end 22 away from the first side 101, and a turning portion 23 between the first end 21 and the second end 22, and the maximum dimension W1 of the first end 21 along the first direction (Y) is greater than the maximum dimension W2 of the turning portion 23 along the first direction (Y), and the maximum dimension W3 of the second end 22 along the first direction (Y) is greater than or equal to the maximum dimension W2 of the turning portion 23 along the first direction (Y), and the first direction (Y) is perpendicular to the stacking direction (X).

[0091] In some embodiments, referring to FIG. 1, this step S3 can include the following steps: 1) as shown in FIG. 1, a first hard mask layer M1 is first formed on the second stack layer 120a. Figures 4e-4k Figure 4e ​filling a sacrificial layer 32 in the initial channel hole 30; 2) as shown in Figure 4f forming a second substrate 42 on the side of the second stack layer 120a away from the first substrate 41; 3) as shown in Figure 4g first substrate 41 is placed on the bottom and the second substrate 42 is placed on the top, then a part of the first substrate 41 can be removed by a wet etching process until the sacrificial layer 32 in the initial channel hole 30 is exposed; 4) as shown in Figures 4h-4k a channel hole 31 is formed by a reaming process on the second initial end 22a of the initial channel hole 30, the channel hole 31 includes a first end 21, a second end 22, and a turning portion 23 between the first end 21 and the second end 22, the maximum dimension of the channel hole 31 along the first direction (Y) gradually decreases from the first end 21 to the turning portion 23, and the maximum dimension of the channel hole 31 along the first direction (Y) gradually decreases or remains unchanged from the second end 22 to the turning portion 23.

[0092] For example, as shown in Figure 4h a second hard mask layer M2 is first formed on the second initial end 22a; as shown in Figure 4i a patterned photoresist PR is formed on the second hard mask layer M2 using a second mask plate, and a second hard mask pattern layer M2’ is formed on the side of the stack layer 10a close to the second initial end 22a (as shown in Figure 4j a second hard mask pattern layer M2’ is formed on the side of the stack layer 10a close to the second initial end 22a (as shown in Figure 4k the second hard mask pattern layer M2’ is used to perform a second etching on the sacrificial layer 32 and the stack layer 10a around the initial channel hole 30, to remove a part of the sacrificial layer 32 and enlarge the size of the initial channel hole 30 around the part of the sacrificial layer 32. The time of the second etching can be controlled, and the turning portion 23 is formed at the position where the second etching stops.

[0093] In some embodiments, the second mask plate and the first mask plate are the same mask plate, i.e., the opening size and shape of the first mask plate and the second mask plate are the same, so the size of the first end 21 and the second end 22 of the channel hole 31 formed is also the same, thereby making the size of the second end 22 larger than the size of the second initial end 22a, i.e., increasing the size of the end of the channel hole 31.

[0094] In some embodiments, the thickness of the second hard mask pattern layer M2’ along the stacking direction (X) is smaller than the thickness of the first hard mask pattern layer along the stack layer 10a, and the depth of the second etching is smaller than the depth of the first etching, so the distance of the turning portion 23 from the second end 22 is smaller than the distance of the turning portion 23 from the first end 21.

[0095] Referring to Figure 4l andFigure 1 The method for manufacturing the semiconductor device 100 further includes: removing the remaining sacrificial layer 32; and sequentially forming a storage layer 203, a channel layer 202, and a first insulating layer 201 in the channel hole 31, thereby forming a channel structure 20.

[0096] The method for manufacturing the semiconductor device provided by the embodiments of the present application forms the first stack layer 110a and then the second stack layer 120a (for forming a bottom select gate layer) when forming the stack layer 10a, and then performs first etching, so that an initial channel hole 30 with a larger size can be formed at one end close to the second stack layer 120a. Then, the structure is flipped, and second etching is performed at the side far away from the second stack layer 120a, so that a channel hole 31 with a larger size can be formed at the other end. Through the two etching processes, the two ends of the channel hole 31 have a larger size, and thus the performance of the channel structure 20 is improved.

[0097] Please refer to Figures 5a-5e , Figures 5a-5e is a structural schematic diagram of a semiconductor device provided by some embodiments of the present application in a manufacturing process. For the convenience of understanding and brief description, the same structure as that of the above embodiments continues to use the same reference numerals, and the same structure will not be described in detail, and the present embodiment only describes the different structure in detail.

[0098] The difference between the present embodiment and the above embodiments is the specific steps of steps S1-S3. In specific embodiments, steps S1 and S2 can include: 1) as shown in Figure 5a , providing a first substrate 41; 2) as shown in Figure 5a , sequentially forming a second stack layer 120a and a first stack layer 110a on the first substrate 41; 3) as shown in Figure 5b , sequentially etching the first stack layer 110a and the second stack layer 120a to form an initial channel hole 30, the initial channel hole 30 includes a first end 21 close to the first stack layer 110a and a second initial end 22a far away from the first stack layer 110a, and the maximum size of the initial channel hole 30 along the first direction (Y) gradually decreases from the first end 21 to the second initial end 22a.

[0099] In some embodiments, step S3 can include: 1) as shown in Figure 5c , first filling a sacrificial layer 32 in the initial channel hole 30, and then forming a second substrate 42 on the side of the first stack layer 110a far away from the first substrate 41; 2) as shown in Figure 5c , removing the first substrate 41; 3) as shown in Figure 5dAs shown, a hole expansion process is performed on the second initial end 22a of the initial channel hole 30 to form a channel hole 31, the channel hole 31 includes the first end 21, the second end 22, and the turning portion 23 between the first end 21 and the second end 22, the maximum dimension of the channel hole 31 along the first direction (Y) gradually decreases from the first end 21 to the turning portion 23, and the maximum dimension of the channel hole 31 along the first direction (Y) gradually decreases or remains unchanged from the second end 22 to the turning portion 23; 4) as shown Figure 5e As shown, the second substrate 42 is removed; 5) as shown Figure 5e As shown, the channel structure 20 is formed in the channel hole 31 first, and then the third substrate 43 is formed on the side of the second stack layer 120a away from the first stack layer 110a.

[0100] In the preparation method of the semiconductor device provided by the embodiments of the present application, the second stack layer 120a (used for forming a bottom select gate layer) is formed first in the process of forming the stack layer 10a, then the first stack layer 110a is formed, then the first etching is performed on the side of the first stack layer 110a, then the second etching is performed on the side of the second stack layer 120a, and finally the third substrate 43 is formed on the side of the second stack layer 120a, so that the channel structure 20 with large end size and small turning portion 23 size can be formed, the end size of the channel structure 20 is increased, and the performance of the device is improved.

[0101] Please refer to Figure 6 , Figure 6 is a structure diagram of a memory provided by some embodiments of the present application. The memory 200 can be a three-dimensional memory, such as a 3D NAND, 3D NOR memory.

[0102] The memory 200 includes a semiconductor device 201 and a peripheral circuit 202, the semiconductor device 201 can be any one of the semiconductor devices in the above embodiments, and the peripheral circuit 202 can be various control structures composed of COMS (complementary metal oxide semiconductor). The peripheral circuit 202 is connected with the semiconductor device 201 to transmit signals with the semiconductor device 201. The peripheral circuit 202 can be used for logic operation and control and detection of the switching state of each storage unit in the above semiconductor device 201 through metal wiring, to realize data storage and reading.

[0103] The semiconductor device 201 includes a stack structure including gate layers and interlayer insulating layers alternately stacked, and a channel structure penetrating the stack structure in a stacking direction of the stack structure. The channel structure includes a first end, a second end, and a turn portion between the first end and the second end in the stacking direction. A maximum dimension of the first end in a first direction perpendicular to the stacking direction is greater than a maximum dimension of the turn portion in the first direction, and a maximum dimension of the second end in the first direction is greater than or equal to the maximum dimension of the turn portion in the first direction.

[0104] Referring to Figure 7 , Figure 7 is a structural schematic diagram of a storage system provided by some embodiments of the present application. The storage system 300 includes a memory 301 and a controller 302. The memory 301 can be any of the memories in the above embodiments, and can include any of the semiconductor devices in the above embodiments. The controller 302 is connected to the memory 301 and is configured to control the memory 301 to store data. The memory 301 can perform the operation of storing data based on the control of the controller 302.

[0105] In some embodiments, the storage system can be implemented as a universal flash storage (UFS) device, a solid state disk (SSD), a multimedia card in the form of an RS-MMC, an eMMC, an MMC, a micro-SD, a secure digital (SD) card in the form of an SD, a mini-SD, and a micro-SD, a storage device in the form of a personal computer memory card international association (PCMCIA) card, a storage device in the form of a peripheral component interconnect (PCI), a storage device in the form of a high-speed PCI (PCI-E), a compact flash (CF) card, a smart media card, or a memory stick, etc.

[0106] The semiconductor device in the memory 301 includes a stack structure including gate layers and interlayer insulating layers alternately stacked, and a channel structure penetrating the stack structure in a stacking direction of the stack structure. The channel structure includes a first end, a second end, and a turn portion between the first end and the second end in the stacking direction. A maximum dimension of the first end in a first direction perpendicular to the stacking direction is greater than a maximum dimension of the turn portion in the first direction, and a maximum dimension of the second end in the first direction is greater than or equal to the maximum dimension of the turn portion in the first direction.

[0107] The above descriptions of the embodiments are only used to help understand the technical solutions of the present application and the core ideas thereof; it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can still be modified, or the equivalent replacement can be made to the technical features thereof; and the modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a stack structure comprising gate layers and interlayer insulating layers stacked alternately; a channel structure penetrating through the stack structure along a stacking direction of the stack structure; wherein the channel structure comprises a first end, a second end and a turning portion between the first end and the second end along the stacking direction; a maximum dimension of the first end along a first direction is greater than a maximum dimension of the turning portion along the first direction, and a maximum dimension of the second end along the first direction is greater than or equal to the maximum dimension of the turning portion along the first direction, the first direction being perpendicular to the stacking direction.

2. The semiconductor device according to claim 1, wherein A dimension of the first end to the turning portion along the stacking direction is greater than or equal to a dimension of the second end to the turning portion along the stacking direction.

3. The semiconductor device of claim 1, wherein A maximum dimension of the channel structure along the first direction gradually decreases from the first end to the turning portion, and a maximum dimension of the channel structure along the first direction gradually decreases from the second end to the turning portion.

4. The semiconductor device of claim 1, wherein The maximum dimension of the first end along the first direction is equal to the maximum dimension of the second end along the first direction.

5. The semiconductor device of claim 2, wherein, The gate layer comprises a bottom select gate layer and a control gate layer stacked along the stacking direction, the second end is located on a side of the bottom select gate layer away from the control gate layer, or the second end is located on a side of the control gate layer away from the bottom select gate layer.

6. The semiconductor device of claim 1, wherein The channel structure comprises: a first insulating layer extending along the stacking direction; a channel layer surrounding the first insulating layer; a storage layer surrounding the channel layer and located between the stack structure and the channel layer.

7. A method of manufacturing a semiconductor device, characterized by The method for manufacturing the semiconductor device comprises: forming a stack layer comprising interlayer dielectric layers and interlayer insulating layers stacked alternately, the stack layer comprising a first side and a second side opposite to each other along a stacking direction of the stack structure; performing an etching process from the first side to form an initial channel hole penetrating through the stack layer along the stacking direction; performing a hole expanding process on an end of the initial channel hole close to the second side to form a channel hole, the channel hole comprising a first end close to the first side, a second end away from the first side and a turning portion between the first end and the second end, and a maximum dimension of the first end along a first direction is greater than a maximum dimension of the turning portion along the first direction, and a maximum dimension of the second end along the first direction is greater than or equal to the maximum dimension of the turning portion along the first direction, the first direction being perpendicular to the stacking direction.

8. The method of producing a semiconductor device according to Claim 7, wherein The step of forming the stack layer and the step of forming the initial channel hole comprise: providing a first substrate; forming a first stack layer and a second stack layer on the first substrate in sequence; performing etching on the second stack layer and the first stack layer in sequence to form an initial channel hole, the initial channel hole comprising a first end close to the second stack layer and a second initial end away from the second stack layer, and a maximum dimension of the initial channel hole along a first direction gradually decreases from the first end to the second initial end.

9. The method of producing a semiconductor device according to claim 8, wherein The step of performing a hole expansion process on an end of the initial via hole close to the second side to form a via hole, comprises: filling a sacrificial layer in the initial via hole; forming a second substrate on a side of the second stack layer away from the first substrate; removing the first substrate; performing a hole expansion process on the second initial end of the initial via hole to form a via hole, the via hole comprising the first end, a second end and a turning portion between the first end and the second end, the maximum dimension of the via hole along the first direction gradually decreases from the first end to the turning portion, and the maximum dimension of the via hole along the first direction gradually decreases or remains unchanged from the second end to the turning portion.

10. The method of producing a semiconductor device according to Claim 9, wherein The step of etching the second stack layer and the first stack layer in sequence to form an initial via hole, comprises: forming a first hard mask pattern layer on the second stack layer using a first mask plate; performing a first etching on the second stack layer and the first stack layer in sequence using the first hard mask pattern layer.

11. The method of producing a semiconductor device according to claim 10, wherein The step of performing a hole expansion process on the second initial end of the initial via hole to form a via hole, comprises: forming a second hard mask pattern layer on a side of the stack layer close to the second initial end using a second mask plate; performing a second etching on the sacrificial layer and the stack layer around the initial via hole using the second hard mask pattern layer to remove part of the sacrificial layer and expand the size of the initial via hole around the part of the sacrificial layer.

12. The method of producing a semiconductor device according to Claim 11, wherein The second mask plate and the first mask plate are the same mask plate, and the thickness of the second hard mask pattern layer along the stacking direction is less than the thickness of the first hard mask pattern layer along the stacking layer, and the depth of the second etching is less than the depth of the first etching.

13. The method of producing a semiconductor device according to Claim 7, wherein The step of forming a stack layer and the step of forming the initial via hole, comprises: providing a first substrate; forming a second stack layer and a first stack layer on the first substrate in sequence; performing etching on the first stack layer and the second stack layer in sequence to form an initial via hole, the initial via hole comprising a first end close to the first stack layer and a second initial end away from the first stack layer, and the maximum dimension of the initial via hole along the first direction gradually decreases from the first end to the second initial end.

14. The method of producing a semiconductor device according to Claim 13, wherein The step of performing a hole expansion process on an end of the initial via hole close to the second side to form a via hole, comprises: forming a second substrate on a side of the first stack layer away from the first substrate; removing the first substrate; performing a hole expansion process on the second initial end of the initial via hole to form a via hole, the via hole comprising the first end, a second end and a turning portion between the first end and the second end, the maximum dimension of the via hole along the first direction gradually decreases from the first end to the turning portion, and the maximum dimension of the via hole along the first direction gradually decreases or remains unchanged from the second end to the turning portion; removing the second substrate; forming a third substrate on a side of the second stack layer away from the first stack layer.

15. A memory, comprising: Comprises: The semiconductor device of any one of claims 1-6; The semiconductor device of any one of claims 1-6; A peripheral circuit connected to the semiconductor device.

16. A storage system, characterized by Comprising: The memory of claim 15; A controller connected to the memory for controlling the memory to store data.

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