Three-dimensional embedded nonvolatile memory, manufacturing method, chip, device and equipment

Abstract

The invention relates to a three-dimensional embedded nonvolatile memory, a manufacturing method, a chip, a device and equipment, a plurality of memory layers are vertically stacked, each memory layer comprises a plurality of self-selection memories, so that more self-selection memories can be integrated in a unit area through a vertically stacked three-dimensional framework, the memory capacity is improved, and the memory performance is improved. According to the method, the high-density storage requirement can be met, for example, the storage requirement of a large language model can be met, in-memory calculation and near-memory calculation are supported, and high-bandwidth and low-delay matrix vector multiplication acceleration capacity is achieved; according to the self-selection memory, self-selection storage can be realized when the threshold voltage is reached, extra area overhead caused by introduction of a transistor is avoided, the area of a single memory is reduced, the structure of a storage layer is simplified, and the integration level of the memory is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a three-dimensional embedded nonvolatile memory, a manufacturing method, a chip, an apparatus and a device. BACKGROUND

[0002] With the rapid development of the Internet of Things, artificial intelligence, data centers and other fields, higher requirements are put forward for the density, speed energy efficiency and integration of memories. For example, edge inference tasks require a certain amount of storage capacity (storage density) within a certain area, and the capacity of on-chip integrated static random access memory (SRAM) is limited, and it is necessary to load the weights on the off-chip dynamic random access memory (DRAM), which brings huge energy consumption overhead. Storing weights on-chip can greatly improve energy efficiency and bandwidth.

[0003] Resistive random access memory (RRAM) has the advantages of non-volatility, low power consumption, and compatibility with CMOS post-process, and has good application prospects in the field of weight storage. However, the current mainstream RRAM architecture is a 1T1R architecture (1 transistor and 1 resistive memory cell), which has bottlenecks in array miniaturization and three-dimensional integration, limiting its large-scale three-dimensional integration in storage or computing systems. SUMMARY

[0004] Therefore, it is necessary to provide a three-dimensional embedded nonvolatile memory, a manufacturing method, a chip, an apparatus and a device to solve the problems in the prior art.

[0005] In a first aspect, the present application provides a three-dimensional embedded nonvolatile memory, which is integrated with a logic chip; the three-dimensional embedded nonvolatile memory comprises a plurality of vertically stacked storage layers;

[0006] Each of the storage layers comprises:

[0007] a first selection line extending along a first direction and being arranged at intervals along a second direction;

[0008] a second selection line extending along the second direction and being arranged at intervals along the first direction, the first direction intersecting the second direction;

[0009] Self-selecting memory devices are arranged at intersections of the first selection lines and the second selection lines in a vertical direction, between the first selection lines and the second selection lines, and each of the self-selecting memory devices includes at least one functional layer.

[0010] Optionally, adjacent layers of the memory layers in the vertical direction share the first selection lines or share the second selection lines.

[0011] Optionally, when adjacent layers of the memory layers share the first selection lines, the self-selecting memory devices in the same column are independently addressed and operated by different second selection lines.

[0012] When adjacent layers of the memory layers share the second selection lines, the self-selecting memory devices in the same row are independently addressed and operated by different first selection lines.

[0013] Optionally, the self-selecting memory devices include a first functional layer and a second functional layer stacked in the vertical direction, one of the first functional layer and the second functional layer is a gating layer, and the other is a resistive switching layer.

[0014] The resistive switching layer is reversibly switchable between a high resistance state and a low resistance state to store data.

[0015] The gating layer is used to control the on-off of current in the self-selecting memory devices to turn on the current path of the selected self-selecting memory devices during read-write operations.

[0016] Optionally, the material of the gating layer includes at least one of niobium oxide and vanadium oxide.

[0017] The material of the resistive switching layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, hafnium aluminum oxide.

[0018] Optionally, the self-selecting memory devices further include at least one auxiliary functional layer selected from at least one of the following:

[0019] A heat transfer layer is arranged between the first functional layer and the second functional layer, and the thermal conductivity of the heat transfer layer is less than that of the resistive switching layer.

[0020] A barrier layer is arranged between the functional layer and the first selection lines to form a potential barrier with the first selection lines, or arranged between the functional layer and the second selection lines to form a potential barrier with the second selection lines.

[0021] A buffer layer is arranged between the functional layer and the barrier layer, and the electron affinity of the buffer layer is between that of the functional layer and that of the barrier layer.

[0022] a first electrode layer and a second electrode layer, the first electrode layer is arranged between the first functional layer and the first selection line, and the second electrode layer is arranged between the second functional layer and the second selection line;

[0023] a diffusion barrier layer, which is in contact with the first selection line or the second selection line.

[0024] Optionally, the three-dimensional embedded nonvolatile memory further comprises:

[0025] a sidewall passivation layer covering sidewalls of the self-selecting memory;

[0026] a conductive plug arranged on a top surface of the self-selecting memory, the self-selecting memory being connected to the first selection line or the second selection line above it through the conductive plug.

[0027] In a second aspect, the present application provides an edge-end chip, comprising a substrate and a logic chip and a three-dimensional embedded nonvolatile memory integrated on the substrate, as described in the first aspect.

[0028] The three-dimensional embedded nonvolatile memory is arranged on the logic chip, or the three-dimensional embedded nonvolatile memory and the logic chip are arranged on the substrate respectively.

[0029] In a third aspect, the present application provides an electronic device, comprising a three-dimensional embedded nonvolatile memory as described in the first aspect, or an edge-end chip as described in the second aspect.

[0030] In a fourth aspect, the present application provides a manufacturing method of a three-dimensional embedded nonvolatile memory, comprising:

[0031] forming a plurality of first selection lines on a substrate, the first selection lines extending along a first direction and being arranged at intervals along a second direction;

[0032] forming a plurality of self-selecting memories on a side of the first selection lines away from the substrate, the self-selecting memories being arrayed along the first direction and the second direction; the self-selecting memories comprising functional layers;

[0033] forming a plurality of second selection lines on a side of the self-selecting memories away from the first selection lines, the second selection lines extending along the second direction and being arranged at intervals along the first direction; the plurality of first selection lines, the plurality of self-selecting memories and the plurality of second selection lines forming a storage layer;

[0034] repeating the steps of forming the plurality of first selection lines, forming the plurality of self-selecting memories and forming the plurality of second selection lines to form a plurality of vertically stacked storage layers.

[0035] Optionally, forming the memory layer comprises:

[0036] forming a first selection material layer and a functional stack on the substrate, the functional stack comprising at least a first functional layer and a second functional layer;

[0037] etching the functional stack and the first selection material layer to form a first trench extending along the first direction, and dividing the first selection material layer into a plurality of first selection lines;

[0038] forming a second selection material layer covering a top surface of the functional stack;

[0039] etching the second selection material layer and the functional stack to form a second trench extending along the second direction, and dividing the second selection material layer into a plurality of second selection lines; the first trench and the second trench divide the functional stack into a plurality of self-selecting memories; one of the first functional layer and the second functional layer of the self-selecting memory is a resistive switching layer, and the other is a gating layer.

[0040] Optionally, forming the memory layer comprises:

[0041] forming a first selection material layer on the substrate, and etching the first selection material layer to form a plurality of first selection lines;

[0042] forming a functional stack covering a top surface of the first selection material layer, the functional stack comprising at least a first functional layer and a second functional layer;

[0043] patterning and etching the functional stack to form a plurality of self-selecting memories on a side of the first selection lines away from the substrate; one of the first functional layer and the second functional layer of the self-selecting memory is a resistive switching layer, and the other is a gating layer;

[0044] forming a second selection material layer on a side of the self-selecting memory away from the first selection lines, and etching the second selection material layer to form a plurality of second selection lines.

[0045] Optionally, adjacent layers of the memory layer in a vertical direction share the first selection lines or share the second selection lines.

[0046] Optionally, the substrate is a logic chip formed with a CMOS circuit.

[0047] The three-dimensional embedded non-volatile memory, manufacturing method, chip and device of the present application can integrate more self-selecting memories in a unit area through vertically stacking multiple storage layers, each of which contains multiple self-selecting memories, thereby improving the storage capacity to meet the high-density storage demand, such as the storage demand of edge-end or cloud large language models, supporting in-memory computing and near-memory computing, and having high-bandwidth, low-latency matrix-vector multiplication acceleration capability; the self-selecting memory can realize self-selection storage when reaching the turn-on voltage, without the need for additional gating devices and corresponding integration, thereby reducing the occupied area of a single self-selecting memory, simplifying the structure of the storage layer, and improving the integration of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0049] Figure 1 A three-dimensional topological circuit diagram of the three-dimensional embedded non-volatile memory provided in an embodiment;

[0050] Figure 2a A three-dimensional structure schematic diagram of the three-dimensional embedded non-volatile memory provided in an embodiment;

[0051] Figure 2b A cross-sectional view of the three-dimensional embedded non-volatile memory provided in an embodiment;

[0052] Figure 3a A structure schematic diagram of the self-selecting memory provided in an embodiment;

[0053] Figure 3b A structure schematic diagram of the self-selecting memory provided in another embodiment;

[0054] Figure 3c A structure schematic diagram of the self-selecting memory provided in still another embodiment;

[0055] Figure 3d A structure schematic diagram of the self-selecting memory provided in a fourth embodiment;

[0056] Figure 3e A structure schematic diagram of the self-selecting memory provided in a fifth embodiment;

[0057] Figure 3f A structure schematic diagram of the self-selecting memory provided in a sixth embodiment;

[0058] Figure 4 a block diagram of an edge chip provided in an embodiment;

[0059] Figure 5a a structural diagram of an edge chip provided in an embodiment;

[0060] Figure 5b a structural diagram of an edge chip provided in another embodiment;

[0061] Figure 5c a structural diagram of an edge chip provided in an embodiment;

[0062] Figure 5d a structural diagram of an edge chip provided in another embodiment;

[0063] Figure 5e a structural diagram of an edge chip provided in yet another embodiment;

[0064] Figure 5f a structural diagram of an edge chip provided in a fourth embodiment;

[0065] Figure 5g a structural diagram of an edge chip provided in a fifth embodiment;

[0066] Figure 5h a structural diagram of an edge chip provided in a sixth embodiment;

[0067] Figure 6 a process flow diagram of a method for manufacturing a three-dimensional embedded nonvolatile memory provided in an embodiment;

[0068] Figure 7 a process flow diagram of a method for manufacturing a three-dimensional embedded nonvolatile memory provided in an embodiment;

[0069] Figure 8 a structural diagram after forming a first selection material layer and a functional stack provided in an embodiment;

[0070] Figure 9 a structural diagram after forming a first trench provided in an embodiment;

[0071] Figure 10 a structural diagram after filling a first dielectric layer in the first trench provided in an embodiment;

[0072] Figure 11 a structural diagram after forming a second selection material layer provided in an embodiment;

[0073] Figure 12Structure schematic diagram after forming second trench in an embodiment;

[0074] Figure 13 Structure schematic diagram after filling second dielectric layer in second trench in an embodiment;

[0075] Figure 14 Process flow chart of manufacturing method of three-dimensional embedded nonvolatile memory in another embodiment;

[0076] Figure 15 Structure schematic diagram after forming first selection material layer in an embodiment;

[0077] Figure 16 Structure schematic diagram after forming first selection line in an embodiment;

[0078] Figure 17 Structure schematic diagram after forming functional stack in an embodiment;

[0079] Figure 18 Structure schematic diagram after forming self-selecting memory in an embodiment;

[0080] Figure 19 Structure schematic diagram after filling second dielectric layer between self-selecting memories in an embodiment;

[0081] Figure 20 Structure schematic diagram after forming second selection line in an embodiment;

[0082] Figure 21 Structure schematic diagram after forming protection layer on first selection line in another embodiment;

[0083] Figure 22 Structure schematic diagram after removing protection layer on first selection line and forming diffusion barrier layer on first selection line in another embodiment;

[0084] Figure 23 Structure schematic diagram after forming functional stack in another embodiment;

[0085] Figure 24 Structure schematic diagram after forming self-selecting memory in another embodiment;

[0086] Figure 25 Structure schematic diagram after filling second dielectric layer between self-selecting memories in another embodiment;

[0087] Figure 26 Structure schematic diagram after forming second selection line in another embodiment;

[0088] Figure 27Structure schematic diagram after forming an insulating layer to cover the sidewall of the self-selecting memory in one embodiment;

[0089] Figure 28 Structure schematic diagram after forming a third dielectric layer in one embodiment;

[0090] Figure 29 Structure schematic diagram after forming a second dielectric layer to cover the third dielectric layer in one embodiment;

[0091] Figure 30 Structure schematic diagram after forming a via to expose the top surface of the self-selecting memory in one embodiment;

[0092] Figure 31 Structure schematic diagram after forming a conductive plug in one embodiment;

[0093] Figure 32 Structure schematic diagram after forming a bit line to contact the conductive plug in one embodiment.

[0094] Explanation of reference numerals:

[0095] 1. Three-dimensional embedded non-volatile memory; 2. Logic chip; 3. Edge chip; 4. Substrate; 5. Carrier; 6. Middle layer; 7. Solder bump; 10. Storage layer; 11. First select line; 111. First select material layer; 12. Self-selecting memory; 120. Functional stack; 121. First functional layer; 122. Second functional layer; 123. Heat transfer layer; 124. Barrier layer; 125. Buffer layer; 126. First electrode layer; 127. Second electrode layer; 128. Diffusion barrier layer; 13. Second select line; 131. Second select material layer; 141. First dielectric layer; 142. Second dielectric layer; 151. First trench; 152. Second trench; 16. Protective layer; 17. Sidewall passivation layer; 171. Insulating layer; 172. Third dielectric layer; 18. Conductive plug; 20. Peripheral circuit; 30. Driving circuit; 31. First driving transistor; 32. Second driving transistor; 8. Rerouting layer; X. First direction; Y. Second direction; Z. Vertical direction. DETAILED DESCRIPTION

[0096] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is more thorough and complete.

[0097] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application.

[0098] Currently, the resistive random access memory of the 1T1R architecture needs to be matched with an independent transistor as a selection device for each resistive random access memory, resulting in a large area occupied by a single resistive random access memory. The transistor occupies a large area, and the vertical interconnection of the transistor needs to be realized through complex multi-layer metal wiring, resulting in difficulty in three-dimensional integration of the resistive random access memory of the 1T1R architecture, which is difficult to meet the demand of high-density storage.

[0099] In related solutions, a diode or a bidirectional threshold switch (OTS selector) or a metal wire type selector is used to replace the transistor to form a self-selecting memory. However, the diode has the problems of unipolar operation and insufficient driving capability. The OTS selector (Ovonic Threshold Switching Selector) is a nonlinear resistance switching device based on a chalcogenide material (such as Ge-Sb-Te, GeSe, etc.). The chalcogenide material has defects such as insufficient durability, performance fluctuation, and poor thermal stability caused by material intrinsic element segregation, which is difficult to meet the actual demand of edge non-volatile memory. The metal wire type selector has a long relaxation time, resulting in a long off time.

[0100] In addition, in order to meet the production process of the complementary metal oxide semiconductor (CMOS) logic circuit, it is necessary to meet the requirements of thermal budget compatibility and material compatibility. The bearing range of the CMOS back end of line (BEOL) process is below 400℃. For example, the crystallization temperature of the bidirectional threshold switch OTS selector is low, and the high-temperature annealing step will cause the OTS selector to crystallize, thereby losing the threshold transition characteristic. On the other hand, in order to improve the performance of some selectors, multiple element doping or the use of silver (Ag) and other easily diffused metal electrodes and other materials may be introduced in the process. These materials have poor compatibility with the back-end process of the CMOS logic circuit, and the process integration is difficult, which is not conducive to the integration of the resistive random access memory and the CMOS logic circuit.

[0101] In view of this, the application provides a three-dimensional embedded nonvolatile memory, a manufacturing method, a chip, an apparatus and a device. The three-dimensional embedded nonvolatile memory is integrated with a logic chip. The manufacturing process of the three-dimensional embedded nonvolatile memory of the application does not require high-temperature annealing, does not introduce too many new elements, is compatible with CMOS logic process and materials, and can be directly integrated after a standard logic process. Meanwhile, the three-dimensional embedded nonvolatile memory of the application can provide high-density on-chip integrated nonvolatile storage for edge device through multi-layer stacking. For example, using a 40 nm node CMOS process, under the condition of meeting the limitation of the height of the metal layer and the width of the metal line, five layers of single-bit nonvolatile memory cells are stacked, and an array density of ≥ 90 Mb / mm 2 may be achieved. The three-dimensional embedded nonvolatile memory can not only be used as an embedded memory but also as a standalone memory. As a standalone memory, the limitation of the height of the metal layer and the width of the metal line can be relaxed, and a higher storage density can be achieved. For example, using a 16 nm CMOS process for single exposure or a 45 nm CMOS process for double exposure, four layers of nonvolatile memory cells are stacked, and an array density of ≥ 2000 Mb / mm 2 may be achieved. The array density of the application scheme increases with the number of stacked layers and the scaling of the process node, and can be extended to more advanced logic processes. The storage density can be further improved by storing multiple bits of information in each nonvolatile memory cell. In addition, the matrix-vector multiplication calculation in the in-memory computing or near-memory computing can be accelerated, the high read bandwidth and delay are provided, and the efficiency and energy consumption of the artificial intelligence (AI) data stream transmission are reduced. A threshold-adjustable neuron array can also be implemented to realize large-scale three-dimensional integrated neuron circuits and improve the energy efficiency of neuromorphic computing.

[0102] According to an example embodiment, the application provides a three-dimensional embedded nonvolatile memory 1 integrated with a logic chip 2. Referring to Figure 1 、 Figure 2a 、 Figure 2bAs shown, the three-dimensional embedded nonvolatile memory 1 includes a plurality of vertically stacked storage layers 10, the number of the storage layers 10 is at least two, for example, the three-dimensional embedded nonvolatile memory 1 can include two storage layers 10, three storage layers 10, four storage layers 10 or more. Each of the storage layers 10 includes a first selection line 11, a self-selecting memory 12 and a second selection line 13 arranged in sequence along a vertical direction Z, the first selection line 11 extends along a first direction X and is arranged at intervals along a second direction Y; the second selection line 13 extends along the second direction Y and is arranged at intervals along the first direction X, the first direction X and the second direction Y are perpendicular to each other, and the first direction X and the second direction Y are non-parallel; the self-selecting memory 12 is arranged at the intersection of the first selection line 11 and the second selection line 13, and is located between the first selection line 11 and the second selection line 13 along the vertical direction Z, one of the first selection line 11 and the second selection line 13 can be a word line WL, and the other can be a bit line BL; one end of the self-selecting memory 12 is connected to the first selection line 11, and the other end is connected to the second selection line 13, each self-selecting memory 12 includes at least one functional layer, and the self-selecting memory 12 can realize self-selection storage when reaching an opening voltage.

[0103] The three-dimensional embedded nonvolatile memory 1 described above vertically stacks a plurality of storage layers 10, each of which contains a plurality of self-selecting memories 12, so that the vertically stacked architecture can integrate more self-selecting memories 12 in a unit area, thereby improving the storage capacity to meet the demand for high-density storage, such as the storage demand of large language models, supporting Processing-in-Memory (PIM) and Processing Near Memory (PNM), and having high-bandwidth, low-latency matrix-vector multiplication acceleration capability; the self-selecting memory 12 can realize self-selection storage when reaching an opening voltage, without the need for additional gating devices (such as transistors) to be integrated with it, thereby reducing the occupied area of a single self-selecting memory 12, simplifying the structure of the storage layer 10, and improving the integration of the memory.

[0104] The manufacturing of the three-dimensional embedded nonvolatile memory 1 described above does not need to perform steps such as high-temperature annealing that may cause damage to CMOS logic circuits, while reducing the need to introduce materials with poor compatibility with CMOS processes, thereby reducing the difficulty of integration with CMOS processes, so that the three-dimensional embedded nonvolatile memory 1 is compatible with CMOS processes, and the three-dimensional embedded nonvolatile memory 1 described above can be integrated with CMOS logic circuits.

[0105] In some embodiments, with reference to Figure 1 , Figure 2a , Figure 2bAs shown, adjacent layers of storage layers 10 share the first select lines 11 or share the second select lines 13 in the vertical direction Z. That is, in the vertical direction Z (third direction), the first select lines 11 of adjacent layers of storage layers 10 are the same conductive layer, or the second select lines 13 of adjacent layers of storage layers 10 are the same conductive layer. It can be understood that in the vertical direction Z (third direction), the storage layer 10 can share the first select line 11 with one of its adjacent layers of storage layers 10, and share the second select line 13 with another of its adjacent layers of storage layers 10. In this way, the process steps can be reduced, the manufacturing efficiency can be improved, and the product cost can be reduced.

[0106] In some embodiments, referring to Figure 1 , Figure 2a , Figure 2b As shown, when adjacent layers of storage layers 10 share the first select lines 11, the self-selecting memories 12 in the same column are independently addressed and operated by different second select lines 13. When reading data in the self-selecting memory 12 of the target layer of storage layers 10, by applying a read voltage to the shared first select line 11, and at the same time applying an opening voltage to the second select line 13 of the target layer, and keeping the second select lines 13 of other layers in a closed state, data reading of the target column of self-selecting memories 12 in the target layer can be performed without interfering with the memories of other layers.

[0107] In other embodiments, when reading data in the self-selecting memory 12 of the target layer of storage layers 10, a 1 / 2 bias method can also be used. The first select line 11 where the selected self-selecting memory 12 is located is applied with a working voltage Vdd, and the first select line 11 where the remaining unselected self-selecting memories 12 in the same layer are located is applied with 1 / 2 Vdd; the second select line 13 is grounded, and the second select line 13 where the remaining unselected self-selecting memories 12 in the same layer are located is applied with 1 / 2 Vdd. In this way, only the selected self-selecting memory 12 has a bias of Vdd across its terminals, and the remaining self-selecting memories 12 in the same row as the selected self-selecting memory 12 have a bias of 1 / 2 Vdd (1 / 2 Vdd < opening voltage V th ) across their terminals, and the remaining self-selecting memories 12 in the same layer have a bias of 0 V across their terminals. The first select lines 11 and the second select lines 13 of adjacent layers are turned off. And multiple rows can be turned on at the same time to select multiple self-selecting memories 12 to improve parallelism.

[0108] Referring to Figure 1 , Figure 2a , Figure 2bAs shown, the adjacent layers of storage layers 10 share the second selection line 13, and the self-selecting memories 12 in the same row are independently addressed and operated through different first selection lines 11. When reading data in the self-selecting memories 12 in the target layer of storage layers 10, the data in the self-selecting memories 12 in the target column in the target layer can be read without interfering with the memories in other layers by applying a read voltage to the shared second selection line 13 and applying an open voltage to the first selection line 11 of the target layer, while the first selection lines 11 of other layers remain in a closed state. In this way, each self-selecting memory 12 can be accurately addressed and operated.

[0109] In this embodiment, the adjacent layers of storage layers 10 share the selection lines and are independently addressed, which can flexibly select the self-selecting memories 12 in a specific layer, a specific row, or a specific column for operation. When updating data, only the layers in which the self-selecting memories 12 that need to be modified are operated, without the need for large-scale read-write operations on the entire storage layer 10, thereby improving the efficiency of data operation. At the same time, this design is conducive to the capacity expansion of the memory, and the storage capacity and density can be increased by increasing the number of storage layers 10 in the vertical direction Z. The newly added layers can share the selection lines with the existing layers without affecting the original addressing and operating mode.

[0110] In some embodiments, referring to Figure 1 , Figure 2a , Figure 2b As shown, the self-selecting memory 12 includes a first functional layer 121 and a second functional layer 122 stacked in the vertical direction Z, one of the first functional layer 121 and the second functional layer 122 is a gating layer, and the other is a resistive switching layer; the resistive switching layer is reversibly switchable between a high resistance state and a low resistance state to store data; the gating layer is used to control the on-off of current in the self-selecting memory to turn on the current path of the selected self-selecting memory 12 during read-write operation.

[0111] In this embodiment, the gating and resistive switching functions are integrated into the same self-selecting memory 12 through different functional layers, which reduces the complexity of device structure and connection and reduces the difficulty of manufacturing, and is compatible with CMOS process; the self-selecting memory 12 adopts a stacked structure of the first functional layer 121 and the second functional layer 122 in the vertical direction Z, which fully utilizes the third dimension in the vertical direction and is conducive to reducing the area of the self-selecting memory 12, integrating more self-selecting memories 12 in a unit area, and improving the storage density.

[0112] In this embodiment, the resistance ratio of the high resistance state to the low resistance state of the resistive switching layer is ≥2. The leakage current density of the gating layer in the non-conductive state is ≤10 -3 MA / cm², and the open voltage of the gating layer in the conductive state is ≤3.5V.

[0113] The gating layer can quickly respond to read and write operation signals, rapidly turn on or turn off the current path, so as to select the specific self-selecting memory 12 for read and write operation, which is beneficial to improve the stability and reliability of data read and write operation, reduce the probability of data error, and improve the anti-interference ability of the three-dimensional embedded nonvolatile memory 1. During read and write operation, the gating layer can control the current to flow only through the selected self-selecting memory 12, avoid current leakage in the unselected memory, improve information reading accuracy and reduce power consumption; the number of self-selecting memories 12 integrated in the three-dimensional embedded nonvolatile memory 1 is large, and the gating layer limits only the selected self-selecting memory 12 to consume power, thereby reducing the power consumption of the memory during standby and read and write operation, which is beneficial to the endurance and heat dissipation performance of the memory.

[0114] In the embodiments of the present application, suitable materials can be selected according to the functional requirements of the gating layer and the resistive switching layer. The gating layer can select materials with good current control characteristics and fast response speed, and the resistive switching layer can select materials with stable resistive switching performance and long durability.

[0115] In some embodiments, the material of the gating layer includes at least one of niobium oxide and vanadium oxide. In the gating layer, these materials can quickly respond to voltage signals to achieve accurate control of the gating layer on the on-off of the current.

[0116] The material of the resistive switching layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, hafnium aluminum oxide. In the resistive switching layer, these materials have abundant oxygen vacancies and defect states, and under the action of an electric field, oxygen ions or oxygen vacancies will migrate to reversibly switch the resistance of the resistive switching layer between high resistance state and low resistance state, with good reliability and durability, which can meet the long-term data storage requirements of the resistive switching layer.

[0117] In this way, by reasonably setting the materials of the gating layer and the resistive switching layer of the self-selecting memory 12, the materials of the gating layer and the resistive switching layer are matched, the self-selecting memory 12 has a self-rectifying effect, a potential barrier is formed at the interface of the gating layer and the resistive switching layer, under the action of a forward voltage, the current can relatively easily pass through the potential barrier; and under the action of a reverse voltage, the potential barrier will significantly increase to hinder the passage of the current, thereby realizing the self-rectifying characteristic; the self-selecting memory 12 can effectively suppress the generation of leakage current, reduce storage errors caused by leakage current, and suppress additional power consumption caused by leakage current; in the embodiments of the present application, the three-dimensional embedded nonvolatile memory 1 integrates the self-selecting memories 12 with the self-rectifying effect, which can further reduce the spacing between the self-selecting memories 12, thereby reducing the overall size of the memory and improving the storage density.

[0118] For example, the material of the resistance change layer includes tantalum oxide, and the material of the gating layer includes niobium oxide. In this way, the self-selecting memory 12 can further improve the self-rectification capability and inhibit the generation of leakage current.

[0119] In some embodiments, the gating layer can be doped with a doping element to improve the stability and electrical characteristics of the gating layer. For example, the doping element in the gating layer can include one or more of aluminum, copper, titanium, zirconium, nitrogen, silicon, and the like.

[0120] In some embodiments, the self-selecting memory 12 further includes at least one auxiliary functional layer vertically stacked with the first functional layer 121 and the second functional layer 122. The at least one auxiliary functional layer can be arranged between the first functional layer 121 and the second functional layer 122, or arranged between the first functional layer 121 and the first selection line 11, or arranged between the second functional layer 122 and the second selection line 13. The auxiliary functional layer is selected from at least one of a heat transfer layer 123, a barrier layer 124, a buffer layer 125, a first electrode layer 126, a second electrode layer 127, or a diffusion barrier layer 128.

[0121] In some embodiments, referring to Figure 3a , the self-selecting memory 12 further includes a heat transfer layer 123 arranged between the first functional layer 121 and the second functional layer 122. The heat transfer layer 123 has a thermal conductivity less than that of the resistance change layer. In this way, during the read / write operation, the gating layer conducts current and the resistance change layer generates heat. The heat transfer layer 123 limits the heat diffusion, so that the gating layer quickly rises to the opening temperature, thereby reducing the opening voltage (V th ) of the self-selecting memory 12 and achieving self-selecting storage. In the non-read / write state, the gating layer is turned off, and the heat transfer layer 123 further reduces the influence of heat on other functional layers, thereby improving the stability of the memory. At the same time, the heat transfer layer 123 can improve the thermal stability of the gating layer, delay the temperature reduction of the gating layer, and reduce the write voltage and read voltage of the self-selecting memory 12 as a whole. The heat transfer layer 123 can also avoid the mutual diffusion of the materials of the gating layer and the resistance change layer, thereby improving the reliability and performance stability of the self-selecting memory 12.

[0122] For example, the material of the heat transfer layer 123 includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide. The heat transfer layer 123 can be a single-layer structure or a multi-layer structure.

[0123] In some embodiments, referring toFigures 3b-3d The self-selecting memory 12 further comprises a barrier layer 124, which is arranged between the functional layer and the first selection line 11 to form a barrier with the first selection line 11, or which is arranged between the functional layer and the second selection line 13 to form a barrier with the second selection line 13. The barrier layer 124 and the selection line connected thereto form a Schottky barrier or a tunneling barrier. In this way, the current of the self-selecting memory 12 is limited by the barrier. In a read / write operation, when a suitable voltage is applied, electrons can tunnel or pass through the barrier to turn on the current; in a non-read / write state or when a reverse voltage is applied, the barrier hinders the flow of electrons to turn off the current, thereby improving the reliability of the gating function of the self-selecting memory 12.

[0124] For example, the material of the barrier layer 124 can be selected from a material having a high dielectric constant (greater than 3.9) and a wide band gap. For example, the material of the barrier layer 124 includes at least one of neodymium oxide (NdO x ), strontium oxide (SrO x ), germanium oxide (GeO x ), lanthanum oxide (LaO x ), hafnium oxide (HfO x ), gallium oxide (GaO x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), silicon oxide (SiO x ), ytterbium oxide (YbO x ), or magnesium oxide (MgO x ).

[0125] In some embodiments, referring to Figure 3c , Figure 3d The self-selecting memory 12 further comprises a buffer layer 125, which is arranged between the functional layer and the barrier layer 124, and the electron affinity of the buffer layer 125 is between the functional layer and the barrier layer 124. The electron affinity of the buffer layer 125 is between the gating layer and the barrier layer 124, and the buffer layer 125 is used to buffer the difference in electron affinity between the gating layer and the barrier layer 124 to avoid performance fluctuations caused by a large difference in electron affinity between the gating layer and the barrier layer 124. The buffer layer 125 can reduce the voltage division of the barrier layer 124, avoid breakdown of the barrier layer 124 caused by high voltage division, reduce the risk of leakage, and improve the stability and reliability of the device performance.

[0126] For example, the material of the buffer layer 125 can include titanium oxide (TiO x ), nickel oxide (NiO x ), zinc oxide (ZnO x ), chromium oxide (CrO x ), molybdenum oxide (MoO x ), tungsten oxide (WOx bismuth oxide (BiO x antimony oxide (SbO x indium oxide (InO x vanadium oxide (VO x niobium oxide (NbO x manganese oxide (MnO x neodymium oxide (NdO x strontium oxide (SrO x germanium oxide (GeO x lanthanum oxide (LaO x hafnium oxide (HfO x gallium oxide (GaO x aluminum oxide (AlO x zirconium oxide (ZrO x silicon oxide (SiO x ytterbium oxide (YbO x or magnesium oxide (MgO x .

[0127] The material of the buffer layer 125 has good interface characteristics, which can reduce the interface state and defect state between the functional layer and the barrier layer 124, reduce the scattering and recombination probability of electrons at the interface, and improve the transmission efficiency of electrons.

[0128] In some embodiments, referring to Figure 26 The self-selecting memory 12 further includes a first electrode layer 126 and a second electrode layer 127. The first electrode layer 126 is arranged between the first functional layer 121 and the first selection line 11, and the second electrode layer 127 is arranged between the second functional layer 122 and the second selection line 13. The first electrode layer 126 and the second electrode layer 127 reduce the contact resistance between the functional layer and the selection line.

[0129] For example, the material of the first electrode layer 126 can include at least one of niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum tungsten (TiAlW), yttrium (Ir), yttrium oxide (IrO2), indium tin oxide (ITO), aluminum titanium nitride (TiAlN), aluminum nitride (AlNx), aluminum titanium nitride (TiAlN) or (AlTiN), hafnium (Hf), iridium (Ir), copper (Cu). Among them, the first electrode layer 126 can be a single-layer structure or a multi-layer structure.

[0130] The selection range of the material of the second electrode layer 127 is the same as that of the material of the first electrode layer 126, which will not be repeated here.

[0131] In some embodiments, referring toFigure 26 The self-select memory 12 also includes a diffusion barrier layer 128, which is in contact with the first select line 11 or the second select line 13. Thus, the diffusion barrier layer 128 can be disposed between the self-select memory 12 and the first select line 11 or between the self-select memory 12 and the second select line 13. The diffusion barrier layer 128 can effectively prevent the diffusion of metal atoms under high temperature or electric field, prevent mutual contamination between the select line and the self-select memory 12, improve the stability and reliability of the memory, and extend the service life of the memory.

[0132] For example, the material of the diffusion barrier layer 128 is selected from at least one of titanium nitride (TiN), tantalum nitride (TaN), and tungsten carbide (WC).

[0133] In some embodiments, such as Figure 3e , Figure 3f As shown, the three-dimensional embedded non-volatile memory 1 also includes a sidewall passivation layer 17, which covers the sidewall of the self-select memory 12. The sidewall passivation layer 17 is used to enhance the electrical isolation performance between adjacent devices, reduce the risk of short circuits between adjacent devices, and improve the leakage current problem of the self-select memory 12.

[0134] The sidewall passivation layer 17 can be a single-layer structure or a multi-layer structure sequentially covering the sidewalls of the self-select memory 12. In one embodiment, as shown in 3e, the sidewall passivation layer 17 is a single-layer structure, and the material of the sidewall passivation layer 17 may include at least one of silicon oxide, silicon nitride, or aluminum oxide. In another embodiment, as shown in 3f, the sidewall passivation layer 17 includes an insulating layer 171 and a third dielectric layer 172 sequentially covering the sidewalls of the self-select memory 12. The material of the insulating layer 171 may include at least one of silicon oxide, silicon nitride, or aluminum oxide, and the material of the third dielectric layer 172 may include silicon oxide.

[0135] like Figure 3e , Figure 3f As shown, the three-dimensional embedded non-volatile memory 1 also includes a conductive plug 18, which is disposed on the top surface of the self-select memory 12. The self-select memory 12 is connected to the first select line 11 or the second select line 13 above it via the conductive plug 18. The sidewall passivation layer 17 may also cover part of the top surface of the self-select memory 12, and the conductive plug 18 passes through the sidewall passivation layer 17 to contact the top surface of the self-select memory 12 to connect the self-select memory 12 to the first select line 11 or the second select line 13 above it.

[0136] In some embodiments, when the height of the self-selecting memory 12 is less than the process required height difference between the first selection line 11 and the second selection line 13, a conductive plug 18 is formed on the self-selecting memory 12, and the height of the self-selecting memory 12 is increased by the conductive plug 18, so that the height of the self-selecting memory 12 meets the process required height difference between the first selection line 11 and the second selection line 13.

[0137] In some embodiments, referring to Figure 1 , in combination with the description of Figures 5a-5h , the three-dimensional embedded non-volatile memory 1 further includes a peripheral circuit 20 and a driving circuit 30.

[0138] The peripheral circuit 20 is used to receive instructions and data sent by external devices, and read and transmit data in the memory to external systems, and the data interaction between the three-dimensional embedded non-volatile memory 1 and external devices.

[0139] The driving circuit 30 is used to generate corresponding control signals according to the instructions received by the peripheral circuit 20, and the driving circuit 30 controls the working state of each component (such as the first selection line 11, the self-selecting memory 12, and the second selection line 13) in the storage layer 10, to realize data writing, reading and erasing and other operations.

[0140] In this embodiment, referring to Figure 1 , in combination with the description of Figures 5a-5h , the driving circuit 30 includes a plurality of driving transistors, and the plurality of driving transistors includes a first driving transistor 31 and a second driving transistor 32. Each first driving transistor 31 is connected in correspondence with a first selection line 11, and the first driving transistor 31 is used to control the voltage applied to the first selection line 11. Each second driving transistor is connected in correspondence with a second selection line 13, and the second driving transistor 32 is used to control the voltage applied to the second selection line 13. The transistors of the driving circuit 30 and the multi-layer stacked 1S1R memory cells construct a three-dimensional memory array with high integration of 1TnSnR structure; by controlling the voltage of the first selection line 11 and the second selection line 13 through the first driving transistor 31 and the second driving transistor 32, independent addressing and operation of each self-selecting memory 12 in the storage layer 10 can be realized.

[0141] In a second aspect, the present application provides an edge-end chip 3, which is an in-chip homogeneous integration chip. Referring to Figure 4 or Figure 5a , Figure 5b, the edge chip 3 comprises a substrate 4, and the logic chip 2 and the three-dimensional embedded nonvolatile memory 1 according to the first aspect are integrated on the substrate 4; the three-dimensional embedded nonvolatile memory 1 is arranged on the logic chip 2, or the three-dimensional embedded nonvolatile memory 1 and the logic chip 2 are arranged on the substrate 4 respectively. The peripheral circuit 20 and the driving circuit 30 of the three-dimensional embedded nonvolatile memory 1 are manufactured in the front-end process, and the multi-layer storage layer 10 of the three-dimensional embedded nonvolatile memory 1 is manufactured in the back-end process.

[0142] In some embodiments, referring to Figure 5a , the peripheral circuit 20, the driving circuit 30 and the logic chip 2 are formed above which a rewiring layer 8 is formed, and the peripheral circuit 20, the driving circuit 30 and the logic chip 2 are electrically connected through the rewiring layer 8. The multi-layer storage layer 10 of the three-dimensional embedded nonvolatile memory 1 is stacked on the rewiring layer 8, and the multi-layer storage layer 10 is electrically connected with the logic chip 2 through the rewiring layer 8 to realize data interaction. In this way, the vertical space is fully utilized to improve the integration of the edge chip 3, shorten the signal transmission path of the three-dimensional embedded nonvolatile memory 1 and the logic chip 2, improve the signal delay, improve the read-write speed of the memory, and improve the response speed of the edge chip 3; and the additional power consumption caused by the long connection line can also be reduced.

[0143] In other embodiments, referring to Figure 5b , the three-dimensional embedded nonvolatile memory 1 and the logic chip 2 are arranged in different regions of the substrate 4 respectively, and are electrically connected through the wiring layer inside the substrate 4 to realize data interaction. In this way, the logic chip 2 and the three-dimensional embedded nonvolatile memory 1 are independently cooled, avoiding the heat concentration problem caused by the close stacking of the three-dimensional embedded nonvolatile memory 1 and the logic chip 2, which is conducive to improving the stability and reliability of the edge chip 3.

[0144] In other embodiments, the edge chip 3 further comprises a DRAM module. For example, the DRAM module can be a DRAM storage array. The DRAM module is used for temporarily storing intermediate results in the data processing process of the edge chip 3, thereby improving the overall performance and data processing capability of the chip.

[0145] In this embodiment, the DRAM module can include a three-dimensional or planar DRAM storage device based on oxide semiconductor channel Two-Transistor, Zero-Capacitor (2T0C) technology or a traditional DRAM (1T1C DRAM storage device), or a High Bandwidth Memory (HBM), which integrates the DRAM module with the logic chip 2 and the three-dimensional embedded nonvolatile memory 1.

[0146] The DRAM memory device with 2T0C structure is made based on oxide semiconductor material, can be directly integrated with other memory devices (such as the logic chip 2 and the three-dimensional embedded nonvolatile memory 1), simplifies the manufacturing process of the edge chip 3, reduces the compatibility problems between different materials and processes, and improves the production efficiency and yield. At the same time, it is beneficial to improve the stability and reliability of the edge chip 3, and reduce the problems caused by the performance difference between different materials and processes.

[0147] It can be understood that in the task involving a large amount of data processing and complex algorithm, such as the cache (KV Cache) of the intermediate result in the learning model (Transformer) training process is used to store the intermediate calculation result, so as to quickly access in subsequent calculation, reduce repeated calculation, and improve the overall calculation efficiency. With the increase of model size and the increase of processing data amount, the number of intermediate results required to be cached also increases sharply, which requires the intermediate cache to have a large capacity and be able to store a large amount of intermediate data. In the calculation process, the KV Cache will be frequently read and written, and the medium for storing the KV Cache needs to have good durability and relatively fast speed, and can withstand a large number of read and write operations without performance degradation or data loss and other problems.

[0148] The DRAM memory has high read and write speed and good durability, and can withstand a large number of read and write operations. In the embodiment, the DRAM module is integrated with the logic chip 2 and the three-dimensional embedded nonvolatile memory 1, and the durability requirement of the intermediate buffer can be met by using the DRAM module. The three-dimensional embedded nonvolatile memory module can store weights in the chip, and can provide larger bandwidth. It is convenient to load and update weights faster, compared with traditional model training and inference, the data transmission distance and delay between chips are greatly reduced, and the computing energy efficiency is greatly improved.

[0149] In one embodiment, referring to Figure 5c , the peripheral circuit 20 and the driving circuit 30 of the three-dimensional embedded nonvolatile memory 1 are formed above the logic chip 2 with a redistribution layer 8, and the peripheral circuit 20 and the driving circuit 30 of the three-dimensional embedded nonvolatile memory 1 are electrically connected with the logic chip 2 through the redistribution layer 8. The multi-layer storage layer 10 of the three-dimensional embedded nonvolatile memory 1 is stacked on the redistribution layer 8 and electrically connected with the logic chip 2 through the redistribution layer 8. The DRAM module is directly integrated above the multi-layer storage layer 10 of the three-dimensional embedded nonvolatile memory 1, and the DRAM module is a DRAM memory with 2T0C structure.

[0150] In another embodiment, referring to Figure 5d , the DRAM module is directly integrated on the redistribution layer 8, and the multi-layer storage layer 10 of the three-dimensional embedded nonvolatile memory 1 is stacked on the DRAM module.

[0151] In yet another embodiment, referring to Figure 5e , the DRAM module and the multi-layered storage layers 10 of the 3D embedded non-volatile memory 1 are both stacked on the redistribution layer 8.

[0152] In a fourth embodiment, referring to Figure 5f , the peripheral circuit 20, the driving circuit 30 and the logic chip 2 are formed with a redistribution layer 8 on top, and the multi-layered storage layers 10 of the 3D embedded non-volatile memory 1 are stacked on the redistribution layer 8. A connection layer 51 is formed on the multi-layered storage layers 10 of the 3D embedded non-volatile memory 1, and connection plugs (not shown in the figure) are formed in the connection layer 51, such as by a Through-Silicon Via (TSV) technology. The DRAM module is stacked on the side of the connection layer 51 away from the 3D embedded non-volatile memory 1, and is vertically interconnected with the 3D embedded non-volatile memory 1 through the connection plugs of the connection layer 51.

[0153] In a fifth embodiment, referring to Figure 5g , the 3D embedded non-volatile memory 1, the logic chip 2 and the DRAM module are integrated on a carrier board 5, and the carrier board 5 is provided with an intermediate layer 6 having a metal wiring layer, an insulating layer and a via structure. The intermediate layer 6 can redistribute and connect the signal pins of the 3D embedded non-volatile memory 1, the logic chip 2 and the DRAM module. The 3D embedded non-volatile memory 1, the logic chip 2 and the DRAM module are respectively arranged on the intermediate layer 6 through solder bumps 7. Among them, the 3D embedded non-volatile memory 1 and the logic chip 2 are integrated together on a substrate 4, and the substrate 4 is arranged on the intermediate layer 6 through the solder bumps 7, so that the 3D embedded non-volatile memory 1, the logic chip 2 and the DRAM module can interact with each other through the intermediate layer 6.

[0154] In a sixth embodiment, referring to Figure 5h , the peripheral circuit 20, the driving circuit 30, the logic chip 2 and the DRAM module are respectively arranged on the side of the intermediate layer 6 away from the carrier board 5 through the solder bumps 7, and the peripheral circuit 20, the driving circuit 30, the logic chip 2 and the DRAM module are formed with a redistribution layer 8 on top, and the multi-layered storage layers 10 of the 3D embedded non-volatile memory 1 are stacked on the redistribution layer 8.

[0155] According to an exemplary embodiment, the present application provides an electronic device comprising the three-dimensional embedded nonvolatile memory 1 of the above embodiments, or comprising the edge chip of the above embodiments. The electronic device can be a notebook computer, a mobile phone, a wireless device, a personal data assistant (PDA), a handheld or portable computer, a smart wearable device, an augmented reality (AR) device, a virtual reality (VR) head-mounted device, a global positioning system (GPS) receiver / navigator, a camera, a video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automobile display (e.g., an odometer display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, a printer, a set-top box, etc.

[0156] According to an exemplary embodiment, the present application provides a method for manufacturing a three-dimensional embedded nonvolatile memory 1. The method comprises the following steps: Figure 6

[0157] Step S101: Form a plurality of first selection lines 11 on the substrate, the first selection lines 11 extending along the first direction X and being spaced apart along the second direction Y.

[0158] Step S102: Form a plurality of self-selecting memories 12 on the side of the first selection lines 11 away from the substrate, the self-selecting memories 12 being arrayed along the first direction X and the second direction Y; the self-selecting memories 12 comprising functional layers.

[0159] Step S103: Form a plurality of second selection lines 13 on the side of the self-selecting memories 12 away from the first selection lines 11, the second selection lines 13 extending along the second direction Y and being spaced apart along the first direction X; the plurality of first selection lines 11, the plurality of self-selecting memories 12, and the plurality of second selection lines 13 form a memory layer 10.

[0160] ​Step S104: Repeat the steps of forming the plurality of first selection lines 11, forming the plurality of self-selecting memories 12, and forming the plurality of second selection lines 13 to form the vertically stacked multi-layer storage layer 10.

[0161] The manufacturing method of the three-dimensional embedded non-volatile memory 1 of the embodiment can integrate more self-selecting memories 12 in a unit area through the formation of the vertically stacked multi-layer storage layer 10, each layer of which contains a plurality of self-selecting memories 12, thereby improving the storage capacity to meet the high-density storage demand, such as the storage demand of large language models, supporting in-memory computing (PIM) and near-memory computing (PNC), and having high-bandwidth, low-latency matrix-vector multiplication acceleration capability. The self-selecting memory 12 can realize self-selection storage when reaching the turn-on voltage, without the need for additional gating devices (such as transistors) to be integrated correspondingly, thereby reducing the occupied area of a single self-selecting memory 12, simplifying the structure of the storage layer 10, and improving the integration of the memory.

[0162] In some embodiments, as shown in Figure 7 The formation of each layer of the storage layer 10 includes the following steps:

[0163] Step S201: Forming a first selection material layer 111 and a functional stack 120 on a substrate, the functional stack 120 including at least a first functional layer 121 and a second functional layer 122.

[0164] In the embodiment, as shown in Figure 8 The first selection material layer 111 and the functional stack 120 can be deposited on the substrate by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, etc.

[0165] In the embodiment, the first functional layer 121 and the second functional layer 122 are sequentially formed on the first selection material layer 111 to form the functional stack 120. In other embodiments, the functional stack 120 can further include at least one auxiliary functional layer, such as a heat transfer layer 123, a barrier layer 124, a buffer layer 125, a first electrode layer 126, and a second electrode layer 127, or a diffusion barrier layer 128, etc.

[0166] Step S202: Etching the functional stack 120 and the first selection material layer 111 to form a first trench 151 extending along the first direction X, and dividing the first selection material layer 111 into a plurality of first selection lines 11.

[0167] In the embodiment, as shown inFigure 9 As shown in the figure, a mask layer is formed on the side of the functional stack 120 away from the first selection material layer 111, and the mask layer is exposed and developed to define a pattern of the first trench 151. According to the patterned mask layer, the functional stack 120 and the first selection material layer 111 are etched to form at least one first trench 151 penetrating the functional stack 120 and the first selection material layer 111, the first trench 151 divides the first selection material layer 111 into a plurality of first selection lines 11, the first selection lines 11 extend along the first direction X and are arranged at intervals along the second direction Y, and the entire layer of the functional stack 120 is divided into a strip-shaped structure extending along the first direction X, and the strip-shaped functional stack 120 is arranged on the first selection lines 11.

[0168] For example, the functional stack 120 and the first selection material layer 111 can be etched by a dry process or a wet process.

[0169] Step S203: Form a second selection material layer 131 covering the top surface of the functional stack 120.

[0170] In this embodiment, referring to Figure 10 As shown in the figure, the first dielectric layer 141 can be formed by chemical vapor deposition or atomic layer deposition, and the first dielectric layer 141 fills the first trench 151. Then, the first dielectric layer 141 on the top surface of the functional stack 120 is removed by chemical mechanical polishing (CMP).

[0171] Then, referring to Figure 11 As shown in the figure, the second selection material layer 131 is deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, etc., and the second selection material layer 131 covers the top surface of the functional stack 120 and the top surface of the first dielectric layer 141.

[0172] Step S204: Etch the second selection material layer 131 and the functional stack 120 to form a second trench 152 extending along the second direction Y, and divide the second selection material layer 131 into a plurality of second selection lines 13; the first trench 151 and the second trench 152 divide the functional stack 120 into a plurality of self-selecting memories 12; one of the first functional layer 121 and the second functional layer 122 of the self-selecting memory 12 is a resistance change layer, and the other is a gating layer.

[0173] In this embodiment, referring to Figure 12As shown, a mask layer is formed on the side of the second selection material layer 131 away from the functional stack 120, and the mask layer is patterned to define the pattern of the second trench 152. According to the patterned mask layer, the second selection material layer 131 and the functional stack 120 are etched to form at least one second trench 152 penetrating through the second selection material layer 131 and the functional stack 120, and the second trench 152 divides the second selection material layer 131 into a plurality of second selection lines 13 extending along the second direction Y and spaced apart along the first direction X, and divides the strip-shaped functional stack 120 into independently arranged self-selecting memories 12 arranged at the intersections of the first selection lines 11 and the second selection lines 13, and the self-selecting memories 12 are arranged along the first direction X and the second direction Y.

[0174] Then, referring to Figure 13 As shown, a second dielectric layer 142 is formed to fill the second trench 152 and cover the top surface of the second selection lines 13, and the top surface of the second dielectric layer 142 is ground to be flat, and then the top surface of the second dielectric layer 142 is used as a process plane to repeat the steps S201-S204 to form the vertically stacked multi-layer storage layer 10 on the substrate. In this way, the self-selecting memories 12 of each layer storage layer 10 in the three-dimensional embedded non-volatile memory 1 can operate in parallel.

[0175] In the embodiments of the present application, suitable materials can be selected according to the functional requirements of the gating layer and the resistive switching layer. The gating layer can be selected to have good current control characteristics and fast response speed, and the resistive switching layer can be selected to have stable resistive switching performance and long durability.

[0176] In some embodiments, after the step S203 of forming the second selection material layer 131 to cover the top surface of the first layer of functional stack 120, a second layer of functional stack 120 is formed to cover the top surface of the second selection material layer 131. Then, the second layer of functional stack 120, the second selection material layer 131 and the first layer of functional stack 120 are etched to form a second trench 152, which divides the second selection material layer 131 into a plurality of second selection lines 13, divides the first layer of functional stack 120 into a plurality of self-selecting memories 12, and divides the second layer of functional stack 120 into a strip structure on the second selection lines 13. Then, the second dielectric layer 142 is filled in the second trench 152. The first selection material layer 111 and a third layer of functional stack 120 are sequentially formed on the second dielectric layer 142 and the second layer of functional stack 120. The third layer of functional stack 120, the first selection material layer 111 and the second layer of functional stack 120 are etched to form a first trench 151, which divides the second layer of functional stack 120 into a plurality of self-selecting memories 12, divides the first selection material layer 111 into a plurality of first selection lines 11, and divides the third layer of functional stack 120 into a strip structure on the first selection lines 11. In this way, a plurality of layers of storage layers 10 stacked in the vertical direction can be formed, and such a process flow is more concise, has fewer procedures, and is conducive to saving production costs.

[0177] In some embodiments, the material of the gating layer includes at least one of niobium oxide and vanadium oxide. In the gating layer, these materials can quickly respond to a voltage signal to achieve accurate control of the gating layer on the on-off of the current.

[0178] The material of the resistance change layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, hafnium aluminum oxide. In the resistance change layer, these materials have abundant oxygen vacancies and defect states. Under the action of an electric field, oxygen ions or oxygen vacancies will migrate to reversibly switch the resistance of the resistance change layer between a high resistance state and a low resistance state, have good reliability and durability, and can meet the needs of long-term storage of data in the resistance change layer.

[0179] In the above embodiments, the materials of the first dielectric layer 141 and the second dielectric layer 142 in steps S201-S204 may include one or more combinations of silicon oxide, porous silicon carbide (SiCOH), silicate glass (USG), and borosilicate glass (BPSG), and may include a multilayer structure or a mixture of multilayer materials. The fabrication process of the first dielectric layer 141 and the second dielectric layer 142 includes chemical vapor deposition, such as atmospheric pressure chemical vapor deposition (APCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0180] In some embodiments, such as Figure 14 As shown, forming each storage layer 10 includes the following steps:

[0181] Step S301: Form a first selective material layer 111 on the substrate, and etch the first selective material layer 111 to form multiple first selective lines 11.

[0182] In this embodiment, refer to Figure 15 , Figure 16 After forming the first selected material layer 111, a mask layer is directly formed to pattern and etch the first selected material layer 111 to form the first selected line 11. Then, a first dielectric layer 141 is deposited to fill the spaces between the first selected lines 11, and the first dielectric layer 141 on the first selected lines 11 is removed by grinding, which will not be described in detail here.

[0183] Step S302: Form a functional stack 120, which covers the top surface of the first selected material layer 111. The functional stack 120 includes at least a first functional layer 121 and a second functional layer 122.

[0184] Step S303: Pattern the functional stack 120 to form a plurality of self-select memory 12 on the side of the first selection line 11 away from the substrate; one of the first functional layer 121 and the second functional layer 122 of the self-select memory 12 is a resistive switching layer and the other is a gated layer.

[0185] In this embodiment, refer to Figure 17 , Figure 18 Multiple self-selection memories 12 can be formed by etching the functional stack 120 using dual self-aligned imaging technology or self-aligned quadruple imaging technology. The multiple self-selection memories 12 are arranged at intervals along the first direction X on the first selection line 11.

[0186] Step S304: Forming a second selection material layer 131 on the side of the self-selecting memory 12 away from the first selection line 11, and etching the second selection material layer 131 to form a plurality of second selection lines 13.

[0187] In this embodiment, referring to Figure 19 , a second dielectric layer 142 is deposited to fill between adjacent self-selecting memories 12. Then, the second dielectric layer 142 on the top surface of the self-selecting memory 12 is polished away. Referring to Figure 20 , a second selection material layer 131 is deposited to cover the top surface of the self-selecting memory 12 and the top surface of the second dielectric layer 142. The second selection material layer 131 is patterned and etched to form a plurality of second selection lines 13 extending along the second direction Y and connecting a column of self-selecting memories 12 arranged along the second direction Y.

[0188] In some embodiments, referring to Figure 1 , Figure 2a , Figure 2b , adjacent layers of the storage layer 10 in the vertical direction Z share the first selection line 11 or share the second selection line 13.

[0189] In this embodiment, after the second dielectric layer 142 is deposited to fill the second trench 152 and cover the top surface of the second selection line 13, and the second dielectric layer 142 on the second selection line 13 is polished away, a second functional stack 120 is formed on the second selection line 13 and the second dielectric layer 142, and the second functional stack 120 is patterned and etched to form a second array of self-selecting memories 12. Then, the process of filling the dielectric layer, polishing, depositing the first selection material layer 111, and patterning and etching the first selection material layer 111 to form the first selection line 11 is repeated. If more layers of the storage layer 10 are to be formed, the steps of forming the self-selecting memory 12 and the second selection line 13 are repeated.

[0190] In some embodiments, referring to Figures 21-26 , after the first selection line 11 is formed, a first dielectric layer 141 is filled into the first trench 151 between the first selection lines 11. Then, a protective layer 16 is formed to cover the top surface of the first selection line 11 and the first dielectric layer 141, and the material of the protective layer 16 can include silicon oxide, for example. Then, the protective layer 16 on the first selection line 11 is etched to expose the top surface of the first selection line 11. A diffusion barrier layer 128 is formed on the first selection line 11, and the diffusion barrier layer 128 is used to block the material of the self-selecting memory 12 from diffusing to the first selection line 11, and the material of the diffusion barrier layer 128 can include at least one of titanium nitride, tantalum, tantalum nitride, or tungsten nitride, for example.

[0191] In some embodiments, the functional stack 120 further comprises at least one auxiliary functional layer, and the self-selecting memory 12 formed thereby comprises at least one auxiliary functional layer. The at least one auxiliary functional layer is vertically stacked with the first functional layer 121 and the second functional layer 122. The at least one auxiliary functional layer can be arranged between the first functional layer 121 and the second functional layer 122, or arranged between the first functional layer 121 and the first selection line 11, or arranged between the second functional layer 122 and the second selection line 13.

[0192] In some embodiments, referring to Figures 21-26 , the functional stack 120 comprises a first electrode layer 126, a first functional layer 121, a second functional layer 122 and a second electrode layer 127, which are sequentially stacked on the first selection material layer 111. The self-selecting memory 12 formed thereby comprises a first electrode layer 126, a first functional layer 121, a second functional layer 122 and a second electrode layer 127, which are sequentially stacked away from the first selection line 11. The first electrode layer 126 and the second electrode layer 127 reduce the contact resistance between the functional layer and the selection line.

[0193] For example, the material of the first electrode layer 126 can comprise at least one of vanadium, niobium, ruthenium, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, aluminum, titanium aluminum tungsten, yttrium, yttrium oxide, indium tin oxide, aluminum titanium nitride, aluminum nitride, aluminum titanium nitride, hafnium, iridium, copper. The first electrode layer 126 can be a single-layer structure or a multi-layer structure. The material of the second electrode layer 127 is selected from the same range as the material of the first electrode layer 126, and will not be repeated here.

[0194] In some embodiments, referring to Figure 3a , the functional stack 120 further comprises a heat transfer layer 123, and the self-selecting memory 12 formed thereby further comprises a heat transfer layer 123. The heat transfer layer 123 is arranged between the first functional layer 121 and the second functional layer 122, and the thermal conductivity of the heat transfer layer 123 is less than that of the resistance change layer. For example, the material of the heat transfer layer 123 comprises at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, zinc-doped indium oxide. The heat transfer layer 123 can be a single-layer structure or a multi-layer structure.

[0195] In some embodiments, referring to Figure 3b , Figure 3c , Figure 3dThe self-selecting memory 12 can further include a barrier layer 124, which is arranged between the functional layer (the first functional layer 121 and / or the second functional layer 122) and the first selection line 11 to form a barrier with the first selection line 11, or which is arranged between the functional layer and the second selection line 13 to form a barrier with the second selection line 13. The barrier layer 124 and the selection line connected thereto form a Schottky barrier or a tunneling barrier.

[0196] For example, the material of the barrier layer 124 can be selected from a material having a high dielectric constant (greater than 3.9) and a wide band gap. For example, the material of the barrier layer 124 includes at least one of neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, hafnium oxide (HfO x ), gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide, or magnesium oxide.

[0197] In some embodiments, referring to Figure 3c 、 Figure 3d The self-selecting memory 12 can further include a buffer layer 125, which can be arranged between the functional layer (the first functional layer 121 or the second functional layer 122) and the barrier layer 124, and the electron affinity of the buffer layer 125 is between the functional layer and the barrier layer 124. The electron affinity of the buffer layer 125 is between the gating layer and the barrier layer 124, and the buffer layer 125 is used to buffer the difference in electron affinity between the gating layer and the barrier layer 124, so as to avoid performance fluctuations caused by too large difference in electron affinity between the gating layer and the barrier layer 124.

[0198] For example, the material of the buffer layer 125 can include at least one of titanium oxide (TiO x ), nickel oxide (NiO x ), molybdenum oxide (MoO x ), tungsten oxide (WO x ), vanadium oxide (VO x ), niobium oxide (NbO x ), manganese oxide (MnO x ), neodymium oxide (NdO x ), hafnium oxide (HfO x ), gallium oxide (GaO x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), silicon oxide (SiO x ), or magnesium oxide (MgO x ).

[0199] The material of the buffer layer 125 has good interface properties, which can reduce the interface state and defect state between the functional layer and the barrier layer 124, reduce the scattering and recombination probability of electrons at the interface, and improve the transmission efficiency of electrons.

[0200] According to an exemplary embodiment, this embodiment provides a method for fabricating a three-dimensional embedded non-volatile memory 1, including forming a vertically stacked multilayer memory layer 10. The formation of each memory layer 10 includes the following steps:

[0201] Step S401: Form a first selective material layer 111 on the substrate, and etch the first selective material layer 111 to form multiple first selective lines 11.

[0202] Step S402: Form a functional stack 120, which covers the top surface of the first selected material layer 111. The functional stack 120 includes at least a first functional layer 121 and a second functional layer 122.

[0203] Step S403: Pattern the functional stack 120 to form a plurality of self-select memory 12 on the side of the first selection line 11 away from the substrate; one of the first functional layer 121 and the second functional layer 122 of the self-select memory 12 is a resistive switching layer and the other is a gated layer.

[0204] In this embodiment, steps S401-S403 are implemented in the same way as steps S301-S303 in the above embodiment, and will not be described again here.

[0205] Step S404: Form a sidewall passivation layer 17 to cover the sidewall of the self-select memory 12.

[0206] In this embodiment, refer to Figure 27 As shown, and in conjunction with reference Figure 3e , Figure 3f , Figure 24 An insulating layer 171 can be formed using atomic layer deposition (ALD) technology. The insulating layer 171 covers the sidewalls and top surface of the self-select memory 12, as well as the top surface of the first dielectric layer 141 and the first select line 11 between the self-select memory 12. Anisotropic etching is then used to remove the insulating layer 171 covering the top surface of the self-select memory 12, the first dielectric layer 141, and the first select line 11. The insulating layer 171 covering the sidewalls of the self-select memory 12 forms a sidewall passivation layer 17.

[0207] In some embodiments, refer to Figure 28 As shown, and in conjunction with reference Figure 3e , Figure 3f , Figure 24 , Figure 27 After etching the insulating layer 171, an atomic layer deposition process is used to form a third dielectric layer 172 covering the insulating layer 171 on the sidewall of the self-select memory 12 and the top surface of the self-select memory 12.

[0208] For example, the material of the insulating layer 171 can include at least one of silicon oxide, silicon nitride or aluminum oxide; and the material of the third dielectric layer 172 can include silicon oxide.

[0209] Step S405: Forming the second dielectric layer 142 to fill the gaps between the self-selecting memories 12.

[0210] In this embodiment, as shown in FIG. 4A, a photoresist layer is formed on the top surface of the second dielectric layer 142, and the photoresist layer is patterned. Figure 29 As shown in FIG. 4B, the second dielectric layer 142 and the third dielectric layer 172 are etched according to the photoresist layer. Figure 28 As shown in FIG. 4C, a via is formed on the self-selecting memory 12 to expose the top surface of the self-selecting memory 12.

[0211] Step S406: Forming the conductive plug 18 on the top surface of the self-selecting memory 12.

[0212] In this embodiment, as shown in FIG. 4D, a photoresist layer is formed on the top surface of the second dielectric layer 142, and the photoresist layer is patterned. Figure 30 As shown in FIG. 4E, the second dielectric layer 142 and the third dielectric layer 172 are etched according to the photoresist layer. Figure 29 A via is formed on the self-selecting memory 12 to expose the top surface of the self-selecting memory 12.

[0213] Then, as shown in FIG. 4F, the conductive plug 18 is formed in each via by using an atomic layer deposition process or a physical vapor deposition process. Figure 31 As shown in FIG. 4G, the material of the conductive plug 18 is removed by grinding to disconnect the conductive plugs 18 to achieve electrical isolation. Figure 3e 、 Figure 3f 、 Figure 24 、 Figure 30 The material of the conductive plug 18 can include tungsten nitride or the like.

[0214] In some other embodiments, the second dielectric layer 142 can be ground to expose the top surface of the third dielectric layer 172, and then the third dielectric layer 172 on the top surface of the self-selecting memory 12 is removed by wet etching to form a via.

[0215] Step S407: Forming the second selection material layer 131 to cover the top surface of each conductive plug 18 and the top surface of the second dielectric layer 142, and etching the second selection material layer 131 to form a plurality of second selection lines 13.

[0216] In this embodiment, as shown in FIG. 4H, a photoresist layer is formed on the top surface of the second selection material layer 131, and the photoresist layer is patterned. Figure 32 As shown in FIG. 4I, the second selection material layer 131 is etched according to the photoresist layer. Figure 3e 、 Figure 3f 、 Figure 24 The second selection material layer 131 can include a metal material or a semiconductor material.Figure 31 The self-selecting memory 12 is connected with the second select line 13 above it through the conductive plug 18. The conductive plug 18 is in contact with the top surface of the self-selecting memory 12 through the sidewall passivation layer 17 to connect the self-selecting memory 12 with the second select line 13 above it.

[0217] When the process required height difference between the first select line 11 and the second select line 13 of the self-selecting memory 12, the conductive plug 18 is formed on the self-selecting memory 12 to increase the height of the self-selecting memory 12 through the conductive plug 18 so that the height of the self-selecting memory 12 meets the process required height difference between the first select line 11 and the second select line 13.

[0218] The technical features of the above-described embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features of the above-described embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered as falling within the scope of the present disclosure.

[0219] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A three-dimensional embedded nonvolatile memory, characterized by, The three-dimensional embedded nonvolatile memory is integrated with a logic chip; The three-dimensional embedded nonvolatile memory comprises a plurality of vertically stacked memory layers; Each of the memory layers comprises: a first selection line extending in a first direction and spaced apart in a second direction; a second selection line extending in the second direction and spaced apart in the first direction, the first direction intersecting the second direction; a self-selecting memory disposed at the intersection of the first selection line and the second selection line, in a vertical direction, between the first selection line and the second selection line, each of the self-selecting memories comprising at least one functional layer.

2. The 3D embedded nonvolatile memory of claim 1, wherein, Adjacent layers of the memory layers in the vertical direction share the first selection line or share the second selection line.

3. The 3D embedded nonvolatile memory of claim 2, wherein, When adjacent layers of the memory layers share the first selection line, the self-selecting memories in the same column are independently addressed and operated by different second selection lines. When adjacent layers of the memory layers share the second selection line, the self-selecting memories in the same row are independently addressed and operated by different first selection lines.

4. The 3D vertically stacked nonvolatile memory of any one of claims 1-3, wherein, The self-selecting memory comprises a first functional layer and a second functional layer stacked in a vertical direction, one of the first functional layer and the second functional layer being a gating layer and the other being a resistive switching layer; The resistive switching layer is reversibly switchable between a high resistance state and a low resistance state to store data; The gating layer is used to control the on-off of current in the self-selecting memory to turn on the current path of the selected self-selecting memory during read and write operations.

5. The 3D embedded nonvolatile memory of claim 4, wherein, The material of the gating layer comprises at least one of niobium oxide and vanadium oxide; The material of the resistive switching layer comprises at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, hafnium aluminum oxide.

6. The 3D embedded nonvolatile memory of claim 4, wherein, The self-selecting memory further comprises at least one auxiliary functional layer selected from at least one of the following: a heat transfer layer disposed between the first functional layer and the second functional layer, the heat transfer layer having a thermal conductivity less than that of the resistive switching layer; a barrier layer disposed between the functional layer and the first selection line to form a potential barrier with the first selection line, or disposed between the functional layer and the second selection line to form a potential barrier with the second selection line; a buffer layer disposed between the functional layer and the barrier layer, the buffer layer having an electron affinity between that of the functional layer and that of the barrier layer; a first electrode layer disposed between the first functional layer and the first selection line, and a second electrode layer disposed between the second functional layer and the second selection line; a diffusion barrier layer in contact with the first selection line or in contact with the second selection line.

7. The 3D embedded nonvolatile memory of claim 4, wherein, The three-dimensional embedded nonvolatile memory further comprises: a sidewall passivation layer covering the sidewalls of the self-selecting memory; a conductive plug disposed on the top surface of the self-selecting memory, the self-selecting memory being connected to the first selection line or the second selection line above it through the conductive plug.

8. An edge chip, characterized by The substrate and a logic chip integrated on the substrate and the three-dimensional embedded nonvolatile memory as claimed in any one of claims 1-7; The three-dimensional embedded nonvolatile memory is disposed on the logic chip, or the three-dimensional embedded nonvolatile memory and the logic chip are disposed on the substrate respectively.

9. An electronic device, comprising: The three-dimensional embedded nonvolatile memory as claimed in any one of claims 1-7, or the edge chip as claimed in claim 8.

10. A method for fabricating a three-dimensional embedded nonvolatile memory, the method comprising: The substrate and a logic chip integrated on the substrate and the three-dimensional embedded nonvolatile memory as claimed in any one of claims 1-7; Forming a plurality of first selection lines on a substrate, the first selection lines extending along a first direction and being spaced apart along a second direction; Forming a plurality of self-selecting memories on a side of the first selection lines away from the substrate, the self-selecting memories being arrayed along the first direction and the second direction; the self-selecting memories comprising a functional layer; Forming a plurality of second selection lines on a side of the self-selecting memories away from the first selection lines, the second selection lines extending along the second direction and being spaced apart along the first direction; the plurality of first selection lines, the plurality of self-selecting memories and the plurality of second selection lines forming a storage layer; Repeating the steps of forming the plurality of first selection lines, forming the plurality of self-selecting memories and forming the plurality of second selection lines to form a plurality of vertically stacked storage layers.

11. The method of claim 10, wherein the three-dimensional embedded nonvolatile memory is formed by a process comprising: Forming the storage layer comprises: Forming a first selection material layer and a functional stack on the substrate, the functional stack comprising at least a first functional layer and a second functional layer; Etching the functional stack and the first selection material layer to form first grooves extending along the first direction, and dividing the first selection material layer into the plurality of first selection lines; Forming a second selection material layer covering a top surface of the functional stack; Etching the second selection material layer and the functional stack to form second grooves extending along the second direction, and dividing the second selection material layer into the plurality of second selection lines; the first grooves and the second grooves dividing the functional stack into the plurality of self-selecting memories; one of the first functional layer and the second functional layer of the self-selecting memories being a resistive switching layer and the other being a gating layer.

12. The method of claim 10, wherein the three-dimensional embedded nonvolatile memory is formed by a process comprising: Forming the storage layer comprises: Forming a first selection material layer on the substrate and etching the first selection material layer to form the plurality of first selection lines; Forming a functional stack covering a top surface of the first selection material layer, the functional stack comprising at least a first functional layer and a second functional layer; Patterning and etching the functional stack to form the plurality of self-selecting memories on a side of the first selection lines away from the substrate; one of the first functional layer and the second functional layer of the self-selecting memories being a resistive switching layer and the other being a gating layer; Forming a second selection material layer on a side of the self-selecting memories away from the first selection lines and etching the second selection material layer to form the plurality of second selection lines.

13. The method of claim 10, wherein the three-dimensional embedded nonvolatile memory is formed by a process comprising: Adjacent layers of the storage layer in a vertical direction share the first selection lines or share the second selection lines.

14. The method of claim 10, wherein the three-dimensional embedded nonvolatile memory is fabricated by a process comprising: The substrate is a logic chip formed with a CMOS circuit.

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