Semiconductor device

Abstract

The invention relates to the technical field of semiconductors, and provides a semiconductor device, which comprises a substrate; the epitaxial layer is located on the substrate, the epitaxial layer comprises a plurality of injection regions extending from the surface of the side, away from the substrate, of the epitaxial layer to the interior of the epitaxial layer, the doping type of the injection regions is opposite to that of other regions in the epitaxial layer, and the injection regions comprise a plurality of first injection regions and a plurality of second injection regions; the area of the orthographic projection of the first injection region on the substrate is larger than that of the orthographic projection of the second injection region on the substrate, and a plurality of second injection regions are arranged around each first injection region; the first insulating layer is located on the side, away from the substrate, of the epitaxial layer, the first insulating layer comprises a plurality of first insulating parts, the first insulating parts cover at least part of the epitaxial layer between the first injection region and the second injection region, and the first insulating parts make contact with the first injection region and the second injection region; and the Schottky metal layer is positioned on one side, deviating from the substrate, of the epitaxial layer and the first insulating layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device. BACKGROUND

[0002] A Schottky Barrier Diode (SBD), also known as a Schottky diode, is a diode that uses the Schottky barrier of the interface between a metal and a semiconductor as its basic functional unit. The Schottky diode has the characteristics of fast switching speed, low reverse recovery time and low forward voltage drop, which makes it widely used in power electronic fields such as high-frequency switching circuit, power converter and protection circuit.

[0003] The above information disclosed in the background section is only used to enhance the understanding of the background of the technology described herein, therefore, the background section can contain some information which is not considered as prior art by those skilled in the art in the country. SUMMARY

[0004] The main purpose of the present application is to provide a semiconductor device to solve the problem of insufficient large current adaptability of the semiconductor device in the prior art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor device is provided, comprising: a substrate; an epitaxial layer located above the substrate, the epitaxial layer comprising a plurality of implantation regions extending from the surface of the epitaxial layer away from the substrate to the interior of the epitaxial layer, the implantation regions having a doping type opposite to that of other regions in the epitaxial layer, the plurality of implantation regions comprising a plurality of first implantation regions and a plurality of second implantation regions, the area of the orthographic projection of the first implantation region on the substrate being greater than that of the second implantation region, and a plurality of second implantation regions being arranged around each first implantation region; a first insulating layer located on the side of the epitaxial layer away from the substrate, the first insulating layer comprising a plurality of first insulating portions, the first insulating portions covering at least part of the epitaxial layer between the first implantation regions and the second implantation regions, and the first insulating portions being in contact with the first implantation regions and the second implantation regions; and a Schottky metal layer located on the side of the epitaxial layer and the first insulating layer away from the substrate.

[0006] In some embodiments of the present application, the first insulating portions are arranged one by one corresponding to the first implantation regions, and each first insulating portion is in contact with a plurality of second implantation regions; or the first insulating portions are arranged one by one corresponding to the second implantation regions, and a plurality of first insulating portions in contact with the same first implantation region are arranged at intervals and have uniform spacing in the circumferential direction of the first implantation region.

[0007] In some embodiments of the present application, when the first insulating portion is arranged one-to-one corresponding to the first implantation region, a projection of the first insulating portion on a surface of the epitaxial layer away from the substrate surrounds the corresponding first implantation region.

[0008] In some embodiments of the present application, the first insulating portion covers at least one second implantation region adjacent to the first implantation region.

[0009] In some embodiments of the present application, the semiconductor device further comprises a first ohmic metal layer between the epitaxial layer and the Schottky metal layer, the first ohmic metal layer comprising a plurality of ohmic contact portions arranged one-to-one corresponding to the first implantation region, and a projection of the ohmic contact portion on a surface of the epitaxial layer away from the substrate falls in the first implantation region.

[0010] In some embodiments of the present application, the first insulating portion is connected to an edge of the ohmic contact portion.

[0011] In some embodiments of the present application, the thickness of the first insulating layer is greater than the thickness of the first ohmic metal layer.

[0012] In some embodiments of the present application, the semiconductor device further comprises a second insulating layer on a side of the substrate away from the epitaxial layer, the second insulating layer comprising a plurality of second insulating portions arranged at intervals; and a second ohmic metal layer on a side of the second insulating layer away from the substrate.

[0013] In some embodiments of the present application, the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

[0014] In some embodiments of the present application, the distance between any two adjacent second insulating portions is equal.

[0015] The beneficial effects of the present application are as follows:

[0016] The application provides a semiconductor device, comprising: a substrate; an epitaxial layer located above the substrate, the epitaxial layer comprising a plurality of implantation regions extending from a surface of the epitaxial layer away from the substrate to an interior of the epitaxial layer, a doping type of the implantation regions being opposite to a doping type of other regions in the epitaxial layer, the plurality of implantation regions comprising a plurality of first implantation regions and a plurality of second implantation regions, an area of a footprint of the first implantation regions on the substrate being larger than an area of a footprint of the second implantation regions on the substrate, and a plurality of the second implantation regions being arranged around each of the first implantation regions; a first insulating layer located at a side of the epitaxial layer away from the substrate, the first insulating layer comprising a plurality of first insulating portions, the first insulating portions covering at least part of the epitaxial layer between the first implantation regions and the second implantation regions, and the first insulating portions being in contact with the first implantation regions and the second implantation regions; and a Schottky metal layer located at the side of the epitaxial layer and the first insulating layer away from the substrate. By arranging the first insulating layer at the side of the epitaxial layer away from the substrate, and the first insulating layer comprising the first insulating portions, the first insulating portions covering at least part of the epitaxial layer between the first implantation regions and the second implantation regions, and the first insulating portions being in contact with the first implantation regions and the second implantation regions, when the PN junction in the Schottky diode is turned on under a large current condition, the movement of electrons from the region covered by the first insulating layer to the Schottky metal layer is prevented, thereby increasing the electron concentration in the epitaxial layer, improving the implantation efficiency of the implantation regions, and further reducing the resistance of the epitaxial layer, and improving the performance of the device under a large current condition. BRIEF DESCRIPTION OF DRAWINGS

[0017] One or more embodiments are illustrated by way of example in the figures that form a part of this disclosure and which are illustrative of various embodiments of devices disclosed herein. Unless otherwise specifically noted, the drawings shown are not necessarily to scale, the specific dimensions being provided solely for the purpose of providing example of embodiments of the present application. In the figures:

[0018] Figure 1 A cross-sectional structure schematic diagram of a semiconductor device according to an embodiment of the present application is provided.

[0019] Figure 2 A planar structure schematic diagram of a semiconductor device according to an embodiment of the present application is provided.

[0020] Figure 3 A planar structure schematic diagram of another semiconductor device according to an embodiment of the present application is provided.

[0021] Figure 4 A planar structure schematic diagram of another semiconductor device according to an embodiment of the present application is provided.

[0022] Figure 5 This is a schematic cross-sectional view of another semiconductor device provided according to an embodiment of this application;

[0023] Figure 6 This is a schematic cross-sectional view of another semiconductor device provided according to an embodiment of this application;

[0024] Figure 7 This is a schematic cross-sectional view of another semiconductor device provided according to an embodiment of this application.

[0025] The above figures include the following reference numerals:

[0026] 1. Substrate; 2. Epitaxial layer; 21. First implantation region; 22. Second implantation region; 23. Third implantation region; 3. First insulating layer; 30. First insulating portion; 4. Schottky metal layer; 5. First ohmic metal layer; 50. Ohmic contact portion; 6. Second ohmic metal layer; 7. Second insulating layer; 70. Second insulating portion; w1. First spacing; w2. Second spacing. Detailed Implementation

[0027] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0028] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0029] When a component "includes" another component, unless otherwise stated, other components are not excluded, and may be further included. Furthermore, when a component such as a layer, film, region, or plate is said to be "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or there can be another component present in between. Additionally, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located in between.

[0030] The term "and / or" merely describes association between associated objects, and can indicate three cases, for example, A and / or B can indicate that there are A, A and B exist, and B exists. In addition, the character " / " in this paper generally indicates that the front and rear associated objects are a "or" relationship.

[0031] The terms "first", "second", etc. are used to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. It should be understood that the terms thus used can be interchanged under appropriate circumstances to describe the embodiments of the present application.

[0032] When an element (such as a layer, film, region, or substrate) is described as "on" another element, it can be directly on the other element, or there can be an intermediate element. Moreover, in the specification and claims, the terms "mount", "connect", "connect", "fix", and the like should be broadly understood, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0033] The orientation or position relationship indicated by "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the embodiments of the present application and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the embodiments of the present application. In addition, in the drawings corresponding to the embodiments of the present application, the thickness and area of the layer are enlarged for better understanding and convenience of description.

[0034] In addition, the reference to "embodiments" in this paper means that the specific features, structures or characteristics described in conjunction with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment that is not mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application.

[0036] Figure 1 A cross-sectional structure schematic diagram of a semiconductor device provided according to an embodiment of the present application.

[0037] As shown in Figure 1 , the semiconductor device can include a substrate 1, an epitaxial layer 2, a first insulating layer 3 and a Schottky metal layer 4, and the semiconductor device in the embodiment of the present application is specifically a Schottky diode, and the above components will be described in detail in turn.

[0038] The substrate 1 can be a silicon carbide substrate. Silicon carbide has the characteristics of high electron mobility, low resistivity and wide band gap, which can make the Schottky diode have a lower voltage drop when conducting in the forward direction, and can withstand a higher working temperature and a wider temperature range change, so that the Schottky diode can maintain good conduction ability. In addition, silicon carbide also has the characteristics of high breakdown voltage, which can make the Schottky diode be able to withstand a higher voltage without breakdown or damage, so that the Schottky diode has stronger protection ability when facing a sudden high voltage surge, that is, the Schottky diode has better surge capacity. The silicon carbide substrate can be doped to regulate its electrical properties. For example, nitrogen elements can be doped into the substrate 1 to form an N-type doped substrate 1.

[0039] The epitaxial layer 2 is located above the substrate 1, and the material and the doping type of the epitaxial layer 2 are the same as those of the substrate 1. For example, the substrate 1 and the epitaxial layer 2 are both silicon carbide materials, and both are N-type doped. The doping concentration of the epitaxial layer 2 can be different from that of the substrate 1. For example, the doping concentration of the epitaxial layer 2 is lower than that of the substrate 1, so as to reduce the resistance of the device while ensuring that the device can withstand high reverse voltage and prevent breakdown.

[0040] The epitaxial layer 2 includes a plurality of implantation regions, and the implantation regions extend from the surface of the epitaxial layer 2 away from the substrate 1 to the inside of the epitaxial layer 2. The doping type of the implantation region is opposite to that of other regions in the epitaxial layer 2. For example, other regions in the epitaxial layer 2 are N-type doped, and the implantation region is P-type doped. The implantation region can be formed by directly performing ion implantation process and heat activation process in the epitaxial layer 2. In actual application, grooves can also be formed in the epitaxial layer 2, and doping can be performed in the same or different substrate as the epitaxial layer 2, and then the doped substrate is filled into the grooves of the epitaxial layer 2. The forming method of the implantation region is not limited in the embodiment of the present application. It can be understood that the depth of the implantation region is less than the thickness of the epitaxial layer 2.

[0041] Under high current conditions, the holes generated by the P-type doping in the implanted region can modulate the conductivity of the surrounding N-type region. This conductivity modulation effect can significantly reduce the forward voltage drop of the Schottky diode, reduce the power consumption of the Schottky diode in the on-state, and improve the Schottky diode's ability to handle instantaneous high currents, i.e., improve the device's surge capability. Furthermore, the PN junction formed between the N-type and P-type implanted regions in epitaxial layer 2 can effectively block the flow of electrons under reverse bias, thereby reducing reverse leakage current, improving the device's reverse blocking capability, and forming a deeper potential well, thus increasing the device's breakdown voltage, i.e., improving the device's breakdown voltage capability.

[0042] Figure 2 This is a schematic diagram of a planar structure of a semiconductor device according to an embodiment of this application. It should be understood that... Figure 2 This diagram is only used to illustrate the arrangement of the injection regions in the epitaxial layer 2, therefore the first insulating layer 3 is not shown. The first insulating layer 3 will be shown in the accompanying drawings of the corresponding embodiments in the following examples.

[0043] like Figure 1 and Figure 2 As shown, the multiple injection regions include multiple first injection regions 21 and multiple second injection regions 22. The area of ​​the orthographic projection of the first injection region 21 onto the substrate 1 is larger than the area of ​​the orthographic projection of the second injection region 22 onto the substrate 1, that is, the size of the first injection region 21 is larger than the size of the second injection region 22. Multiple second injection regions 22 are disposed around each first injection region 21. The large-sized first injection region 21 can provide a high concentration of holes, while the small-sized second injection region 22 serves as an auxiliary modulation region. When the device is in the forward conduction state, the large-sized first injection region 21 can effectively inject holes and reduce the resistance of the epitaxial layer 2, while the small-sized second injection region 22 around it can further optimize the current distribution and improve the breakdown voltage, thereby improving the breakdown voltage performance of the device.

[0044] like Figure 2 As shown, in some embodiments of this application, the plurality of injection regions may further include a plurality of third injection regions 23. The third injection regions 23 are disposed around the second injection region 22, and the distance between the third injection region 23 and the first injection region 21 is greater than the distance between the third injection region 23 and the second injection region 22. That is, with Figure 2 For example, the doped layer includes multiple repeating units. Each repeating unit is centered on a larger first implantation region 21, and its periphery is provided with multiple smaller second implantation regions 22 and third implantation regions 23. The function of the third implantation region 23 is similar to that of the second implantation region 22, and will not be described in detail here.

[0045] The shapes of any two of the first implantation region 21, the second implantation region 22, and the third implantation region 23 can be the same or different, and the implantation depths of any two of the first implantation region 21, the second implantation region 22, and the third implantation region 23 can be the same or different. The shapes of the projections of the implantation regions on the substrate 1 can be any one or more of a circle, a hexagon, a square, or other regular or irregular shapes. The shapes of the implantation regions can be designed according to actual needs, which are not limited in the embodiments of the present application. Figure 2 The second implantation region 22 can be understood as a plurality of small-size implantation regions closest to the large-size first implantation region 21 in the embodiments of the present application, but is not limited thereto.

[0046] In the same repeating unit, the distances between any two adjacent second implantation regions 22 can be the same to make the current more uniform. Similarly, in the same repeating unit, the distances between any two adjacent third implantation regions 23 can be the same to make the current more uniform. It can be understood that the distance between any two adjacent second implantation regions 22 refers to the distance between any two adjacent second implantation regions 22 in the arrangement direction of the plurality of second implantation regions 22, and the distance between any two adjacent third implantation regions 23 refers to the distance between any two adjacent third implantation regions 23 in the arrangement direction of the plurality of third implantation regions 23. The number and distance of the second implantation regions 22 and the third implantation regions 23 can be designed according to actual needs, which are not limited in the embodiments of the present application.

[0047] The first insulating layer 3 is located on the side of the epitaxial layer 2 away from the substrate 1, and can be made of an insulating material with a high dielectric constant and a high breakdown electric field strength, including but not limited to one or more of silicon oxide, silicon nitride, aluminum oxide, etc. The thickness of the first insulating layer 3 can be set according to the voltage resistance requirement of the device and the dielectric strength of the insulating material, and the specific material and thickness of the first insulating layer 3 are not limited in the embodiments of the present application.

[0048] The first insulating layer 3 includes a plurality of first insulating portions 30, the first insulating portions 30 cover at least part of the epitaxial layer 2 between the first implantation region 21 and the second implantation region 22, and the first insulating portions 30 are in contact with the first implantation region 21 and the second implantation region 22. It should be understood that the first insulating portions 30 are in contact with the first implantation region 21 and the second implantation region 22, which means that one end of the first insulating portion 30 is in contact with the first implantation region 21 and the other end is in contact with the second implantation region 22. The meaning of “contact” is that the edge of the first insulating portion 30 is in contact with the edge of the implantation region, or the edge of the first insulating portion 30 is within the range of the implantation region, that is, the projection of the first insulating portion 30 on the surface of the epitaxial layer 2 away from the substrate 1 has an overlapping part with the implantation region.

[0049] In a large current condition, the PN junction formed by the injection region (P type) and the other region (N type) of the epitaxial layer 2 except the injection region is conducted. For the convenience of description, the region of the epitaxial layer 2 except the injection region is referred to as the other region. Electrons move from the other region of the epitaxial layer 2 to the Schottky metal layer 4, and holes are injected from the injection region to the other region of the epitaxial layer 2. In the embodiment of the present application, the first insulation part 30 is arranged on the epitaxial layer 2 between the first injection region 21 and the second injection region 22. The region of the epitaxial layer 2 covered by the first insulation part 30 is isolated from the Schottky metal layer 4. Therefore, the first insulation part 30 can prevent the electrons in the region between the first injection region 21 and the second injection region 22 from flowing from the epitaxial layer 2 to the Schottky metal layer 4, thereby increasing the electron concentration of the epitaxial layer 2 in the region, i.e., the electron concentration near the first injection region 21. This means that the injection region adjacent to the region can inject more holes into the region, i.e., the conductivity modulation effect can be enhanced, thereby reducing the resistance of the epitaxial layer 2 and improving the efficiency of the device.

[0050] The Schottky metal layer 4 is located on the side of the epitaxial layer 2 and the first insulation layer 3 away from the substrate 1, and covers the epitaxial layer 2 and the first insulation layer 3. The Schottky metal can form a Schottky contact with the other region of the epitaxial layer 2 except the injection region and not covered by the first insulation layer 3. When a forward bias is applied to the device, the barrier at the Schottky contact is reduced, allowing electrons to flow from the epitaxial layer 2 to the Schottky metal layer 4, forming a current. Conversely, under a reverse bias, the Schottky barrier is increased, effectively preventing the flow of electrons, forming a reverse blocking state. The material of the Schottky metal layer 4 includes but is not limited to at least one of titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), platinum (Pt), and gold (Au). The specific material can be set according to requirements, which is not limited in the embodiment of the present application.

[0051] In the semiconductor device of the embodiment of the present application, the first insulation layer 3 is arranged on the side of the epitaxial layer 2 away from the substrate 1, and the first insulation layer 3 includes the first insulation part 30. The first insulation part 30 covers at least part of the epitaxial layer 2 between the first injection region 21 and the second injection region 22, and is in contact with the first injection region 21 and the second injection region 22. Therefore, when the PN junction in the Schottky diode is conducted in a large current condition, the movement of electrons from the region covered by the first insulation layer 3 to the Schottky metal layer 4 is prevented, thereby increasing the electron concentration in the epitaxial layer 2, improving the injection efficiency of the injection region, further reducing the resistance of the epitaxial layer 2, and improving the performance of the device in a large current condition.

[0052] Figure 3 Another planar structure of a semiconductor device according to the embodiment of the present application is provided.

[0053] As Figure 3As shown, the first insulating part 30 can be arranged one-to-one with the first injection region 21, each first insulating part 30 is in contact with a plurality of second injection regions 22, and the orthogonal projection of the first insulating part 30 on the surface of the epitaxial layer 2 away from the substrate 1 surrounds the corresponding first injection region 21. In the embodiment of the present application, the first insulating part 30 covers the entire region of the epitaxial layer 2 between the first injection region 21 and the second injection region 22, and the first insulating layer 3 can greatly block the transmission of electrons, ensuring that the area around the first injection region 21 has a high electron concentration, thereby greatly improving the injection efficiency of the injection region, keeping the resistance of the epitaxial layer 2 at a low level, reducing the on-voltage and energy loss of the device, and improving the current carrying capacity and efficiency of the device. The device using this design can be applied to application scenarios that require to handle large current.

[0054] In actual application, the first insulating part 30 can also be arranged to be in contact with only part of the second injection regions 22 among the plurality of second injection regions 22 surrounding the first injection region 21, which may cause the electron concentration of the local region of the epitaxial layer 2 to decrease slightly, but at the same time, it also provides better carrier balance opportunities and avoids non-ideal effects caused by excessively high electron concentration. This design can adapt to the situation of current concentration between specific second injection regions 22 to adapt to the requirements of special circuit layout or working mode.

[0055] Figure 4 Another planar structure schematic diagram of a semiconductor device according to an embodiment of the present application is provided.

[0056] As shown, Figure 4 The first insulating part 30 can also be arranged one-to-one with the second injection region 22, and the plurality of first insulating parts 30 in contact with the same first injection region 21 are arranged at intervals and have uniform spacing in the circumferential direction of the first injection region 21. It can be understood that the uniform spacing of the plurality of first insulating parts 30 in contact with the same first injection region 21 in the circumferential direction of the first injection region 21 means that the spacing of any two adjacent first insulating parts 30 in the plurality of first insulating parts 30 arranged in the circumferential direction of the first injection region 21 is consistent, for example, Figure 4 The first spacing w1 and the second spacing w2 in the above are consistent.

[0057] In the embodiment of the present application, by uniformly distributing the plurality of first insulating parts 30 at intervals, a plurality of independent carrier injection channels can be created, thereby improving the uniformity and control accuracy of carrier injection, avoiding excessive aggregation of carriers in a single path, and reducing non-ideal current leakage. The first insulating part 30 arranged at uniform intervals can provide uniform channels for current transmission, and the current channels are separated by the first insulating part 30, which helps to disperse the current, prevent local current density from being too high, reduce the electrothermal effect and electromigration phenomenon, and improve the stability and reliability of the device under large current conditions.

[0058] In summary, it should be understood that the coverage area of the first insulating part 30 can be designed according to actual needs, and can completely or partially cover the area of the epitaxial layer 2 between the first injection region 21 and the second injection region 22. The coverage area is related to the performance requirements of the Schottky diode. Increasing the area of the epitaxial layer 2 covered by the first insulating part 30 can increase the electron concentration near the first injection region 21, reduce the on-resistance, improve the injection efficiency of carriers, and improve the current transmission capability of the device. Reducing the area of the epitaxial layer 2 covered by the first insulating part 30 can increase the area of the Schottky contact, thereby improving the reverse breakdown voltage of the device and improving the reliability of the device. In actual applications, the area of the epitaxial layer 2 covered by the first insulating part 30 can be adjusted according to the focus of the device requirements to achieve a balance between the efficiency and reliability of the device.

[0059] In addition, the first insulating part 30 can be regular or irregular in shape, and the shapes of the first insulating parts 30 can be the same or different, which is not limited in the embodiments of the present application. Figure 5 Optionally, the shapes of the first insulating parts 30 are the same, which is not only beneficial to form a more uniform current distribution and improve the uniformity of device performance, but also beneficial to reduce the process difficulty and the probability of process defects that may be encountered, and improve the consistency of the quality of the first insulating part 30.

[0060] Figure 5 Another cross-sectional structure diagram of a semiconductor device according to an embodiment of the present application is provided.

[0061] As shown in Figure 5 , the first insulating part 30 also covers at least one second injection region 22 adjacent to the first injection region 21. The first insulating part 30 covers the second injection region 22, that is, the first insulating part 30 has a larger size, which is beneficial to reduce the alignment difficulty in the preparation process of the first insulating part 30. Moreover, since the size of the second injection region 22 is small, covering the second injection region 22 by the first insulating part 30 will not excessively affect the overall injection efficiency of the injection region, ensuring that the device can still maintain good performance.

[0062] Figure 6 Another cross-sectional structure diagram of a semiconductor device according to an embodiment of the present application is provided.

[0063] As shown in Figure 6As shown, the semiconductor device can further include a first ohmic metal layer 5, which is located between the epitaxial layer 2 and the Schottky metal layer 4, and includes a plurality of ohmic contact portions 50 corresponding to the first implanted regions 21 one by one, and the orthographic projection of the ohmic contact portions 50 on the surface of the epitaxial layer 2 away from the substrate 1 falls in the first implanted regions 21. The material of the first ohmic metal layer 5 includes, but is not limited to, at least one of nickel (Ni), aluminum (Al), titanium (Ti), copper (Cu), silver (Ag), etc.

[0064] According to the embodiment of the present application, by arranging the ohmic contact portions 50 between the first implanted regions 21 and the Schottky metal, the contact resistance at the first implanted regions 21 can be reduced, that is, the resistance of the contact between the first implanted regions 21 and the first ohmic metal layer 5 is lower than that of the direct contact between the first implanted regions 21 and the Schottky metal layer 4, thereby improving the current transmission capability of the device and the surge capability of the device.

[0065] Referring to Figure 6 , the edge of the first insulating portion 30 can be connected to the edge of the ohmic contact portion 50, so that the first insulating portion 30 can effectively shield the lateral electric field, reduce the carrier deflection and diffusion caused by the lateral electric field, further optimize the current path, and prevent the lateral transmission of electrons to the ohmic contact portion 50. In actual application, due to process deviation, the edge of the first insulating portion 30 can also have a small spacing with the edge of the ohmic contact portion 50, or a small part of the first insulating portion 30 can cover the ohmic contact portion 50, which is not limited in the embodiment of the present application.

[0066] Referring to Figure 6 , the thickness of the first insulating layer 3 can be greater than the thickness of the first ohmic metal layer 5, so that the first insulating portion 30 can completely shield the sidewall of the ohmic contact portion 50, further preventing the lateral transmission of electrons and optimizing the current transmission path in the device.

[0067] As shown in Figure 1 , Figure 5 and Figure 6 , the semiconductor device further includes a second ohmic metal layer 6, and the Schottky metal layer 4 and the second ohmic metal layer 6 respectively serve as an electrode of the semiconductor device. The material of the second ohmic metal layer 6 includes, but is not limited to, at least one of nickel (Ni), aluminum (Al), titanium (Ti), copper (Cu), silver (Ag), etc., and the material of the second ohmic metal layer 6 and the first ohmic metal layer 5 can be the same or different, which is not limited in the embodiment of the present application.

[0068] Figure 7 Fig. 6 is a schematic view of a cross section of another semiconductor device according to an embodiment of the present application.

[0069] As shown in Figure 7As shown, the semiconductor device can further include a second insulating layer 7 located on the side of the substrate 1 away from the epitaxial layer 2, and the second ohmic metal layer 6 is located on the side of the second insulating layer 7 away from the substrate 1, i.e., the second insulating layer 7 is located between the substrate 1 and the second ohmic metal layer 6. The second insulating layer 7 includes a plurality of second insulating portions 70 arranged at intervals, so that the second insulating portions 70 can block the hole flow in the covered area, thereby increasing the hole concentration in the substrate 1 and the epitaxial layer 2, reducing the resistivity of the substrate 1 and the epitaxial layer 2, and thus improving the surge capacity of the device. The area not covered by the second insulating portion 70 can be used for current passing in the normal working state of the device.

[0070] The area of the region covered by the second insulating layer 7 is not limited here, and needs to be determined according to the design purpose of the device, focusing on improving its current transmission capacity or focusing on improving its surge capacity. For example, if the design purpose is to improve the current transmission capacity of the device, the area covered by the second insulating layer 7 can be reduced, and if the design purpose is to improve the surge capacity of the device, the area covered by the second insulating layer 7 can be appropriately increased. By adjusting the size of the area covered by the second insulating layer 7, the balance between the current transmission capacity and the surge capacity of the Schottky diode can be achieved.

[0071] The thickness of the first insulating layer 3 can be greater than the thickness of the second insulating layer 7, because in some working conditions, the device can need to withstand a short-term forward and reverse voltage, and the forward blocking capacity of the device needs to be strong enough to avoid being broken down in the forward non-conductive state. In order to ensure that the device does not fail in the forward transient blocking state, the forward voltage resistance needs to be designed to be higher than the reverse voltage resistance to cope with the possible forward overvoltage working condition. The thickness of the first insulating layer 3 is designed to be greater than the thickness of the second insulating layer 7 in the embodiment of the application, which can improve the voltage resistance capacity of the device to cope with the above-mentioned forward overvoltage situation.

[0072] In some embodiments of the application, the distance between any two adjacent second insulating portions 70 is equal, i.e., the second insulating portions 70 are uniformly distributed on the side of the substrate 1 away from the epitaxial layer 2, so as to provide a uniform transmission path for the transmission of current, improve the uniformity of the current, and thus improve the reliability of the device.

[0073] It should be understood that the interval of the adjacent second insulating portions 70 can be the interval of any two adjacent second insulating portions 70 in the arrangement direction of the second insulating portions 70. For example, the plurality of second insulating portions 70 can be arranged in an array in the first direction and the second direction, the interval of any two adjacent second insulating portions 70 in the first direction is the same, the interval of any two adjacent second insulating portions 70 in the second direction is the same, and the interval of the second insulating portion 70 and the second insulating portion 70 adjacent to it in the first direction and the second direction can also be the same. The specific size and interval of the second insulating portion 70 can be designed according to actual needs, and the embodiments of the present application are not limited herein.

[0074] Based on the same concept, the embodiments of the present application also provide a preparation method of the above semiconductor device. The preparation method of the semiconductor can include the following steps:

[0075] Step S1, providing a substrate 1.

[0076] Step S2, forming an epitaxial layer 2 on the substrate 1.

[0077] Step S3, forming a first implantation region 21 and a second implantation region 22 in the epitaxial layer 2. For example, a layer of hard mask material can be first deposited on the epitaxial layer 2, and the positions of the first implantation region 21 and the second implantation region 22 are defined by a photolithography technology, and then ion implantation is performed on the first implantation region 21 and the second implantation region 22.

[0078] Step S4, forming a first insulating layer 3 on the epitaxial layer 2. For example, a layer of insulating material can be first deposited on the epitaxial layer 2, and then a part of the insulating material is removed by a patterning process (such as photolithography) to leave a first insulating portion 30 covering a part of the epitaxial layer 2 between the first implantation region 21 and the second implantation region 22.

[0079] Step S5, forming a Schottky metal layer 4 on the first insulating layer 3 and the epitaxial layer 2. For example, the above-mentioned Schottky metal layer 4 can be formed by a deposition process, and the Schottky metal layer 4 covers the first insulating layer 3 and the epitaxial layer 2.

[0080] Step S6, forming a second ohmic metal layer 6 on the side of the substrate 1 away from the epitaxial layer 2. For example, the above-mentioned second ohmic metal layer 6 can be formed by a deposition process.

[0081] After the above steps S1-S6 are completed, a semiconductor device as shown in Figure 1 or Figure 5 can be formed.

[0082] In some embodiments of the present application, between step S4 and step S5, there can further comprise step S405: forming a first ohmic metal layer 5 on the epitaxial layer 2. Illustratively, a layer of ohmic metal can be first deposited on the epitaxial layer 2, and then part of the layer of ohmic metal is removed by a patterning process, leaving the part of the layer of ohmic metal above the first injection region 21 for forming ohmic contact with the first injection region 21. After completing steps S1-S6 and step S405, a semiconductor device as shown in FIG. 4A can be formed. Figure 6

[0083] In some embodiments of the present application, between step S5 and step S6, there can further comprise step S506: forming a second insulating layer 7 on the side of the substrate 1 away from the epitaxial layer 2. Illustratively, a layer of insulating material can be deposited on the side of the substrate 1 away from the epitaxial layer 2, and then a patterning process is performed on the layer of insulating material to form a plurality of second insulating portions 70. After completing steps S1-S6 and step S506, a semiconductor device as shown in FIG. 4B can be formed. Figure 7

[0084] The technical features of the above-described embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features in the above-described embodiments are described, however, as long as the combinations of the technical features do not result in contradictions, they shall be considered within the scope of the present disclosure.

[0085] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.​​

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; an epitaxial layer on the substrate, the epitaxial layer comprising a plurality of implantation regions extending from a surface of the epitaxial layer away from the substrate into the epitaxial layer, the implantation regions having a doping type opposite to that of other regions of the epitaxial layer, the plurality of implantation regions comprising a plurality of first implantation regions and a plurality of second implantation regions, the first implantation regions having a larger area of a footprint on the substrate than the second implantation regions, and each of the first implantation regions being surrounded by the second implantation regions; a first insulating layer on a side of the epitaxial layer away from the substrate, the first insulating layer comprising a plurality of first insulating portions, the first insulating portions covering at least part of the epitaxial layer between the first implantation regions and the second implantation regions, and the first insulating portions being in contact with the first implantation regions and the second implantation regions; a Schottky metal layer on a side of the epitaxial layer and the first insulating layer away from the substrate.

2. The semiconductor device according to claim 1, wherein The first insulating portions are in one-to-one correspondence with the first implantation regions, and each of the first insulating portions is in contact with the second implantation regions; or, the first insulating portions are in one-to-one correspondence with the second implantation regions, and the first insulating portions in contact with the same first implantation region are spaced apart and have a uniform spacing in a circumferential direction of the first implantation region.

3. The semiconductor device of claim 2, wherein, When the first insulating portions are in one-to-one correspondence with the first implantation regions, a footprint of the first insulating portions on the surface of the epitaxial layer away from the substrate surrounds the corresponding first implantation regions.

4. The semiconductor device of claim 1, wherein The first insulating portions cover at least one of the second implantation regions adjacent to the first implantation regions.

5. The semiconductor device of claim 1, wherein The semiconductor device further comprises: a first ohmic metal layer between the epitaxial layer and the Schottky metal layer, the first ohmic metal layer comprising a plurality of ohmic contact portions in one-to-one correspondence with the first implantation regions, and a footprint of the ohmic contact portions on the surface of the epitaxial layer away from the substrate falling within the first implantation regions.

6. The semiconductor device of claim 5, wherein, The first insulating portions are in contact with edges of the ohmic contact portions.

7. The semiconductor device of claim 5, wherein The first insulating layer has a thickness greater than that of the first ohmic metal layer.

8. The semiconductor device according to any one of Claims 1 to 7, wherein The semiconductor device further comprises: a second insulating layer on a side of the substrate away from the epitaxial layer, the second insulating layer comprising a plurality of second insulating portions spaced apart; a second ohmic metal layer on a side of the second insulating layer away from the substrate.

9. The semiconductor device of claim 8, wherein, The first insulating layer has a thickness greater than that of the second insulating layer.

10. The semiconductor device of claim 8, wherein, Any two adjacent second insulating portions have an equal spacing.

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