Semiconductor device

Abstract

A semiconductor device includes an oxide semiconductor layer, a gate electrode disposed separately from the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The gate insulating layer includes a plurality of layers having different energy band gaps. The gate insulating layer includes a plurality of first insulating layers disposed apart from each other in a thickness direction of the gate insulating layer, a second insulating layer between the first group of adjacent first insulating layers and having a smaller energy band gap than each first insulating layer, and a third insulating layer between the second set of adjacent first insulating layers and having a larger energy band gap than each of the first insulating layers. The third insulating layer is closer to the oxide semiconductor layer than the second insulating layer.

Description

TECHNICAL FIELD

[0001] The present inventive concepts relate to semiconductor devices, and more particularly, to semiconductor devices including an oxide semiconductor. BACKGROUND

[0002] As a semiconductor device that performs an electric switching function, a transistor has been used for various integrated circuit (IC) devices including memories, driver ICs, logic devices, and the like. In order to increase the degree of integration of IC devices, the space occupied by transistors arranged therein is rapidly reduced, and thus, research has been conducted to reduce the size of transistors while maintaining the performance of the transistors.

[0003] As a transparent semiconductor device having a characteristic of having a wide band gap of 3.0 eV or more, an oxide semiconductor device has been researched for many years. An oxide semiconductor device used as a large-area display driver device has excellent characteristics such as a low off-state current and a high on / off ratio. Research has been conducted to use an oxide semiconductor device having such advantages as a memory or a logic device. SUMMARY

[0004] Some example embodiments of the present inventive concepts include a semiconductor device including a gate insulating layer including a plurality of insulating layers having different energy band gaps stacked therein.

[0005] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description or can be learned by practice of the presented embodiments of the present inventive concepts.

[0006] According to some example embodiments of the present inventive concepts, a semiconductor device includes an oxide semiconductor layer, a gate electrode arranged apart from the oxide semiconductor layer, and a gate insulating layer arranged between the oxide semiconductor layer and the gate electrode in a thickness direction of the gate insulating layer, wherein the gate insulating layer includes a plurality of first insulating layers arranged apart from each other in the thickness direction of the gate insulating layer, a second insulating layer arranged between a first group of adjacent first insulating layers among the plurality of first insulating layers and having a smaller energy band gap than the first insulating layers, and a third insulating layer arranged between a second group of adjacent first insulating layers among the plurality of first insulating layers and having a larger energy band gap than the first insulating layers, and wherein the third insulating layer is closer to the oxide semiconductor layer than the second insulating layer.

[0007] The content of the second insulating layer in the gate insulating layer can be 10 at% or less.

[0008] The content of the third insulating layer in the gate insulating layer can be 10 at% or less.

[0009] The plurality of first insulating layers can include two outermost first insulating layers among the plurality of first insulating layers in a thickness direction of the gate insulating layer and at least one inner first insulating layer between the two outermost first insulating layers, and each of the two outermost first insulating layers among the plurality of first insulating layers has a thickness in a vertical direction that is greater than or equal to a thickness of the gate insulating layer in the thickness direction of the gate insulating layer.

[0010] One of the two outermost first insulating layers contacts the oxide semiconductor layer.

[0011] One of the two outermost first insulating layers contacts the gate electrode.

[0012] The first insulating layer among the plurality of first insulating layers can be disposed between the second insulating layer and the third insulating layer.

[0013] Each of the plurality of first insulating layers has a thickness in a thickness direction of the gate insulating layer that is greater than a thickness of each of the second insulating layer and the third insulating layer in the thickness direction of the gate insulating layer.

[0014] At least one of the second insulating layer and the third insulating layer can include a monatomic layer.

[0015] At least one of the second insulating layer and the third insulating layer has a thickness in a thickness direction of the gate insulating layer that is 3 Å or less.

[0016] Each of the plurality of first insulating layers has a thickness in a thickness direction of the gate insulating layer that is 5 Å or more.

[0017] The gate insulating layer has a thickness in a thickness direction of the gate insulating layer that is about 3 nm to about 10 nm.

[0018] A total of layers of the plurality of first insulating layers, the second insulating layer, and the third insulating layer can be 4n+1, where n is a natural number.

[0019] The second insulating layer can include a plurality of second insulating layers and the third insulating layer can include a plurality of third insulating layers, and the plurality of second insulating layers and the plurality of third insulating layers can be alternately disposed one after another in a thickness direction of the gate insulating layer.

[0020] The first insulating layer among the plurality of first insulating layers can be disposed between the second insulating layer and the third insulating layer.

[0021] A band gap difference between the second insulating layer and the third insulating layer can be 5 eV or more.

[0022] The third insulating layer can include an oxide including at least one of silicon (Si) and magnesium (Mg).

[0023] The second insulating layer can include at least one of titanium (Ti) and hafnium (Hf).

[0024] A band gap difference between the first insulating layer among the plurality of first insulating layers and at least one of the second insulating layer and the third insulating layer can be 2 eV or more.

[0025] The plurality of first insulating layers can each independently include an oxide including at least one of aluminum (Al), calcium (Ca), yttrium (Y), zirconium (Zr), and hafnium (Hf).

[0026] The semiconductor device can further include a bit line electrically connected to one end of the oxide semiconductor layer and a capacitor electrically connected to the other end of the oxide semiconductor layer, wherein the gate electrode can be an element of a word line. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and other aspects, features and advantages of some example embodiments of the inventive concepts will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a diagram illustrating a semiconductor device according to some example embodiments;

[0029] Figure 2 is a diagram illustrating a semiconductor device including a plurality of second insulating layers and a plurality of third insulating layers according to some example embodiments;

[0030] Figure 3 is a diagram illustrating results of measuring performance of a semiconductor device including various types of insulating layers according to some example embodiments;

[0031] Figure 4 is a diagram illustrating results of measuring positive bias temperature instability (PBTI) of a semiconductor device according to some example embodiments;

[0032] Figure 5 is a diagram illustrating results of measuring negative bias temperature instability (NBTI) of a semiconductor device according to some example embodiments;

[0033] Figure 6 is a diagram illustrating a semiconductor device as a transistor according to some example embodiments;

[0034] Figure 7 is a diagram illustrating a semiconductor device further including a plurality of gate electrodes according to some example embodiments;

[0035] Figure 8 is a diagram illustrating a semiconductor device according to some example embodiments;

[0036] Figure 9 is a diagram illustrating a semiconductor device according to some example embodiments;

[0037] Figure 10 is a diagram illustrating a semiconductor device according to some example embodiments;

[0038] Figure 11 is a diagram illustrating a semiconductor device according to some example embodiments;

[0039] Figure 12 is a perspective view illustrating a schematic structure of a vertically stacked memory device according to some example embodiments;

[0040] Figure 13 is a perspective view illustrating a schematic structure of a vertically stacked memory device according to some example embodiments;

[0041] Figure 14 is a block diagram illustrating an electronic system according to some example embodiments; and

[0042] Figure 15 is a block diagram of an electronic system according to some example embodiments. DETAILED DESCRIPTION

[0043] Reference will now be made in detail embodiments, some example embodiments of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the drawings, to explain aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the list of elements individually.

[0044] Hereinafter, a semiconductor device including a multi-layer structure according to various embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings will represent the same elements, and the size of elements in the drawings can be exaggerated for clarity and convenience of description.

[0045] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, when a certain element is referred to as being "included," unless otherwise indicated, it is understood that the certain element can be included, without being limited to, another element. Also, the size and thickness of each element shown in the drawings can be exaggerated or reduced for the purpose of description. Further, when a layer, region or element is referred to as being "on" another layer, region or element, it can be directly on the other layer, region or element, or intervening layers, regions or elements can be present. Also, in the following embodiments, because the material forming each layer is merely an example, other materials can also be used.

[0046] Further, as used herein, the terms "unit" and "module" can refer to a unit that performs at least one function or operation, and the unit can be implemented as hardware or software or a combination of hardware and software.

[0047] The specific embodiments described in the present embodiments are merely examples and do not limit the scope of the inventive concept in any way. For the sake of clarity, descriptions of related art electronic configurations, control systems, software, and other functional aspects of the system can be omitted.

[0048] Further, the connection or connecting member between elements shown in the drawings can represent a functional connection and / or a physical or logical connection, and can be represented as various alternative or additional functional connections, physical connections, or logical connections in actual devices.

[0049] The use of the terms "a" and "the" and other similar referents are to be construed as covering both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context.

[0050] Expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, expressions such as "at least one of A, B, and C" or "at least one of the group consisting of A, B, and C" can be construed as merely A, B, or C individually, or any combination of A, B, and C, such as A, B, and C, A and B, B and C, and A and C.

[0051] It will be understood that elements and / or their properties (e.g., structures, surfaces, directions, etc.) that can be referred to as being "perpendicular," "parallel," "coplanar," etc., with respect to other elements and / or their properties may, respectively, be "perpendicular," "parallel," "coplanar," etc., with respect to the other elements and / or their properties, or may, respectively, be "substantially perpendicular," "substantially parallel," "substantially coplanar," with respect to the other elements and / or their properties.

[0052] Elements and / or properties thereof that are “substantially perpendicular,” “substantially parallel,” or “substantially coplanar” relative to other elements and / or properties thereof will be understood to be “perpendicular,” “parallel,” or “coplanar,” respectively, relative to other elements and / or properties thereof within manufacturing tolerances and / or material tolerances, and / or can have magnitude and / or angular deviations from “perpendicular,” “parallel,” or “coplanar,” respectively, that are equal to or less than 10% (e.g., tolerances of ±10%) relative to other elements and / or properties thereof.

[0053] It will be understood that elements and / or properties thereof can be recited herein as being “in accordance with,” “the same as,” or “equal to” other elements and / or properties thereof, and it will be further understood that elements and / or properties recited herein as being “in accordance with,” “the same as,” or “equal to” other elements and / or properties thereof can be “in accordance with,” “the same as,” or “equal to” or “substantially in accordance with,” “substantially the same as,” or “substantially equal to” other elements and / or properties thereof. Elements and / or properties that are “substantially in accordance with,” “substantially the same as,” or “substantially equal to” other elements and / or properties thereof will be understood to include elements and / or properties that are in accordance with, the same as, or equal to other elements and / or properties thereof within manufacturing tolerances and / or material tolerances. Elements and / or properties that are in accordance with or substantially in accordance with, equal to or substantially equal to, and / or the same as or substantially the same as other elements and / or properties thereof can be structurally the same or substantially the same, functionally the same or substantially the same, and / or compositionally the same or substantially the same. While the terms “the same,” “equal,” or “in accordance with” can be used in the description of some example embodiments, it will be understood that there can be some imprecision. Thus, when an element or property is referred to as being in accordance with, equal to, or the same as another element or property, it will be understood that the element or property is the same as the other element or property within a desired range of manufacturing or operational tolerances (e.g., ±10%).

[0054] It will be understood that elements and / or properties described herein as being “substantially” the same, equal, and / or in accordance with encompass elements and / or properties having relative magnitude differences equal to or less than 10%. Furthermore, whether or not elements and / or properties are modified as “substantially,” it will be understood that these elements and / or properties should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the recited elements and / or properties.

[0055] When the term "about" or "substantially" is used in the description herein in connection with a numerical value, it is intended to encompass manufacturing or operational tolerances around the stated value (e.g., ±10%). Moreover, when the words "about" and "substantially" are used in connection with a geometric shape, it is intended that precision of the geometric shape is not required, but rather a tolerance of the shape is within the scope of the present disclosure. Furthermore, whether or not a numerical value or shape is modified by "about" or "substantially", it will be understood that such values and shapes are to be interpreted to include manufacturing or operational tolerances around the stated value or shape (e.g., ±10%). When a range is specified, the range includes all values therebetween, such as in increments of 0.1%.

[0056] As described herein, when an operation is described as being performed, or an effect of a structure is described as being established "by" or "through" performance of an additional operation, it will be understood that the operation can be performed "based on" the additional operation and / or the effect / structure can be established "based on" the additional operation, which can include performing the additional operation alone or in combination with other further additional operations.

[0057] As described herein, elements described as being "spaced apart from" or "disposed apart from" another element (e.g., vertically spaced apart, laterally spaced apart, etc.) generally and / or in a particular direction and / or elements described as being "separated from" another element can be understood to be isolated from the other element generally and / or in the particular direction without direct contact (e.g., isolated from the other element in a vertical direction without direct contact, isolated from the other element in a lateral or horizontal direction without direct contact, etc.). Similarly, elements described as being "spaced apart from" each other (e.g., vertically spaced apart, laterally spaced apart, etc.) generally and / or in a particular direction and / or elements described as being "separated from" each other can be understood to be isolated from each other generally and / or in the particular direction without direct contact (e.g., isolated from each other in a vertical direction without direct contact, isolated from each other in a lateral or horizontal direction without direct contact, etc.). Similarly, structures described herein as being between two other structures to separate the two other structures from each other can be understood to be configured to isolate the two other structures from direct contact with each other.

[0058] Although terms such as "first" and "second" can be used herein to describe various elements or components, these elements or components should not be limited by such terms. These terms are only used to distinguish one element or component from another.

[0059] All examples or illustrative terms used herein are intended to be non- limiting examples of the technical idea of the present inventive concept, and the scope of the present inventive concept is not limited to such examples or illustrative terms unless otherwise specified in the appended claims.

[0060] Figure 1is a diagram illustrating a semiconductor device 1 according to some example embodiments. Figure 1 The semiconductor device 1 can be a transistor or a memory cell. Referring to Figure 1 The semiconductor device 1 can include an oxide semiconductor layer 10, a gate electrode 20 arranged apart from the oxide semiconductor layer 10, and a gate insulating layer 30 arranged between the oxide semiconductor layer 10 and the gate electrode 20. It will be understood that an element recited herein as being "arranged apart from" another element can be referred to interchangeably as being "spaced apart from" the other element, "isolated from direct contact with" the other element, and the like.

[0061] The oxide semiconductor layer 10 according to some example embodiments can include an oxide of a material selected from Group 12, Group 13, and Group 14 metal elements, such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), or hafnium (Hf), or any combination thereof. For example, the oxide semiconductor layer 10 can include a Zn-oxide based material, such as Zn-oxide, In-Zn-oxide, or In-Ga-Zn-oxide. As an example, the oxide semiconductor layer 10 can be provided in a single layer or a multi-layer structure. The oxide semiconductor layer 10 can have a thickness of about 10 nm or less, about 8 nm or less, or about 7 nm or less. For example, the oxide semiconductor layer 10 can have a thickness of about 0.01 nm to about 10 nm, about 0.01 nm to about 8 nm, or about 0.01 nm to about 7 nm. Oxide semiconductors can have excellent properties, such as low off-current, low subthreshold swing, and high on / off ratio, and thus can be used in memory devices or logic devices.

[0062] The semiconductor device 1 according to some example embodiments can include a gate electrode 20 arranged apart from the oxide semiconductor layer 10. The gate electrode 20 can include at least one of tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), titanium (Ti), molybdenum (Mo), chromium (Cr), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), silver (Ag), gold (Au), aluminum (Al), copper (Cu), tin (Sb), vanadium (V), ruthenium (Ru), platinum (Pt), zinc (Zn), and magnesium (Mg). When the semiconductor device 1 is a component of a memory cell, the gate electrode 20 can be a partial region of a word line.

[0063] The semiconductor device 1 according to some example embodiments can include a gate insulating layer 30 arranged between the oxide semiconductor layer 10 and the gate electrode 20. The gate insulating layer 30 can be in the form of a stack of multiple layers having different energy bandgaps. For example, the gate insulating layer 30 can include multiple layers arranged such that the energy bandgaps increase and decrease repeatedly in a direction from the oxide semiconductor layer 10 to the gate electrode 20 (or a thickness direction of the insulating layer, or a Z-axis direction). The Z-axis direction can be interchangeably referred to herein as a vertical direction, a thickness direction, and the like. The thickness (e.g., thickness in the Z-axis direction) of the gate insulating layer 30 can be about 3 nm to about 10 nm. As described herein, the thickness direction, the Z-axis direction, and the like can be a direction extending perpendicular to a surface of the semiconductor device 1 (e.g., perpendicular to an upper surface 10u of the oxide semiconductor layer 10 facing the gate electrode 20 and the gate insulating layer 30). Thus, the X-axis and Y-axis directions, which can be referred to as a horizontal direction, a first horizontal direction, and a second horizontal direction, and the like, can extend perpendicular to the Z-axis direction and can extend perpendicular to each other and / or can each extend parallel to a surface of the semiconductor device 1 (e.g., parallel to the upper surface 10u of the oxide semiconductor layer 10 facing the gate electrode 20 and the gate insulating layer 30).

[0064] The gate insulating layer 30 according to some example embodiments can include a plurality of first insulating layers 31 arranged apart (e.g., spaced apart) from each other in a thickness direction (Z-axis direction) of the gate insulating layer 30. The plurality of first insulating layers 31 can be three or more in number. For example, the plurality of first insulating layers 31 can include two first insulating layers 31a and 31b (which can be interchangeably referred to herein as two outermost first insulating layers 31a and 31b) arranged at an outer side among the plurality of first insulating layers 31 and one or more first insulating layers 31c (which can be interchangeably referred to herein as one or more inner first insulating layers 31c each between two or more first insulating layers among the plurality of first insulating layers 31) arranged at an inner side among the plurality of first insulating layers 31. Restated, the plurality of first insulating layers 31 can include two outermost first insulating layers 31a and 31b in the Z-axis direction among the plurality of first insulating layers 31 and one or more inner first insulating layers 31c each between two or more first insulating layers among the plurality of first insulating layers 31 (e.g., between at least the two outermost first insulating layers 31a and 31b) in the Z-axis direction. Among the two first insulating layers 31a and 31b arranged at the outer side (e.g., the two outermost first insulating layers), one first insulating layer 31a can contact (e.g., directly contact) the oxide semiconductor layer 10, and the other first insulating layer 31b can contact (e.g., directly contact) the gate electrode 20.

[0065] The thickness of each of the plurality of first insulating layers 31 can be about 5 A or more, for example, between about 5 A and about 500 A, between about 5 A and about 100 A, between about 5 A and about 50 A, or between about 5 A and about 10 A. The thickness of each of the two first insulating layers 31a and 31b disposed at the outer side (e.g., the thickness of each of the two outermost first insulating layers 31a and 31b among the plurality of first insulating layers 31 in the Z-axis direction) can be greater than or equal to the thickness of the first insulating layer 31c disposed at the inner side (e.g., the thickness of at least one inner first insulating layer 31c among the plurality of first insulating layers 31 in the Z-axis direction). For example, the thickness of each of the two first insulating layers 31a and 31b disposed at the outer side can be about 1.5 times or more the thickness of the first insulating layer 31c disposed at the inner side. For example, the thickness of each of the two first insulating layers 31a and 31b disposed at the outer side can be about 1.5 times to about 100 times the thickness of the first insulating layer 31c disposed at the inner side, about 1.5 times to about 50 times the thickness of the first insulating layer 31c disposed at the inner side, about 1.5 times to about 10 times the thickness of the first insulating layer 31c disposed at the inner side, or about 1.5 times to about 5 times the thickness of the first insulating layer 31c disposed at the inner side.

[0066] In the gate insulating layer 30, the content of the plurality of first insulating layers 31 can dominate. For example, the content of the plurality of first insulating layers 31 in the gate insulating layer 30 can be about 80 at% or more or about 85 at% or more compared to the total amount of atoms of the gate insulating layer 30. For example, the content of the plurality of first insulating layers 31 in the gate insulating layer 30 can be about 85 at% to about 99 at%, about 85 at% to about 95 at%, about 85 at% to about 90 at%, 80 at% to about 99 at%, about 80 at% to about 95 at%, or about 80 at% to about 90 at% compared to the total amount of atoms of the gate insulating layer 30. Thus, the threshold voltage of the semiconductor device 1 can be determined mainly by the plurality of first insulating layers 31. The plurality of first insulating layers 31 can include a material having a band gap of about 4 eV to about 7 eV. In some example embodiments, the plurality of first insulating layers 31 can include a material having a dielectric constant of about 10 to about 40. For example, the plurality of first insulating layers 31 can include an oxide including at least one of aluminum (Al), calcium (Ca), yttrium (Y), zirconium (Zr), lanthanum (La), and hafnium (Hf), for example, at least one of an aluminum oxide, a calcium oxide, a yttrium oxide, a zirconium oxide, a lanthanum oxide, and a hafnium oxide.

[0067] In a semiconductor device including an insulating layer including a layer of a material, excess oxygen can be easily generated in the insulating layer in a subsequent process or a heat treatment process. The generated excess oxygen can move to the oxide semiconductor layer to inhibit generation of oxygen vacancies in the oxide semiconductor layer. The gate insulating layer 30 according to some example embodiments can restrict movement of the excess oxygen generated in the gate insulating layer 30 by including a plurality of layers having different energy bandgaps (e.g., the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33) in the gate insulating layer 30, thereby improving generation of oxygen vacancies in the oxide semiconductor layer 10 and, thus, improving the function and reliability of the semiconductor device 1.

[0068] The gate insulating layer 30 according to some example embodiments can further include a second insulating layer 32 arranged between (e.g., directly between or indirectly between) adjacent first insulating layers 31b and 31c (e.g., a first set of adjacent first insulating layers) among the plurality of first insulating layers 31 and having a smaller energy bandgap than the plurality of first insulating layers 31. Opposite sides (e.g., opposite sides of the second insulating layer 32 in the Z-axis direction) of the second insulating layer 32 from each other can respectively contact the first insulating layers 31b and 31c.

[0069] The content of the second insulating layer 32 in the gate insulating layer 30 can be low. For example, the content of the second insulating layer 32 in the gate insulating layer 30 can be about 10 at% or less. For example, the content of the second insulating layer 32 in the gate insulating layer 30 can be about 0.01 at% to about 10 at%, about 0.1 at% to about 10 at%, about 1 at% to about 10 at%, 1 at% to about 8 at%, about 1 at% to about 5 at%, or about 1 at% to about 2 at% compared to the total amount of atoms of the gate insulating layer 30. The thickness (e.g., the thickness in the Z-axis direction) of the second insulating layer 32 can be less than the respective thickness of each of the plurality of first insulating layers 31. For example, the thickness (e.g., the thickness in the Z-axis direction) of the second insulating layer 32 can be about 3 A or less, for example, about 2 A or less. For example, the thickness (e.g., the thickness in the Z-axis direction) of the second insulating layer 32 can be about 0.01 A to about 2 A, about 0.1 A to about 2 A, about 1 A to about 2 A, about 1 A to about 1.5 A, or about 1 A to about 1.1 A. In some example embodiments, the second insulating layer 32 can be a monolayer. Thus, the threshold voltage of the semiconductor device 1 can be less affected by the second insulating layer 32.

[0070] The difference between the band gap of the first insulating layer 31 and the band gap of the second insulating layer 32 can be about 2 eV or more, such as about 2 eV to about 200 eV, about 2 eV to about 100 eV, about 2 eV to about 50 eV, about 2 eV to about 20 eV, about 2 eV to about 10 eV, or about 2 eV to about 5 eV. For example, the second insulating layer 32 can include a material having a band gap of about 4 eV or less (e.g., about 0.01 eV to about 4 eV, about 0.1 eV to about 4 eV, about 1 eV to about 4 eV, about 1 eV to about 3 eV, about 1 eV to about 2 eV, or about 1 eV to about 1.5 eV). In some example embodiments, the second insulating layer 32 can include a material having a dielectric constant of about 20 or more (e.g., about 20 to about 200, about 20 to about 100, about 20 to about 50, about 20 to about 40, or about 20 to about 30). For example, the second insulating layer 32 can include an oxide including at least one of hafnium (Hf), tantalum (Ta), barium (Ba), and titanium (Ti) (e.g., at least one of hafnium oxide, tantalum oxide, barium oxide, and titanium oxide).

[0071] The gate insulating layer 30, which can be configured to improve the function and / or reliability of the semiconductor device 1, can include a plurality of layers having different band gaps. For example, the second insulating layer 32 having a small band gap can easily generate dielectric polarization by an applied electric field, thus increasing the on-current of the oxide semiconductor layer 10, and thereby improving the function and / or reliability of the semiconductor device 1. Further, the second insulating layer 32 having a small band gap can have a small oxygen scavenging effect, thus attracting oxygen from adjacent layers to restrain oxygen from moving to the oxide semiconductor layer 10, and thereby improving the function and / or reliability of the semiconductor device 1.

[0072] However, when the second insulating layer 32 having a small band gap is disposed adjacent to (e.g., directly adjacent to, in contact with, etc.) the oxide semiconductor layer 10, the reliability of the semiconductor device 1 can be degraded due to charge trapping and / or de-trapping. Thus, the second insulating layer 32 according to some example embodiments can be disposed between (e.g., directly or indirectly between) adjacent first insulating layers 31b and 31c so as not to contact the oxide semiconductor layer 10, thereby improving the function and / or reliability of the semiconductor device 1.

[0073] Further, the gate insulating layer 30 according to some example embodiments can also include a third insulating layer 33 having a larger band gap than the first insulating layer 31, thereby preventing charge trapping and / or de-trapping, or reducing or minimizing such trapping and / or de-trapping, and thereby improving functionality and / or reliability of the semiconductor device 1. The third insulating layer 33 can be arranged closer to the oxide semiconductor layer 10 than the second insulating layer 32 (e.g., closer to the oxide semiconductor layer 10 in the Z-axis direction), thereby preventing charge trapping and / or de-trapping through the second insulating layer 32, or reducing or minimizing such trapping and / or de-trapping, and thereby improving functionality and / or reliability of the semiconductor device 1. The third insulating layer 33 can be arranged between (e.g., directly arranged between) the first insulating layers 31a and 31c (e.g., a second group of adjacent first insulating layers among the plurality of first insulating layers 31). Two surfaces of the third insulating layer 33 opposite to each other (e.g., opposite surfaces of the third insulating layer 33 in the Z-axis direction) can respectively contact the first insulating layers 31a and 31c. That is, the first insulating layer 31c can be arranged between the second insulating layer 32 and the third insulating layer 33.

[0074] The third insulating layer 33 in the gate insulating layer 30 can have a low content. For example, the third insulating layer 33 in the gate insulating layer 30 can have a content of about 10 at% or less. For example, the third insulating layer 33 in the gate insulating layer 30 can have a content of about 0.01 at% to about 10 at%, about 0.1 at% to about 10 at%, about 1 at% to about 10 at%, 1 at% to about 8 at%, about 1 at% to about 5 at%, or about 1 at% to about 2 at%, as compared to the total amount of atoms of the gate insulating layer 30. The thickness of the third insulating layer 33 (e.g., its thickness in the Z-axis direction) can be less than the thickness of the first insulating layer 31. In some example embodiments, the thickness of the third insulating layer 33 can be 0.5 times to 1.5 times the thickness of the second insulating layer 32. For example, the thickness of the third insulating layer 33 can be about 3 A or less, e.g., about 2 A or less. For example, the thickness of the third insulating layer 33 (e.g., its thickness in the Z-axis direction) can be about 0.01 A to about 2 A, about 0.1 A to about 2 A, about 1 A to about 2 A, about 1 A to about 1.5 A, or about 1 A to about 1.1 A. In some example embodiments, the third insulating layer 33 can be a monolayer. Thus, the threshold voltage of the semiconductor device 1 can be less affected by the third insulating layer 33, thereby improving functionality and / or reliability of the semiconductor device 1.

[0075] The difference between the band gap of the first insulating layer 31 and the band gap of the third insulating layer 33 can be about 2 eV or more, for example, about 2 eV to about 200 eV, about 2 eV to about 100 eV, about 2 eV to about 50 eV, about 2 eV to about 20 eV, about 2 eV to about 10 eV, or about 2 eV to about 5 eV. For example, the third insulating layer 33 can include a material having a band gap of about 7 eV or more (for example, about 7 eV to about 700 eV, about 7 eV to about 500 eV, about 7 eV to about 200 eV, about 7 eV to about 100 eV, about 7 eV to about 70 eV, about 7 eV to about 50 eV, about 7 eV to about 20 eV, or about 7 eV to about 10 eV). In another example, the third insulating layer 33 can include a material having a dielectric constant of about 20 or less (for example, about 0.01 to about 20, about 0.1 to about 20, about 1 to about 20, about 1 to about 10, or about 1 to about 5). For example, the third insulating layer 33 can include an oxide including at least one of silicon (Si) and magnesium (Mg) (for example, at least one of a silicon oxide and a magnesium oxide). Also, the band gap difference between the second insulating layer 32 and the third insulating layer 33 can be 5 eV or more.

[0076] In Figure 1 , the gate insulating layer 30 is shown to include three first insulating layers 31, one second insulating layer 32, and one third insulating layer 33; however, the inventive concept is not limited thereto. The gate insulating layer 30 can include a plurality of second insulating layers and a plurality of third insulating layers.

[0077] Figure 2 is a diagram showing a semiconductor device 2 including a plurality of second insulating layers and a plurality of third insulating layers according to some example embodiments. Comparing Figure 1 and Figure 2 , Figure 2 The gate insulating layer 30 of the semiconductor device 2 of

[0078] The number (amount) of layers included in the gate insulating layer 30, which can be the total of layers of the plurality of first insulating layers 31, the one or more second insulating layers 32, and the one or more third insulating layers 33, can be 4n + 1 (where n is a natural number). For example, in the gate insulating layer 30, layers of the third insulating layer 33, the first insulating layer 31c, the second insulating layer 32, and the first insulating layer 31c, which are sequentially arranged in the thickness direction of the gate insulating layer 30, can be referred to as a group insulating layer 30s. The gate insulating layer 30 can include a plurality of group insulating layers 30s. For example, the gate insulating layer 30 can include the first insulating layer 31a, two or more group insulating layers 30s, the third insulating layer 33, the first insulating layer 31c, the second insulating layer 32, and the first insulating layer 31b. The thickness of each of the first insulating layers 31a and 31b among the plurality of first insulating layers 31, which are adjacent to the gate electrode 20 and the oxide semiconductor layer 10, respectively, can be greater than or equal to the thickness of the first insulating layer 31c arranged between the second insulating layer 32 and the third insulating layer 33.

[0079] The gate insulating layer 30 can include a plurality of group insulating layers 30s, thereby increasing the on-current of the oxide semiconductor layer 10 and further improving the reliability and / or the function of the semiconductor device 2.

[0080] Figure 3 is a graph showing results of measuring the performance of a semiconductor device including various types of insulating layers according to some example embodiments. Comparative Example 1 can be a semiconductor device including an insulating layer containing only aluminum oxide, and Comparative Example 2 can be a semiconductor device including an insulating layer including an aluminum oxide layer, a titanium oxide layer, and an aluminum oxide layer sequentially arranged therein. Further, Figure 3 The example embodiments indicated in Figure 1 and / or Figure 2 The example embodiments shown in and can include a semiconductor device including an insulating layer including ten layers stacked therein. The insulating layer can include an aluminum oxide layer (e.g., the first insulating layer 31a) and three group insulating layers 30s in the direction (e.g., the thickness direction) from the oxide semiconductor layer 10 to the gate electrode 20, and each group insulating layer 30s can be layers in which a silicon oxide layer (e.g., the third insulating layer 33), an aluminum oxide layer (e.g., the first insulating layer 31c), a titanium oxide layer (e.g., the second insulating layer 32), and an aluminum oxide layer (e.g., the first insulating layer 31c) are sequentially arranged in the direction (e.g., the thickness direction) from the oxide semiconductor layer 10 to the gate electrode 20. The semiconductor devices of Comparative Example 1, Comparative Example 2, and the example embodiments can be transistors.

[0081] Reference is made to Figure 3It can be seen that the on-state current of Comparative Example 2, which is a semiconductor device further including a titanium oxide layer having a small energy band gap, increases compared to the on-state current of Comparative Example 1, which is a semiconductor device including an insulating layer including only aluminum oxide. However, in Comparative Example 2, it can be seen that the performance of the semiconductor device deteriorates due to an increase in contact resistance between the gate electrode 20 (here, the gate electrode 20 can be a source gate electrode 20 or a drain gate electrode 20) and the oxide semiconductor layer.

[0082] It can be seen that the on-state current of the semiconductor device according to the example embodiment increases compared to the on-state current of Comparative Example 1, which includes a single layer. Furthermore, it can be seen that the contact resistance is still low. The increase in the on-state current can increase the contact resistance; however, it can be seen that by further arranging a silicon oxide layer having a high energy band gap, the on-state current can be increased while maintaining a low contact resistance.

[0083] Figure 4 is a graph showing results of measuring positive bias temperature instability (PBTI) of a semiconductor device according to some example embodiments. In the semiconductor device of Comparative Example 2, it can be seen that an abnormal change in threshold voltage occurs within about 10 seconds after a positive gate voltage is applied thereto, and in the semiconductor device of Comparative Example 1, it can be seen that the threshold voltage increases over time after a positive gate voltage is applied thereto. However, in the semiconductor device of the example embodiment (which can be a semiconductor device according to some example embodiments as described with reference to Figure 3 semiconductor device according to some example embodiments, including Figure 1 and / or Figure 2 example embodiments shown in FIG. 6B, it can be seen that the threshold voltage hardly changes even over time. This can mean that the semiconductor device according to the example embodiment (e.g., a semiconductor device according to some example embodiments) is reliable under a positive gate voltage, for example, based on including one or more gate insulating layers including a plurality of layers having different energy band gaps.

[0084] Figure 5 is a graph showing results of measuring negative bias temperature instability (NBTI) of a semiconductor device according to some example embodiments. In the semiconductor device of Comparative Example 1, it can be seen that the threshold voltage decreases over time after a negative gate voltage is applied thereto. However, in the semiconductor device of the example embodiment (which can be a semiconductor device according to some example embodiments as described with reference to Figure 3 semiconductor device according to some example embodiments, including Figure 1 and / or Figure 2As can be seen in the example embodiment shown, the threshold voltage remains within a certain range even as time passes after a negative gate voltage is applied thereto. This can mean that the semiconductor device according to example embodiments (e.g., a semiconductor device according to some example embodiments) is reliable at a negative gate voltage, for example, based on including one or more gate insulating layers including a plurality of layers having different energy bandgaps.

[0085] The semiconductor device described above can operate as a transistor. For example, the oxide semiconductor layer can have different oxygen concentrations depending on the region.

[0086] Figure 6 FIG. 1 is a diagram illustrating a semiconductor device 100 according to some example embodiments. Compare Figure 2 and Figure 6 , Figure 6 The oxide semiconductor layer 10 of the semiconductor device 100 can include a region overlapping with the gate electrode 20 in the thickness direction of the gate insulating layer 30 (e.g., the Z-axis direction) and a region not overlapping with the gate electrode 20 (e.g., exposed from the gate electrode 20) in the thickness direction of the gate insulating layer 30 (e.g., the Z-axis direction). For example, the oxide semiconductor layer 10 can include a channel region 10c overlapping with the gate electrode 20 in the thickness direction of the gate insulating layer 30, a source region 10s arranged at one end of the oxide semiconductor layer 10 and not overlapping with the gate electrode 20 in the thickness direction of the gate insulating layer 30, and a drain region 10d arranged at the other end of the oxide semiconductor layer 10 and not overlapping with the gate electrode 20 in the thickness direction of the gate insulating layer 30. That is, the channel region 10c can be located between the source region 10s and the drain region 10d. Figure 6 The gate electrode 20 and the gate insulating layer 30 shown can correspond to the gate electrode 20 and the gate insulating layer 30, respectively, of the semiconductor device according to any example embodiment (including Figure 1 or Figure 2 the example embodiment shown.

[0087] The oxygen content of the channel region 10c can be different from the oxygen content of the source region 10s and the drain region 10d. In the oxide semiconductor layer 10, carriers (e.g., free electrons) can be mainly generated by oxygen vacancies. Therefore, to reduce contact resistance, the source region 10s and the drain region 10d can have a relatively high carrier density, that is, a relatively high oxygen vacancy density. In some example embodiments, the channel region 10c can have a relatively low oxygen vacancy density, thereby increasing the threshold voltage and reducing the leakage current. In other words, the oxygen content in the channel region 10c can be higher than the oxygen content in the source region 10s and the drain region 10d. Figure 6 The gate electrode 20 of the semiconductor device 100 can correspond to the gate electrode 20 described above, and its gate insulating layer 30 can correspond to the gate insulating layer described above. Figure 6 The gate insulating layer 30 of the semiconductor device 100 can correspond to the gate insulating layer 30 described above.Figure 2 The gate insulating layer 30 shown in FIG. 1 can correspond to the gate insulating layer 30 shown in FIG. 2. The oxide semiconductor layer 10 shown in FIG. 1 can correspond to the oxide semiconductor layer 10 shown in FIG. 2. The gate electrode 20 shown in FIG. 1 can correspond to the gate electrode 20 shown in FIG. 2. The first electrode 40 and the second electrode 50 shown in FIG. 1 can correspond to the first electrode 40 and the second electrode 50 shown in FIG. 2. Figure 6 The gate insulating layer 30 shown in FIG. 1 can correspond to the gate insulating layer 30 shown in FIG. 2. The oxide semiconductor layer 10 shown in FIG. 1 can correspond to the oxide semiconductor layer 10 shown in FIG. 2. The gate electrode 20 shown in FIG. 1 can correspond to the gate electrode 20 shown in FIG. 2. The first electrode 40 and the second electrode 50 shown in FIG. 1 can correspond to the first electrode 40 and the second electrode 50 shown in FIG. 2. Figure 1 The gate insulating layer 30 shown in FIG. 1 can correspond to the gate insulating layer 30 shown in FIG. 2. The oxide semiconductor layer 10 shown in FIG. 1 can correspond to the oxide semiconductor layer 10 shown in FIG. 2. The gate electrode 20 shown in FIG. 1 can correspond to the gate electrode 20 shown in FIG. 2. The first electrode 40 and the second electrode 50 shown in FIG. 1 can correspond to the first electrode 40 and the second electrode 50 shown in FIG. 2. Figure 1 The gate electrode 20 shown in FIG. 1 can correspond to the gate electrode 20 shown in FIG. 2. The first electrode 40 and the second electrode 50 shown in FIG. 1 can correspond to the first electrode 40 and the second electrode 50 shown in FIG. 2. The oxide semiconductor layer 10 shown in FIG. 1 can correspond to the oxide semiconductor layer 10 shown in FIG. 2. The gate insulating layer 30 shown in FIG. 1 can correspond to the gate insulating layer 30 shown in FIG. 2. Thus, the description of the gate electrode 20 will be omitted for the sake of brevity.

[0088] Figure 7 is a diagram illustrating a semiconductor device 101 according to some example embodiments further including a plurality of gate electrodes 20. Comparing FIG. 3 to FIG. 1, the semiconductor device 101 of FIG. 3 can further include a plurality of gate electrodes 20. Figure 6 The semiconductor device 101 of FIG. 3 can further include a substrate S and a first electrode 40 and a second electrode 50 arranged apart from each other on the substrate S. Figure 7 , Figure 7 The semiconductor device 101 of FIG. 3 can further include a substrate S and a first electrode 40 and a second electrode 50 arranged apart from each other on the substrate S. Figure 7 The gate electrode 20 and the gate insulating layer 30 shown in FIG. 3 can respectively correspond to the gate electrode 20 and the gate insulating layer 30 according to any example embodiment (including the example embodiments shown in FIG. 1 and FIG. 2). The oxide semiconductor layer 10 shown in FIG. 3 can correspond to the oxide semiconductor layer 10 shown in FIG. 1 and FIG. 2. Figure 1 The gate electrode 20 and the gate insulating layer 30 shown in FIG. 3 can respectively correspond to the gate electrode 20 and the gate insulating layer 30 according to any example embodiment (including the example embodiments shown in FIG. 1 and FIG. 2). The oxide semiconductor layer 10 shown in FIG. 3 can correspond to the oxide semiconductor layer 10 shown in FIG. 1 and FIG. 2. Figure 2 The gate electrode 20 and the gate insulating layer 30 shown in FIG. 3 can respectively correspond to the gate electrode 20 and the gate insulating layer 30 according to any example embodiment (including the example embodiments shown in FIG. 1 and FIG. 2). The oxide semiconductor layer 10 shown in FIG. 3 can correspond to the oxide semiconductor layer 10 shown in FIG. 1 and FIG. 2.

[0089] The substrate S can be an insulating substrate, or can be a semiconductor substrate on a surface of which an insulating layer is formed. In some example embodiments, the substrate S can be a semiconductor substrate. The semiconductor substrate can include, for example, Si, Ge, SiGe, or a group III-V semiconductor material. The substrate S can be, for example, a silicon substrate on a surface of which silicon oxide is formed; however, the inventive concept is not limited thereto.

[0090] The first electrode 40 and the second electrode 50 arranged on the substrate S can contact the oxide semiconductor layer 10. One of the first electrode 40 and the second electrode 50 can be a source electrode, and the other can be a drain electrode.

[0091] The first electrode 40 and the second electrode 50 can include a metallic material. The first electrode 40 and the second electrode 50 can include at least one selected from tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), titanium (Ti), molybdenum (Mo), chromium (Cr), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), silver (Ag), gold (Au), aluminum (Al), copper (Cu), tin (Sb), vanadium (V), ruthenium (Ru), platinum (Pt), zinc (Zn), and magnesium (Mg).

[0092] Figure 8 is a diagram illustrating a semiconductor device 102 according to some example embodiments. Referring to FIG. 4, the semiconductor device 102 of FIG. 4 can include a substrate S, a first electrode 40 and a second electrode 50 arranged apart from each other on the substrate S, and a gate insulating layer 30 on the substrate S. Figure 8The semiconductor device 102 can include a substrate S, a first electrode 40 arranged over the substrate S, an oxide semiconductor layer 10 arranged over the first electrode 40, and a second electrode 50 arranged over the oxide semiconductor layer 10. The materials of the oxide semiconductor layer 10, the gate electrode 20, the gate insulating layer 30, the first electrode 40, and the second electrode 50 have been described above, and thus, redundant description thereof will be omitted for simplicity.

[0093] The oxide semiconductor layer 10 can be arranged so that its length direction is a direction perpendicular to the substrate S (Z-axis direction). Here, the length direction can refer to a direction in which a component is longer when viewed in the drawings.

[0094] The first electrode 40 and the second electrode 50 can be arranged apart from each other in a direction perpendicular to the substrate S (Z-axis direction extending perpendicular to a surface Su of the substrate S facing at least the first electrode 40 and the second electrode 50). For example, the first electrode 40, the oxide semiconductor layer 10, and the second electrode 50 can be arranged in a column in a direction perpendicular to the substrate S or in a thickness direction of the first electrode 40 (Z-axis direction).

[0095] The gate electrode 20 can be arranged on one side of the oxide semiconductor layer 10. The gate electrode 20 can correspond to the above-described gate electrode 20. The gate insulating layer 30 can be arranged between the oxide semiconductor layer 10 and the gate electrode 20. The gate electrode 20 can be arranged so that its length direction (Z-axis direction) is perpendicular to the substrate S. The oxide semiconductor layer 10, the gate insulating layer 30, and the gate electrode 20 can be arranged in a row in a direction parallel to the substrate S (X-axis direction extending parallel to a surface Su of the substrate S facing at least the first electrode 40 and the second electrode 50).

[0096] The molded insulating layer 60 can be arranged over the substrate S to fill an empty space thereof. The first electrode 40 can be arranged apart from the substrate S by the molded insulating layer 60.

[0097] Figure 9 is a diagram illustrating a semiconductor device 103 according to some example embodiments. In Figure 9 , components denoted by the same reference numerals as those in Figure 8 will have the same or substantially the same configurations and effects as those described above with reference to Figure 8 , and thus, redundant description thereof will be omitted for simplicity.

[0098] Figure 9The semiconductor device 103 shown may include a first electrode 40, an oxide semiconductor layer 10, and a second electrode 50 arranged in a direction perpendicular to the substrate S (Z-axis direction). A gate insulating layer 30 may be arranged around the oxide semiconductor layer 10, and a gate electrode 20 may be arranged around the gate insulating layer 30. The gate electrode 20 may be arranged around the oxide semiconductor layer 10 to increase the area where the gate electrode 20 and the oxide semiconductor layer 10 face each other, and to improve the short-channel effect.

[0099] Figure 10 This is a diagram illustrating a semiconductor device 104 according to some example embodiments. Figure 10 In the middle, by and Figure 9 The same reference numerals in the figures may indicate parts that have the same reference numerals as those in the above references. Figure 9 The configurations and effects described are basically the same, so for the sake of brevity, their redundant descriptions will be omitted.

[0100] refer to Figure 10 The semiconductor device 104 may include a substrate S, a first electrode 40 disposed on the substrate S, and a second electrode 50 disposed separately from the first electrode 40. The first electrode 40 and the second electrode 50 may be disposed separately from each other in a direction perpendicular to the substrate S (a Z-axis direction perpendicular to the surface Su of the substrate S that extends at least toward the first electrode 40 and the second electrode 50).

[0101] The oxide semiconductor layer 10 may be disposed on the exterior between the first electrode 40 and the second electrode 50. The oxide semiconductor layer 10 may include a first portion 10j parallel to the substrate S (e.g., in the +X-axis direction), a second portion 10e bent and extending from the first portion 10j in a direction perpendicular to the substrate S (e.g., in the Z-axis direction), and a third portion 10f bent and extending from the second portion 10e in a direction opposite to the first portion 10j (e.g., in the -X-axis direction). The second portion 10e may be disposed on the side of the second electrode 50 and the first electrode 40, and the third portion 10f may be disposed in contact with the second electrode 50.

[0102] The gate electrode 20 may have a similar shape to the oxide semiconductor layer 10 and may be disposed separately from the oxide semiconductor layer 10. In other words, the gate electrode 20 may include a first portion 20d parallel to the substrate S (e.g., in the +X-axis direction), a second portion 20e bent and extending from the first portion 20d in a direction perpendicular to the substrate S (e.g., in the Z-axis direction), and a third portion 20f bent and extending from the second portion 20e in a direction opposite to the first portion 20d (e.g., in the -X-axis direction). A gate insulating layer 30 may be disposed between the oxide semiconductor layer 10 and the gate electrode 20.

[0103] Figure 11 is a diagram illustrating a semiconductor device 105 according to some example embodiments. In Figure 11 In the above-described drawings, components with the same reference numerals can have the same configuration and effects as those described above, and thus, redundant descriptions thereof will be omitted for the sake of brevity.

[0104] Figure 11 The semiconductor device 105 illustrated in FIG. 1A can include a first electrode 40 and an oxide semiconductor layer 10 arranged on the first electrode 40. The oxide semiconductor layer 10 can have a U-shaped cross-sectional shape. The oxide semiconductor layer 10 can include a bottom portion 10i in contact with the first electrode 40, a first vertically extending portion 10g extending from one end of the bottom portion 10i in a direction perpendicular to the first electrode 40 (a Z-axis direction extending perpendicularly to a surface 40s of the first electrode 40 facing the oxide semiconductor layer 10), and a second vertically extending portion 10h extending from the other end of the bottom portion 10i in the direction perpendicular to the first electrode 40 (the Z-axis direction).

[0105] The first gate electrode 20a can be arranged separately from the first vertically extending portion 10g, and the second gate electrode 20b can be arranged separately from the second vertically extending portion 10h. The first gate insulating layer 30a can be arranged between the first vertically extending portion 10g and the first gate electrode 20a, and the second gate insulating layer 30b can be arranged between the second vertically extending portion 10h and the second gate electrode 20b.

[0106] The first gate electrode 20a and / or the second gate electrode 20b can extend in the second horizontal direction (the Y-axis direction). The first gate electrode 20a and the second gate electrode 20b can be positioned separately from each other. The first gate electrode 20a and / or the second gate electrode 20b can constitute a word line. An electrical signal input to the first gate electrode 20a can not correspond to an electrical signal input to the second gate electrode 20b. The first gate electrode 20a can control a channel of the first vertically extending portion 10g, and the second gate electrode 20b can control a channel of the second vertically extending portion 10h.

[0107] The insulating spacer 71 can be arranged between the first gate electrode 20a and the second gate electrode 20b spaced apart from each other. The insulating spacer 71 can be conformally arranged on the side walls facing each other of the first gate electrode 20a and the second gate electrode 20b and / or the upper surface of the oxide semiconductor layer 10. The insulating spacer 71 can have an upper surface arranged on the same plane as the first gate electrode 20a and the second gate electrode 20b. The insulating spacer 71 can include, for example, silicon nitride. The buried insulating layer 72 can fill the space between the first gate electrode 20a and the second gate electrode 20b spaced apart from each other on the insulating spacer 71. The buried insulating layer 72 can include, for example, silicon oxide. The upper insulating layer 73 can be arranged on the upper surface of the first gate electrode 20a, the second gate electrode 20b, and / or the buried insulating layer 72. The upper surface of the upper insulating layer 73 can be arranged on the same level as the upper surface of the molded insulating layer 60.

[0108] The second electrode 50 can be arranged on the oxide semiconductor layer 10. The second electrode 50 can function as a landing pad. The second electrode 50 can include a first sub-electrode 51 and a second sub-electrode 52. The first sub-electrode 51 can be electrically connected to the first vertically extending portion 10g. The second sub-electrode 52 can be electrically connected to the second vertically extending portion 10h. The first sub-electrode 51 and the second sub-electrode 52 can not be electrically connected to each other.

[0109] The second electrode 50 can include an upper portion and a lower portion. The upper portion of the second electrode 50 can be a portion of the second electrode 50 arranged at a level higher than the upper surface of the molded insulating layer 60. The lower portion of the second electrode 50 can be a portion of the second electrode 50 arranged in an electrode recess defined between the molded insulating layer 60 and the upper insulating layer 73.

[0110] In some example embodiments, the upper portion of the second electrode 50 can have a first width in the first horizontal direction (X-axis direction), and the lower portion of the second electrode 50 can have a second width smaller than the first width in the first horizontal direction (X-axis direction). The lower portion of the second electrode 50 can be arranged in the electrode recess, and the upper portion of the second electrode 50 can have a bottom surface arranged on the upper surface of the molded insulating layer 60 and the upper surface of the upper insulating layer 73 on the lower portion of the second electrode 50, and thus the second electrode 50 can have a T-shaped vertical cross-section.

[0111] The bottom surface of the lower portion of the second electrode 50 can contact the upper surfaces of the first vertical extension portion 10g and / or the second vertical extension portion 10h. The two side walls of the lower portion of the second electrode 50 can be aligned with the two side walls of the first vertical extension portion 10g and the second vertical extension portion 10h. The bottom surface of the lower portion of the second electrode 50 can be disposed at a level higher than the upper surfaces of the first gate electrode 20a and / or the second gate electrode 20b, and a portion of the side walls of the lower portion of the second electrode 50 can be covered by the first gate insulating layer 30a and / or the second gate insulating layer 30b.

[0112] The insulating layer 74 surrounding the periphery of the second electrode 50 can be disposed on the upper surfaces of the molding insulating layer 60 and the upper insulating layer 73. The semiconductor device 105 can have a vertical channel transistor (VCT) structure including a vertical channel region extending in a direction perpendicular to the first electrode 40 (Z-axis direction).

[0113] The semiconductor device according to some example embodiments can be a component of a memory device. Figure 12 is a perspective view showing a schematic structure of a vertical stack memory device 200 according to some example embodiments. Referring to Figure 12 , the vertical stack memory device 200 can include a plurality of bit lines BL extending in a first direction (i.e., Z direction), a plurality of oxide semiconductor layers 10 respectively connected to the plurality of bit lines BL and extending in a second direction (i.e., X direction) intersecting the first direction perpendicularly, a plurality of capacitors Cap respectively electrically connected to the plurality of oxide semiconductor layers 10, and a plurality of word lines WL extending in a third direction (i.e., Y direction) intersecting the plurality of oxide semiconductor layers 10 perpendicularly. In Figure 12 , each of the plurality of word lines WL is shown as intersecting a corresponding oxide semiconductor layer 10 among the plurality of oxide semiconductor layers 10; however, the inventive concept is not limited thereto and each of the plurality of word lines WL can intersect under the corresponding oxide semiconductor layer 10.

[0114] Further, the vertical stack memory device 200 can further include a growth substrate S and a drive circuit substrate CS disposed on the growth substrate S. The drive circuit substrate CS can include a circuit connected to an external circuit to perform an input / output operation of receiving data from the outside or outputting data to the outside and an operation of writing data into the capacitor Cap or reading data written in the capacitor Cap.

[0115] The plurality of bit lines BL can be disposed on the drive circuit substrate CS so as to be perpendicular to an upper surface of the drive circuit substrate CS. For convenience, Figure 12Only three bit lines BL arranged in a row at intervals in the third direction are shown; however, in practice, a larger number of bit lines BL can be arranged two-dimensionally. For example, a plurality of bit lines BL extending in the vertical direction (i.e., the first direction) can be arranged two-dimensionally at intervals in the second direction and the third direction on the drive circuit substrate CS. The plurality of bit lines BL can be arranged in parallel with each other.

[0116] The plurality of oxide semiconductor layers 10 connected to respective bit lines BL among the plurality of bit lines BL can be arranged at intervals in the first direction. In Figure 12 In the embodiment, for convenience, only two oxide semiconductor layers 10 are shown for one bit line BL; however, a larger number of oxide semiconductor layers 10 can be arranged at intervals in the first direction. Further, in the same layer, the plurality of oxide semiconductor layers 10 can be arranged in parallel with each other at intervals in the third direction. The plurality of oxide semiconductor layers 10 arranged on the same layer can be connected to different respective bit lines among the plurality of bit lines BL, respectively. Like the plurality of bit lines BL, the plurality of oxide semiconductor layers 10 can also be arranged two-dimensionally at intervals in the second direction and the third direction. Each of the plurality of oxide semiconductor layers 10 can extend in the second direction. A first end portion of each of the plurality of oxide semiconductor layers 10 can be electrically connected to a respective bit line among the plurality of bit lines BL. A second end portion of each of the plurality of oxide semiconductor layers 10 opposite to the first end portion in the second direction can be electrically connected to a capacitor Cap.

[0117] In Figure 12 In the embodiment, for convenience, the capacitor Cap is shown as a monolith; however, in practice, the capacitor Cap can include a first electrode, a second electrode, and a dielectric layer arranged between the first electrode and the second electrode. The first electrode of the capacitor Cap can be electrically connected to the second end portion of a respective oxide semiconductor layer 10 among the plurality of oxide semiconductor layers 10. Thus, one oxide semiconductor layer 10 and one capacitor Cap can be connected to each other one-to-one. Although not shown, the second electrode of the capacitor Cap can be connected to a ground line of the vertically-stacked memory device 200.

[0118] The word line WL can extend in the third direction to intersect a plurality of respective oxide semiconductor layers 10. Further, a plurality of word lines WL can be arranged at intervals in the first direction. For convenience, Figure 12 Only one word line WL arranged on one layer is shown; however, a plurality of word lines WL can be arranged in parallel with each other on one layer at intervals in the second direction.

[0119] The gate insulating layer 30 can be arranged between the oxide semiconductor layer 10 and the word line WL. Although not shown for convenience, Figure 12The insulating material filling the spaces between the plurality of bit lines BL, between the plurality of oxide semiconductor layers 10, and between the plurality of word lines WL is not illustrated, but the vertically-stacked memory device 200 can further include the insulating material filling the spaces.

[0120] One oxide semiconductor layer 10 can form one oxide semiconductor transistor together with one word line WL corresponding thereto. The word line WL can function as a gate electrode 20 of the oxide semiconductor transistor. When a gate signal higher than a threshold voltage is applied to the word line WL, current can flow along the channel region 10c. Then, the bit line BL and the capacitor Cap corresponding to each other can be electrically connected to each other, and thus data can be written into the capacitor Cap or data written into the capacitor Cap can be read.

[0121] Accordingly, one oxide semiconductor layer 10 and one capacitor Cap corresponding thereto can form one memory cell. The vertically-stacked memory device 200 according to some example embodiments can include a plurality of memory cells arranged two-dimensionally on one layer. Further, the vertically-stacked memory device 200 can have a structure in which a plurality of layers in which a plurality of memory cells arranged two-dimensionally are stacked are included. Accordingly, since the degree of integration of the memory cells is high, the recording capacity of the vertically-stacked memory device 200 can be improved.

[0122] Figure 13 is a perspective view illustrating a schematic structure of a vertically-stacked memory device 201 according to some example embodiments. Reference is made to Figure 12 and Figure 13 , Figure 13 The vertically-stacked memory device 201 of Figure 12 Each of the plurality of word lines WL illustrated in

[0123] One oxide semiconductor layer 10 can form an oxide semiconductor transistor together with a first word line WL1 and a second word line WL2 corresponding thereto. The operation of one oxide semiconductor transistor can be controlled by the first word line WL1 disposed on the oxide semiconductor layer 10 and the second word line WL2 disposed below the oxide semiconductor layer 10. Thus, the driving reliability of the oxide semiconductor transistor can be improved. Figure 13 The other components of the vertical stack memory device 201 shown can be the same as those of the vertical stack memory device 200 shown in FIG. 1, and thus, a redundant description thereof will be omitted for the sake of brevity. Figure 12 The components of the vertical stack memory device 200 shown are the same as those of the vertical stack memory device 100 shown in FIG. 1, and thus, a redundant description thereof will be omitted for the sake of brevity.

[0124] Figure 14 FIG. 3 is a block diagram illustrating an electronic system 300 according to some example embodiments.

[0125] The electronic system 300 can include a memory 310 and a memory controller 320. The memory controller 320 can control the memory 310 to read data from and / or write data into the memory 310 in response to a request from a host 330. At least one of the memory 310 and the memory controller 320 can include a semiconductor device according to some example embodiments described above.

[0126] Figure 15 FIG. 4 is a block diagram of an electronic system 400 according to some example embodiments.

[0127] The electronic system 400 can be configured as a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. The electronic system 400 can include a controller 410, an input / output (I / O) device 420, a memory 430, and a wireless interface 440, which can be connected to each other through a bus 450.

[0128] The controller 410 can include at least one of a microprocessor, a digital signal processor, and any similar processor. The I / O device 420 can include at least one of a keypad, a keyboard, and a display. The memory 430 can be used to store commands executed by the controller 410. For example, the memory 430 can be used to store user data. The electronic system 400 can transmit / receive data through a wireless communication network using the wireless interface 440. The wireless interface 440 can include an antenna and / or a wireless transceiver. The electronic system 400 can include a semiconductor device according to some example embodiments described above.

[0129] A semiconductor device according to some example embodiments can include a gate insulating layer including a plurality of insulating layers having different energy bandgaps stacked therein, thus increasing an on-current value thereof and also improving reliability and / or functionality thereof.

[0130] A semiconductor device according to some example embodiments can include a gate insulating layer including a plurality of layers having different energy bandgaps stacked therein, thereby increasing an on-current value of the semiconductor device, and thereby improving a function and / or reliability of the semiconductor device.

[0131] A semiconductor device according to some example embodiments can include a gate insulating layer including a plurality of layers having different energy bandgaps stacked therein, thereby maintaining a reliability of the semiconductor device even when an operation time of the semiconductor device becomes longer.

[0132] A semiconductor device according to some example embodiments can be used for a high integration memory device, a logic device, etc. by including an insulating layer including a plurality of layers having different energy bandgaps stacked therein.

[0133] As described herein, any device, system, module, portion, unit, controller, circuit, and / or part thereof, and / or any part thereof (including, but not limited to, electronic system 300, memory 310, memory controller 320, host 330, electronic system 400, controller 410, input / output (I / O) device 420, memory 430, wireless interface 440, any part thereof, etc.) according to any example embodiment, and / or any part thereof, can include, can be included in, and / or can be implemented by one or more instances of processing circuitry (such as hardware including a logic circuit; a hardware / software combination, such as a processor executing software; or a combination thereof). For example, the processing circuitry can include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), and a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), a neural-network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry can include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing a program of instructions and a processor (e.g., a CPU) configured to execute the program of instructions to implement functions and / or methods performed by some or all of any device, system, module, portion, unit, controller, circuit, and / or part thereof according to any example embodiment.

[0134] It should be understood that the example implementations described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each example implementation should typically be considered as being applicable to other similar features or aspects in other similar example implementations. While some example implementations have been described with reference to the accompanying drawings, it is to be understood that the various changes in form and detail can be made thereto without departing from the spirit and scope as defined by the following claims.

[0135] This application is based on and claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2024-0059885, filed on May 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

Claims

1. A semiconductor device comprising: an oxide semiconductor layer; a gate electrode arranged apart from the oxide semiconductor layer; and a gate insulating layer arranged between the oxide semiconductor layer and the gate electrode, wherein the gate insulating layer includes a plurality of first insulating layers arranged apart from each other in a thickness direction of the gate insulating layer, a second insulating layer arranged between a first group of adjacent first insulating layers among the plurality of first insulating layers, the second insulating layer having a smaller energy band gap than each of the plurality of first insulating layers, and a third insulating layer arranged between a second group of adjacent first insulating layers among the plurality of first insulating layers, the third insulating layer having a larger energy band gap than each of the plurality of first insulating layers, and wherein the third insulating layer is closer to the oxide semiconductor layer than the second insulating layer.

2. The semiconductor device according to claim 1, wherein a content of the second insulating layer in the gate insulating layer is 10 at% or less.

3. The semiconductor device according to claim 1, wherein a content of the third insulating layer in the gate insulating layer is 10 at% or less.

4. The semiconductor device according to claim 1, wherein the plurality of first insulating layers include two outermost first insulating layers among the plurality of first insulating layers in the thickness direction of the gate insulating layer and at least one inner first insulating layer between the two outermost first insulating layers, and a thickness in the thickness direction of the gate insulating layer of each of the two outermost first insulating layers among the plurality of first insulating layers is greater than or equal to a thickness in the thickness direction of the gate insulating layer of the at least one inner first insulating layer among the plurality of first insulating layers.

5. The semiconductor device according to claim 4, wherein one of the two outermost first insulating layers contacts the oxide semiconductor layer.

6. The semiconductor device according to claim 4, wherein one of the two outermost first insulating layers contacts the gate electrode.

7. The semiconductor device according to claim 1, wherein a first insulating layer among the plurality of first insulating layers is arranged between the second insulating layer and the third insulating layer.

8. The semiconductor device according to claim 1, wherein a thickness in the thickness direction of the gate insulating layer of each of the plurality of first insulating layers is greater than a thickness in the thickness direction of the gate insulating layer of each of the second insulating layer and the third insulating layer.

9. The semiconductor device according to claim 1, wherein a thickness in the thickness direction of the gate insulating layer of at least one of the second insulating layer and the third insulating layer is 3 A or less.

10. The semiconductor device according to claim 1, wherein a thickness in the thickness direction of the gate insulating layer of each of the plurality of first insulating layers is 5 A or more. ​ 11. The semiconductor device according to claim 1, wherein a thickness of the gate insulating layer in the thickness direction of the gate insulating layer is 3 nm to 10 nm.

12. The semiconductor device according to claim 1, wherein a sum of the number of the plurality of first insulating layers, the second insulating layer, and the third insulating layer is 4n+1, where n is a natural number.

13. The semiconductor device according to claim 1, wherein the second insulating layer includes a plurality of second insulating layers, the third insulating layer includes a plurality of third insulating layers, and the plurality of second insulating layers and the plurality of third insulating layers are alternately arranged one after another in the thickness direction of the gate insulating layer.

14. The semiconductor device according to claim 1, wherein a first insulating layer of the plurality of first insulating layers is arranged between the second insulating layer and the third insulating layer.

15. The semiconductor device according to claim 1, wherein a band gap difference between the second insulating layer and the third insulating layer is 5 eV or more.

16. The semiconductor device according to claim 1, wherein the third insulating layer includes an oxide including at least one of silicon (Si) and magnesium (Mg).

17. The semiconductor device according to claim 1, wherein the second insulating layer includes at least one of titanium (Ti) and hafnium (Hf).

18. The semiconductor device according to claim 1, wherein a band gap difference between a first insulating layer of the plurality of first insulating layers and at least one of the second insulating layer and the third insulating layer is 2 eV or more.

19. The semiconductor device according to claim 1, wherein the plurality of first insulating layers each independently include an oxide including at least one of aluminum (Al), calcium (Ca), yttrium (Y), zirconium (Zr), and hafnium (Hf).

20. The semiconductor device according to claim 1, further comprising: a bit line electrically connected to one end of the oxide semiconductor layer; and a capacitor electrically connected to the other end of the oxide semiconductor layer, wherein the gate electrode is an element of a word line. ​

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