Semiconductor structure and preparation method thereof
By using a silicon nitride layer and two chemical mechanical polishing processes in the semiconductor structure, the problem of poor surface flatness after metal gate CMP is solved, improving the yield and reliability of the device, especially in processes below 28nm.
Patent Information
- Application Number
- CN202511045157.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-28
- Publication Date
- 2025-11-07
AI Technical Summary
In existing RPG processes with feature sizes below 28nm, the poor surface smoothness after metal gate CMP process leads to a decrease in device yield and reliability, mainly due to the depression between ILD0 and the spacer layer and the non-uniformity of material removal rate.
By setting a silicon nitride layer as an etching protection layer in the semiconductor structure, controlling the removal rate, and employing a two-stage chemical mechanical polishing process, the filling and polishing process of the metal gate is optimized, reducing the depression morphology and improving the surface flatness.
It increases the process window of chemical mechanical polishing, improves the surface flatness and stability of metal gates, and enhances the yield and reliability of devices, especially in small-sized devices.
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Figure CN120916474A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a semiconductor structure and a preparation method thereof. BACKGROUND
[0002] Dual gate oxide can integrate thin gate oxide devices (core region) and thick gate oxide devices (IO region) on the same chip, so as to further improve the gate field control ability, and is compatible with the existing standard CMOS process, and is therefore widely used in high-voltage CMOS. With the continuous reduction of the CMOS process feature size to below 28 nm, high-k gate dielectric layer and metal gate electrode capable of realizing smaller gate leakage current and gate resistance are needed to improve the device speed, and these functions are generally realized through the Replacement Poly-Gate (RPG) process.
[0003] In the existing RPG process with a feature size below 28 nm, gate oxide removal is needed on the surface of the core region. In order to ensure that the gate oxide in the edge corner is also removed cleanly, a large amount of overetch (OE) is needed, which will cause the loss of spacer and ILD0 oxide height. The difference in height loss of the spacer and ILD0 will form a dishing between ILD0 and the spacer, thereby reducing the process window of the CMP after the deposition of the work function metal layer and the metal gate, and the material removal rate is different between the regions with different pattern densities in the IO region and the core region, resulting in uneven material removal rate on the entire wafer surface. This unevenness will affect the stability of the CMP process and the final surface flatness, the uniformity of the metal gate height, and the defect distribution, thereby affecting the overall yield and reliability of the device.
[0004] Therefore, there is an urgent need for a structure or method capable of improving the surface flatness after the metal gate CMP process.
[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application, and for the convenience of understanding by those skilled in the art, and the above technical scheme cannot be considered as known to those skilled in the art only because it is described in the background section of the present application. SUMMARY
[0006] In view of the above shortcomings of the prior art, the present application aims to provide a semiconductor structure and a preparation method thereof, which can solve the problem of poor surface flatness after the metal gate CMP of the dual gate oxide process using the back gate process of the prior art.
[0007] To achieve the above object, the present application provides a preparation method of a semiconductor structure, which comprises:
[0008] A structure to be processed is provided, which comprises a substrate, a stress material region, a gate oxide layer, a spacer layer, a dummy gate and a primary interlayer dielectric layer; the stress material region is arranged at intervals near the upper surface of the substrate, and is exposed on the upper surface of the substrate; the gate oxide layer covers the upper surface of the substrate which is not provided with the stress material region, and the dummy gate is arranged at intervals in the region of the gate oxide layer corresponding to the space between the stress material regions; the spacer layer covers the exposed surface of the gate oxide layer and the sidewall of the dummy gate; the primary interlayer dielectric layer is filled between the dummy gates which are arranged at intervals and covered by the spacer layer; and the primary interlayer dielectric layer is flush with the upper surface of the structure to be processed which is exposed by the spacer layer covering the sidewall of the dummy gate and the primary interlayer dielectric layer;
[0009] A silicon nitride layer with a preset thickness is arranged on the upper surface of the structure to be processed;
[0010] The silicon nitride layer is patterned to expose the upper surface of the dummy gate;
[0011] The patterned silicon nitride layer is used as a mask to continue etching downward to remove the dummy gate, thereby obtaining recesses arranged at intervals;
[0012] An oxide layer with a preset thickness is arranged on the surface exposed by the silicon nitride layer and the recesses;
[0013] The oxide layer corresponding to the preset core region and the gate oxide layer exposed thereby are removed;
[0014] A work function metal layer is arranged on the exposed surface;
[0015] A metal gate is arranged on the surface of the work function metal layer, the metal gate is filled in the recesses and covers the surface exposed by the work function metal layer; the removal rate of the metal gate is greater than the removal rate of the silicon nitride layer and less than the removal rate of the primary interlayer dielectric layer;
[0016] A first chemical mechanical polishing process is performed on the upper surface of the obtained structure until the silicon nitride layer is completely removed;
[0017] A second chemical mechanical polishing process is performed again until the upper surface of the obtained structure is flush.
[0018] Optionally, after the silicon nitride layer is patterned, when the sidewall of the patterned silicon nitride layer is located on the dummy gate, a back etching process is performed on the sidewall of the patterned silicon nitride layer, so that the sidewall of the silicon nitride layer is located on the spacer layer of the sidewall of the dummy gate.
[0019] Optionally, if the width of the dummy gate is less than or equal to 28 nm, the sidewall of the patterned silicon nitride layer is located on the spacer layer of the sidewall of the dummy gate when the silicon nitride layer is patterned.
[0020] Optionally, if the width of the dummy gate is greater than 28 nm, the sidewall of the patterned silicon nitride layer is located on the spacer layer of the sidewall of the dummy gate or the width of the overlap between the sidewall of the patterned silicon nitride layer and the projection of the dummy gate on the upper surface of the substrate is less than 10% of the width of the dummy gate when the silicon nitride layer is patterned.
[0021] Optionally, the thickness of the silicon nitride layer is less than or equal to 100 angstroms.
[0022] Optionally, the thickness of the oxide layer is 30 angstroms-100 angstroms and the thickness of the gate oxide layer is 20 angstroms-50 angstroms.
[0023] Optionally, the thickness of the work function metal layer is 50 angstroms-200 angstroms; after the metal gate is set, the height of the upper surface of the metal gate beyond the upper surface of the work function metal layer not located in the first groove is 800 angstroms-1000 angstroms.
[0024] Optionally, the material of the metal gate is copper, aluminum or tungsten.
[0025] Optionally, the first chemical mechanical polishing process adopts an alumina abrasive liquid and the second chemical mechanical polishing process adopts a silicon oxide abrasive liquid.
[0026] The application further provides a semiconductor structure obtained by any one of the above preparation methods, which comprises a substrate, a stress material region, a gate oxide layer, a spacer layer, an oxide layer, a work function metal layer, a metal gate and a primary interlayer dielectric layer.
[0027] The stress material region is arranged at intervals near the upper surface of the substrate and is exposed on the upper surface of the substrate; the gate oxide layer covers the upper surface of the substrate where the stress material region is not arranged; the gate structure is arranged at intervals in the region corresponding to the region between the stress material regions on the gate oxide layer, and the gate structure comprises a metal gate and a work function metal layer wrapping the sidewall and bottom surface of the metal gate.
[0028] The region corresponding to the region between the stress material regions on the gate oxide layer comprises an input / output region and a core region, and the sidewall and bottom surface of the gate structure in the input / output region are wrapped with an oxide layer with a preset thickness.
[0029] The grooves are formed between the gate structures, the sidewalls and bottom surfaces of the grooves are covered with a spacer layer, and the primary interlayer dielectric layer is filled on the surface of the spacer layer in the grooves.
[0030] As described above, the semiconductor structure and the preparation method thereof have the following beneficial effects:
[0031] The semiconductor structure and the preparation method thereof have the following beneficial effects:
[0032] The semiconductor structure and the preparation method thereof have the following beneficial effects:
[0033] The semiconductor structure and the preparation method thereof have the following beneficial effects:
[0034] The semiconductor structure and the preparation method thereof have the following beneficial effects: BRIEF DESCRIPTION OF DRAWINGS
[0035] Figure 1 A structure schematic diagram showing the dishing morphology after the gate oxide of the core region is removed in the prior art.
[0036] Figure 2 A structure schematic diagram showing the structure to be processed in step 1 of the preparation method of the semiconductor structure of the present application.
[0037] Figure 3 A structure schematic diagram showing the structure in which the silicon nitride layer is arranged in step 2 of the preparation method of the semiconductor structure of the present application.
[0038] Figure 4 A structure schematic diagram showing the structure in which the patterned mask layer is arranged in step 3 of the preparation method of the semiconductor structure of the present application.
[0039] Figure 5 A structure schematic diagram showing the structure in which the patterned silicon nitride layer is arranged in step 3 of the preparation method of the semiconductor structure of the present application.
[0040] Figure 6Figure 3 shows a structure schematic diagram of the step 3 of the method for preparing the semiconductor structure of the present application, which presents the structure after the patterning of the silicon nitride layer in an example.
[0041] Figure 7 Figure 4 shows a structure schematic diagram of the step 4 of the method for preparing the semiconductor structure of the present application, which presents the structure after the removal of the dummy gate.
[0042] Figure 8 Figure 5 shows a structure schematic diagram of the step 5 of the method for preparing the semiconductor structure of the present application, which presents the structure after the covering of the oxide layer.
[0043] Figure 9 Figure 6 shows a structure schematic diagram of the step 6 of the method for preparing the semiconductor structure of the present application, which presents the structure after the setting of the mask layer in an example.
[0044] Figure 10 Figure 7 shows a structure schematic diagram of the step 6 of the method for preparing the semiconductor structure of the present application, which presents the structure after the removal of the core region oxide layer and the gate oxide layer in an example.
[0045] Figure 11 Figure 8 shows a structure schematic diagram of the step 6 of the method for preparing the semiconductor structure of the present application, which presents the structure after the setting of the interface layer in an example.
[0046] Figure 12 Figure 9 shows a structure schematic diagram of the step 7 of the method for preparing the semiconductor structure of the present application, which presents the structure after the covering of the work function metal layer.
[0047] Figure 13 Figure 10 shows a structure schematic diagram of the step 8 of the method for preparing the semiconductor structure of the present application, which presents the structure after the setting of the metal gate.
[0048] Figure 14 Figure 11 shows a structure schematic diagram of the step 9 of the method for preparing the semiconductor structure of the present application, which presents the structure after the first chemical mechanical polishing process.
[0049] Figure 15 Figure 12 shows a structure schematic diagram of the step 10 of the method for preparing the semiconductor structure of the present application, which presents the structure after the second chemical mechanical polishing process.
[0050] BRIEF DESCRIPTION OF THE DRAWINGS
[0051] 10, substrate; 11, stress material region; 12, silicon nitride layer;
[0052] 21, gate oxide layer; 22, spacer layer; 23, recess; 24, oxide layer; 25, interface layer; 26, work function metal layer; 27, metal gate; 28, primary interlayer dielectric layer; 29, dummy gate.
[0053] 31, dishing topography; 32, mask layer; A, core region; B, input / output region; C, overlap. DETAILED DESCRIPTION
[0054] Other advantages and benefits of the present application will become apparent to those skilled in the art upon consideration of the disclosure, or can be learned by practice of the application. The advantages and benefits of the present application can be realized and attained by means of the instrumentalities particularly pointed out in the specification and claims of the present application.
[0055] In describing the embodiments of the present application, specific terminology is employed for the sake of clarity. The description is not intended to be limited to the details of the specific illustrated embodiments. Rather, the description is intended to be illustrative of the present application, with the scope being defined by the claims.
[0056] For the sake of convenience, the terms "lower," "bottom," "bottom portion," "upper," "top," and the like can be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. These spatially relative terms are intended to encompass different positions of the devices in use or operation in addition to the positions depicted in the figures.
[0057] In the context of this application, the description of a structure as being "on" another structure can include embodiments in which the first and second structures form direct contact, as well as embodiments in which additional structures are formed between the first and second structures, such that the first and second structures can not be in direct contact.
[0058] It should be noted that the drawings provided herein are merely schematic and are intended to conceptually illustrate the structures described herein. Thus, the actual number of components, shapes, and sizes of the components shown in the drawings can be varied in actual implementation, and the layout of the components can be more complex. The ranges of numbers given in the present application are intended to include both boundary values of the ranges unless otherwise specified.
[0059] Dual gate oxide using Replacement Poly-Gate (RPG) process generally grows oxide layer by In-Situ Steam Generation (ISSG) first, then nitridates the grown oxide layer by Decoupled Plasma Nitridation (DPN), and further optimizes the structure and performance of the nitridated layer by Post Nitridation Annealing (PNA) to get 30 angstrom thick gate oxide. Then, after forming dummy poly and initial interlayer dielectric layer (ILD0), the ILD0 is polished by Chemical Mechanical Polishing (CMP) to expose the dummy poly for Dummy Poly Removal (DPR). Then, 40 angstrom thick gate oxide is grown by Atomic Layer Deposition (ALD). Then, about 70 angstrom thick gate oxide is removed in the core region, and an interfacial layer (IL) is formed between the gate oxide and high-k material in the core region to redefine the gate oxide thickness in the core region. Then, high-k and Metal Gate (MG) are deposited to complete the front-end-of-line (FEOL) process of CMOS.
[0060] However, in CIS (Complementary Metal-Oxide-Semiconductor Image Sensor) devices, when gate oxide is removed in the core region, a large amount of overetch (OE) is needed to ensure that the gate oxide in the edge corner is also removed completely, which will result in the loss of spacer and ILD0 oxide height. At the same time, the spacer height loss is about 60 angstrom, and the ILD0 height loss is about 240 angstrom, which will form a dishing of about 180 angstrom depth between ILD0 and spacer, as shown in Figure 1 Figure 1 The schematic diagram of the dishing morphology obtained in the prior art reduces the process window of the CMP after the deposition of the work function metal layer and the metal gate. The main purpose of the CMP process is to remove the excess metal material by chemical mechanical polishing to achieve the required flatness and height uniformity of the metal gate. However, due to the dishing between the ILD0 and the spacer layer, and the different material removal rates between the different pattern density regions of the IO region and the core region, the material removal rate of the entire wafer surface is uneven. This unevenness affects the stability of the CMP process and the final surface flatness, GH U% (metal gate height uniformity), and defect distribution, thereby affecting the overall yield and reliability of the device.
[0061] To solve the above problems, the present application provides a preparation method of a semiconductor structure, which comprises the following steps:
[0062] Step 1: providing a to-be-processed structure, wherein the to-be-processed structure comprises a substrate, a stress material region, a gate oxide layer, a spacer layer, a dummy gate, and a primary interlayer dielectric layer; the stress material region is arranged at intervals near the upper surface of the substrate and is exposed on the upper surface of the substrate; the gate oxide layer covers the upper surface of the substrate which is not provided with the stress material region, and the dummy gate is arranged at intervals in the region corresponding to the stress material region on the gate oxide layer; the spacer layer covers the exposed surface of the gate oxide layer and the sidewall of the dummy gate; and the primary interlayer dielectric layer fills the space between the dummy gates which are arranged at intervals and covered by the spacer layer, and the upper surface of the to-be-processed structure covered by the spacer layer around the sidewall of the dummy gate is flush with the dummy gate;
[0063] Step 2: arranging a silicon nitride layer with a predetermined thickness on the upper surface of the to-be-processed structure;
[0064] Step 3: patterning the silicon nitride layer to expose the upper surface of the dummy gate;
[0065] Step 4: using the patterned silicon nitride layer as a mask to continue etching downward to remove the dummy gate, thereby obtaining spaced grooves;
[0066] Step 5: covering the exposed surface of the silicon nitride layer and the grooves with an oxide layer with a predetermined thickness;
[0067] Step 6: removing the oxide layer corresponding to the predetermined core region and the exposed gate oxide layer;
[0068] Step 7: covering the exposed surface with a work function metal layer;
[0069] Step 8: A metal gate is formed on the surface of the work function metal layer, the metal gate fills the groove and covers the exposed surface of the work function metal layer; the removal rate of the metal gate is greater than the removal rate of the silicon nitride layer and less than the removal rate of the primary interlayer dielectric layer;
[0070] Step 9: Perform a first chemical mechanical polishing process on the upper surface of the obtained structure until the silicon nitride layer is completely removed;
[0071] Step 10: Perform a second chemical mechanical polishing process until the upper surface of the resulting structure is flush.
[0072] The method for preparing the semiconductor structure of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the preparation method of the semiconductor structure protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.
[0073] First, proceed to step 1, as follows: Figure 2 As shown, a structure to be processed is provided, the structure to be processed including a substrate 10, stress material regions 11, a gate oxide layer 21, a spacer layer 22, dummy gates 29, and a primary interlayer dielectric layer 28; the stress material regions 11 are spaced apart near the upper surface of the substrate 10, the stress material regions 11 are exposed on the upper surface of the substrate 10; the gate oxide layer 21 covers the upper surface of the substrate 10 where the stress material regions 11 are not located, and the dummy gates 29 are spaced apart on the gate oxide layer 21 in the regions corresponding to the stress material regions 11; the spacer layer 22 covers the exposed surface of the gate oxide layer 21 and the sidewalls of the dummy gates 29, the primary interlayer dielectric layer 28 fills the spaces between the dummy gates 29 whose sidewalls are covered by the spacer layer 22 and spaced apart, the primary interlayer dielectric layer 28 is flush with the upper surface of the structure to be processed exposed by the dummy gates 29 and the spacer layer 22 that wraps the sidewalls of the dummy gates 29.
[0074] In one embodiment, the structure to be processed is used to fabricate a PMOS, and the stress material region 11 is a germanium-silicon region.
[0075] In one embodiment, the structure to be processed is used to fabricate an NMOS, and the stress material region 11 is a phosphorus silicon region.
[0076] Specifically, the stress material region 11 can also be selected from other suitable stress materials according to application requirements, all of which are within the protection scope of this invention.
[0077] Then, proceed to step 2, as follows: Figure 3 As shown, a silicon nitride layer 12 of a preset thickness is provided on the upper surface of the structure to be processed.
[0078] The present application sets a silicon nitride layer 12 as an etching protection layer on the upper surface of the structure to be processed, so as to reduce the dishing between the spacer layer 22 and the primary interlayer dielectric layer 28 due to different etching rates when the oxide layer 24 corresponding to the core area A is removed in the subsequent step 6, thereby increasing the process window when the subsequent chemical mechanical polishing process is performed on the metal gate 27. When the process window is increased, it means that the polishing rate difference tolerance of different areas in the polishing process is higher, which makes the metal gate 27 in different areas be removed more uniformly in the polishing process, thereby reducing the local unevenness and improving the surface flatness of the metal gate 27, and the global flatness is more consistent. Meanwhile, the larger process window allows better balance between chemical action and mechanical action in the polishing process. When the chemical action is dominant, there are fewer scratch defects, and the tolerance to over-polishing is also higher, further improving the surface flatness. In addition, the increase of the process window means that the sensitivity of the polishing process to parameter changes is reduced. In the selection of polishing liquid, the wear of polishing pad, the fluctuation of polishing pressure and other aspects, a larger process window can provide more adjustment space, so that the polishing process is more stable, and the control of surface flatness is more accurate.
[0079] In one embodiment, the thickness of the silicon nitride layer 12 is less than or equal to 100 angstroms.
[0080] The present application sets the thickness range of the silicon nitride layer 12 to protect the subsequent removal of the oxide layer 24 of the core area A, while not affecting the subsequent metal gate 27 filling and polishing process, and adjusts the final surface flatness in cooperation with the two subsequent CMP processes, to optimize the final surface flatness.
[0081] Then, step 3 is performed to pattern the silicon nitride layer 12 to expose the upper surface of the dummy gate 29.
[0082] In one embodiment, the method of patterning the silicon nitride layer 12 includes: as shown in Figure 4 a patterned mask layer 32 is provided on the silicon nitride layer 12, and the patterned mask layer 32 exposes the silicon nitride layer 12 above the dummy gate 29; as shown in Figure 5 the silicon nitride layer 12 is patterned by using the patterned mask layer 32 as a mask for patterned etching, to obtain a patterned silicon nitride layer 12.
[0083] In one embodiment, after the silicon nitride layer 12 is patterned, as shown in Figure 6 the sidewall of the patterned silicon nitride layer 12 is subjected to a back etching process when the sidewall of the silicon nitride layer 12 is located on the spacer layer 22 of the sidewall of the dummy gate 29.
[0084] In one embodiment, a phosphoric acid is used to perform a back-etching process on the sidewall of the patterned silicon nitride layer 12.
[0085] The present application can ensure that the sidewall of the silicon nitride layer 12 is located on the spacer layer 22 of the sidewall of the dummy gate 29 after performing a back-etching process on the patterned silicon nitride layer 12, thereby improving the process window of the subsequent metal gate 27 filling process. This makes it possible to more uniformly fill the metal material when removing the dummy gate 29 and filling the metal gate 27, reduces the filling defects or voids of the metal gate 27 caused by the uneven sidewall of the groove 23 formed after the removal of the dummy gate 29, and improves the height uniformity and integrity of the metal gate 27, thereby improving the yield and reliability of the device.
[0086] In one embodiment, if the width of the dummy gate 29 is less than or equal to 28 nanometers, the sidewall of the patterned silicon nitride layer 12 is located on the spacer layer 22 of the sidewall of the dummy gate 29 when the silicon nitride layer 12 is patterned, as shown in FIG. 2B. Figure 5 In one embodiment, if the width of the dummy gate 29 is greater than 28 nanometers, the width of the overlap part C of the sidewall of the patterned silicon nitride layer 12 and the projection of the dummy gate 29 on the upper surface of the substrate 10 is less than 10% of the width of the dummy gate 29 when the silicon nitride layer 12 is patterned, as shown in FIG. 2D.
[0087] Since the small size of the dummy gate 29 requires higher precision in the removal process of the dummy gate 29 and the filling process of the metal gate 27, the slight shielding of the dummy gate 29 by the silicon nitride layer 12 is more likely to cause incomplete removal of the dummy gate 29 or poor sidewall morphology after removal, thereby resulting in poor filling effect of the subsequent metal gate 27. The present application can reduce the possibility that the incomplete removal of the dummy gate 29 and the difficulty in achieving good filling of the subsequent metal gate 27 in the small-size, high-density dummy gate 29 structure caused by the residual of the sidewall of the silicon nitride layer 12 on the dummy gate 29, which is beneficial to the process yield in small-size devices.
[0088] In one embodiment, if the width of the dummy gate 29 is greater than 28 nanometers, the sidewall of the patterned silicon nitride layer 12 is located on the spacer layer 22 of the sidewall of the dummy gate 29 when the silicon nitride layer 12 is patterned.
[0089] In one embodiment, if the width of the dummy gate 29 is greater than 28 nanometers, the width of the overlap part C of the sidewall of the patterned silicon nitride layer 12 and the projection of the dummy gate 29 on the upper surface of the substrate 10 is less than 10% of the width of the dummy gate 29 when the silicon nitride layer 12 is patterned, as shown in FIG. 2D. Figure 6
[0090] Since the slight shielding of the dummy gate 29 by the silicon nitride layer 12 does not have a significant impact on the filling quality and electrical performance of the metal gate 27 in the device structure with a large size of the dummy gate 29, the device reliability can be ensured, the patterning precision of the silicon nitride layer 12 is reduced, and the etching back process of the patterned silicon nitride layer 12 can be omitted according to the requirement.
[0091] Then, step 4 is performed, as shown in the figure, the silicon nitride layer 12 after patterning is used as a mask, and etching is continued downward to remove the dummy gate 29, so that the recesses 23 are obtained. Figure 7
[0092] Specifically, since the scheme of the present application is applied to the back gate process of setting the dummy gate 29 first, removing the dummy gate 29, and then setting the metal gate 27, a large height difference exists between the spacer layer 22 and the primary interlayer dielectric layer 28 when the oxide layer 24 of the core area A is removed after the dummy gate 29 is removed. At the same time, since different thicknesses of the oxide layer 24 of the core area A and the input / output area B (IO area) are required in the dual oxygen gate process, the oxide layer 24 of the core area A needs to be removed in the process, which leads to the formation of a large dishing morphology 31 between the spacer layer 22 and the primary interlayer dielectric layer 28 after the oxide layer 24 of the core area A is removed, and has a significant impact on the process window of the subsequent CMP of the metal gate 27. Therefore, the scheme of the present application is mainly used to reduce the impact of the dishing morphology 31 formed in the dual oxygen gate process using the back gate process on the flatness effect of the subsequent CMP of the metal gate 27.
[0093] Then, step 5 is performed, as shown in the figure, a predetermined thickness of the oxide layer 24 is covered on the surface of the silicon nitride layer 12 and the surface exposed by the recesses 23. Figure 8
[0094] In one embodiment, the thickness of the oxide layer 24 is set to 30 angstroms-100 angstroms, and the thickness of the gate oxide layer 21 is set to 20 angstroms-50 angstroms.
[0095] In one embodiment, the thickness of the oxide layer 24 is 40 angstroms, and the thickness of the gate oxide layer 21 is 30 angstroms.
[0096] Specifically, the thickness of the gate oxide layer 21 cannot exceed 100 angstroms due to process limitations, and the thicknesses of the oxide layer 24 and the gate oxide layer 21 can be set to other suitable thicknesses according to the requirement, which are all within the protection scope of the present application.
[0097] Then, step 6 is performed, and the oxide layer 24 corresponding to the predetermined core area A (core area) and the exposed gate oxide layer 21 are removed.
[0098] Specifically, the core region A and the input / output region are preset regions in the dual-gate oxide process. The IO region is mainly used for input and output of signals, and thus requires higher voltage resistance and reliability. Therefore, the gate oxide layer 24 in this region is usually thicker to improve the voltage resistance and reliability of the device. The core region A is mainly used for logic operation, and thus requires higher speed and lower power consumption. Therefore, the gate oxide layer 24 in this region is thinner to improve the switching speed and reduce the power consumption of the device.
[0099] In one embodiment, the method for removing the oxide layer 24 in the core region A and exposing the gate oxide layer 21 is as follows: Figure 9 As shown, a mask layer 32 is covered on the preset input / output region B (IO region) outside the core region A. Figure 10 As shown, the exposed oxide layer 24 in the core region A is etched with the mask layer 32 as a mask, and the gate oxide layer 21 on the bottom surface of the groove 23 is exposed after the oxide layer 24 is removed by further etching.
[0100] In one embodiment, as shown, Figure 11 After the oxide layer 24 in the core region A and the exposed gate oxide layer 21 are removed, a preset thickness of an interfacial layer 25 (IL) is arranged on the surface of the substrate 10 layer exposed after the gate oxide layer 21 is removed in the core region A, to form a thin-gate-oxide core region A.
[0101] Then, step 7 is performed, as shown, Figure 12 The exposed surface is covered with a work function metal layer 26.
[0102] In one embodiment, the thickness of the work function metal layer 26 is set to 50 angstroms-200 angstroms.
[0103] Specifically, the thickness of the work function metal layer 26 can be set to other suitable thicknesses according to requirements, which are all within the protection scope of the present application.
[0104] Then, step 8 is performed, as shown, Figure 13 A metal gate 27 is arranged on the surface of the work function metal layer 26. The metal gate 27 is filled in the groove 23 and covers the exposed surface of the work function metal layer 26. The removal rate of the metal gate 27 is greater than the removal rate of the silicon nitride layer 12 and less than the removal rate of the primary interlayer dielectric layer 28.
[0105] The application can control the removal rate of the metal gate 27 to be greater than the removal rate of the silicon nitride layer 12 in the first chemical mechanical polishing process, so that the metal gate 27 can be lower than the bottom surface of the silicon nitride layer 12 when the silicon nitride layer 12 is completely removed; and the removal rate of the metal gate 27 is less than the removal rate of the primary interlayer dielectric layer 28 in the second chemical mechanical polishing process, so that the surface height difference after the two chemical mechanical polishing processes is complementary and offset, and a surface with high final flatness is obtained, and the performance of the metal gate 27 is improved.
[0106] Specifically, the metal gate 27 is filled in the groove 23, and the metal gate 27 and the inner surface of the groove 23 are covered by the work function metal layer 26.
[0107] Specifically, the removal rate refers to the removal rate in the first chemical mechanical polishing process and the second chemical mechanical polishing process.
[0108] In one embodiment, after the metal gate 27 is provided, the height of the upper surface of the metal gate 27 beyond the upper surface of the work function metal layer 26 which is not located in the first groove 23 is 800 angstroms-1000 angstroms.
[0109] The application can further ensure the surface flatness after the two CMP processes by setting the height range of the upper surface of the metal gate 27 beyond the work function metal layer 26.
[0110] In one embodiment, the material of the metal gate 27 is copper, aluminum or tungsten. Specifically, the material of the metal gate 27 can also be any other suitable metal gate material, which is within the protection scope of the application.
[0111] The application sets the material of the metal gate 27 as tungsten, which matches the commonly used silicon dioxide material of the silicon nitride layer 12 and the primary interlayer dielectric layer 28, meets the requirement of the removal rate relationship, and can be used as a good metal gate 27 material, meeting the dual requirements of devices and processes.
[0112] Next, the first chemical mechanical polishing process is performed on the upper surface of the obtained structure, as shown in step 9. Figure 14 The silicon nitride layer 12 is completely removed.
[0113] In one embodiment, the first chemical mechanical polishing process uses an aluminum oxide abrasive.
[0114] The present application can adjust the removal rate of the silicon nitride layer 12 and the metal gate 27 in the first chemical mechanical polishing process by using the alumina polishing liquid, so as to better meet the requirement of the removal rate and improve the surface flatness of the final product.
[0115] Specifically, the polishing liquid used in the first chemical mechanical polishing process can also be other suitable polishing liquid according to the requirement, which is within the protection scope of the present application.
[0116] Finally, the step 10 is performed, as shown in the figure, the second chemical mechanical polishing process is performed again until the upper surface of the structure is flush. Figure 15
[0117] In one embodiment, the second chemical mechanical polishing process uses a silicon oxide polishing liquid.
[0118] The present application can adjust the removal rate of the primary interlayer dielectric layer 28 and the metal gate 27 in the second chemical mechanical polishing process by using the silicon oxide polishing liquid, so as to better meet the requirement of the removal rate and improve the surface flatness of the final product.
[0119] Specifically, the polishing liquid used in the second chemical mechanical polishing process can also be other suitable polishing liquid according to the requirement, which is within the protection scope of the present application.
[0120] The present application can adjust the removal rate of the primary interlayer dielectric layer 28 and the metal gate 27 in the second chemical mechanical polishing process by using the silicon oxide polishing liquid, so as to better meet the requirement of the removal rate and improve the surface flatness of the final product. Figure 15 As shown in the figure, the dishing morphology 31 in the metal gate 27 area after the first chemical mechanical polishing process is repaired and flattened in the second chemical mechanical polishing process, compared with the prior art, the surface flatness of the final product is greatly improved, and the problem of the surface flatness caused by the dishing morphology 31 and the difference in the CMP polishing rate of different materials in the double oxygen gate process of the back gate process is overcome. Figure 2
[0121] The present application also provides a semiconductor structure obtained by using any one of the preparation methods, as shown in the figure, the semiconductor structure comprises a substrate 10, a stress material region 11, a gate oxide layer 21, a spacer layer 22, an oxide layer 24, a work function metal layer 26, a metal gate 27 and a primary interlayer dielectric layer 28. Figure 15
[0122] The stress material area 11 is arranged on the upper surface of the substrate 10, and the gate oxide layer 21 is arranged on the upper surface of the substrate 10 without the stress material area 11.
[0123] The area between the stress material areas 11 on the gate oxide layer 21 includes an input / output area B and a core area A, and the sidewall and bottom surface of the gate structure in the input / output area B are wrapped with an oxide layer 24 with a preset thickness.
[0124] The recess 23 is formed between the gate structures arranged at intervals, and the sidewall and bottom surface of the recess 23 are covered with a spacer layer 22, and the primary interlayer dielectric layer 28 is filled in the recess 23 on the surface of the spacer layer 22.
[0125] The semiconductor structure prepared by the preparation method has improved flatness of the upper surface, thereby reducing defects and improving the device yield and performance reliability of the semiconductor structure, and is particularly beneficial to meet the higher requirements of small-size devices of 28 nm or less on the flatness of the metal gate 27.
[0126] In an embodiment, the semiconductor structure is used for a CIS (Complementary Metal-Oxide-Semiconductor Image Sensor) device.
[0127] In summary, the semiconductor structure and the preparation method thereof can protect the initial interlayer dielectric layer by the silicon nitride layer in the double-gate oxide process using the post-gate process, reduce the recessed morphology between the spacer layer and the primary interlayer dielectric layer in the process of removing the core area oxide layer, increase the process window of the chemical mechanical polishing process of the metal gate, and be beneficial to improve the flatness of the metal gate after polishing. Meanwhile, the removal rate relationship between the silicon nitride layer, the initial interlayer dielectric layer and the metal gate and the specific two chemical mechanical polishing processes further reduce the recess between the metal gate and the primary interlayer dielectric layer caused by the difference in polishing rate after the chemical mechanical polishing process, and further repair the surface flatness after polishing. In addition, by setting the thickness of the silicon nitride layer, the repair effect on the device surface flatness is ensured. Finally, by setting the overlapping area range between the patterned edge of the silicon nitride layer and the edge of the metal gate, the filling effect of the metal gate is optimized, and the surface flatness of the final obtained device is further improved.
[0128] Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.
[0129] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.
Claims
1. A method of fabricating a semiconductor structure, characterized by, The preparation method comprises: providing a structure to be processed, which comprises a substrate, stress material regions, a gate oxide layer, a spacer layer, dummy gates and a primary interlayer dielectric layer; the stress material regions are arranged at intervals near the upper surface of the substrate and exposed on the upper surface of the substrate; the gate oxide layer covers the upper surface of the substrate where no stress material regions are arranged, and the dummy gates are arranged at intervals in the regions of the gate oxide layer corresponding to the spaces between the stress material regions; the spacer layer covers the exposed surface of the gate oxide layer and the sidewalls of the dummy gates; the primary interlayer dielectric layer fills the spaces between the dummy gates which are arranged at intervals and covered by the spacer layer; the upper surface of the structure to be processed covered by the spacer layer and the dummy gates is flush with the upper surface of the primary interlayer dielectric layer; arranging a silicon nitride layer with a preset thickness on the upper surface of the structure to be processed; performing patterning on the silicon nitride layer to expose the upper surface of the dummy gates; continuing to etch downward with the patterned silicon nitride layer as a mask to remove the dummy gates and obtain recesses arranged at intervals; covering the exposed surface of the silicon nitride layer and the recesses with an oxide layer with a preset thickness; removing the oxide layer corresponding to the preset core region and the exposed gate oxide layer; covering the exposed surface with a work function metal layer; arranging a metal gate on the surface of the work function metal layer, wherein the metal gate fills the recesses and covers the exposed surface of the work function metal layer; the removal rate of the metal gate is greater than the removal rate of the silicon nitride layer and less than the removal rate of the primary interlayer dielectric layer; performing a first chemical mechanical polishing process on the upper surface of the obtained structure until the silicon nitride layer is completely removed; performing a second chemical mechanical polishing process again until the upper surface of the obtained structure is flush.
2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: after the patterning of the silicon nitride layer, if the sidewall of the patterned silicon nitride layer is located on the dummy gate, performing a re-etching process on the sidewall of the patterned silicon nitride layer so that the sidewall of the silicon nitride layer is located on the spacer layer of the sidewall of the dummy gate.
3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: if the width of the dummy gate is less than or equal to 28 nm, after the patterning of the silicon nitride layer, the sidewall of the patterned silicon nitride layer is located on the spacer layer of the sidewall of the dummy gate.
4. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: if the width of the dummy gate is greater than 28 nm, after the patterning of the silicon nitride layer, the sidewall of the patterned silicon nitride layer is located on the spacer layer of the sidewall of the dummy gate or the width of the projection of the sidewall of the patterned silicon nitride layer and the dummy gate on the upper surface of the substrate is less than 10% of the width of the dummy gate.
5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: the thickness of the silicon nitride layer is less than or equal to 100 angstroms.
6. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: the thickness of the oxide layer is 30 angstroms-100 angstroms and the thickness of the gate oxide layer is 20 angstroms-50 angstroms.
7. The method of claim 1, wherein the semiconductor structure is formed by a method comprising: the thickness of the work function metal layer is 50 angstroms-200 angstroms; after the metal gate is arranged, the upper surface of the metal gate protrudes from the upper surface of the work function metal layer by a height of 800 angstroms-1000 angstroms.
8. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: the material of the metal gate is copper, aluminum or tungsten.
9. The method of claim 8, wherein the semiconductor structure is prepared by a method comprising: The first chemical mechanical polishing process adopts an alumina polishing liquid, and the second chemical mechanical polishing process adopts a silicon oxide polishing liquid.
10. A semiconductor structure, characterized by The semiconductor structure is obtained by the preparation method in any one of claims 1-9, and the semiconductor structure comprises a substrate, a stress material region, a gate oxide layer, a spacer layer, an oxide layer, a work function metal layer, a metal gate, and a primary interlayer dielectric layer. The stress material region is arranged at intervals near the upper surface of the substrate and exposed on the upper surface of the substrate; the gate oxide layer covers the upper surface of the substrate without the stress material region; the gate structure is arranged at intervals in the region between the stress material regions on the gate oxide layer, and the gate structure comprises a metal gate and a work function metal layer wrapping the sidewall and bottom surface of the metal gate; The region between the stress material regions on the gate oxide layer comprises an input / output region and a core region, and the sidewall and bottom surface of the gate structure in the input / output region are wrapped with an oxide layer with a preset thickness; The gate structures arranged at intervals form a groove, the sidewall and bottom surface of the groove are covered with a spacer layer, the primary interlayer dielectric layer is filled in the groove on the surface of the spacer layer, and the upper surfaces of the primary interlayer dielectric layer, the spacer layer, the oxide layer, and the gate structure are flush.