Highly robust esd protection device

Abstract

The application provides a high-robust ESD protection device, comprising: a substrate, a surface of the substrate being covered by an N-type well layer and a P-type well layer side by side; a first P-type doped layer and a second P-type doped layer being covered on the N-type well layer, a first N-type doped layer, a second N-type doped layer and a third P-type doped layer being covered on the P-type well layer; the first N-type doped layer being close to the second P-type doped layer, and a spacing region being arranged between the first N-type doped layer and the second N-type doped layer; a first groove being arranged between the first P-type doped layer and the second P-type doped layer; a second groove being arranged between the second P-type doped layer and the first N-type doped layer; and a Zener doped layer being arranged in the N-type well layer, the Zener doped layer being located between the first groove and the second groove. Through the SCR structure of Zener triggering and NMOS auxiliary discharging, a lower triggering voltage, a moderate holding voltage and a higher unit area robustness are realized, and the performance deficiency problem of a traditional ESD device is effectively solved.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge protection for integrated circuits, and more specifically to highly robust ESD protection devices. Background Technology

[0002] Electrostatic discharge (ESD) is a common natural phenomenon in integrated circuits. Although the charge carried by an ESD event is very small, its rapid rise time and large current can cause a sharp increase in the internal temperature of the chip. Therefore, even an extremely weak electrostatic voltage can cause irreversible damage to an integrated circuit. In particular, with the rapid development of integrated circuits and semiconductor processes, the ESD design window is constantly narrowing as linewidths shrink, and the miniaturization of feature sizes places higher demands on ESD protection.

[0003] Diodes, gate-grounded NMOS transistors (GGNMOS), and thyristors (SCRs) are three commonly used ESD protection devices. Among them, SCRs have high current carrying capacity per unit area and low capacitance, making them a hot research topic in the industry. However, traditional SCRs have problems with excessively high trigger voltage and excessively low holding voltage, which prevents them from being directly used in actual products, such as applications with a typical operating voltage of 5V.

[0004] To address the aforementioned issues, auxiliary triggering methods can be used to reduce the trigger voltage of the SCR, while increasing the length of the SCR device can improve the holding voltage. However, increasing the device length increases the layout area, leading to a decrease in robustness per unit area and an increase in cost to achieve the same protection capability. Therefore, novel device structures are needed to improve robustness per unit area. Summary of the Invention

[0005] The purpose of this invention is to solve the technical problem that existing ESD protection devices cannot guarantee robustness and discharge capability while increasing the holding voltage.

[0006] A first aspect of the present invention provides a highly robust ESD protection device, comprising:

[0007] Substrate;

[0008] The surface of the substrate is covered with N-type well layers and P-type well layers side by side;

[0009] The N-type well layer is covered with a first P-type doped layer and a second P-type doped layer, and the P-type well layer is covered with a first N-type doped layer, a second N-type doped layer and a third P-type doped layer; the first N-type doped layer is close to the second P-type doped layer, and a gap region is provided between the first N-type doped layer and the second N-type doped layer.

[0010] A first trench is provided between the first P-type doped layer and the second P-type doped layer; a second trench is provided between the second P-type doped layer and the first N-type doped layer; and a third trench is provided between the second N-type doped layer and the third P-type doped layer.

[0011] The N-type well layer contains a Zener doped layer, which is located between the first trench and the second trench.

[0012] Furthermore, the Zener doped layer is N-type doped, and its doping concentration is higher than that of the N-type well layer.

[0013] Furthermore, the surface of the P-type well layer is provided with a gate structure, and the gate structure is placed on the spacer region between the first N-type doped layer and the second N-type doped layer.

[0014] Furthermore, the first P-type doped layer and the N-type doped layer are connected to the anode together via a metal interconnect.

[0015] The second P-type doped layer, the gate structure, the second N-type doped layer, and the third P-type doped layer are connected to the cathode via metal interconnects.

[0016] Furthermore, the first N-type doped layer, the gate structure, the second N-type doped layer, and the P-type well layer together constitute an NMOS transistor.

[0017] Furthermore, the second P-type doped layer and the Zener doped layer form a Zener diode.

[0018] Furthermore, the first P-type doped layer and the N-type well layer constitute an anode diode;

[0019] The first P-type doped layer, the N-type well layer, and the P-type well layer constitute a parasitic PNP transistor;

[0020] The N-type well layer, the P-type well layer, and the second N-type doped layer constitute a first parasitic NPN transistor;

[0021] The parasitic PNP transistor and the first parasitic NPN transistor form an SCR structure;

[0022] The first N-type doped layer, the second N-type doped layer, and the P-type well layer constitute the second parasitic NPN transistor.

[0023] Furthermore, the anode diode and the Zener diode form a trigger path;

[0024] The SCR structure forms the main discharge path;

[0025] The second parasitic NPN transistor forms an auxiliary discharge path.

[0026] A second aspect of the present invention provides a highly robust ESD protection method, employing an ESD protection device with high voltage retention as described in any of the preceding claims, wherein when the ESD voltage reaches the sum of the forward conduction voltage of the anode diode and the Zener breakdown voltage, the trigger path formed by the first P-type doped layer, the N-type well layer, the Zener doped layer and the second P-type doped layer is turned on.

[0027] When the ESD voltage increases further, the second trigger path formed by the first P-type doped layer, the N-type well layer, the P-type well layer, and the second N-type doped layer is turned on, and...

[0028] The auxiliary triggering path formed by the first N-type doped layer, the P-type well layer, and the second N-type doped layer is turned on.

[0029] Furthermore, in the first triggering path, the current flows from the first P-type doped layer, through the N-type well layer and the Zener doped layer, to the second P-type doped layer;

[0030] In the second trigger path, the current flows from the second P-type doped layer, through the N-type well layer and the P-type well layer, to the second N-type doped layer;

[0031] In the auxiliary triggering path, the current flows from the first N-type doped layer, through the P-type well layer, to the second N-type doped layer.

[0032] Compared to existing technologies, this invention offers at least the following advantages: By employing a parallel layout of N-type and P-type well layers and a multi-layered doped structure design, combined with the layered isolation configuration of the first, second, and third trenches, a lower trigger voltage, a moderate holding voltage, and higher robustness per unit area are achieved while maintaining a compact layout area. The Zener structure reduces the trigger voltage, the NMOS transistor improves device area utilization, and a multi-layered synergistic discharge mechanism involving the Zener branch, GGNMOS branch, and SCR branch is formed during ESD events. This enhances the current carrying capacity and thermal stability per unit area, effectively solving the technical problems of excessively high trigger voltage, excessively low holding voltage, and low protection efficiency per unit area in traditional SCR devices. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained as provided without creative effort.

[0034] Figure 1 This is a cross-sectional view of a traditional GGNMOS device;

[0035] Figure 2 This is a cross-sectional view of a traditional voltage-maintaining SCR device;

[0036] Figure 3 This is a cross-sectional view of an ESD protection device according to an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the discharge path of the ESD protection device during operation in one embodiment of the present invention;

[0038] Figure 5 This is a comparison of the voltage-current characteristics of the ESD protection device and GGNMOS under ESD simulation in one embodiment of the present invention;

[0039] Figure 6 This is a comparison diagram of the lattice temperature of the ESD protection device and GGNMOS under ESD simulation in one embodiment of the present invention.

[0040] Wherein, 1-substrate; 2-N-type well layer; 3-P-type well layer; 4-first trench; 5-second trench; 6-third trench; 7-gate structure; 8-first P-type doped layer; 9-second P-type doped layer; 10-first N-type doped layer; 11-second N-type doped layer; 12-third P-type doped layer; 13-Zener doped layer. Detailed Implementation

[0041] The present invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being broadly known to those skilled in the art and is not intended to limit the invention.

[0042] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0043] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer as explained below. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0044] Please refer to Figure 1 This is a cross-sectional view of a traditional GGNMOS. Connecting the drain of an NMOS transistor to the anode and the gate to the source, while simultaneously connecting the gate and source to the cathode, forms a GGNMOS. The parasitic NPN transistor in a GGNMOS consists of an N+ injection region (equivalent to the emitter) connected to the cathode, a P-well (equivalent to the base), and an N+ injection region (equivalent to the collector) connected to the anode. When an ESD event occurs, the anode potential rises rapidly. When it reaches the N+ / P-well avalanche breakdown voltage, current flows through the P-well, causing a voltage drop. At this point, the collector junction of the NPN transistor is reverse-biased, and the emitter junction is forward-biased, causing the parasitic NPN transistor to turn on and discharge the ESD current. GGNMOS is widely used, often in medium-to-high voltage (e.g., 5V) ESD protection, but its protection efficiency per unit area is low.

[0045] Please refer to Figure 2 This is a cross-sectional view of a traditional voltage-holding SCR device. The Zener diode layer and the P+ injection region above it form a Zener diode, which, together with the forward-biased P+ / N-well structure formed by the P+ injection region connected to the anode and the N-well below, constitutes the Zener trigger path of the device. In an SCR, the parasitic PNP transistor is composed of the P+ injection region connected to the anode (equivalent to the emitter), the N-well (equivalent to the base), and the P-well (equivalent to the collector) below the P+ injection region connected to the anode; the parasitic NPN transistor is composed of the N-well (equivalent to the collector), the P-well (equivalent to the base), and the N+ injection region connected to the cathode (equivalent to the emitter). When an ESD event occurs, the anode potential rises rapidly. When the sum of the forward bias voltage of the P+ / N-well and the reverse bias voltage of the Zener diode is reached, the Zener trigger path conducts. At this time, the base-emitter junction of the PNP transistor is forward-biased, turning on the PNP transistor; simultaneously, the collector junction of the NPN transistor is reverse-biased, and the emitter junction is forward-biased, turning on the NPN transistor. Ultimately, the PNP and NPN transistors form a positive feedback path, thereby rapidly discharging a large amount of ESD current. To obtain a sufficient holding voltage, a sufficient anode-cathode spacing must be ensured, thus increasing the device area.

[0046] Example 1

[0047] This embodiment provides a highly robust ESD protection device; please refer to [reference needed]. Figures 3-4 , including: substrate 1.

[0048] The surface of the substrate 1 is covered with an N-type well layer 2 and a P-type well layer 3 side by side.

[0049] The N-type well layer 2 is covered with a first P-type doped layer 8 and a second P-type doped layer 9, and the P-type well layer 3 is covered with a first N-type doped layer 10, a second N-type doped layer 11 and a third P-type doped layer 12; the first N-type doped layer 10 is close to the second P-type doped layer 9, and there is a gap between the first N-type doped layer 10 and the second N-type doped layer 11.

[0050] A first trench 4 is provided between the first P-type doped layer 8 and the second P-type doped layer 9.

[0051] A second trench 5 is provided between the second P-type doped layer 9 and the first N-type doped layer 10. A third trench 6 is provided between the second N-type doped layer 11 and the third P-type doped layer 12.

[0052] The N-type well layer 2 is provided with a Zener doped layer 13, which is located between the first trench 4 and the second trench 5.

[0053] Specifically, substrate 1 can be either silicon substrate 1 or SOI substrate 1, wherein the N-type well layer 2 and P-type well layer 3 are formed by ion implantation or diffusion processes. The width of the spacer region can be adjusted according to the device performance requirements.

[0054] By employing a multi-trench structure and composite doped layer design, multiple ESD protection paths are achieved while maintaining a small footprint. The second trench 5 and the third trench 6 form a synergistic protection structure. Optimizing trench location and doping distribution effectively improves the device's holding voltage and robustness, resolving the conflict between trigger and holding voltages faced by traditional ESD protection devices in miniaturization processes. Compared to devices with a single protection structure, this design offers superior ESD protection performance within the same area.

[0055] Furthermore, a Zener doped layer 13 is disposed within the N-type well layer 2, and the Zener doped layer 13 is located between the first trench 4 and the second trench 5.

[0056] Zener doped layer 13 is heavily N-type doped, with a doping concentration higher than that of N-type well layer 2.

[0057] Furthermore, the surface of the P-type well layer 3 is provided with a gate structure 7, and the gate structure 7 is placed on the spacer region. The spacer region refers to the undoped region reserved between the first N-type doped layer 10 and the second N-type doped layer 11 (i.e., a part of the P-type well layer 3 near the upper surface).

[0058] In this embodiment, please refer to Figure 3The first P-type doped layer 8 and the N-type doped layer 10 are connected to the anode via metal interconnects. The second P-type doped layer 9, the gate structure 7, the second N-type doped layer 11, and the third P-type doped layer 12 are connected to the cathode via metal interconnects.

[0059] Furthermore, the second P-type doped layer 9 and the Zener doped layer 13 form a Zener diode.

[0060] A Zener diode structure is formed by incorporating a high-concentration Zener doped layer 13 within the N-type well layer 2 and the adjacent second P-type doped layer 9. When the ESD voltage reaches the Zener breakdown voltage, this diode conducts first, forming a trigger path, thereby effectively reducing the device's trigger voltage. Compared to traditional SCR structures, this design maintains the high current handling capability of the original SCR while improving the device's triggering characteristics through the auxiliary triggering mechanism of the Zener diode.

[0061] Furthermore, the first N-type doped layer 10, the gate structure 7, the second N-type doped layer 11, and the P-type well layer 3 together constitute an NMOS transistor. In this embodiment, the NMOS transistor uses a standard device from a process library, and its size can be adjusted as needed.

[0062] Specifically, the first N-type doped layer 10, the second N-type doped layer 11, and the P-type well layer 3 form a PN junction; the gate structure 7 is placed on the spacer region, and the conduction state of the channel region can be controlled by applying a gate voltage. Thus, these three elements together constitute an NMOS transistor structure with a source, drain, and gate. By placing the gate structure 7 in the spacer region, the first N-type doped layer 10, the second N-type doped layer 11, the gate structure 7, and the P-type well layer 3 together constitute an NMOS transistor. Introducing this NMOS transistor adds a discharge path and improves the area utilization of the device.

[0063] Furthermore, the first P-type doped layer 8, the N-type well layer 2, and the P-type well layer 3 constitute a parasitic PNP transistor.

[0064] The N-type well layer 2, the P-type well layer 3, and the second N-type doped layer 11 constitute the first parasitic NPN transistor.

[0065] The parasitic PNP transistor and the first parasitic NPN transistor constitute an SCR structure.

[0066] Specifically, the SCR structure is composed of parasitic PNP transistors. The parasitic PNP transistor is formed by a first P-type doped layer 8 (equivalent to the emitter region), an N-type well layer 2 (equivalent to the base region), and a P-type well layer 3 (equivalent to the collector region). The first parasitic NPN transistor is formed by an N-type well layer 2 (equivalent to the collector region), a P-type well layer (equivalent to the collector region), and a second N-type doped layer 11 (equivalent to the emitter region). These parasitic PNP transistors, together with the first parasitic NPN transistor, constitute the SCR structure. Furthermore, the thickness of each layer can be adjusted according to actual process conditions.

[0067] In this embodiment, please refer to Figure 4 The first P-type doped layer 8 and the N-type well layer 2 constitute an anode diode. The first N-type doped layer 10, the second N-type doped layer 11, and the P-type well layer 3 constitute a second parasitic NPN transistor.

[0068] The anode diode and the Zener diode form a trigger path. The SCR structure forms the main discharge path. The second parasitic NPN transistor forms an auxiliary discharge path.

[0069] Example 2

[0070] This embodiment provides a highly robust ESD protection method, employing the highly robust ESD protection device as described in Embodiment 1.

[0071] When the ESD voltage reaches the sum of the forward conduction voltage of the anode diode and the Zener breakdown voltage, the trigger path formed by the first P-type doped layer 8, the N-type well layer 2, the Zener doped layer 13 and the second P-type doped layer 9 is turned on, that is, the anode diode and the Zener diode are turned on.

[0072] When the ESD voltage increases further, the main discharge path formed by the first P-type doped layer 8, the N-type well layer 2, the P-type well layer 3 and the second N-type doped layer 11 is turned on, that is, the SCR structure is turned on.

[0073] In addition, the auxiliary discharge path formed by the first N-type doped layer 10, the P-type well layer 3 and the second N-type doped layer 11 is turned on, that is, the second parasitic NPN transistor is turned on.

[0074] Furthermore, in the triggering path, the current flows from the first P-type doped layer 8, through the N-type well layer 2 and the Zener doped layer 13 to the second P-type doped layer 9.

[0075] In the main discharge path, the current flows from the second P-type doped layer 9, through the N-type well layer 2 and the P-type well layer 3 to the second N-type doped layer 11;

[0076] In the auxiliary discharge path, the current flows from the first N-type doped layer 10 through the P-type well layer 3 to the second N-type doped layer 11.

[0077] Specifically, when an ESD event occurs, the anode voltage rises rapidly, triggering the path to conduct when it reaches the sum of the forward bias voltage of the anode diode and the reverse bias voltage of the Zener diode. Due to the high doping concentration of the Zener layer, its reverse breakdown voltage is lower, reducing the device's trigger voltage.

[0078] When the voltage increases further to the N+ / P-well avalanche breakdown voltage, the GGNMOS branch and the trigger path discharge a small current together. In the trigger path, the forward-biased P+ / N-well is the base-emitter junction of the parasitic PNP transistor. When current is injected into the N-well, the parasitic PNP transistor is in the conducting state. In the auxiliary discharge path, the P-type well layer 3 is the base-emitter junction of the second parasitic NPN transistor. When current is injected into the P-type well layer 3, the second parasitic NPN transistor is in the conducting state. At this time, a positive feedback path is formed, and the SCR branch conducts and discharges a large amount of ESD current. At the same time, the GGNMOS branch and the Zener branch act as a current shunt, discharging in tandem with the SCR branch to improve the overall current discharge capability of the device.

[0079] The following discussion uses specific simulation experiments as examples:

[0080] Please refer to Figures 5-6 The device's triggering characteristics under ESD events were simulated using pulses with a rise time of 10 ns and a pulse width of 100 ns. The average values ​​of voltage and current between 70 ns and 90 ns were taken, and the simulation data were recorded and voltage-current curves were plotted. The simulated voltage-current curves are shown below. Figure 5 As shown, the trigger voltage of GGNMOS is 8.2V, and the holding voltage is 6.8V; in this embodiment, the trigger voltage of the ESD protection device is 6.9V, and a slight hysteresis occurs when the voltage increases to 7.3V, with a holding voltage of 7V. Compared to GGNMOS, the trigger voltage of the ESD protection device in this embodiment is lower.

[0081] The GGNMOS device has a total length of 7.5 μm, while the ESD protection device in this embodiment has a total length of 12.5 μm. Both devices have a width of 50 μm, making the area of ​​the SCR device in this invention approximately 1.67 times that of the GGNMOS device. To compare the discharge capability per unit area, the current applied to the ESD protection device in this embodiment is 1.67 times the current applied to the GGNMOS in the simulation. Therefore, a 0.6A ESD-like pulse is applied to the GGNMOS, and a 1A ESD-like pulse is applied to the ESD protection device. The simulation results are as follows. Figure 6As shown, under ESD simulation with a current of 0.6A, the maximum lattice temperature of GGNMOS is 1435K, indicating that the device is close to failure. In contrast, the ESD protection device in this embodiment has a maximum lattice temperature of 403K under ESD simulation with a current of 1A, significantly lower than that of GGNMOS. Therefore, compared to GGNMOS, the ESD protection device in this embodiment has a higher failure current and stronger discharge capability per unit area.

[0082] In summary, the ESD protection device of this invention utilizes both a Zener structure and a GGNMOS structure to trigger the SCR to conduct. After the SCR conducts, the GGNMOS branch, Zener branch, and SCR branch share the discharge current. Compared to traditional GGNMOS devices, the SCR device of this invention has a lower trigger voltage, stronger discharge capability per unit area, and a suitable holding voltage, making it suitable for ESD protection under medium to high operating voltages (e.g., 5V).

[0083] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A highly robust ESD protection device, characterized in that, include: Substrate; The surface of the substrate is covered with N-type well layers and P-type well layers side by side; The N-type well layer is covered with a first P-type doped layer and a second P-type doped layer, and the P-type well layer is covered with a first N-type doped layer, a second N-type doped layer and a third P-type doped layer; the first N-type doped layer is close to the second P-type doped layer, and a spacer region is provided between the first N-type doped layer and the second N-type doped layer, and a gate structure is provided on the spacer region; A first trench is provided between the first P-type doped layer and the second P-type doped layer; a second trench is provided between the second P-type doped layer and the first N-type doped layer; and a third trench is provided between the second N-type doped layer and the third P-type doped layer. The N-type well layer is provided with a Zener doped layer, which is located between the first trench and the second trench; The first P-type doped layer and the N-type doped layer are connected to the anode together via a metal interconnection wire; The second P-type doped layer, the gate structure, the second N-type doped layer, and the third P-type doped layer are connected to the cathode via metal interconnects. The second P-type doped layer and the Zener doped layer form a Zener diode; The first P-type doped layer and the N-type well layer constitute an anode diode; The first P-type doped layer, the N-type well layer, and the P-type well layer constitute a parasitic PNP transistor; The N-type well layer, the P-type well layer, and the second N-type doped layer constitute a first parasitic NPN transistor; The parasitic PNP transistor and the first parasitic NPN transistor form an SCR structure; The first N-type doped layer, the second N-type doped layer, and the P-type well layer constitute a second parasitic NPN transistor; The anode diode and the Zener diode form a trigger path; The SCR structure forms the main discharge path; The second parasitic NPN transistor forms an auxiliary discharge path.

2. The highly robust ESD protection device as described in claim 1, characterized in that, The Zener doped layer is N-type doped, and its doping concentration is higher than that of the N-type well layer.

3. The highly robust ESD protection device as described in claim 1, characterized in that, The surface of the P-type well layer is provided with a gate structure, and the gate structure is placed on the spacer region.

4. The highly robust ESD protection device as described in claim 3, characterized in that, The first N-type doped layer, the gate structure, the second N-type doped layer, and the P-type well layer together constitute an NMOS transistor.

5. A highly robust ESD protection method, employing the highly robust ESD protection device as described in any one of claims 1-4, characterized in that, When the ESD voltage reaches the sum of the forward conduction voltage of the anode diode and the Zener breakdown voltage, the trigger path formed by the first P-type doped layer, the N-type well layer, the Zener doped layer and the second P-type doped layer is turned on. When the ESD voltage increases further, the main discharge path formed by the first P-type doped layer, the N-type well layer, the P-type well layer, and the second N-type doped layer is turned on, and... The auxiliary discharge path formed by the first N-type doped layer, the P-type well layer, and the second N-type doped layer is turned on.

6. The highly robust ESD protection method as described in claim 5, characterized in that, In the triggering path, the current flows from the first P-type doped layer, through the N-type well layer and the Zener doped layer, to the second P-type doped layer; In the main discharge path, the current flows from the second P-type doped layer, through the N-type well layer and the P-type well layer, to the second N-type doped layer; In the auxiliary discharge path, the current flows from the first N-type doped layer, through the P-type well layer, to the second N-type doped layer.

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