Photovoltaic cell and method for producing a photovoltaic cell, photovoltaic module

Abstract

The application relates to a photovoltaic cell and a preparation method thereof, and a photovoltaic module. The photovoltaic cell comprises a silicon substrate, a doped silicon layer, a composite barrier layer and a metal electrode; the silicon substrate has a silicon substrate with oppositely arranged first and second surfaces, the first surface comprises a first region and a second region, and the second surface comprises a third region and a fourth region; the doped silicon layer is arranged on at least one of the first and second surfaces; a composite barrier layer and a metal electrode are arranged on the surface of the doped silicon layer away from the silicon substrate in the first and / or third region, the metal electrode is electrically connected with the doped silicon layer; the composite barrier layer is arranged between the metal electrode and the doped silicon layer, and the material of the composite barrier layer comprises TiO x and TiN. The photovoltaic cell can reduce the risk of silver penetrating the doped silicon layer, reduce the electric leakage, and thus realize a higher conversion efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic, in particular to a photovoltaic cell, a preparation method thereof and a photovoltaic module. BACKGROUND

[0002] TOPCon cell is the abbreviation of Tunnel Oxide Passivated Contact photovoltaic cell, which is one of the mainstream technologies of high-efficiency crystalline silicon photovoltaic cells at present. With high conversion efficiency and good industrialization prospect, it has become a research and application hotspot in the photovoltaic industry. However, in the preparation method of the traditional TOPCon photovoltaic cell, when the printed conductive silver paste is sintered at high temperature to prepare the electrode, silver is easy to penetrate the doped silicon layer, causing leakage. SUMMARY

[0003] Therefore, it is necessary to provide a photovoltaic cell, a preparation method thereof and a photovoltaic module. The photovoltaic cell of the present application can reduce the risk of silver penetrating the doped silicon layer, reduce leakage, and thus achieve high conversion efficiency.

[0004] In a first aspect, the present application provides a photovoltaic cell, comprising a silicon substrate, a doped silicon layer, a composite barrier layer and a metal electrode; the silicon substrate has a silicon substrate with oppositely arranged first and second surfaces, the first surface includes a first region and a second region, and the second surface includes a third region and a fourth region; the doped silicon layer is arranged on at least one of the first surface and the second surface; the surface of the doped silicon layer away from the silicon substrate in the first region and / or the third region is provided with the composite barrier layer and the metal electrode, and the metal electrode and the doped silicon layer are electrically connected; the composite barrier layer is arranged between the metal electrode and the doped silicon layer, and the material of the composite barrier layer includes TiO x and TiN.

[0005] In some embodiments, the thickness of the composite barrier layer is 5-8 nm.

[0006] In some embodiments, the atomic ratio of N element to O element in the composite barrier layer is (3-7):7.

[0007] In some embodiments, the thickness of the doped silicon layer is 70-90 nm.

[0008] In some embodiments, the percentage of the depth of the composite barrier layer into the doped silicon layer to the thickness of the doped silicon layer is 15-20%.

[0009] In some embodiments, the depth of the composite barrier layer into the doped silicon layer is 12-18 nm.

[0010] In some embodiments, the doped silicon layer comprises a first doped silicon layer on the first surface and a second doped silicon layer on the second surface, the first doped silicon layer and the second doped silicon layer are oppositely doped; the composite barrier layer comprises a first composite barrier layer and a second composite barrier layer; the metal electrode comprises a first metal electrode and a second metal electrode.

[0011] The first composite barrier layer and the first metal electrode are sequentially stacked on the surface of the first doped silicon layer in the first region away from the silicon substrate; the second composite barrier layer and the second metal electrode are sequentially stacked on the surface of the second doped silicon layer in the third region away from the silicon substrate.

[0012] In some embodiments, the photovoltaic cell further comprises a tunneling oxide layer and an aluminum oxide layer; the tunneling oxide layer is between the silicon substrate and the second doped silicon layer; the aluminum oxide layer is between the tunneling oxide layer and the second doped silicon layer.

[0013] In some embodiments, the thickness of the aluminum oxide layer is 0.2 nm to 0.5 nm.

[0014] In a second aspect, the present application provides a method for preparing a photovoltaic cell, the photovoltaic cell being any one of the above-mentioned photovoltaic cells, comprising the following steps:

[0015] Providing the silicon substrate;

[0016] Preparing a doped silicon layer on at least one of the first surface and the second surface;

[0017] Coating an electrode paste on the surface of the doped silicon layer in the first region and / or the third region, the electrode paste comprising an organic carrier, glass powder, Ag particles and TiN particles;

[0018] Sintering the electrode paste to form the metal electrode and the composite barrier layer.

[0019] In some embodiments, the mass percentage of the TiN particles in the electrode paste is 3% to 8%.

[0020] In some embodiments, the particle size of the TiN particles is 20 nm to 50 nm.

[0021] In some embodiments, the highest temperature of the sintering process is 700°C to 750°C.

[0022] In some embodiments, the doped silicon layer includes a first doped silicon layer on the first surface and a second doped silicon layer on the second surface, the first doped silicon layer and the second doped silicon layer have opposite doping types; the recombination barrier layer includes a first recombination barrier layer and a second recombination barrier layer; the metal electrode includes a first metal electrode and a second metal electrode;

[0023] The first recombination barrier layer and the first metal electrode are sequentially stacked on a surface of the first doped silicon layer in the first region away from the silicon substrate; the second recombination barrier layer and the second metal electrode are sequentially stacked on a surface of the second doped silicon layer in the third region away from the silicon substrate;

[0024] The photovoltaic cell further includes a tunneling oxide layer and an aluminum oxide layer; the tunneling oxide layer is between the silicon substrate and the second doped silicon layer; the aluminum oxide layer is between the tunneling oxide layer and the second doped silicon layer;

[0025] The method for preparing the aluminum oxide layer includes the following steps:

[0026] An aluminum oxide atomic layer is prepared on a surface of the tunneling oxide layer by an aluminum precursor and an oxygen precursor layer by layer, and the number of layers of the aluminum oxide atomic layer is 2-5.

[0027] In some embodiments, the method further includes the following steps:

[0028] A second doped silicon layer is prepared on a second surface of the silicon substrate by boron diffusion using a boron source;

[0029] The boron diffusion includes preheating treatment, diffusion treatment, and relaxation treatment performed sequentially;

[0030] The temperature of the diffusion treatment is higher than the temperature of the preheating treatment, and the temperature of the relaxation treatment is between the temperature of the diffusion treatment and the temperature of the preheating treatment.

[0031] In a third aspect, the present application provides a photovoltaic module, comprising:

[0032] A cover plate;

[0033] At least one cell string, the cell string including the photovoltaic cell of any one of the above or the photovoltaic cell prepared by the method for preparing the photovoltaic cell of any one of the above;

[0034] And a packaging layer, the packaging layer being between the cover plate and the cell string, the cover plate being connected with the cell string through the packaging layer.

[0035] In the aforementioned photovoltaic cell, a composite barrier layer is disposed between the metal electrode and the doped silicon layer in the region where the metal electrode is located. The material of the composite barrier layer includes TiO2. x TiN and other materials can control the diffusion depth of metal atoms during the metal electrode fabrication process, thereby reducing the risk of metal atoms penetrating the doped silicon layer, reducing leakage current, and thus achieving higher conversion efficiency of photovoltaic cells. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of a photovoltaic cell provided in one embodiment of this application;

[0037] Figure 2 A schematic diagram of a structure in which a tunneling oxide layer, an aluminum oxide layer, and a second doped silicon layer are sequentially stacked on the second surface of a silicon substrate;

[0038] Figure 3 In order to be in Figure 2 A schematic diagram of the structure for fabricating the first doped silicon layer based on the structure shown;

[0039] Figure 4 In order to be in Figure 3 A schematic diagram of the structure for fabricating the first passivation layer and the second passivation layer based on the structure shown;

[0040] Figure 5 In order to be in Figure 4 A schematic diagram of the structure for fabricating the first metal electrode and the first composite barrier layer based on the structure shown.

[0041] Explanation of reference numerals in the attached figures:

[0042] 10-Silicon substrate; 11-First region; 12-Second region; 13-Third region; 14-Fourth region; 21-First doped silicon layer; 22-Second doped silicon layer; 30-First passivation layer; 41-First composite barrier layer; 42-Second composite barrier layer; 50-First metal electrode; 60-Tunneling oxide layer; 70-Alumina layer; 80-Second passivation layer; 90-Second metal electrode. Detailed Implementation

[0043] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, a detailed description of specific embodiments of this application is provided below. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0045] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0047] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0048] Reference Figure 1As shown, one embodiment of this application provides a photovoltaic cell, including a silicon substrate 10, a doped silicon layer, a composite barrier layer, and a metal electrode; the silicon substrate 10 has a first surface and a second surface disposed opposite to each other, the first surface includes a first region 11 and a second region 12, and the second surface includes a third region 13 and a fourth region 14; the doped silicon layer is disposed on at least one of the first surface and the second surface; a composite barrier layer and a metal electrode are disposed on the surface of the doped silicon layer located in the first region 11 and / or the third region 13 away from the silicon substrate 10, and the metal electrode and the doped silicon layer are electrically connected; the composite barrier layer is disposed between the metal electrode and the doped silicon layer, and the material of the composite barrier layer includes TiO2. x And TiN.

[0049] In the aforementioned photovoltaic cell, a composite barrier layer is disposed between the metal electrode and the doped silicon layer in the region where the metal electrode is located. The material of the composite barrier layer includes TiO2. x TiN and other materials can control the diffusion depth of metal atoms during the metal electrode fabrication process, thereby reducing the risk of metal atoms penetrating the doped silicon layer, reducing leakage current, and thus achieving higher conversion efficiency of photovoltaic cells.

[0050] In some embodiments, the composite barrier layer is made of TiO2. x Composite materials formed with TiN.

[0051] In some embodiments, the thickness of the composite barrier layer is 5 nm to 8 nm.

[0052] Optionally, the thickness of the composite barrier layer is 5nm, 5.2nm, 5.5nm, 5.8nm, 6nm, 6.2nm, 6.5nm, 6.8nm, 7nm, 7.2nm, 7.5nm, 7.8nm or 8nm, or the thickness of the composite barrier layer may be within any two of the above thicknesses.

[0053] In some embodiments, the atomic ratio of N to O elements in the composite barrier layer is (3~7):7.

[0054] Optionally, in the composite barrier layer, the atomic ratio of N to O elements is 3:7, 3.5:7, 4:7, 4.5:7, 5:7, 5.5:7, 6:7, 6.5:7, or 7:7. Alternatively, in the composite barrier layer, the atomic ratio of N to O elements can also be within the range of any two of the above atomic ratios.

[0055] In some embodiments, the thickness of the doped silicon layer is 70 nm to 90 nm.

[0056] Optionally, the thickness of the doped silicon layer is 70nm, 72nm, 74nm, 76nm, 78nm, 80nm, 82nm, 84nm, 86nm, 88nm or 90nm, or the thickness of the doped silicon layer may be within any two of the above thicknesses.

[0057] In some embodiments, the composite barrier layer penetrates to a depth of 15% to 20% of the thickness of the doped silicon layer.

[0058] In traditional conductive silver paste sintering for metal electrode fabrication, the silver diffusion depth is typically 80%–90% of the thickness of the doped silicon layer. In the technical solution of this application, the silver diffusion depth is reduced by at least 60% through the obstruction of silver diffusion by a composite barrier layer. (See again...) Figure 1 As shown, it can be understood that the depth of the composite barrier layer into the doped silicon layer refers to the distance between the surface of the composite barrier layer near the silicon substrate 10 and the surface of the doped silicon layer away from the silicon substrate 10. For example, Figure 1 In this context, 'a' represents the depth of the composite barrier layer penetrating the doped silicon layer. Optionally, the percentage of the depth of the composite barrier layer penetrating the doped silicon layer to the thickness of the doped silicon layer is 15%, 16%, 17%, 18%, 19%, or 20%, or the percentage of the depth of the composite barrier layer penetrating the doped silicon layer to the thickness of the doped silicon layer can be within any two of the above percentages.

[0059] In some embodiments, the composite barrier layer penetrates the doped silicon layer to a depth of 12 nm to 18 nm.

[0060] Optionally, the composite barrier layer penetrates the doped silicon layer to a depth of 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, or 18nm, or the composite barrier layer penetrates the doped silicon layer to a depth between any two of the above depths.

[0061] In some embodiments, the doped silicon layer includes a first doped silicon layer 21 located on a first surface and a second doped silicon layer 22 located on a second surface, wherein the doping types of the first doped silicon layer 21 and the second doped silicon layer 22 are opposite; the composite barrier layer includes a first composite barrier layer 41 and a second composite barrier layer 42; and the metal electrode includes a first metal electrode 50 and a second metal electrode 90.

[0062] A first composite barrier layer 41 and a first metal electrode 50 are sequentially stacked on the surface of the first doped silicon layer 21 located in the first region 11 away from the silicon substrate 10; a second composite barrier layer 42 and a second metal electrode 90 are sequentially stacked on the surface of the second doped silicon layer 22 located in the third region 13 away from the silicon substrate 10.

[0063] In some embodiments, the photovoltaic cell further includes a tunneling oxide layer 60 and an aluminum oxide layer 70; the tunneling oxide layer 60 is located between the silicon substrate 10 and the second doped silicon layer 22; the aluminum oxide layer 70 is located between the tunneling oxide layer 60 and the second doped silicon layer 22.

[0064] An aluminum oxide layer 70 is disposed between the tunneling oxide layer 60 and the second doped silicon layer 22, which can fill oxygen vacancy defects and reduce the interface state density to 5 × 10⁻⁶. 10 cm -2 eV -1 In traditional TOPCon cells, the interface recombination defect rate is high, and the interface state density between the doped silicon layer and the tunneling oxide layer is typically greater than 1 × 10⁶. 11 cm -2 eV -1 In this application, the alumina layer 70 can reduce the interface state density between the doped silicon layer and the tunnel oxide layer 60, thereby improving Voc and conversion efficiency.

[0065] In some embodiments, the thickness of the alumina layer 70 is 0.2 nm to 0.5 nm.

[0066] Understandably, the alumina layer 70 of the aforementioned thickness can be prepared through 2-5 atomic layer deposition cycles. If only one atomic layer is prepared, i.e., an alumina layer 70 only about 0.11 nm thick, it is easy to fail to completely cover the surface dangling bonds and oxygen vacancies of the tunneling oxide layer 60. If the thickness of the alumina layer 70 is too large, it may lead to band structure degradation, forming a carrier transport barrier, thereby affecting carrier transport and reducing conversion efficiency. Within the aforementioned range of alumina layer 70 thickness, it is easier to improve the conversion efficiency of photovoltaic cells. At the same time, an excessively thick alumina layer 70, due to its high coefficient of thermal expansion, is also prone to interfacial cracks during subsequent processing, leading to an increased fragmentation rate. Optionally, the thickness of the alumina layer 70 is 0.2nm, 0.22nm, 0.25nm, 0.28nm, 0.3nm, 0.32nm, 0.35nm, 0.38nm, 0.4nm, 0.42nm, 0.45nm, 0.48nm, or 0.5nm, or the thickness of the alumina layer 70 may be within any two of the above-mentioned thicknesses.

[0067] It should be noted that while the alumina layer 70 and the composite barrier layer in this application operate relatively independently, they work synergistically. The alumina layer 70 reduces interfacial recombination, allowing more charge carriers to reach the contact area of ​​the photovoltaic cell. Simultaneously, the composite barrier layer reduces metal recombination, improving charge carrier collection efficiency, thereby jointly enhancing the conversion efficiency of the photovoltaic cell. Furthermore, the compressive stress of the alumina layer 70 can also counteract the tensile stress during the sintering of the slurry used to prepare the composite barrier layer, thus reducing the wafer breakage rate. Simultaneously, because the composite barrier layer reduces metal atom penetration, the structure of this application allows for the fabrication of thinner doped silicon layers within thin silicon wafers. The thinner doped silicon layer, through the alumina layer 70 and the tunneling oxide layer 60, generates a high-field passivation effect, offsetting the potential increase in contact resistance caused by the thinner layer. In other words, although the composite barrier layer and the alumina layer 70 optimize contact and passivation respectively, they achieve a synergistic effect in both structure and function, collectively improving the electrical performance of the photovoltaic cell.

[0068] In some embodiments, the thickness of the tunneling oxide layer 60 is 1 nm to 2 nm.

[0069] Optionally, the thickness of the tunneling oxide layer 60 is 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm or 2 nm, or the thickness of the tunneling oxide layer 60 may be within any two of the above thicknesses.

[0070] In some embodiments, the material of the tunneling oxide layer 60 includes SiO2.

[0071] In some embodiments, the photovoltaic cell further includes a first passivation layer 30 disposed on the surface of the first doped silicon layer 21 away from the silicon substrate 10, and the first metal electrode 50 and the first doped silicon layer 21 are electrically connected.

[0072] In some embodiments, the material of the first passivation layer 30 includes at least one of aluminum oxide, silicon nitride, and silicon oxynitride.

[0073] In some embodiments, the photovoltaic cell further includes a second passivation layer 80 disposed on the surface of the second doped silicon layer 22 away from the silicon substrate 10, and the second metal electrode 90 is electrically connected to the second doped silicon layer 22.

[0074] In some embodiments, the material of the second passivation layer 80 includes at least one of aluminum oxide, silicon nitride, and silicon oxynitride.

[0075] In some embodiments, the thickness of the silicon substrate 10 is 100µm to 150µm.

[0076] It is understandable that the probability of fragmentation is higher when using a thin silicon substrate 10 during fabrication. The solar cell structure and fabrication method of this application can be applied to thinner silicon substrates 10, reducing the probability of fragmentation during photovoltaic cell fabrication. It is understood that N-type silicon wafers can be used as the silicon substrate 10, with doping elements including at least one of P, As, Sb, and Bi. P-type silicon wafers can also be used as the silicon substrate 10, with doping elements including at least one of B, Al, Ga, and In.

[0077] Another embodiment of this application provides a method for preparing a photovoltaic cell, wherein the photovoltaic cell is any one of the photovoltaic cells described above, comprising the following steps:

[0078] Provide silicon substrate 10;

[0079] A doped silicon layer is prepared on at least one of the first surface and the second surface;

[0080] An electrode paste is coated on the surface of a doped silicon layer located in the first region 11 and / or the third region 13. The electrode paste includes an organic carrier, glass powder, Ag particles, and TiN particles.

[0081] The electrode slurry is sintered to form a metal electrode and a composite barrier layer.

[0082] In this application, a composite barrier layer is formed in the electrode fabrication area by sintering an electrode slurry containing TiN particles, eliminating the need for additional pre-processing steps to prevent silver atom diffusion. During the sintering process, the TiN nanoparticles react with the native oxide layer on the silicon surface to generate TiO2. x When the sintering temperature is above 700℃, TiN and TiO x These can form chemically bonded heterostructures, thus creating a continuously distributed TiN / TiO₂ structure. x Composite barrier layer, which can be understood as TiN / TiO x Composite barrier layers refer to composite barrier layers made of materials including TiN and TiO. x This invention relates to a composite material formed from two materials. Simultaneously, the TiN nanoparticles form a three-dimensional penetration barrier network in the electrode slurry, which increases the tortuosity of the diffusion path of Ag atoms and causes Ag atoms to preferentially diffuse laterally along the surface of the TiN nanoparticles rather than penetrating longitudinally. In other words, the electrode fabrication method of this application can form a composite barrier layer, reducing the risk of silver atoms penetrating the doped silicon layer.

[0083] In some embodiments, TiN particles account for 3% to 8% of the electrode slurry by mass.

[0084] Optionally, the mass percentage of TiN particles in the electrode slurry is 3%, 3.5%, 4%, 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, or 8%, or the mass percentage of TiN particles in the electrode slurry can be within any two of the above-mentioned mass percentages.

[0085] In some embodiments, the organic carrier accounts for 10% to 25% of the electrode slurry by mass.

[0086] Optionally, the organic carrier accounts for 10%, 12%, 15%, 18%, 20%, 2%, or 25% of the mass of the electrode slurry, or the organic carrier accounts for a range between any two of the above mass percentages.

[0087] In some embodiments, the organic carrier includes a film-forming agent, a solvent, a plasticizer, and a surfactant.

[0088] In some embodiments, the film-forming agent includes at least one selected from ethyl cellulose, nitrocellulose, polyisocyanate, polyvinyl alcohol, polymethyl methacrylate, polymethyl methacrylate, acrylic resin, and polyvinyl butyral.

[0089] In some embodiments, the solvent includes at least one selected from terpineol, butyl carbitol acetate, ethylene glycol ethyl ether acetate, tributyl citrate, lecithin, diethylene glycol butyl ether acetate, and tributyl citrate.

[0090] In some embodiments, the plasticizer includes at least one of dibutyl phthalate, diethylene glycol dibutyl ether, and dioctyl adipate.

[0091] In some embodiments, the surfactant includes at least one selected from toluene, ethanol, cyclohexanone, dibutyl phthalate, and dioctyl adipate.

[0092] In some embodiments, the glass powder accounts for 1% to 5% of the electrode paste by mass.

[0093] Optionally, the mass percentage of glass powder in the electrode slurry is 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, or 5%, or the mass percentage of glass powder in the electrode slurry may be within the range of any two of the above mass percentages.

[0094] In some embodiments, the glass powder includes SiO2.

[0095] In some embodiments, the glass powder also includes at least one of B2O3 and P2O5.

[0096] In some embodiments, the glass powder further includes at least one of PbO, ZnO, Bi2O3, Li2O, Al2O3, ZrO2, TiO2, NaF, and CaF2.

[0097] In some embodiments, Ag particles account for 70% to 90% of the electrode slurry by mass.

[0098] Optionally, the mass percentage of Ag particles in the electrode slurry is 70%, 72%, 74%, 76%, 78%, 80%, 82%, 84%, 86%, 88%, or 90%, or the mass percentage of Ag particles in the electrode slurry may be within the range of any two of the above mass percentages.

[0099] In some embodiments, the TiN particles have a particle size of 20 nm to 50 nm.

[0100] Optionally, the particle size of TiN particles is 20nm, 22nm, 25nm, 28nm, 30nm, 32nm, 35nm, 38nm, 40nm, 42nm, 45nm, 48nm or 50nm, or the particle size of TiN particles can be within the range of any two of the above particle sizes.

[0101] In some embodiments, the maximum temperature for sintering is 700°C to 750°C.

[0102] Optionally, the maximum temperature for sintering is 700℃, 705℃, 710℃, 715℃, 720℃, 725℃, 730℃, 735℃, 740℃, 745℃ or 750℃, or the maximum temperature for sintering can be within the range of any two of the above temperatures.

[0103] In some embodiments, the method for preparing the alumina layer 70 includes the following steps:

[0104] Alumina atomic layers are prepared layer by layer on the surface of tunneling oxide layer 60 using aluminum precursor and oxygen precursor, with the number of alumina atomic layers ranging from 2 to 5.

[0105] Optionally, the number of aluminum oxide atomic layers is 2, 3, 4 or 5.

[0106] In some of these embodiments, the atomic layer deposition temperature is 190°C to 210°C.

[0107] Optionally, the atomic layer deposition temperature is 190°C, 192°C, 194°C, 196°C, 198°C, 200°C, 202°C, 204°C, 206°C, 208°C, or 210°C, or the atomic layer deposition temperature may be within any two of the above temperatures.

[0108] In some of these embodiments, the oxygen precursor includes trimethylaluminum.

[0109] In some of these embodiments, the oxygen precursor includes water.

[0110] In some embodiments, the pulse ratio of the aluminum precursor to the oxygen precursor is 1:1.

[0111] In some implementations, the following steps are also included:

[0112] A second doped silicon layer 22 is prepared on the second surface of the silicon substrate 10 by boron diffusion using a boron source;

[0113] Boron diffusion involves sequential preheating, diffusion, and relaxation treatments.

[0114] The temperature of the diffusion treatment is higher than that of the preheating treatment, and the temperature of the relaxation treatment is between that of the diffusion treatment and the preheating treatment.

[0115] The segmented boron diffusion method of this application can achieve high boron diffusion uniformity and reduce the sheet resistance of the boron-doped silicon layer on the back side of the silicon substrate 10. It should be noted that there is a correlation between the segmented boron diffusion method and the interface stability of the alumina layer 70. During the preheating process, the interfacial thermal stress between the tunneling oxide layer 60 and the alumina layer 70 can be reduced, lowering its mismatch rate. Simultaneously, it can also prevent the alumina layer 70 from crystallizing at the initial high temperature stage during direct diffusion. The relaxation treatment can also repair silicon lattice damage caused by boron diffusion and reduce the density of dangling bonds at the alumina layer 70 / silicon interface. Furthermore, the above-mentioned boron diffusion process can achieve a relatively smooth doping effect, thereby optimizing the contact band structure of the composite barrier layer obtained by subsequent slurry sintering. In other words, the boron diffusion method of this application can serve as a hub connecting the alumina layer 70 interface passivation and electrode structure optimization, simultaneously achieving interface defect repair and metal contact optimization through temperature timing control. These three aspects synergistically improve the conversion efficiency of photovoltaic cells.

[0116] In some embodiments, the relaxation treatment is held at a temperature 3.8 to 4 times that of atomic layer deposition.

[0117] Within the range where the holding temperature for the relaxation treatment is a multiple of the atomic layer deposition temperature, the relaxation treatment is effective in reducing the density of dangling bonds at the alumina layer 70 / silicon interface. Optionally, the holding temperature for the relaxation treatment can be 3.8 times, 3.82 times, 3.84 times, 3.86 times, 3.88 times, 3.9 times, 3.92 times, 3.94 times, 3.96 times, 3.98 times, or 4 times the atomic layer deposition temperature; alternatively, the holding temperature for the relaxation treatment can be a multiple of any two of the above multiples.

[0118] In some embodiments, the preheating temperature is 600℃~700℃, the holding time is 3min~7min, and the volume concentration of the boron source is 0.08%~0.12%.

[0119] Optionally, the heat preservation temperature for preheating is 600℃, 620℃, 640℃, 660℃, 680℃ or 700℃, or the heat preservation temperature for preheating can be within the range of any two of the above heat preservation temperatures.

[0120] Optionally, the heat preservation time for preheating is 3 min, 3.5 min, 4 min, 4.5 min, 5 min, 5.5 min, 6 min, 6.5 min, or 7 min, or the heat preservation time for preheating can be within the range of any two of the above heat preservation times.

[0121] Optionally, the volume concentration of the boron source in the preheating treatment is 0.08%, 0.085%, 0.09%, 0.095%, 0.1%, 0.105%, 0.11%, 0.115%, or 0.12%, or the volume concentration of the boron source in the preheating treatment may be within the range of any two of the above volume concentrations.

[0122] In some embodiments, the diffusion treatment is held at a temperature of 820°C to 900°C for 12 min to 18 min, and the volume concentration of the boron source is 0.3% to 0.8%.

[0123] Optionally, the insulation temperature for the diffusion treatment is 820℃, 840℃, 860℃, 880℃ or 900℃, or the insulation temperature for the diffusion treatment can be within the range of any two of the above insulation temperatures.

[0124] Optionally, the holding time for diffusion treatment is 12 min, 13 min, 14 min, 15 min, 16 min, 17 min or 18 min, or the holding time for diffusion treatment can be within the range of any two of the above holding times.

[0125] Optionally, the volume concentration of the boron source in the diffusion treatment is 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, or 0.8%, or the volume concentration of the boron source in the diffusion treatment can be within the range of any two of the above volume concentrations.

[0126] In some embodiments, the relaxation treatment is held at a temperature of 760°C to 800°C for 6 min to 10 min, and the volume concentration of the boron source is 0.03% to 0.08%.

[0127] Optionally, the relaxation treatment insulation temperature is 760℃, 765℃, 770℃, 775℃, 780℃, 785℃, 790℃, 795℃ or 800℃, or the relaxation treatment insulation temperature can be within the range of any two of the above insulation temperatures.

[0128] Optionally, the holding time for relaxation treatment is 6 min, 7 min, 8 min, 9 min or 10 min, or the holding time for relaxation treatment can be within the range of any two of the above holding times.

[0129] Optionally, the volume concentration of the boron source undergoing relaxation treatment is 0.03%, 0.04%, 0.05%, 0.06%, 0.07%, or 0.08%, or the volume concentration of the boron source undergoing relaxation treatment may be within the range of any two of the above volume concentrations.

[0130] In some embodiments, the method for preparing a photovoltaic cell includes the following steps:

[0131] S10: Provide a silicon substrate 10; sequentially prepare a tunneling oxide layer 60, an aluminum oxide layer 70 and a second doped silicon layer 22 on the second surface;

[0132] Reference Figure 2 As shown, Figure 2 This is a schematic diagram of a structure in which a tunneling oxide layer, an aluminum oxide layer, and a second doped silicon layer are sequentially stacked on the second surface of a silicon substrate.

[0133] S20: A first doped silicon layer 21 is prepared on the first surface;

[0134] Reference Figure 3 As shown, Figure 3 In order to be in Figure 2 A schematic diagram of the structure for fabricating the first doped silicon layer based on the structure shown.

[0135] S30: A first passivation layer 30 is formed on the first doped silicon layer 21, and a second passivation layer 80 is formed on the second doped silicon layer 22;

[0136] Reference Figure 4 As shown,Figure 4 In order to be in Figure 3 The diagram shows a structure for fabricating the first passivation layer and the second passivation layer based on the structure shown.

[0137] S40: The electrode paste is coated onto the first passivation layer 30 located in the first region 11, and the electrode paste is sintered to form the first metal electrode 50 and the first composite barrier layer 41.

[0138] Reference Figure 5 As shown, Figure 5 In order to be in Figure 4 A schematic diagram of the structure for fabricating the first metal electrode 50 and the first composite barrier layer 41 based on the structure shown.

[0139] S50 coats the electrode paste onto the second passivation layer 80 located in the third region 13, and performs sintering treatment on the electrode paste to form the second metal electrode 90 and the second composite barrier layer 42.

[0140] Refer again Figure 1 As shown, Figure 1 In order to be in Figure 5 A schematic diagram of the structure for fabricating the second metal electrode 90 and the second composite barrier layer 42 based on the structure shown.

[0141] In some embodiments, the first doped silicon layer 21 is a P-type doped silicon layer.

[0142] In some embodiments, the material of the P-type doped silicon layer includes at least one of P-type doped amorphous silicon and P-type doped polycrystalline silicon.

[0143] In some embodiments, the doping element of the P-type doped silicon layer includes at least one of B, Al, Ga, and In.

[0144] In some embodiments, the second doped silicon layer 22 is an N-type doped silicon layer.

[0145] In some embodiments, the material of the N-type doped silicon layer includes at least one of N-type doped amorphous silicon and N-type doped polycrystalline silicon.

[0146] In some embodiments, the doping element of the N-type doped silicon layer includes at least one of P, As, Sb, and Bi.

[0147] Another embodiment of this application provides a photovoltaic module, including:

[0148] Cover plate;

[0149] At least one battery string, the battery string comprising a photovoltaic cell of any one of the above, or a photovoltaic cell prepared by any one of the above methods;

[0150] And the encapsulation layer, which is located between the cover plate and the battery string, with the cover plate connected to the battery string through the encapsulation layer.

[0151] The following are specific examples:

[0152] Example 1

[0153] Methods for preparing photovoltaic cells:

[0154] (1) Provide an N-type silicon substrate 10 with a thickness of 130µm;

[0155] (2) A 1.2 nm tunneling oxide layer 60 is prepared on the second surface. Two cycles of alumina atomic layers are deposited on the tunneling oxide layer 60 by trimethylaluminum and water atomic layers to obtain an alumina layer 70 of 0.22 nm. The atomic layer deposition temperature is 200 °C. A phosphorus-doped polycrystalline silicon layer is deposited on the alumina layer 70 by LPCVD.

[0156] (3) A boron-doped silicon layer is prepared on the first surface. The preheating temperature is 650℃ and the holding time is 5min. The volume concentration of the boron source is 0.1%. The diffusion temperature is 850℃ and the holding time is 15min. The volume concentration of the boron source is 0.5%. The relaxation temperature is 780℃ and the holding time is 8min. The volume concentration of the boron source is 0.05%.

[0157] (4) A first passivation layer 30 is prepared on a boron-doped silicon layer, and a second passivation layer 80 is prepared on a phosphorus-doped silicon layer;

[0158] (5) The electrode paste is coated on the first passivation layer 30 located in the first region 11. The electrode paste contains 6% glass powder and 5% TiN nanoparticles by mass, and has a viscosity of 35 Pa·s. The electrode paste is sintered. The peak temperature of the sintering treatment is 730℃, the duration is 3s, and the cooling rate is 80℃ / s to form the first metal electrode 50 and the first composite barrier layer 41.

[0159] (6) The electrode paste is coated on the second passivation layer 80 located in the third region 13. The electrode paste contains 6% glass powder and 5% TiN nanoparticles by mass, and has a viscosity of 35 Pa·s. The electrode paste is sintered at a peak temperature of 730°C for 3s and a cooling rate of 80°C / s to form a second metal electrode 90 and a second composite barrier layer 42.

[0160] Example 2

[0161] The preparation method of the photovoltaic cell in Example 2 is basically the same as that in Example 1. The only difference is that: in step (2), the alumina layer 70 is not prepared; in step (3), the diffusion temperature of the boron-doped silicon layer is 850℃ and the holding time is 23min.

[0162] Comparative Example 1

[0163] The preparation method of the photovoltaic cell in Comparative Example 1 is basically the same as that in Example 1, except that: in step (2), the alumina layer 70 is not prepared; in step (3), the diffusion temperature of the boron-doped silicon layer is 850℃ and the holding time is 23min; in steps (5) and (6), the electrode paste does not contain TiN nanoparticles.

[0164] Comparative Example 2

[0165] The preparation method of the photovoltaic cell in Comparative Example 2 is basically the same as that in Example 1, except that the electrode slurry does not contain TiN nanoparticles in steps (5) and (6).

[0166] The photovoltaic cells prepared in Example 1 and Comparative Example 1 were tested, and the test results are shown in Table 1 below. It can be understood that the test results below are the average values ​​of 200 samples.

[0167] Table 1

[0168]

[0169] The test results show that the photovoltaic cells prepared in Examples 1 and 2 of this application have a composite barrier layer between the metal electrode and the doped silicon layer in the area where the metal electrode is located. The material of the composite barrier layer includes TiO2. x TiN can control the diffusion depth of metal atoms during the metal electrode fabrication process. Compared with Comparative Example 1 and Comparative Example 2, it can reduce the risk of metal atoms penetrating the doped silicon layer and reduce leakage current.

[0170] Furthermore, in Comparative Example 2, the electrode slurry does not contain TiN nanoparticles, which significantly improves the open-circuit voltage, but the metal contact problem still exists, resulting in a large contact resistance and leakage current. In Example 2, compared to Comparative Example 1, only the electrode slurry was improved, which effectively suppressed Ag penetration and improved the contact effect, but failed to improve bulk passivation and interface passivation, resulting in limited improvement in Voc.

[0171] Comparing the test data of Example 1 with those of Example 2, Comparative Example 1, and Comparative Example 2, it can be seen that the photovoltaic cell in Example 1 exhibits comprehensively improved performance compared to the photovoltaic cells in Example 2, Comparative Example 1, and Comparative Example 2, including lower contact resistance, lower leakage current, and higher Voc and average conversion efficiency. This demonstrates a synergistic effect between the different improvements in this application. Furthermore, through the synergistic effect of these improvements, Example 1 also achieves a significantly reduced sheet breakage rate compared to Example 2, Comparative Example 1, and Comparative Example 2.

[0172] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0173] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims, and the specification and drawings can be used to interpret the content of the claims.

Claims

1. A photovoltaic cell, characterized in that, The system comprises a silicon substrate, a doped silicon layer, a composite barrier layer, and a metal electrode. The silicon substrate has a first surface and a second surface disposed opposite to each other. The first surface includes a first region and a second region, and the second surface includes a third region and a fourth region. The doped silicon layer is disposed on at least one of the first surface and the second surface. The composite barrier layer and the metal electrode are disposed on the surface of the doped silicon layer located in the first region and / or the third region, away from the silicon substrate. The metal electrode and the doped silicon layer are electrically connected. The composite barrier layer is disposed between the metal electrode and the doped silicon layer, and the material of the composite barrier layer includes TiO₂. x In the composite barrier layer, the atomic ratio of N to O elements is (3~7):7; The doped silicon layer includes a first doped silicon layer located on the first surface and a second doped silicon layer located on the second surface, wherein the doping types of the first doped silicon layer and the second doped silicon layer are opposite; the composite barrier layer includes a first composite barrier layer and a second composite barrier layer; the metal electrode includes a first metal electrode and a second metal electrode. The first composite barrier layer and the first metal electrode are sequentially stacked on the surface of the first doped silicon layer in the first region away from the silicon substrate; the second composite barrier layer and the second metal electrode are sequentially stacked on the surface of the second doped silicon layer in the third region away from the silicon substrate.

2. The photovoltaic cell according to claim 1, characterized in that, The thickness of the composite barrier layer is 5nm~8nm.

3. The photovoltaic cell according to claim 1, characterized in that, The thickness of the doped silicon layer is 70nm~90nm.

4. The photovoltaic cell according to claim 1, characterized in that, The depth of the composite barrier layer into the doped silicon layer is 15% to 20% of the thickness of the doped silicon layer.

5. The photovoltaic cell according to claim 1, characterized in that, The composite barrier layer penetrates the doped silicon layer to a depth of 12nm~18nm.

6. The photovoltaic cell according to claim 1, characterized in that, The photovoltaic cell further includes a tunneling oxide layer and an aluminum oxide layer; the tunneling oxide layer is located between the silicon substrate and the second doped silicon layer; the aluminum oxide layer is located between the tunneling oxide layer and the second doped silicon layer.

7. The photovoltaic cell according to claim 6, characterized in that, The thickness of the alumina layer is 0.2 nm to 0.5 nm.

8. A method for preparing a photovoltaic cell, wherein the photovoltaic cell is the photovoltaic cell according to any one of claims 1 to 7, characterized in that, Includes the following steps: Provide the silicon substrate; A doped silicon layer is prepared on at least one of the first surface and the second surface; An electrode paste is coated onto the surface of the doped silicon layer located in the first region and / or the third region. The electrode paste includes an organic carrier, glass powder, Ag particles, and TiN particles. The electrode slurry is sintered to form the metal electrode and the composite barrier layer.

9. The method for preparing a photovoltaic cell according to claim 8, characterized in that, The TiN particles constitute 3% to 8% of the electrode slurry by mass; and / or, The TiN particles have a particle size of 20 nm to 50 nm.

10. The method for preparing a photovoltaic cell according to claim 8, characterized in that, The maximum temperature for the sintering process is 700℃~750℃.

11. The method for preparing a photovoltaic cell according to claim 8, characterized in that, The doped silicon layer includes a first doped silicon layer located on the first surface and a second doped silicon layer located on the second surface, wherein the doping types of the first doped silicon layer and the second doped silicon layer are opposite; the composite barrier layer includes a first composite barrier layer and a second composite barrier layer; the metal electrode includes a first metal electrode and a second metal electrode. The first composite barrier layer and the first metal electrode are sequentially stacked on the surface of the first doped silicon layer in the first region away from the silicon substrate; the second composite barrier layer and the second metal electrode are sequentially stacked on the surface of the second doped silicon layer in the third region away from the silicon substrate. The photovoltaic cell further includes a tunneling oxide layer and an aluminum oxide layer; the tunneling oxide layer is located between the silicon substrate and the second doped silicon layer; the aluminum oxide layer is located between the tunneling oxide layer and the second doped silicon layer; The method for preparing the alumina layer includes the following steps: Alumina atomic layers are prepared layer by layer on the surface of the tunneling oxide layer using aluminum and oxygen precursors by atomic layer deposition, wherein the number of alumina atomic layers is 2 to 5.

12. The method for preparing a photovoltaic cell according to claim 11, characterized in that, It also includes the following steps: A second doped silicon layer is prepared on the second surface of the silicon substrate by boron diffusion using a boron source; The boron diffusion process includes a preheating treatment, a diffusion treatment, and a relaxation treatment performed sequentially. The temperature of the diffusion treatment is higher than the temperature of the preheating treatment, and the temperature of the relaxation treatment is between the temperature of the diffusion treatment and the temperature of the preheating treatment.

13. A photovoltaic module, characterized in that, include: Cover plate; At least one battery string, the battery string comprising a photovoltaic cell according to any one of claims 1 to 7, or a photovoltaic cell prepared by the method of preparing a photovoltaic cell according to any one of claims 8 to 12; And an encapsulation layer, which is located between the cover plate and the battery string, and the cover plate is connected to the battery string through the encapsulation layer.

Images