Display panel and display terminal

Abstract

The invention relates to a display panel and a display terminal, the display panel comprises a display area and a frame area arranged on one side of the display area, and the display panel comprises a substrate, a cathode layer, a first metal layer and a second metal layer; the cathode layer is arranged on one side of the substrate and comprises a cathode part located in the display area and a lap joint part located in the frame area; the first metal layer is arranged between the cathode layer and the substrate, and the first metal layer comprises a circuit wiring part located in the frame area; the second metal layer is arranged between the first metal layer and the cathode layer, and the second metal layer comprises a second connecting part located in the frame area; wherein the second connecting part is electrically connected with the lap joint part, and the second connecting part and the circuit wiring part are overlapped in the thickness direction of the display panel. According to the display panel provided by the embodiment of the invention, the second connecting part and the circuit wiring part are overlapped in the thickness direction of the display panel, so that the width of the second connecting part is increased, the impedance of the lap joint part is reduced, and the IR voltage drop of the cathode part is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display terminal. BACKGROUND

[0002] With the development of display technology, the demand for narrow frame display products in the market is increasing. The narrow frame display product has a small frame width, a high screen ratio, and a better appearance.

[0003] However, the frame width is small, which compresses the wiring space at the frame, causing problems in the reliability of the circuit at the frame. For example, the cathode voltage of the display panel is transferred through the multi-layer wiring at the frame. When the frame width is small, the overlap area between the two adjacent layers of wiring is reduced, resulting in a large difference in IR drop of the cathode. The display panel is prone to uneven brightness when displaying. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display terminal, which improve the technical problem that the difference in IR drop of the cathode is large when the frame width is small, and the display panel is prone to uneven brightness when displaying.

[0005] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a display panel is provided, comprising a display area and a frame area arranged on one side of the display area, the display panel comprising:

[0006] a substrate;

[0007] a cathode layer arranged on one side of the substrate, the cathode layer comprising a cathode part located in the display area and an overlap part located in the frame area;

[0008] a first metal layer arranged between the cathode layer and the substrate, the first metal layer comprising a circuit wiring part located in the frame area;

[0009] a second metal layer arranged between the first metal layer and the cathode layer, the second metal layer comprising a second connecting part located in the frame area;

[0010] wherein the second connecting part and the overlap part are electrically connected, and the second connecting part and the circuit wiring part overlap in the thickness direction of the display panel.

[0011] Optionally, the display panel comprises an anode layer arranged between the second metal layer and the cathode layer, the anode layer comprising an anode part located in the display area and a third connecting part located in the frame area;

[0012] The second connecting portion and the overlapping portion are both electrically connected with the third connecting portion, and the third connecting portion overlaps the circuit trace portion in a thickness direction of the display panel.

[0013] Optionally, the display panel comprises a first planar layer disposed between the second metal layer and the anode layer, and the third connecting portion is provided with a plurality of first openings to expose the first planar layer; and / or,

[0014] The display panel comprises a second planar layer disposed between the first metal layer and the second metal layer, and the second connecting portion is provided with a plurality of second openings to expose the second planar layer.

[0015] Optionally, the circuit trace portion comprises a plurality of timing control signal lines, and at least one of the first openings and the second openings exposes the timing control signal lines.

[0016] Optionally, the timing control signal lines comprise clock signal lines and start pulse signal lines.

[0017] Optionally, the clock signal lines comprise a plurality of clock signal sub-lines, each clock signal sub-line has a same overlapping area with the second connecting portion; and / or, each clock signal sub-line has a same overlapping area with the third connecting portion.

[0018] Optionally, the first openings and the second openings are staggered in a thickness direction of the display panel, or the first openings and the second openings overlap in the thickness direction of the display panel.

[0019] Optionally, the plurality of first openings are aligned or staggered in an extension direction of the timing control signal lines; and / or, the plurality of second openings are aligned or staggered in the extension direction of the timing control signal lines.

[0020] Optionally, the plurality of first openings are aligned or staggered in an arrangement direction of the plurality of timing control signal lines; and / or, the plurality of second openings are aligned or staggered in the arrangement direction of the plurality of timing control signal lines.

[0021] Optionally, at least one of the first openings and the second openings exposes one of the timing control signal lines, or at least one of the first openings and the second openings exposes a plurality of the timing control signal lines.

[0022] Optionally, each of the first openings has a same shape, and / or each of the second openings has a same shape.

[0023] Optionally, the first metal layer further comprises a first connecting portion, the first connecting portion is located on a side of the circuit trace portion away from the display area, and the first connecting portion is electrically connected with the second connecting portion.

[0024] According to a second aspect of the present application, a display terminal is provided, comprising the display panel described above.

[0025] In the display panel of the embodiments of the present application, the second connecting portion and the circuit trace portion are overlapped in the thickness direction of the display panel, so as to widen the width of the second connecting portion, reduce the impedance of the lap joint portion, and reduce the IR drop of the cathode portion.

[0026] Other features and advantages of the present application will be described in detail in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0028] In order to more completely understand the present application and its advantages, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0029] Figure 1 is a top view structural schematic diagram of a display panel provided in an exemplary embodiment of the present disclosure;

[0030] Figure 2 is Figure 1 is a sectional structural schematic diagram at C-C in

[0031] Figure 3 is a simulation diagram of the IR drop of the cathode portion of a comparative example and an embodiment of the present disclosure;

[0032] Figure 4A is a sectional structural schematic diagram of a second connecting portion with a bulge defect;

[0033] Figure 4B is a sectional structural schematic diagram of a second connecting portion without a bulge defect;

[0034] Figure 5A and Figure 5B is an enlarged schematic diagram of a local structure of a frame area;

[0035] Figure 6A and Figure 6B is an enlarged schematic diagram of another local structure of a frame area;

[0036] Figure 7 A waveform comparison diagram of a timing control signal line of a display panel provided in an exemplary embodiment of the present disclosure;

[0037] Figure 8A A current density distribution comparison diagram of a second connection part and a third connection part of a display panel provided in an exemplary embodiment of the present disclosure;

[0038] Figure 8B A current density distribution comparison diagram of a second connection part of a display panel provided in an exemplary embodiment of the present disclosure;

[0039] Figures 9A to 9E An enlarged structure schematic diagram of a second connection part provided in an exemplary embodiment of the present disclosure;

[0040] Figure 10 A structure schematic diagram of a display terminal provided in an exemplary embodiment of the present disclosure.

[0041] Explanation of reference signs:

[0042] 1 - display panel; AA - display area; NA - frame area; 11 - sub-pixel;

[0043] 10 - substrate;

[0044] 20 - first metal layer; 21 - first connection part; 22 - circuit trace part; 221 - timing control signal line; 2211 - clock signal sub-line;

[0045] 30 - second metal layer; 31 - second connection part; 31a - second opening; 31b - bulge;

[0046] 40 - anode layer; 41 - anode part; 42 - third connection part; 42a - first opening;

[0047] 50 - cathode layer; 51 - cathode part; 52 - lap joint part;

[0048] 61 - first planar layer; 62 - second planar layer; 63 - light emitting material layer; 64 - encapsulation layer;

[0049] 70 - thin film transistor; 71 - first gate; 72 - second gate; 73 - first source; 74 - first drain; 75 - second source; 76 - second drain; 77 - active part;

[0050] D1 - first direction; D2 - second direction;

[0051] 2 - display terminal; 3 - terminal main body. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0053] According to a first aspect of the present application, as shown in Figure 1 and Figure 2 , a display panel 1 is provided, comprising a display area AA and a frame area NA arranged on one side of the display area AA, the display panel 1 comprising a substrate 10, a cathode layer 50, a first metal layer 20 and a second metal layer 30; the cathode layer 50 is arranged on one side of the substrate 10, the cathode layer 50 comprising a cathode part 51 located in the display area AA and an overlapping part 52 located in the frame area NA; the first metal layer 20 is arranged between the cathode layer 50 and the substrate 10, the first metal layer 20 comprising a circuit trace part 22 located in the frame area NA; the second metal layer 30 is arranged between the first metal layer 20 and the cathode layer 50, the second metal layer 30 comprising a second connecting part 31 located in the frame area NA; wherein the second connecting part 31 and the overlapping part 52 are electrically connected, and the second connecting part 31 and the circuit trace part 22 overlap in the thickness direction of the display panel 1.

[0054] The display panel 1 can be an LCD panel, an OLED panel, a Mini-LED panel, a Micro-LED panel, etc.

[0055] As shown in Figure 1 , the display panel 1 comprises a display area AA and a frame area NA arranged on one side of the display area AA. The display area AA can be provided with a plurality of sub-pixels 11, and the sub-pixels 11 can include red sub-pixels, green sub-pixels and blue sub-pixels, so as to realize color display. The frame area NA can be provided with a gate drive circuit, etc., which can provide a driving signal for the sub-pixels 11.

[0056] In some embodiments, the substrate 10 can be a rigid material or a flexible material. The rigid material can be glass, quartz or a silicon wafer. The flexible material can adopt one of polyimide (PI), polycarbonate (PC), poly (norbornene) (PNB) and polyethylene terephthalate (PET), etc.

[0057] As shown in Figure 2 , the cathode layer 50 comprises a cathode part 51 located in the display area AA and an overlapping part 52 located in the frame area NA. The cathode part 51 is used to provide a cathode voltage (VSS) for the sub-pixels 11 of the display area AA, and the overlapping part 52 is used to input the cathode voltage (VSS) of the frame area NA to the cathode part 51.

[0058] In some embodiments, the cathode layer 50 may be a single, continuous layer. That is, the overlap portion 52 and the cathode portion 51 are continuously disposed. It should be noted that the cathode layer 50 may be a continuous film layer that is not patterned or a patterned film layer.

[0059] In some embodiments, the cathode layer 50 may be an alloy of one or more of the following: silver, aluminum, magnesium, etc.

[0060] In some embodiments, the materials of the first metal layer 20 and the second metal layer 30 may be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0061] like Figure 2 As shown, the first metal layer 20 includes a circuit trace portion 22 located in the border region NA. The circuit trace portion 22 can be a portion of the trace in the gate drive circuit. That is to say, a part of the structure in the gate drive circuit is located in the first metal layer 20, and another part of the structure can be located on other metal layers or semiconductor layers between the first metal layer 20 and the substrate 10.

[0062] The second metal layer 30 includes a second connection portion 31 located in the border region NA. The second connection portion 31 is electrically connected to the overlap portion 52, and the second connection portion 31 transmits the cathode voltage (VSS) of the cathode to the overlap portion 52. That is to say, the second connection portion 31 and the overlap portion 52 are connected in parallel. By connecting the second connection portion 31 and the overlap portion 52 in parallel, the impedance of the overlap portion 52 can be reduced.

[0063] The second connecting portion 31 overlaps with the circuit trace portion 22 in the thickness direction of the display panel 1. This means that the second connecting portion 31 and the circuit trace portion 22 are disposed on different layers, and the orthographic projection of the second connecting portion 31 on the substrate 10 overlaps with the orthographic projection of the circuit trace portion 22 on the substrate 10. With this arrangement, the second connecting portion 31 can be extended towards the display area AA, thereby widening the width of the second connecting portion 31, reducing the impedance of the overlap portion 52, and reducing the IR voltage drop of the cathode portion 51.

[0064] Figure 3A simulation diagram of IR drop of a cathode portion 51 of an embodiment of the present disclosure and a comparative example, where (a) is a simulation result of IR drop of the cathode portion 51 when the second connecting portion 31 is not extended above the circuit trace portion 22, the cathode voltage (VSS) in (a) ranges from -6.0 V (volt) to -4.56 V (volt), and the IR drop is 1.44 V (volt). (b) is a simulation result of IR drop of the cathode portion 51 when the second connecting portion 31 is extended above the circuit trace portion 22, the cathode voltage (VSS) in (b) ranges from -6.0 V (volt) to -4.61 V (volt), and the IR drop is 1.39 V (volt). It can be concluded that the IR drop of (b) is 0.05 V (volt) less than that of (a), and the IR drop of the cathode portion 51 can be reduced to some extent. Since the luminance of the sub-pixel 11 is affected by the voltage of the cathode portion 51, when the IR drop of the cathode portion 51 is reduced, the problem of luminance unevenness of the sub-pixel 11 in the display area AA can be improved.

[0065] In the related art, the overlap size of the second connecting portion 31 and the lap portion 52 in the width direction of the frame is greater than 400 um. The overlap size refers to the contact size of the second connecting portion 31 and the lap portion 52 in the width direction of the frame. However, as the display panel 1 develops towards a narrow frame, the frame width is not sufficient to ensure the overlap size of the second connecting portion 31 and the lap portion 52. In the embodiments of the present application, by extending the second connecting portion 31 above the circuit trace portion 22, the impedance of the lap portion 52 can be reduced without increasing the frame width, thereby reducing the IR drop of the cathode portion 51 and improving luminance unevenness.

[0066] In some embodiments, the second connecting portion 31 overlaps the circuit trace portion 22 in the thickness direction of the display panel 1, and the overlapping width is set according to the frame width. The overlapping width refers to the size in the first direction D1 in Figure 1

[0067] In some embodiments, the display panel 1 further includes an encapsulation layer 64 disposed on the side of the cathode layer 50 away from the substrate 10. The encapsulation layer 64 is used to realize encapsulation of the display panel 1. The encapsulation layer 64 can be a thin film encapsulation. The encapsulation layer 64 can be formed by alternately stacking one or more organic layers and one or more inorganic layers. For example, the organic layer can be a single layer or multiple layers formed of any one of polyethylene terephthalate, polyimide, polycarbonate, epoxy resin, polyethylene, and polyacrylate. The inorganic layer can be a single layer or multiple layers of metal oxide or metal nitride, for example, silicon nitride, aluminum oxide, silicon oxide, etc.

[0068] Optionally, as Figure 2 ​As shown, the display panel 1 includes an anode layer 40, which is disposed between the second metal layer 30 and the cathode layer 50. The anode layer 40 includes an anode portion 41 located in the display area AA and a third connecting portion 42 located in the bezel area NA. The second connecting portion 31 and the overlapping portion 52 are both electrically connected to the third connecting portion 42, and the third connecting portion 42 overlaps with the circuit trace portion 22 in the thickness direction of the display panel 1.

[0069] The anode layer 40 can be made of metal or metal oxide materials, such as one or more of indium tin oxide, indium zinc oxide, silver, etc.

[0070] The anode portion 41 is used to provide an anode voltage (VDD) to the sub-pixel 11. The sub-pixel 11 emits light under the drive of the voltage provided by the anode portion 41 and the cathode portion 51.

[0071] like Figure 2 As shown, when the display panel 1 is an OLED panel, a light-emitting material layer 63 is also provided between the anode portion 41 and the cathode portion 51 within the display area AA. Holes are injected into the anode portion 41, and electrons are injected into the cathode portion 51. The holes and electrons recombine in the light-emitting material layer 63 to emit light, thereby realizing the display function.

[0072] In some embodiments, such as Figure 2 As shown, the display area AA is also provided with a thin-film transistor 70, which is used to control the light emission of the sub-pixel 11. The thin-film transistor 70 can be a dual-gate transistor, and the thin-film transistor 70 includes a first gate 71 and a second gate 72.

[0073] In some embodiments, such as Figure 2 As shown, the thin-film transistor 70 may include two source-drain layers, namely, the thin-film transistor 70 includes a first source 73, a first drain 74, a second source 75, and a second drain 76. The first source 73 and the first drain 74 are disposed on the same layer, and the second source 75 and the second drain 76 are disposed on the same layer, but the first source 73 and the second source 75 are disposed on different layers. The second drain 76 of the thin-film transistor 70 can be electrically connected to the anode portion 41, thereby inputting an anode voltage (VDD) to the anode portion 41. The thin-film transistor 70 also includes an active portion 77, with the first source 73 electrically connected to one end of the active portion 77, and the first drain 74 electrically connected to the other end of the active portion 77.

[0074] In some embodiments, such as Figure 2 As shown, the first source 73 and the first drain 74 can be located on the first metal layer 20, that is, the circuit trace 22, the first source 73, and the first drain 74 are disposed on the same layer. The second source 75 and the second drain 76 can be located on the second metal layer 30, that is, the second connection portion 31, the second source 75, and the second drain 76 are disposed on the same layer. With the above arrangement, the manufacturing process of the display panel 1 can be simplified.

[0075] like Figure 2 As shown, the third connecting portion 42 is located in the frame area NA, and both the second connecting portion 31 and the overlapping portion 52 are electrically connected to the third connecting portion 42. Specifically, the third connecting portion 42 can be electrically connected to the second connecting portion 31 through a via, and the overlapping portion 52 can be connected to the third connecting portion 42 through a via. By connecting the second connecting portion 31 and the overlapping portion 52 in parallel with the third connecting portion 42, the impedance of the overlapping portion 52 is reduced, thereby reducing the IR voltage drop of the cathode portion 51.

[0076] It should be noted that the size of the via can be set as needed. To increase the contact area between the third connecting part 42 and the second connecting part 31, the via can be a rectangular cutout area, exposing the second connecting part 31, with the third connecting part 42 deposited inside the via and in contact with the second connecting part 31. Similarly, to increase the contact area between the overlapping part 52 and the third connecting part 42, the via can be a rectangular cutout area, exposing the third connecting part 42, with the overlapping part 52 deposited inside the via and in contact with the third connecting part 42.

[0077] like Figure 2 As shown, in order to reduce the width of the border area NA, the patterns of the vias connecting the third connecting portion 42 and the second connecting portion 31, and the patterns of the vias connecting the overlapping portion 52 and the third connecting portion 42 are projected onto the substrate 10 in an orthogonal projection.

[0078] In some embodiments, such as Figure 2 As shown, the third connecting portion 42 overlaps with the circuit trace portion 22 in the thickness direction of the display panel 1. With the above arrangement, the third connecting portion 42 can be extended above the circuit trace portion 22, thereby increasing the width of the third connecting portion 42, further reducing the impedance of the overlapping portion 52, and reducing the IR voltage drop of the cathode portion 51.

[0079] Optionally, such as Figure 2 As shown, the display panel 1 includes a first planarization layer 61 disposed between the second metal layer 30 and the anode layer 40, and the third connecting portion 42 is provided with a plurality of first openings 42a to expose the first planarization layer 61; and / or, the display panel 1 includes a second planarization layer 62 disposed between the first metal layer 20 and the second metal layer 30, and the second connecting portion 31 is provided with a plurality of second openings 31a to expose the second planarization layer 62.

[0080] The first planarization layer 61 and the second planarization layer 62 can be made of organic materials, such as those selected from acrylic resins, epoxy resins, and perfluoroalkoxy resins (PFA). Organic materials have leveling properties and can provide a relatively smooth surface.

[0081] like Figure 2As shown, the anode portion 41 is disposed on the surface of the first planarization layer 61, which provides a relatively flat surface for the anode portion 41. When the anode portion 41 is not flat, it will affect the brightness uniformity of the sub-pixel 11. That is, by disposing the anode portion 41 on the first planarization layer 61, the brightness uniformity of the sub-pixel 11 can be improved.

[0082] like Figure 4A As shown, the second planarization layer 62 can be formed by coating an organic material onto the substrate 10 and then baking and curing it. During the baking process, gases from the organic material may escape. When these escaped gases are blocked by the metal layer, the second connection portion 31 may be pushed up, forming a bulge 31b. Figure 4B As shown, in order to avoid the bulge 31b defect, a second opening 31a is provided on the second connection part 31 to expose the second planarization layer 62. Gas overflowing from the second planarization layer 62 during the baking and curing process can be discharged from the second opening 31a.

[0083] A first planarization layer 61 is provided between the second metal layer 30 and the anode layer 40, and a second planarization layer 62 can further improve the flatness of the film layer below the anode portion 41. Similarly, in order to prevent the gas overflowing from the first planarization layer 61 during the baking and curing process from causing bulge 31b defects, a plurality of first openings 42a can be provided in the third connecting portion 42, through which the gas overflowing from the first planarization layer 61 during the baking and curing process can be discharged.

[0084] In some embodiments, the display panel 1 may include a first planarization layer 61 and a second planarization layer 62. By providing two planarization layers, the flatness of the film layer below the anode portion 41 can be further improved, thereby enhancing the uniformity of the brightness of the sub-pixels 11.

[0085] In some other embodiments, the display panel 1 may include a first planarization layer 61 but not a second planarization layer 62.

[0086] In other embodiments, the display panel 1 may include a second planarization layer 62 but not the first planarization layer 61.

[0087] Optionally, such as Figure 5A and Figure 5B As shown, the circuit trace portion 22 includes a plurality of timing control signal lines 221, and at least one of the first aperture 42a and the second aperture 31a exposes the timing control signal lines 221.

[0088] like Figure 2 and Figure 5AAs shown, the circuit trace portion 22 includes a plurality of timing control signal lines 221, which are part of the gate driving circuit and can be used to provide pulse signals and the like to the gate driving circuit. The pulse signals can be acyclic or periodic signals, whose voltage suddenly changes (rises or falls) in a short time and then quickly returns to the initial level, forming a single or series of "pulses".

[0089] As shown in Figure 2 and Figure 5A When the second connecting portion 31 and / or the third connecting portion 42 extends above the circuit trace portion 22, the second connecting portion 31 overlaps the circuit trace portion 22 in the thickness direction of the display panel 1. Since the second connecting portion 31 and the circuit trace portion 22 are both conductive materials, they are separated by an insulating material, i.e. a coupling capacitance is formed between the second connecting portion 31 and the circuit trace portion 22.

[0090] Since the control signals of the timing control signal lines 221 include pulse signals, when the coupling capacitance between the second connecting portion 31 and the circuit trace portion 22 is too large, the rising time (Tr) and the falling time (Tf) of the pulse signals will increase, causing the pulse signals to deform, thereby affecting the function of the gate driving circuit, and causing the display panel 1 to have horizontal lines and other defects. Horizontal lines refer to strip-shaped lines appearing in the horizontal direction of the display panel 1. The brightness of the horizontal line area is different from that of the area outside the horizontal line area, and due to the uneven brightness, the horizontal lines are visually presented.

[0091] In some embodiments, as shown in Figure 5A and Figure 5B The second opening 31a of the second connecting portion 31 exposes the timing control signal lines 221. Through the above arrangement, the overlapping area of the second connecting portion 31 and the timing control signal lines 221 in the thickness direction of the display panel 1 can be reduced, thereby reducing the coupling capacitance between the second connecting portion 31 and the timing control signal lines 221 and improving the horizontal line defect.

[0092] Figure 7A waveform comparison diagram of a timing control signal line 221 of a display panel 1 provided in an exemplary embodiment of the present disclosure is shown in FIG. 6, in which the horizontal axis represents time and the vertical axis represents voltage. Waveform s1 is a pulse signal waveform of the timing control signal line 221 when the second opening 31a is not provided, and waveform s2 is a pulse signal waveform of the timing control signal line 221 after the second opening 31a is provided. As can be seen from the diagram, the waveform s2 is closer to the ideal state of a square wave, i.e., the rising edge time (Tr2) of the waveform s2 is less than the rising edge time (Tr1) of the waveform s1, and the falling edge time (Tf2) of the waveform s2 is less than the falling edge time (Tf1) of the waveform s1. Therefore, by providing the second opening 31a, the influence of the coupling capacitance between the second connection portion 31 and the timing control signal line 221 can be reduced.

[0093] Similarly, the second opening 31a exposes the timing control signal line 221, thereby reducing the influence of the coupling capacitance between the third connection portion 42 and the timing control signal line 221.

[0094] In some embodiments, as shown in FIG. 4, Figure 6A and Figure 6B the first opening 42a exposes the timing control signal line 221.

[0095] In other embodiments, as shown in FIG. 5, Figure 5A and Figure 5B the second opening 31a exposes the timing control signal line 221.

[0096] In other embodiments, as shown in FIG. 6, Figure 6A and Figure 6B the first opening 42a and the second opening 31a both expose the timing control signal line 221, while reducing the influence of the coupling capacitance between the second connection portion 31 and the timing control signal line 221 and the coupling capacitance between the third connection portion 42 and the timing control signal line 221.

[0097] Optionally, the timing control signal line 221 includes a clock signal line, a start pulse signal line.

[0098] In some embodiments, the timing control signal line 221 includes a clock signal line (CLK line). The clock signal line is used to provide a periodic pulse signal for the gate driving circuit, control the working timing of the gate driving unit in the gate driving circuit, so that it performs signal transmission and processing at a certain rhythm, and realizes the line-by-line scanning of each row of sub-pixels 11 in the display panel 1.

[0099] In some embodiments, the timing control signal line 221 includes a start pulse signal line (STV line). The pulse signal of the start pulse signal line marks the beginning of a frame image display, and the pulse signal of the start pulse signal line provides a start trigger signal to enable the gate driving unit to sequentially scan from the first row to the last row. Then the start pulse signal line provides the next pulse signal to start the scanning of the next frame.

[0100] Alternatively, as shown in Figures 5A to 6B , the clock signal line includes a plurality of clock signal sub-lines 2211, each of which has the same overlapping area with the second connection part 31; and / or, each of which has the same overlapping area with the third connection part 42.

[0101] The clock signal line includes a plurality of clock signal sub-lines 2211, such as CK1, CK2, CK3, CK4, etc., which cooperate with each other to achieve accurate driving and control of the gate driving unit. For example, the clock signal line can be designed as 4CLK, 6CLK, 8CLK, etc. Taking 4CLK as an example, the clock signal line includes CK1, CK2, CK3, and CK4, which provide clock input signals to different scanning lines in sequence. One scanning line can correspond to one row of sub-pixels 11. Among them, each clock signal sub-line 2211 is 1 / 4 period earlier than the previous clock signal sub-line 2211, so that at one time, one of every four scanning lines provides an output voltage, thereby reducing the load of the clock signal sub-line 2211. The structural principles of 6CLK and 8CLK are basically the same as 4CLK, except that more clock signal sub-lines 2211 are used, so that the load of a single clock signal sub-line 2211 is further reduced.

[0102] As shown in Figure 5A and Figure 5B , since a plurality of clock signal sub-lines 2211 provide clock input signals to different scanning lines in sequence, in order to avoid the formation of horizontal lines due to the waveform difference of the clock signals of adjacent two scanning lines, each clock signal sub-line 2211 can have the same overlapping area with the second connection part 31, so that the coupling capacitances formed by the plurality of clock signal sub-lines 2211 and the second connection part 31 are the same, reducing the clock signal difference between adjacent scanning lines and further improving the horizontal line defect.

[0103] Similarly, as shown in Figure 6A and Figure 6B , each clock signal sub-line 2211 can have the same overlapping area with the third connection part 42, so that the coupling capacitances formed by the plurality of clock signal sub-lines 2211 and the third connection part 42 are the same, reducing the clock signal difference between adjacent scanning lines and further improving the horizontal line defect.

[0104] In some embodiments, the overlap area between each clock signal sub-line 2211 and the second connection portion 31 is the same.

[0105] In some embodiments, the overlap area between each clock signal sub-line 2211 and the third connection portion 42 is the same.

[0106] In some embodiments, the overlapping area of ​​each clock signal sub-line 2211 with the second connection portion 31 is the same, and the overlapping area of ​​each clock signal sub-line 2211 with the third connection portion 42 is the same, thereby further reducing the clock signal difference between adjacent multiple scan lines and further improving the horizontal stripe defect.

[0107] like Figure 7 As shown, waveforms s2 and s3 both correspond to pulse signal waveforms in the timing control signal line 221 after the second opening 31a is set. The difference between waveforms s2 and s3 is that the overlap area of ​​multiple clock signal sub-lines 2211 with the second connection portion 31 is different in waveform s2, while the overlap area of ​​multiple clock signal sub-lines 2211 with the second connection portion 31 is the same in waveform s3. It can be seen that when the overlap area of ​​multiple clock signal sub-lines 2211 with the second connection portion 31 is the same, the waveform of the pulse signal of waveform s3 is closer to the ideal state of a square wave, that is, the rise time (Tr3) of waveform s3 is less than the rise time (Tr2) of waveform s2, and the fall time (Tf3) of waveform s3 is less than the fall time (Tf3) of waveform s2. Therefore, by making the overlap area of ​​multiple clock signal sub-lines 2211 with the second connection portion 31 the same, and / or making the overlap area of ​​multiple clock signal sub-lines 2211 with the third connection portion 42 the same, the horizontal stripe defect can be further improved.

[0108] Optionally, such as Figure 6A and Figure 6B As shown, the first opening 42a and the second opening 31a are offset in the thickness direction of the display panel 1, or the first opening 42a and the second opening 31a overlap in the thickness direction of the display panel 1.

[0109] In some embodiments, such as Figure 6A As shown, the first opening 42a and the second opening 31a are offset in the thickness direction of the display panel 1. This means that the orthographic projection pattern of the first opening 42a on the substrate 10 does not overlap with the orthographic projection pattern of the second opening 31a on the substrate 10. This arrangement guides the current flow between the second connecting portion 31 and the third connecting portion 42, preventing excessive current density in the same area from causing heat generation. Simultaneously, fine-tuning the electric field distribution in the bezel area NA helps improve the brightness uniformity of the display area AA, thereby enhancing display quality.

[0110] like Figure 8A As shown, Figure 8A This is a comparison diagram of the current density distribution of the second connecting portion 31 and the third connecting portion 42 of a display panel 1 provided in an exemplary embodiment of this disclosure. (a) shows the current density distribution when the first opening 42a and the second opening 31a are not offset in the thickness direction of the display panel 1, and (b) shows the current density distribution when the first opening 42a and the second opening 31a are offset in the thickness direction of the display panel 1. Figure 8A As can be seen from the data, in (a), the color change at the first opening 42a is large and the current density distribution is relatively uneven; in (b), the color change at the first opening 42a is small and the current density distribution is more uniform. That is, by offsetting the first opening 42a and the second opening 31a in the thickness direction of the display panel 1, the problem of uneven brightness of the display screen can be further improved.

[0111] Meanwhile, the first opening 42a and the second opening 31a are staggered in the thickness direction of the display panel 1. This allows the positions of the first opening 42a and the second opening 31a to better adapt to processes such as photolithography and etching, avoiding excessive concentration of the first opening 42a and the second opening 31a, which would increase the difficulty of the process and thus improve manufacturing yield and efficiency. Furthermore, staggering the first opening 42a and the second opening 31a in the thickness direction of the display panel 1 avoids the situation where the opening area is too low, preventing subsequent encapsulation material from fully filling the low-lying area. In other words, by staggering the first opening 42a and the second opening 31a in the thickness direction of the display panel 1, the sealing performance of subsequent encapsulation materials can be improved, better protecting the gate drive circuit and other circuit structures of the display panel 1, and extending the lifespan of the display panel 1.

[0112] Furthermore, by offsetting the first opening 42a and the second opening 31a in the thickness direction of the display panel 1, the stress distribution in the bezel area NA can be made more uniform, ensuring the structural strength of the bezel area NA. Figure 8B As shown, the current density distribution of the second connection portion 31 is illustrated, and this current density distribution is also characterized as a stress distribution. Figure 8B In the diagram, (a) shows the current density distribution when the second connection portion 31 does not have the second opening 31a, and the color change is large in (a). (b) shows the current density distribution after the second connection portion 31 has the second opening 31a, and the color change is small in (b). Figure 8B It can be seen that the stress distribution in (b) is more balanced than that in (a). This means that the current density distribution is more balanced after the second opening 31a is provided in the second connection part 31.

[0113] In other embodiments, such as Figure 6BAs shown, the first opening 42a and the second opening 31a overlap in the thickness direction of the display panel 1. That is to say, the orthographic projection pattern of the first opening 42a on the substrate 10 overlaps with the orthographic projection pattern of the second opening 31a on the substrate 10.

[0114] Optionally, such as Figure 5A and Figure 5B As shown, multiple first openings 42a are aligned or staggered in the extension direction of the timing control signal line 221; and / or, multiple second openings 31a are aligned or staggered in the extension direction of the timing control signal line 221. The extension direction of the timing control signal line 221 is the second direction D2 in the figure.

[0115] In some embodiments, such as Figure 6A and Figure 6B As shown, the plurality of first openings 42a are aligned or staggered in the extension direction of the timing control signal line 221. Alignment of the plurality of first openings 42a in the extension direction of the timing control signal line 221 means that the plurality of first openings 42a are arranged along the extension direction of the timing control signal line 221. Staggering of the plurality of first openings 42a in the extension direction of the timing control signal line 221 means that the line connecting the centers of at least two first openings 42a is not parallel to the extension direction of the timing control signal line 221.

[0116] In some embodiments, such as Figure 5A and Figure 5B As shown, the plurality of second openings 31a are aligned or staggered in the extension direction of the timing control signal line 221. Alignment of the plurality of second openings 31a in the extension direction of the timing control signal line 221 means that the plurality of second openings 31a are arranged along the extension direction of the timing control signal line 221. Staggering of the plurality of second openings 31a in the extension direction of the timing control signal line 221 means that the line connecting the centers of at least two second openings 31a is not parallel to the extension direction of the timing control signal line 221.

[0117] Optionally, such as Figures 9A to 9E As shown, multiple first openings 42a are aligned or staggered in the arrangement direction of multiple timing control signal lines 221; and / or, multiple second openings 31a are aligned or staggered in the arrangement direction of multiple timing control signal lines 221. The arrangement direction of the timing control signal lines 221 is the first direction D1 in the figure.

[0118] It should be noted that, Figures 9A to 9E Only the first opening 42a is shown; the arrangement of the second opening 31a is similar.

[0119] In some embodiments, the plurality of first openings 42a are aligned or staggered in the arrangement direction of the timing control signal lines 221. The plurality of first openings 42a are aligned in the arrangement direction of the timing control signal lines 221 means that the line connecting the centers of the plurality of first openings 42a is parallel to the arrangement direction of the timing control signal lines 221. The plurality of first openings 42a are staggered in the arrangement direction of the timing control signal lines 221 means that the line connecting the centers of at least two first openings 42a is not parallel to the arrangement direction of the timing control signal lines 221.

[0120] In some embodiments, as shown in FIG. 3A, the plurality of second openings 31a are aligned or staggered in the arrangement direction of the timing control signal lines 221. The plurality of second openings 31a are aligned in the arrangement direction of the timing control signal lines 221 means that the line connecting the centers of the plurality of second openings 31a is parallel to the arrangement direction of the timing control signal lines 221. The plurality of second openings 31a are staggered in the arrangement direction of the timing control signal lines 221 means that the line connecting the centers of at least two second openings 31a is not parallel to the arrangement direction of the timing control signal lines 221. Figures 9A to 9E

[0121] In some embodiments, as shown in FIG. 3A, the plurality of second openings 31a are aligned or staggered in the arrangement direction of the timing control signal lines 221. The plurality of second openings 31a are aligned in the arrangement direction of the timing control signal lines 221 means that the line connecting the centers of the plurality of second openings 31a is parallel to the arrangement direction of the timing control signal lines 221. The plurality of second openings 31a are staggered in the arrangement direction of the timing control signal lines 221 means that the line connecting the centers of at least two second openings 31a is not parallel to the arrangement direction of the timing control signal lines 221.

[0121] In some embodiments, as shown in FIG. 3A, the plurality of second openings 31a are aligned or staggered in the arrangement direction of the timing control signal lines 221. The plurality of second openings 31a are aligned in the arrangement direction of the timing control signal lines 221 means that the line connecting the centers of the plurality of second openings 31a is parallel to the arrangement direction of the timing control signal lines 221. The plurality of second openings 31a are staggered in the arrangement direction of the timing control signal lines 221 means that the line connecting the centers of at least two second openings 31a is not parallel to the arrangement direction of the timing control signal lines 221. Figures 5A to 6B

[0122] In some embodiments, as shown in FIG. 3A, at least one of the first openings 42a and the second openings 31a exposes one timing control signal line 221, or at least one of the first openings 42a and the second openings 31a exposes a plurality of timing control signal lines 221.

[0122] In some embodiments, as shown in FIG. 3A, at least one of the first openings 42a and the second openings 31a exposes one timing control signal line 221. That is, the first openings 42a are small holes, and one small hole pair exposes only one timing control signal line 221. The second openings 31a are small holes, and one small hole pair exposes only one timing control signal line 221. Figure 5A In some embodiments, the size of the first openings 42a and / or the second openings 31a is 25um*25um.

[0123] In some embodiments, the size of the first openings 42a and / or the second openings 31a is 5um*5um.

[0124] In some embodiments, the size of the first openings 42a and / or the second openings 31a is 75um*25um.

[0125] In some embodiments, the spacing between adjacent two holes can be set as needed, for example, the spacing between adjacent two holes can be the size of the hole.

[0126] In some embodiments, as shown in FIG. 3A, at least one of the first openings 42a and the second openings 31a exposes one timing control signal line 221, or at least one of the first openings 42a and the second openings 31a exposes a plurality of timing control signal lines 221.

[0127] Figures 5B to 6BAs shown, at least one of the first openings 42a and the second openings 31a exposes the plurality of timing control signal lines 221. That is, the first openings 42a are large holes, one large hole exposes the plurality of timing control signal lines 221. The second openings 31a are large holes, one large hole exposes the plurality of timing control signal lines 221.

[0128] Optionally, as shown, the shape of each first opening 42a is the same, and / or, the shape of each second opening 31a is the same. Figures 9A to 9E

[0129] In some embodiments, as shown, the shape of each first opening 42a is the same, and the shape of each second opening 31a is the same. Figures 9A to 9E

[0130] In some embodiments, as shown, the shape of each first opening 42a is the same, and the shape of each second opening 31a is the same. Figures 9A to 9E

[0131] In some embodiments, the shape of each second opening 31a is the same, and the shape of each first opening 42a is the same.

[0132] Optionally, as shown, Figure 2 Figures 5A to 6B As shown, the first metal layer 20 further comprises a first connecting part 21, the first connecting part 21 is located on the side of the circuit trace part 22 away from the display area AA, and the first connecting part 21 is electrically connected to the second connecting part 31.

[0133] As shown, the second connecting part 31 is electrically connected to the first connecting part 21 through a via. The first connecting part 21 and the circuit trace part 22 are both located on the first metal layer 20. Figure 2 The display panel 1 further comprises a binding member (not shown in the figure), which is bound to the display panel 1. The binding member includes a chip on film, a printed circuit board, a flexible printed circuit board, etc. The binding member is used to provide driving signals for the display panel 1, such as VSS, VDD, CLK, STV, etc. The first metal layer 20 further comprises a plurality of binding terminals, which are electrically connected to the binding member.

[0134] By arranging the first connecting part 21 and the circuit trace part 22 on the same layer on the first metal layer 20, it is convenient to directly input signals to the first connecting part 21 and the circuit trace part 22 through the traces on the first metal layer 20, without having to transfer through other conductive layers, thereby improving the reliability of signal transmission.

[0135] ​​​​​

[0136] According to a second aspect of the present application, as shown in Figure 10 The display terminal 2 comprises the display panel 1.

[0137] In the embodiment, as shown in Figure 10 The display terminal 2 comprises the display panel 1 and a terminal body 3, and the display panel 1 and the terminal body 3 are combined as a whole.

[0138] In the embodiment, the display terminal 2 can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0139] In the description of the present application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0140] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0141] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0142] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment without departing from the technical solution of the present application and according to the technical essence of the present application still falls within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a display area and a frame area arranged on one side of the display area, and the display panel comprises: a substrate; a cathode layer arranged on one side of the substrate, the cathode layer comprising a cathode part in the display area and an overlapping part in the frame area; a first metal layer arranged between the cathode layer and the substrate, the first metal layer comprising a circuit trace part in the frame area; a second metal layer arranged between the first metal layer and the cathode layer, the second metal layer comprising a second connecting part in the frame area; wherein the second connecting part and the overlapping part are electrically connected, and the second connecting part and the circuit trace part overlap in the thickness direction of the display panel.

2. The display panel of claim 1, wherein, The display panel comprises an anode layer arranged between the second metal layer and the cathode layer, the anode layer comprising an anode part in the display area and a third connecting part in the frame area; wherein the second connecting part and the overlapping part are both electrically connected to the third connecting part, and the third connecting part and the circuit trace part overlap in the thickness direction of the display panel.

3. The display panel of claim 2, wherein, The display panel comprises a first planar layer arranged between the second metal layer and the anode layer, the third connecting part is provided with a plurality of first openings to expose the first planar layer; and / or, The display panel comprises a second planar layer arranged between the first metal layer and the second metal layer, the second connecting part is provided with a plurality of second openings to expose the second planar layer.

4. The display panel of claim 3, wherein, The circuit trace part comprises a plurality of timing control signal lines, and at least one of the first openings and the second openings exposes the timing control signal lines.

5. The display panel of claim 4, wherein, The timing control signal lines comprise clock signal lines and start pulse signal lines.

6. The display panel of claim 5, wherein, The clock signal lines comprise a plurality of clock signal sub-lines, each clock signal sub-line has the same overlapping area with the second connecting part; and / or, each clock signal sub-line has the same overlapping area with the third connecting part.

7. The display panel of claim 4, wherein, The first openings and the second openings are staggered in the thickness direction of the display panel, or the first openings and the second openings overlap in the thickness direction of the display panel.

8. The display panel of claim 7, wherein, A plurality of the first openings are aligned or staggered in the extension direction of the timing control signal lines; and / or, a plurality of the second openings are aligned or staggered in the extension direction of the timing control signal lines.

9. The display panel of claim 7, wherein, A plurality of the first openings are aligned or staggered in the arrangement direction of a plurality of the timing control signal lines; and / or, a plurality of the second openings are aligned or staggered in the arrangement direction of a plurality of the timing control signal lines.

10. The display panel of claim 8, wherein, At least one of the first openings and the second openings exposes one of the timing control signal lines, or at least one of the first openings and the second openings exposes a plurality of the timing control signal lines.

11. The display panel of claim 3, wherein, Each of the first openings has the same shape, and / or each of the second openings has the same shape.

12. The display panel of any one of claims 1 to 11, wherein, The first metal layer further comprises a first connecting part, the first connecting part is located on the side of the circuit trace part away from the display area, and the first connecting part is electrically connected to the second connecting part.

13. A display terminal, characterized by A display panel comprising any of claims 1 to 12.

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