Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of improving capacitance without increasing the size of the multilayer ceramic capacitor. In a laminated ceramic capacitor (1), a first facing portion (EA) of a first internal electrode layer (31) has a first high coverage area (EA0) which is disposed further toward the outside of a laminated body (10) in a lamination direction (T) than a first lead-out portion (D1) and which has a higher coverage rate than the first lead-out portion (D1), and a second high coverage area (EA0) which is disposed further toward the outside of the laminated body (10) in a lamination direction (T) than the first lead-out portion (D1). The second opposing portion (EB) has a second high coverage area (EB0) that is disposed further toward the outside of the laminated body (10) in the lamination direction (T) than the second lead-out portion (D2) and that has a higher coverage than the coverage of the second lead-out portion (D2).

Description

TECHNICAL FIELD

[0001] The present application relates to a multilayer ceramic capacitor. BACKGROUND

[0002] In the past, a multilayer ceramic capacitor has been known as a multilayer ceramic electronic component. Generally, the multilayer ceramic capacitor has a multilayer body in which a plurality of dielectric layers and internal electrode layers are alternately stacked, and external electrodes connected to the internal electrode layers and provided on both end surfaces of the multilayer body (see Patent Document 1).

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent Application Publication No. 2003-243249 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] With respect to the multilayer ceramic capacitor, miniaturization is required, and an increase in electrostatic capacity is required. However, it is difficult to satisfy both of these characteristics.

[0008] An object of the present application is to provide a multilayer ceramic capacitor capable of increasing the capacity without increasing the size of the multilayer ceramic capacitor.

[0009] TECHNICAL SOLUTION FOR SOLVING THE PROBLEMS

[0010] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including a plurality of stacked dielectric layers, and including a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction; a first internal electrode layer disposed on the dielectric layers and exposed on the first end surface; a second internal electrode layer disposed on the dielectric layers and exposed on the second end surface; a first external electrode disposed on the first end surface and connected to the first internal electrode layer; and a second external electrode disposed on the second end surface and connected to the second internal electrode layer, wherein the first internal electrode layer... The electrode layer has a first opposing portion opposite to the second internal electrode layer and a first lead-out portion extending from the first opposing portion toward the first end face side. The second internal electrode layer has a second opposing portion opposite to the first internal electrode layer and a second lead-out portion extending from the second opposing portion toward the second end face side. The first opposing portion has a first high coverage area, which is a region that is configured relative to the first lead-out portion and is biased toward the outside of the laminate in the stacking direction and has a higher coverage than the first lead-out portion. The second opposing portion has a second high coverage area, which is a region that is configured relative to the second lead-out portion and is biased toward the outside of the laminate in the stacking direction and has a higher coverage than the second lead-out portion.

[0011] Invention Effects

[0012] According to the present invention, a multilayer ceramic capacitor that can increase capacitance without increasing the size of the multilayer ceramic capacitor can be provided. Attached Figure Description

[0013] Figure 1 This is a perspective view of the stacked ceramic capacitor according to the first embodiment.

[0014] Figure 2A yes Figure 1 Sectional view II-II, and is a diagram used to illustrate the general structure of the laminate.

[0015] Figure 2B yes Figure 1 Sectional view II-II, which is a diagram used to illustrate the details of the internal electrode layers of the laminate.

[0016] Figure 3 yes Figure 2A Sectional view III-III.

[0017] Figure 4A yes Figure 2A The IVA-IVA cross-sectional view, and is a cross-sectional view along the first inner electrode layer.

[0018] Figure 4B is Figure 2A a cross-sectional view of the IVB-IVB, and is a cross-sectional view along the 2nd internal electrode layer.

[0019] Figure 5 is a photograph showing a part of the cross section of the laminate.

[0020] Figure 6 is a photograph of a part of Figure 5 which contains the 1st central region and the 2nd central region of the internal electrode layer.

[0021] Figure 7 is a photograph of a part of Figure 5 which contains the 2nd region and the 3rd region of the internal electrode layer.

[0022] Figure 8 is a graph showing the measurement points when the thicknesses of the internal electrode layer and the dielectric layer are measured.

[0023] Figure 9 is a graph in which an example of a SEM-based enlarged image of the exposed internal layer cross section is attached.

[0024] Figure 10 is a schematic view showing the cross section of the dielectric sheet on which the conductive paste P1 is printed.

[0025] Figure 11 is a schematic view showing the cross section of the dielectric sheet on which the conductive paste P2 is printed in Figure 10 .

[0026] Figure 12 is a schematic view showing a part of the laminate sheet in which a part to become the 1st main face side external layer portion and a part to become the 2nd main face side external layer portion are formed above and below a part to become the internal layer portion.

[0027] Figure 13 is an appearance perspective view of the laminate ceramic capacitor to which the 2nd embodiment is directed.

[0028] Figure 14A is a view of the laminate ceramic capacitor to which the 2nd embodiment is directed, which corresponds to Figure 4A .

[0029] Figure 14B is a view of the laminate ceramic capacitor to which the 2nd embodiment is directed, which corresponds to Figure 4B . DETAILED DESCRIPTION

[0030] <1st Embodiment>

[0031] A stacked ceramic capacitor 1 as a stacked ceramic electronic component according to a first embodiment of the present disclosure will be described with reference to the drawings. Figure 1 is a perspective view of the stacked ceramic capacitor 1 according to the first embodiment. Figure 2A is Figure 1 is a II-II sectional view of the stacked ceramic capacitor 1 according to the first embodiment, and is a view for explaining the outline structure of the stack. Figure 2B is Figure 1 is a II-II sectional view of the stacked ceramic capacitor 1 according to the first embodiment, and is a view for explaining the details of the internal electrode layers of the stack. Figure 3 is Figure 2A is a III-III sectional view of the stacked ceramic capacitor 1 according to the first embodiment. Figure 4A is Figure 2A is a IVA-IVA sectional view of the stacked ceramic capacitor 1 according to the first embodiment, and is a sectional view along the first internal electrode layer. Figure 4B is Figure 2A is a IVB-IVB sectional view of the stacked ceramic capacitor 1 according to the first embodiment, and is a sectional view along the second internal electrode layer.

[0032] In addition, the drawings are used to explain the content of the invention, and are sometimes drawn schematically simplified, and sometimes the ratio of the sizes of the constituent elements or between the constituent elements drawn is not consistent with the ratio of these sizes described in the specification. Further, there are cases where the constituent elements described in the specification are omitted in the drawings, cases where the number of omissions is drawn, and the like. For example, in order to facilitate the explanation, the number of internal electrode layers described in Figure 2A , Figure 2B , Figure 3 is 12, but this does not mean the number of the actual internal electrode layers 30. In addition, regarding the terms such as "parallel", "orthogonal", "identical", and the like, the values of the length, the angle, and the like used in the present invention, they are not limited in the strict sense, and are interpreted to include the range that can be expected to have the same function to the extent that they are determined

[0033] As shown in Figure 1 , the stacked ceramic capacitor 1 according to the first embodiment has a substantially rectangular parallelepiped shape. The stacked ceramic capacitor 1 has a stack 10 having a substantially rectangular parallelepiped shape, and a pair of external electrodes 40 disposed separately from each other at both end portions of the stack 10.

[0034] In Figure 1 , an arrow T shows the stacking direction of the stacked ceramic capacitor 1 and the stack 10. This stacking direction T is also the thickness direction and the height direction of the stacked ceramic capacitor 1 and the stack 10. In Figure 1 , an arrow L shows the length direction of the stacked ceramic capacitor 1 and the stack 10 orthogonal to the stacking direction T. In Figure 1In the diagram, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the multilayer 10, which is orthogonal to the stacking direction T and the length direction L. A pair of external electrodes 40 are respectively disposed at one end and the other end of the multilayer 10 along the length direction L.

[0035] exist Figures 1-4B And the following Figure 5 , Figure 8 , Figures 13-14B The diagram illustrates an XYZ orthogonal coordinate system. The length direction L of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the X-direction. The width direction W of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the Y-direction. The stacking direction T of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the Z-direction. Figure 2A , Figure 2B as well as Figure 8 The cross-section shown is also called the LT cross-section. Figure 3 The cross-section shown is also known as the WT cross-section. Figure 4A , Figure 4B , Figure 14A as well as Figure 14B The cross-section shown is also called the LW cross-section.

[0036] like Figures 1-4B As shown, the laminate 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the lamination direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L orthogonal to the lamination direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W orthogonal to the lamination direction T and the length direction L.

[0037] like Figure 1 As shown, the laminate 10 has a generally rectangular parallelepiped shape. Furthermore, the length L of the laminate 10 is not necessarily longer than its width W. It is preferable that the corners and edges of the laminate 10 have rounded corners. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Additionally, some or all of the surfaces constituting the laminate 10 may be formed with irregularities or depressions.

[0038] The dimensions of the laminate 10 are not particularly limited, but if the length direction L of the laminate 10 is defined as dimension L, then dimension L is preferably 0.2 mm or more and 6 mm or less. Furthermore, if the lamination direction T of the laminate 10 is defined as dimension T, then dimension T is preferably 0.05 mm or more and 5 mm or less. Furthermore, if the width direction W of the laminate 10 is defined as dimension W, then dimension W is preferably 0.1 mm or more and 5 mm or less.

[0039] like Figure 2A , Figure 2B as well as Figure 3As shown, the laminate 10 has an inner layer portion 11 and a first main face side outer layer portion 12 and a second main face side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0040] The inner layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers alternately stacked in the stacking direction T. The inner layer portion 11 includes, in the stacking direction T, from the internal electrode layer 30 located closest to the first main face TS1 side to the internal electrode layer 30 located closest to the second main face TS2 side. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged in opposition with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and substantially functions as a capacitor. In addition, the thickness of the inner layer portion 11 in the stacking direction T varies along the length direction L in accordance with the shape of the internal electrode layer 30 located closest to the first main face TS1 side and the shape of the internal electrode layer 30 located closest to the second main face TS2 side.

[0041] The plurality of dielectric layers 20 are composed of a dielectric material. The dielectric material may, for example, also be a dielectric ceramic including BaTiO3, CaTiO3, SrTiO3, or CaZrO3, or the like as a main component. Further, the dielectric material may also be a dielectric material to which a sub-component such as a Mn compound, a Fe compound, a Cr compound, a Co compound, a Ni compound, or the like is added to the main components. The dielectric material is particularly preferably a material including BaTiO3 as a main component.

[0042] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. The number of pieces of the dielectric layers 20 that are stacked is preferably 15 pieces or more and 1200 pieces or less. In addition, the number of pieces of the dielectric layers 20 is the total number of the number of pieces of the dielectric layers 20 of the inner layer portion 11 and the number of pieces of the dielectric layers 20 of each of the first main face side outer layer portion 12 and the second main face side outer layer portion 13.

[0043] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 as a plurality of first internal conductor layers and a plurality of second internal electrode layers 32 as a plurality of second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the stacking direction T with the dielectric layer 20 interposed therebetween. The first internal electrode layers 31 are led out to the first end face LSI. The second internal electrode layers 32 are led out to the second end face LS2. In addition, hereinafter, in cases where it is not necessary to distinguish between the first internal electrode layers 31 and the second internal electrode layers 32 and description is made without distinguishing therebetween, the first internal electrode layers 31 and the second internal electrode layers 32 are sometimes collectively referred to as the internal electrode layers 30.

[0044] As shown in FIG. 1, the laminate 10 has a first main face TS1 and a second main face TS2. The first main face TS1 is a face on which the first end face LSI is located. The second main face TS2 is a face on which the second end face LS2 is located. The first main face TS1 and the second main face TS2 are parallel to each other. The first main face TS1 and the second main face TS2 are opposite to each other in the stacking direction T. Figure 2A , Figure 4AAs shown, the first internal electrode layer 31 has a first opposing portion EA and a first lead-out portion D1. The first opposing portion EA is the region that sandwiches the dielectric layer 20 in the middle and opposes the second internal electrode layer 32, and is located inside the laminate 10. The first lead-out portion D1 is the portion that extends from the first opposing portion EA to the first end face LS1 and is exposed at the first end face LS1.

[0045] like Figure 2A , Figure 4B As shown, the second internal electrode layer 32 has a second opposing portion EB and a second lead-out portion D2. The second opposing portion EB is the region that sandwiches the dielectric layer 20 in the middle and opposes the first internal electrode layer 31, and is located inside the laminate 10. The second lead-out portion D2 is the portion that extends from the second opposing portion EB to the second end face LS2 and is exposed at the second end face LS2.

[0046] In this embodiment, the first opposing portion EA and the second opposing portion EB are opposed to each other through the dielectric layer 20, thereby forming a capacitor and exhibiting the characteristics of a capacitor.

[0047] The shapes of the first opposing portion EA and the second opposing portion EB are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may also be rounded, and the corners of the rectangular shape may also be formed at an angle. The shapes of the first lead-out portion D1 and the second lead-out portion D2 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may also be rounded, and the corners of the rectangular shape may also be formed at an angle.

[0048] The width W of the first opposing part EA and the width W of the first lead-out part D1 can be formed with the same dimensions, or either of them can be made smaller. The width W of the second opposing part EB and the width W of the second lead-out part D2 can be formed with the same dimensions, or either of them can be made narrower.

[0049] The first internal electrode layer 31 and the second internal electrode layer 32 are made of suitable conductive materials, such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may also be made of, for example, an Ag-Pd alloy.

[0050] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 0.2 μm or more and 2.0 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 15 or more and 1000 or less.

[0051] like Figure 2A , Figure 2B as well asFigure 3 As shown, the first main surface side outer layer 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the inner electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the inner electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer 12 and the second main surface side outer layer 13 can be the same as the dielectric layers 20 used in the inner layer 11.

[0052] Additionally, the laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion opposite to the first counter portion EA of the first inner electrode layer 31 and the second counter portion EB of the second inner electrode layer 32. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figure 4A as well as Figure 4B The diagram shows the width W and length L of the counter electrode portion 11E. The counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0053] Additionally, the laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the counter electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the counter electrode portion 11E and the second side WS2. Figure 3 , Figure 4A as well as Figure 4B The diagram shows the width direction W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layers are also referred to as W gaps or lateral gaps.

[0054] Additionally, the laminate 10 has an end-face side outer layer. The end-face side outer layer has a first end-face side outer layer LG1 and a second end-face side outer layer LG2. The first end-face side outer layer LG1 is a portion including a dielectric layer 20 located between the counter electrode portion 11E and the first end face LS1, and a first lead-out portion D1. That is, the first end-face side outer layer LG1 is an assembly of multiple dielectric layers 20 on the first end face LS1 side and multiple first leads-out portions D1. The second end-face side outer layer LG2 is a portion including a dielectric layer 20 located between the counter electrode portion 11E and the second end face LS2, and a second lead-out portion D2. That is, the second end-face side outer layer LG2 is an assembly of multiple dielectric layers 20 on the second end face LS2 side and multiple second leads-out portions D2. Figure 2A ,Figure 2B , Figure 4A and Figure 4B In the drawings, the range of the length direction L of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 is shown. Further, the end surface side outer layer portion is also referred to as an L gap or an end gap.

[0055] As shown in Figure 1 , Figure 2A and Figure 2B The external electrode 40 has a first external electrode 40A arranged on the first end surface LSI side of the laminate 10, and a second external electrode 40B arranged on the second end surface LS2 side of the laminate 10.

[0056] Further, the first external electrode 40A and the second external electrode 40B have the same basic structure. Further, the first external electrode 40A and the second external electrode 40B have a substantially face-symmetrical shape with respect to the central WT cross section of the length direction L of the laminate ceramic capacitor 1. Thus, hereinafter, in the case where it is not necessary to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B are sometimes collectively referred to as the external electrode 40.

[0057] The first external electrode 40A is arranged on the first end surface LSI. The first external electrode 40A is in contact with the first lead-out portion D1 of each of the plurality of first internal electrode layers 31 exposed on the first end surface LSI. Thereby, the first external electrode 40A is electrically connected to the plurality of first internal electrode layers 31. The first external electrode 40A can also be arranged on a part of the first main surface TS1 and a part of the second main surface TS2, and a part of the first side surface WS1 and a part of the second side surface WS2. In the present embodiment, the first external electrode 40A is formed so as to extend from the first end surface LSI to a part of the first main surface TS1 and a part of the second main surface TS2, and a part of the first side surface WS1 and a part of the second side surface WS2.

[0058] The second external electrode 40B is arranged on the second end surface LS2. The second external electrode 40B is in contact with the second lead-out portion D2 of each of the plurality of second internal electrode layers 32 exposed on the second end surface LS2. Thereby, the second external electrode 40B is electrically connected to the plurality of second internal electrode layers 32. The second external electrode 40B can also be arranged on a part of the first main surface TS1 and a part of the second main surface TS2, and a part of the first side surface WS1 and a part of the second side surface WS2. In the present embodiment, the second external electrode 40B is formed so as to extend from the second end surface LS2 to a part of the first main surface TS1 and a part of the second main surface TS2, and a part of the first side surface WS1 and a part of the second side surface WS2.

[0059] As described above, in the stack 10, the first opposing portion EA of the first internal electrode layer 31 and the second opposing portion EB of the second internal electrode layer 32 oppose each other via the dielectric layer 20, thereby forming a capacitor. Therefore, a characteristic of a capacitor appears between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0060] As shown in FIG. 1, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. Further, the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B. Figure 2A Figure 2B Figure 4A Figure 4B As shown in FIG. 1, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. Further, the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0061] The first base electrode layer 50A is disposed on the first end surface LSI. The first base electrode layer 50A is connected to the first lead portion Dl of each of the plurality of first internal electrode layers 31 exposed on the first end surface LSI. In the present embodiment, the first base electrode layer 50A is formed so as to extend from the first end surface LSI to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0062] The second base electrode layer 50B is disposed on the second end surface LS2. The second base electrode layer 50B is in contact with the second lead portion D2 of each of the plurality of second internal electrode layers 32 exposed on the second end surface LS2. In the present embodiment, the second base electrode layer 50B is formed so as to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0063] The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a fired layer, a thin film layer, and the like.

[0064] ​​​The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are sintered layers. The sintered layer preferably contains either a metal component and a glass component or a ceramic component, or both. The metal component contains, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like. The glass component contains, for example, at least one selected from B, Si, Ba, Mg, Al, Li, and the like. The ceramic component can use the same kind of ceramic material as the dielectric layer 20 or a different kind of ceramic material from the dielectric layer 20. The ceramic component contains, for example, at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, and the like.

[0065] The sintered layer is, for example, a sintered layer obtained by applying a conductive paste containing glass and a metal to the laminate 10 and sintering. The sintered layer can be formed by simultaneously sintering a raw material of the laminate 10 having a plurality of internal electrodes and dielectric layers, i.e., a laminate chip before sintering, and a conductive paste applied to the laminate chip. Alternatively, the sintered layer can be formed by applying a conductive paste to the laminate 10 after sintering the laminate chip to obtain the laminate 10 and sintering. In the above structure, the sintered layer is preferably formed by sintering a material in which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferable to use the same kind of ceramic material as the dielectric layer 20. In addition, the sintered layer can be a plurality of layers.

[0066] The thickness of the first base electrode layer 50A on the first end surface LSI corresponding to the length direction L is, for example, preferably 3 μm or more and 200 μm or less at the central portion in the stacking direction T and the width direction W of the first base electrode layer 50A.

[0067] The thickness of the second base electrode layer 50B on the second end surface LSI corresponding to the length direction L is, for example, preferably 3 μm or more and 200 μm or less at the central portion in the stacking direction T and the width direction W of the second base electrode layer 50B.

[0068] In the case where a portion of at least one of the first main surface TS1 or the second main surface TS2 is provided with the first base electrode layer 50A, the thickness of the first base electrode layer 50A provided in the portion corresponding to the stacking direction T is, for example, preferably 3 μm or more and 25 μm or less at the central portion in the length direction L and the width direction W of the first base electrode layer 50A provided in the portion.

[0069] In a case where the first base electrode layer 50A is also provided in a portion of at least one of the first side surface WS1 or the second side surface WS2, a thickness of the first base electrode layer 50A provided in the portion in correspondence with the width direction W is, for example, preferably in an order of 3 μm or more and 25 μm or less in a central portion in the length direction L and the stacking direction T of the first base electrode layer 50A provided in the portion.

[0070] In a case where the second base electrode layer 50B is also provided in a portion of at least one of the first main surface TS1 or the second main surface TS2, a thickness of the second base electrode layer 50B provided in the portion in correspondence with the stacking direction T is, for example, preferably in an order of 3 μm or more and 25 μm or less in a central portion in the length direction L and the width direction W of the second base electrode layer 50B provided in the portion.

[0071] In a case where the second base electrode layer 50B is also provided in a portion of at least one of the first side surface WS1 or the second side surface WS2, a thickness of the second base electrode layer 50B provided in the portion in correspondence with the width direction W is, for example, preferably in an order of 3 μm or more and 25 μm or less in a central portion in the length direction L and the stacking direction T of the second base electrode layer 50B provided in the portion.

[0072] In addition, in the present embodiment, the first base electrode layer 50A and the second base electrode layer 50B can also be thin film layers. The thin film layer is a layer in which metal particles are deposited.

[0073] In a case where the first base electrode layer 50A and the second base electrode layer 50B are formed by thin film layers, it is preferable to form by a thin film formation method such as a sputtering method or an evaporation method. Here, a sputtering electrode formed by a sputtering method will be described.

[0074] The first base electrode layer 50A of the present embodiment is constituted by a first thin film layer formed by a sputtering electrode. The second base electrode layer 50B is constituted by a second thin film layer formed by a sputtering electrode. In a case where the base electrode layer is formed by a sputtering electrode, it is preferable to directly form the sputtering electrode in a portion of at least either of the first main surface TS1 and the second main surface TS2 of the laminate 10. In the present embodiment, the first thin film layer formed by a sputtering electrode is disposed in a portion on the first side surface WS1 side of the first main surface TS1. The second thin film layer formed by a sputtering electrode is disposed in a portion on the second side surface WS2 side of the first main surface TS1.

[0075] The thin film layer formed by sputtering the electrode, for example, preferably contains at least one metal selected from the group containing Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. Thereby, the adhesion of the external electrode 40 to the laminate 10 can be improved. The thin film layer can be a single layer or can be formed of a plurality of layers. For example, it can be formed of a two-layer structure of a layer of a Ni-Cr alloy and a layer of a Ni-Cu alloy.

[0076] The first plating layer 60A is configured to cover the first base electrode layer 50A.

[0077] The second plating layer 60B is configured to cover the second base electrode layer 50B.

[0078] The first plating layer 60A and the second plating layer 60B, for example, can also contain at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, and the like. The first plating layer 60A and the second plating layer 60B can each be formed of a plurality of layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure of a Sn plating layer formed on a Ni plating layer.

[0079] In the present embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0080] In the present embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B.

[0081] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being eroded by solder when the laminate ceramic capacitor 1 is mounted. In addition, the Sn plating layer improves the wettability of solder when the laminate ceramic capacitor 1 is mounted. Thereby, the mounting of the laminate ceramic capacitor 1 is facilitated. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 10 μm or less.

[0082] In addition, the external electrode 40 of the present embodiment, for example, can also have a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer can be configured to cover the fired layer. In the case where the conductive resin layer is configured to cover the fired layer, the conductive resin layer is disposed between the fired layer and the plating layer (the first plating layer 60A, the second plating layer 60B). The conductive resin layer can cover the entire fired layer or can cover a part of the fired layer.

[0083] The conductive resin layer containing a thermosetting resin is, for example, more flexible than a conductive layer containing a plated film, a sintered product of a conductive paste. Therefore, even in the case where a physical impact, an impact due to a thermal cycle is applied to the multilayer ceramic capacitor 1, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses generation of cracks in the multilayer ceramic capacitor 1.

[0084] The metal constituting the conductive particles can be Ag, Cu, Ni, Sn, Bi, or an alloy containing them. The conductive particles preferably contain Ag. The conductive particles are, for example, a metal powder of Ag. Ag has a low electric resistivity among metals, and thus is suitable for an electrode material. In addition, Ag is a noble metal, and thus is not easily oxidized, and has high weather resistance. Thus, a metal powder of Ag is suitable as the conductive particles.

[0085] In addition, the conductive particles can also be a metal powder on the surface of which Ag is coated. When a material on the surface of which Ag is coated is used for the metal powder, the metal powder is preferably a Cu, Ni, Sn, Bi, or an alloy powder thereof. In order to maintain the properties of Ag and make the metal of the base material inexpensive, a metal powder on which Ag is coated is preferably used.

[0086] Further, the conductive particles can also be conductive particles to which an oxidation prevention treatment is applied to Cu, Ni. In addition, the conductive particles can also be a metal powder on the surface of which Sn, Ni, Cu is coated. When a material on the surface of which Sn, Ni, Cu is coated is used for the metal powder, the metal powder is preferably a Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0087] The shape of the conductive particles is not particularly limited. The conductive particles can use conductive particles having a spherical shape, a flat shape, or the like, but a spherical metal powder and a flat metal powder are preferably used in mixture.

[0088] The conductive particles contained in the conductive resin layer mainly function to ensure the electric conductivity of the conductive resin layer. Specifically, a plurality of conductive particles contact each other, and thus an electric conduction path is formed inside the conductive resin layer.

[0089] The resin constituting the conductive resin layer can also contain, for example, at least one selected from various known thermosetting resins such as an epoxy resin, a phenol resin, a polyurethane resin, a silicone resin, a polyimide resin, and the like. Among them, an epoxy resin, which is excellent in heat resistance, moisture resistance, adhesion, and the like, is one of the most suitable resins. In addition, the resin of the conductive resin layer preferably contains a curing agent together with the thermosetting resin. In the case where an epoxy resin is used as a base resin, the curing agent of the epoxy resin can also be various known compounds such as a phenol-based, an amine-based, an acid anhydride-based, an imidazole-based, an active ester-based, an amide imide-based, and the like.

[0090] Further, the conductive resin layer can be formed of a plurality of layers. The thickness of the thickest portion of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0091] Further, it can also be a structure in which the first base electrode layer 50A and the second base electrode layer 50B are not provided, and the first plating layer 60A and the second plating layer 60B described later are directly arranged on the laminate 10. That is, the laminate ceramic capacitor 1 can also be a structure including plating layers directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, it can also be a structure in which the plating layers are formed after a catalyst is provided on the surface of the laminate 10 as pretreatment.

[0092] In this case, the plating layer is also preferably a plurality of layers. The lower plating layer and the upper plating layer each, for example, preferably include at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni having a solder resist property. The upper plating layer is more preferably formed using Sn or Au having a good solder wettability. Further, for example, in the case where the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, the lower plating layer is preferably formed using Cu having a good joint property with Ni. Further, the upper plating layer can be formed as needed, and the external electrode 40 can also be constituted only of the lower plating layer. Furthermore, the plating layer can have the upper plating layer as the outermost layer, or can further form another plating layer on the surface of the upper plating layer.

[0093] The thickness of each layer of the plating layer arranged without the base electrode layer is preferably 2 μm or more and 10 μm or less. Further, the plating layer preferably does not include glass. The proportion of metal per unit volume of the plating layer is preferably 99% or more by volume.

[0094] Further, in the case where the plating layer is directly formed on the laminate 10, the thickness of the base electrode layer can be reduced. Thus, the size in the height direction T of the laminate ceramic capacitor 1 can be reduced in accordance with the amount of reduction in the thickness of the base electrode layer, and the low height of the laminate ceramic capacitor 1 can be sought. Or, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 can be made thicker in accordance with the amount of reduction in the thickness of the base electrode layer, and the increase in the body thickness can be sought. In this way, by directly forming the plating layer on the laminate 10, the design freedom of the laminate ceramic capacitor can be increased.

[0095] The above describes the basic structure of the multilayer ceramic capacitor 1 according to the embodiment. Furthermore, if the length dimension of the multilayer ceramic capacitor 1, including the laminate 10 and the external electrode 40, is defined as dimension L, then dimension L is preferably 0.2 mm or more and 6 mm or less. Furthermore, if the dimension in the lamination direction of the multilayer ceramic capacitor 1 is defined as dimension T, then dimension T is preferably 0.05 mm or more and 5 mm or less. Furthermore, if the width dimension of the multilayer ceramic capacitor 1 is defined as dimension W, then dimension W is preferably 0.1 mm or more and 5 mm or less.

[0096] Here, the inventors of this application, through repeated research, experiments, and simulations, have obtained the following insight: In order to increase capacitance without increasing the size of the multilayer ceramic capacitor, it is preferable to set the size and coverage of each structure included in the multilayer ceramic capacitor appropriately. Furthermore, in the inner electrode layer 30, in addition to the metal material, there are also voids where no metal material is present. The proportion of metal material in the inner electrode layer 30 is described as the coverage. The coverage is also referred to as the coverage ratio of the inner electrode layer 30 relative to the dielectric layer 20. In addition, the voids where no metal material is present may contain ceramic components such as dielectrics, glass components such as silicon dioxide, or voids. Hereinafter, using… Figures 1-7 This embodiment will be described in detail.

[0097] like Figures 2A-3 As shown, the inner layer 11 has a first main surface side inner layer 112, a second main surface side inner layer 113, and a central inner layer 111 disposed between the first main surface side inner layer and the second main surface side inner layer.

[0098] The first main surface side inner layer portion 112 is the portion of the inner layer portion 11 on the first main surface TS1 side. The first main surface side inner layer portion 112 is, for example, the portion of the inner layer portion 11 on the first main surface TS1 side, and includes the inner electrode layer 30 from the inner electrode layer 30 closest to the first main surface TS1 to at least the fifth inner electrode layer 30. The first main surface side inner layer portion 112 is, for example, 25% of the portion of the inner layer portion 11 on the first main surface TS1 side in the stacking direction.

[0099] The second main surface side inner layer portion 113 is the portion of the inner layer portion 11 on the second main surface TS2 side. The second main surface side inner layer portion 113 is, for example, the portion of the inner layer portion 11 on the second main surface TS2 side, and includes the inner electrode layer 30 from the inner electrode layer 30 closest to the second main surface TS2 to at least the fifth inner electrode layer 30. The second main surface side inner layer portion 113 is, for example, 25% of the portion of the inner layer portion 11 on the second main surface TS2 side in the stacking direction.

[0100] The central inner layer portion 111 is a portion of the inner layer portion 11 that is on the central side in the stacking direction T of the laminate 10. The central inner layer portion 111 is, for example, a portion that includes at least the internal electrode layer 30 disposed in the central region in the stacking direction T of the laminate. Further, the thickness of the central inner layer portion 111, the first main surface side inner layer portion 112, and the second main surface side inner layer portion 113 in the stacking direction T varies along the length direction L in accordance with the shape of the internal electrode layer 30.

[0101] As shown in FIG. 1, the inner layer portion 11 includes a first main surface side inner layer portion 112, a second main surface side inner layer portion 113, and a central inner layer portion 111. Figures 3-4B As shown in FIG. 1, the inner layer portion 11 includes a first main surface side inner layer portion 112, a second main surface side inner layer portion 113, and a central inner layer portion 111.

[0102] The first side surface side counter electrode portion 112E is a portion of the counter electrode portion 11E on the first side surface WS1 side. The first side surface side counter electrode portion 112E is, for example, a portion of 25% of the counter electrode portion 11E on the first side surface WS1 side in the width direction W. Further, the first side surface side counter electrode portion 112E has a region that overlaps with a portion of the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111.

[0103] The second side surface side counter electrode portion 113E is a portion of the counter electrode portion 11E on the second side surface WS2 side. The second side surface side counter electrode portion 113E is, for example, a portion of 25% of the counter electrode portion 11E on the second side surface WS2 side in the width direction W. Further, the second side surface side counter electrode portion 113E has a region that overlaps with a portion of the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111.

[0104] The central counter electrode portion 111E is disposed between the first side surface side counter electrode portion 112E and the second side surface side counter electrode portion 113E. The central counter electrode portion 111E is a portion that includes a central region in the width direction W of the counter electrode portion 11E in the width direction W. Further, the central counter electrode portion 111E has a region that overlaps with a portion of the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111.

[0105] Next, details of the internal electrode layer 30 will be described with reference to FIGS. 2A and 2B. Figure 2B Figures 4A-4B

[0106] ​​The first opposing portion EA has a first region EA1, a second region EA2, and a first central region EA0, which is a first high coverage region. The first region EA1 is disposed on the first end face LS1 side. The second region EA2 is disposed on the second end face LS2 side. The first central region EA0 is located between the first region EA1 and the second region EA2. The coverage of the first central region EA0 is higher than that of the first region EA1 and the second region EA2. Furthermore, as... Figure 2B As shown, the first central region EA0 is positioned further outward than the first region EA1 and the second region EA2 of the laminate 10. Furthermore, the coverage of the first central region EA0, which is the first high-coverage region, is higher than the coverage of the first lead-out portion D1. The first central region EA0 is positioned further outward than the first lead-out portion D1 of the laminate 10.

[0107] Specifically, in the first main surface side inner layer 112, the first central region EA0 of the first internal electrode layer 31 is positioned biased towards the first main surface TS1 side of the laminate 10 compared to the first lead-out portion D1, the first region EA1, and the second region EA2. Furthermore, in this embodiment, in the second main surface side inner layer 113, the first central region EA0 of the first internal electrode layer 31 is positioned biased towards the second main surface TS2 side of the laminate 10 compared to the first lead-out portion D1, the first region EA1, and the second region EA2. Alternatively, in at least either the first main surface side inner layer 112 or the second main surface side inner layer 113, the first central region EA0 may be positioned biased towards the outer side of the laminate 10 compared to the first lead-out portion D1, the first region EA1, and the second region EA2.

[0108] The second opposing portion EB has a third region EB1, a fourth region EB2, and a second central region EB0, which is a second high-coverage region. The third region EB1 is disposed on the second end face LS2 side. The fourth region EB2 is disposed on the first end face LS1 side. The second central region EB0 is located between the third region EB1 and the fourth region EB2. The coverage of the second central region EB0 is higher than that of the third region EB1 and the fourth region EB2. Furthermore, as... Figure 2B As shown, the second central region EB0 is positioned further outward than the third region EB1 and the fourth region EB2 of the laminate 10. Furthermore, the coverage of the second central region EB0, which is the second high-coverage region, is higher than the coverage of the second lead-out portion D2. The second central region EB0 is positioned further outward than the second lead-out portion D2 of the laminate 10.

[0109] Specifically, in the 1st main surface side inner layer portion 112, the 2nd central region EB0 of the 2nd internal electrode layer 32 is disposed more toward the 1st main surface TSl side of the laminate 10 than the 2nd lead-out portion D2, the 3rd region EB1, and the 4th region EB2. Further, in the present embodiment, in the 2nd main surface side inner layer portion 113, the 2nd central region EB0 of the 2nd internal electrode layer 32 is disposed more toward the 2nd main surface TS2 side of the laminate 10 than the 2nd lead-out portion D2, the 3rd region EB1, and the 4th region EB2. Also, it can be that, in at least either the 1st main surface side inner layer portion 112 or the 2nd main surface side inner layer portion 113, the 2nd central region EB0 is disposed more toward the outside of the laminate 10 than the 2nd lead-out portion D2, the 3rd region EB1, and the 4th region EB2.

[0110] Thus, it is possible to suppress the size of the laminate ceramic capacitor 1 from becoming large, and to increase the thickness of the internal electrode layer 30 of the 1st central region EA0 and the 2nd central region EB0 to improve the coverage ratio, thereby improving the capacitance.

[0111] The 1st central region EA0 is preferably substantially parallel to a plane orthogonal to the stacking direction T. The 1st central region EA0 and the 1st region EA1 and the 2nd region EA2 preferably have a substantially parallel portion. More preferably, the 1st central region EA0 and the 1st region EA1 and the 2nd region EA2 have a substantially parallel portion to a plane orthogonal to the stacking direction T.

[0112] The 2nd central region EB0 is preferably substantially parallel to a plane orthogonal to the stacking direction T. The 2nd central region EB0 and the 3rd region EB1 and the 4th region EB2 preferably have a substantially parallel portion. More preferably, the 2nd central region EB0 and the 3rd region EB1 and the 4th region EB2 have a substantially parallel portion to a plane orthogonal to the stacking direction T.

[0113] Thus, as the laminate ceramic capacitor 1, it is possible to suppress the formation of a portion in which the size locally becomes large, and to improve the capacitance without increasing the size of the laminate ceramic capacitor 1.

[0114] In the length direction L, the distance Le0 of the 1st central region EA0 is shorter than the distance LI between the 1st external electrode 40A and the 2nd external electrode 40B. Further, in the length direction L, the distance Le0 of the 2nd central region EB0 is shorter than the distance LI between the 1st external electrode 40A and the 2nd external electrode 40B. Also, in the length direction L, the distance of the 1st central region EA0 and the distance of the 2nd central region EB0 are preferably substantially equal, but are not limited thereto. Also, it is preferable that, in the length direction L, the 1st central region EA0 and the 2nd central region EB0 are disposed within the range of the distance LI between the 1st external electrode 40A and the 2nd external electrode 40B.

[0115] In addition, in the length direction L, the end portion of the first central region EA0 and the second central region EB0 on the first end face LS1 side is arranged on the second end face LS2 side compared to the end portion 40AE arranged on the laminate central side of the first external electrode 40A of the first main face TS1 and the second main face TS2. In addition, in the length direction L, the end portion of the first central region EA0 and the second central region EB0 on the second end face LS2 side is arranged on the first end face LS1 side compared to the end portion 40BE arranged on the laminate central side of the second external electrode 40B of the first main face TS1 and the second main face TS2.

[0116] Thus, it is possible to suppress the size of the multilayer ceramic capacitor 1 from becoming large, and to increase the thickness of the internal electrode layer 30 of the first central region EA0 and the second central region EB0 to improve the coverage ratio, thereby improving the capacitance.

[0117] In addition, in the length direction L, the end portion of the first region EA1 and the fourth region EB2 on the first end face LS1 side (left end of the EA, EB region in Figure 2B is arranged on the first end face LS1 side compared to the end portion 40AE arranged on the laminate central side of the first external electrode 40A of the first main face TS1 and the second main face TS2. In addition, in the length direction L, the end portion of the second region EA2 and the third region EB1 on the second end face LS2 side (right end of the EA, EB region in Figure 2B is arranged on the second end face LS2 side compared to the end portion 40BE arranged on the laminate central side of the second external electrode 40B of the first main face TS1 and the second main face TS2.

[0118] Thus, it is possible to suppress the size of the multilayer ceramic capacitor 1 from becoming large, and to ensure a large region of the opposing electrode portion 11E, thereby improving the capacitance.

[0119] The thickness in the stacking direction T of the first central region EA0 of the first internal electrode layer 31 is thicker than the thickness in the stacking direction T of the first region EA1 and the thickness in the stacking direction T of the second region EA2.

[0120] For example, the thickness of the first central region EA0 is preferably 101.6% or more and 111.3% or less of the thickness of the first region EA1 and the thickness of the second region EA2. The thickness of the first central region EA0 can also be 101.6% or more and 109.8% or less of the thickness of the first region EA1 and the thickness of the second region EA2, and more preferably 102.0% or more and 109.8% or less. For example, the thickness of the first central region EA0 is further preferably 103.0% or more and 109.8% or less of the thickness of the first region EA1 and the thickness of the second region EA2.

[0121] The thickness of the second central region EB0 of the second internal electrode layer 32 in the stacking direction T is thicker than the thickness of the third region EB1 and the thickness of the fourth region EB2.

[0122] For example, the thickness of the second central region EB0 is preferably 101.6% or more and 111.3% or less of the thickness of the third region EB1 and the thickness of the fourth region EB2. The thickness of the second central region EB0 can also be 101.6% or more and 109.8% or less of the thickness of the third region EB1 and the thickness of the fourth region EB2, and is more preferably 102.0% or more and 109.8% or less. For example, the thickness of the second central region EB0 is further preferably 103.0% or more and 109.8% or less of the thickness of the third region EB1 and the thickness of the fourth region EB2.

[0123] If the first internal electrode layer 31 and the second internal electrode layer 32 are collectively described, the thickness of the first central region EA0 and the second central region EB0 is thicker than the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. The thickness of the first central region EA0 and the second central region EB0 is preferably 101.6% or more and 111.3% or less of the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. The thickness of the first central region EA0 and the second central region EB0 can also be 101.6% or more and 109.8% or less of the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2, and is more preferably 102.0% or more and 109.8% or less. For example, the thickness of the first central region EA0 and the second central region EB0 is further preferably 103.0% or more and 109.8% or less of the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2.

[0124] The thickness of the first central region EA0 of the first internal electrode layer 31 in the stacking direction T is thicker than the thickness of the first lead-out portion D1.

[0125] For example, the thickness of the first central region EA0 is preferably 101.6% or more and 111.3% or less of the thickness of the first lead-out portion D1. For example, the thickness of the first central region EA0 can also be 101.6% or more and 109.8% or less of the thickness of the first lead-out portion D1, and is more preferably 102.0% or more and 109.8% or less. For example, the thickness of the first central region EA0 is further preferably 103.0% or more and 109.8% or less of the thickness of the first lead-out portion D1.

[0126] The thickness of the second central region EB0 of the second internal electrode layer 32 in the stacking direction T is thicker than the thickness of the second lead-out portion D2.

[0127] For example, the thickness of the second central region EB0 is preferably 101.6% or more and 111.3% or less of the thickness of the second lead D2. For example, the thickness of the second central region EB0 can also be 101.6% or more and 109.8% or less of the thickness of the second lead D2, more preferably 102.0% or more and 109.8% or less. For example, the thickness of the second central region EB0 is further preferably 103.0% or more and 109.8% or less of the thickness of the second lead D2.

[0128] The coverage ratio of the first central region EA0 is higher than the coverage ratios of the first region EA1 and the second region EA2.

[0129] The difference between the coverage ratio of the first central region EA0 and the coverage ratios of the first region EA1 and the second region EA2 is preferably 2.2 percentage points or more. Furthermore, the difference between the coverage ratio of the first central region EA0 and the coverage ratios of the first region EA1 and the second region EA2 is preferably 2.2 percentage points or more and 11.4 percentage points or less.

[0130] The difference between the coverage ratio of the first central region EA0 and the coverage ratios of the first region EA1 and the second region EA2 is more preferably 3.0 percentage points or more and 11.4 percentage points or less, and a higher effect can be expected. Furthermore, the difference between the coverage ratio of the first central region EA0 and the coverage ratios of the first region EA1 and the second region EA2 is further preferably 4.0 percentage points or more and 11.4 percentage points or less.

[0131] The coverage ratio of the second central region EB0 is higher than the coverage ratios of the third region EB1 and the fourth region EB2.

[0132] The difference between the coverage ratio of the second central region EB0 and the coverage ratios of the third region EB1 and the fourth region EB2 is preferably 2.2 percentage points or more. Furthermore, the difference between the coverage ratio of the second central region EB0 and the coverage ratios of the third region EB1 and the fourth region EB2 is preferably 2.2 percentage points or more and 11.4 percentage points or less.

[0133] The difference between the coverage ratio of the second central region EB0 and the coverage ratios of the third region EB1 and the fourth region EB2 is more preferably 3.0 percentage points or more and 11.4 percentage points or less, and a higher effect can be expected. Furthermore, the difference between the coverage ratio of the second central region EB0 and the coverage ratios of the third region EB1 and the fourth region EB2 is further preferably 4.0 percentage points or more and 11.4 percentage points or less.

[0134] If the first internal electrode layer 31 and the second internal electrode layer 32 are collectively described, the coverage ratio of the first central region EA0 and the second central region EB0 is higher than that of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. Further, the coverage ratio of the first central region EA0 and the second central region EB0 is higher than that of the first lead D1 and the second lead D2. The coverage ratio of the first central region EA0 and the second central region EB0 is preferably higher than that of the first lead D1, the second lead D2, the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 by 2.2 percent points or more. Further, the difference between the coverage ratio of the first central region EA0 and the second central region EB0 and that of the first lead D1, the second lead D2, the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is preferably 2.2 percent points or more and 11.4 percent points or less. The difference between the coverage ratio of the first central region EA0 and the second central region EB0 and that of the first lead D1, the second lead D2, the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is more preferably 3.0 percent points or more and 11.4 percent points or less, and a higher effect is expected. Further, the difference between the coverage ratio of the first central region EA0 and the second central region EB0 and that of the first lead D1, the second lead D2, the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is further preferably 4.0 percent points or more and 11.4 percent points or less.

[0135] Thus, the thickness of the internal electrode layer 30 of the first central region EA0 and the second central region EB0 can be increased to sufficiently increase the coverage ratio, and thus the capacitance can be further increased without increasing the size of the multilayer ceramic capacitor 1.

[0136] As shown in FIG. 6, the first internal electrode layer 31 further has a first inclined portion FA1 connecting the first region EA1 and the first central region EA0, and a second inclined portion FA2 connecting the second region EA2 and the first central region EA0. Figure 2B

[0137] The second internal electrode layer 32 further has a third inclined portion FB1 connecting the third region EB1 and the second central region EB0, and a fourth inclined portion FB2 connecting the fourth region EB2 and the second central region EB0.

[0138] Thus, the size of the multilayer ceramic capacitor 1 can be prevented from increasing, and the thickness of the internal electrode layer 30 of the first central region EA0 and the second central region EB0 can be increased to increase the coverage ratio and thus the capacitance.

[0139] ​The length direction L distance Le3 of the first inclined portion FA1 and the length direction L distance Le4 of the second inclined portion FA2 are shorter than the length direction L distance Le0 of the first central region EA0. Also, the length direction L distance Le4 of the third inclined portion FB1 and the length direction L distance Le3 of the fourth inclined portion FB2 are shorter than the length direction L distance Le0 of the second central region EB0.

[0140] Thus, the areas of the first central region EA0 and the second central region EB0, which have high coverage, can be ensured, and the capacitance can be further improved without increasing the size of the multilayer ceramic capacitor 1.

[0141] Also, the length direction L distance Le1 of the first region EA1 and the length direction L distance Le2 of the second region EA2 can be shorter than the length direction L distance Le0 of the first central region EA0. Also, the length direction L distance Le2 of the third region EB1 and the length direction L distance Le1 of the fourth region EB2 can be shorter than the length direction L distance Le0 of the second central region EB0.

[0142] Also, the ratio of the area of the first central region EA0 to the area of the first opposing portion EA is preferably 50% or more and 90% or less, and can be 60% or more and 85% or less. More preferably, it is 70% or more and 80% or less, for example, 75%. The ratio of the area of the second central region EB0 to the area of the second opposing portion EB is preferably 50% or more and 90% or less, and can be 60% or more and 85% or less. More preferably, it is 70% or more and 80% or less, for example, 75%.

[0143] Thus, the area of the opposing electrode portion 11E can be ensured to be large, and the area in which the first external electrode 40A and the second external electrode 40B are disposed can also be ensured, and further, the areas of the first central region EA0 and the second central region EB0, which have high coverage, can be appropriately ensured, and thus the capacitance can be further improved without increasing the size of the multilayer ceramic capacitor 1.

[0144] Further, the distance Le3 in the length direction L of the first inclined portion FA1 and the fourth inclined portion FB2 and the distance Le4 in the length direction L of the second inclined portion FA2 and the third inclined portion FB1 are preferably substantially equal, but are not limited thereto. Further, it is preferable that the first central region EA0 and the second central region EB0 are arranged in the range of the distance LI between the first external electrode 40A and the second external electrode 40B in the length direction L, and the first inclined portion FA1, the second inclined portion FA2, the third inclined portion FB1, and the fourth inclined portion FB2 are arranged. The distance (= Le0 + Le3 + Le4) obtained by adding the distance Le0 in the length direction L of the first central region EA0 and the second central region EB0, the distance Le3 in the length direction L of the first inclined portion FA1 and the fourth inclined portion FB2, and the distance Le4 in the length direction L of the second inclined portion FA2 and the third inclined portion FB1 is preferably shorter than the distance LI between the first external electrode 40A and the second external electrode 40B. However, it is not limited thereto.

[0145] The inclination angle θ of the first inclined portion FA1 with respect to the first central region EA0 is preferably 1° or more. For example, the inclination angle θ of the first inclined portion FA1 with respect to the first central region EA0 can also be 1° or more and 12° or less. More preferably, the inclination angle θ of the first inclined portion FA1 with respect to the first central region EA0 can also be 2° or more and 10° or less.

[0146] The inclination angle θ of the second inclined portion FA2 with respect to the first central region EA0 is preferably 1° or more. For example, the inclination angle θ of the second inclined portion FA2 with respect to the first central region EA0 can also be 1° or more and 12° or less. More preferably, the inclination angle θ of the second inclined portion FA2 with respect to the first central region EA0 can also be 2° or more and 10° or less.

[0147] The inclination angle θ of the third inclined portion FB1 with respect to the second central region EB0 is preferably 1° or more. For example, the inclination angle θ of the third inclined portion FB1 with respect to the second central region EB0 can also be 1° or more and 12° or less. More preferably, the inclination angle θ of the third inclined portion FB1 with respect to the second central region EB0 can also be 2° or more and 10° or less.

[0148] The inclination angle θ of the fourth inclined portion FB2 with respect to the second central region EB0 is preferably 1° or more. For example, the inclination angle θ of the fourth inclined portion FB2 with respect to the second central region EB0 can also be 1° or more and 12° or less. More preferably, the inclination angle θ of the fourth inclined portion FB2 with respect to the second central region EB0 can also be 2° or more and 10° or less.

[0149] Further, in Figure 2BIn the present embodiment, as a representative of the inclination angle θ, the inclination angle θ of the third inclined portion FB1 with respect to the second central region EB0 in the second internal electrode layer 32 is shown.

[0150] Thus, it is possible to suppress the size of the multilayer ceramic capacitor 1 from becoming large, and to increase the thickness of the internal electrode layer 30 of the first central region EA0 and the second central region EB0 to improve the coverage ratio, thereby improving the capacitance. Specifically, by setting the inclination angle θ described above to 1° or more, preferably 2° or more, it is possible to secure a region for thickening the thickness of the internal electrode layer 30 of the first central region EA0 and the second central region EB0. Further, by setting the inclination angle θ described above to 12° or less, preferably 10° or less, it is possible to suppress the surface of the multilayer body 10 from bulging too much in the stacking direction T so as to protrude more outward than the surface of the external electrode 40. More specifically, by setting the inclination angle θ within the range described above, it becomes easy to set the relationship between the thickness of the first central region EA0 and the second central region EB0 and the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 within the range of the present embodiment. Further, by setting the inclination angle θ within the range described above, it becomes easy to set the relationship between the distance T0 at the center of the exposed portion Ep of the multilayer body 10 described later and the maximum distance T1 at the covered portion of the multilayer body 10 described later within the range of the present embodiment described later.

[0151] As shown in Figs. 1 and 2, the thickness of the first inclined portion FA1 decreases as it goes toward the first end surface LS1. Further, as shown in Figs. 1 and 2, the thickness of the second inclined portion FA2 decreases as it goes toward the second end surface LS2. Figure 2A Figure 2B As shown in Figs. 1 and 2, the thickness of the first inclined portion FA1 decreases as it goes toward the first end surface LS1. Further, as shown in Figs. 1 and 2, the thickness of the second inclined portion FA2 decreases as it goes toward the second end surface LS2. Figure 2A Figure 2B As shown in Figs. 1 and 2, the thickness of the first inclined portion FA1 decreases as it goes toward the first end surface LS1. Further, as shown in Figs. 1 and 2, the thickness of the second inclined portion FA2 decreases as it goes toward the second end surface LS2.

[0152] As shown in Figs. 1 and 2, the thickness of the first inclined portion FA1 decreases as it goes toward the first end surface LS1. Further, as shown in Figs. 1 and 2, the thickness of the second inclined portion FA2 decreases as it goes toward the second end surface LS2. Figure 2A Figure 2B As shown in Figs. 1 and 2, the thickness of the first inclined portion FA1 decreases as it goes toward the first end surface LS1. Further, as shown in Figs. 1 and 2, the thickness of the second inclined portion FA2 decreases as it goes toward the second end surface LS2. Figure 2A Figure 2B As shown in Figs. 1 and 2, the thickness of the first inclined portion FA1 decreases as it goes toward the first end surface LS1. Further, as shown in Figs. 1 and 2, the thickness of the second inclined portion FA2 decreases as it goes toward the second end surface LS2.

[0153] If there is a portion where the thickness of the internal electrode layer 30 changes sharply, it is possible that a portion where the distance between the internal electrode layers 30 sandwiching the dielectric layer 20 becomes locally short will be formed. In this case, the electric field concentrates in this portion, and thus the reliability of the multilayer ceramic capacitor 1 can possibly decrease. If the structure described above is employed, it is possible to suppress the formation of a portion where the distance between the internal electrode layers 30 becomes locally short in the vicinity of the inclined portion, and thus it is possible to improve the capacitance without increasing the size of the multilayer ceramic capacitor 1, and to suppress the decrease in the reliability of the multilayer ceramic capacitor 1 due to the concentration of the electric field.​​​​

[0154] Furthermore, it can prevent stress concentration at the inclined portion, thus increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1, and further suppressing the generation of cracks in the multilayer 10.

[0155] like Figure 2B As shown, the height difference distance ls1 between the first region EA1 and the first central region EA0 generated by the first inclined portion FA1 in the stacking direction T is greater than the thickness Tc of the dielectric layer 20 disposed between the inner electrode layers 30 in the stacking direction T. More preferably, the height difference distance ls1 between the first region EA1 and the first central region EA0 generated by the first inclined portion FA1 in the stacking direction T is greater than the sum Tt (=Te+Tc) of the thickness Te of the inner electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. More preferably, the height difference distance ls1 between the first region EA1 and the first central region EA0 generated by the first inclined portion FA1 in the stacking direction T is more than twice the sum Tt of the thickness Te of the inner electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Furthermore, the height difference distance ls1 between the first region EA1 and the first central region EA0 generated by the first inclined portion FA1 can also be more than 3 times the sum of the thickness Te of the stacking direction T of the internal electrode layer 30 and the thickness Tc of the stacking direction T of the dielectric layer 20.

[0156] like Figure 2B As shown, the height difference distance ls2 between the second region EA2 and the first central region EA0 generated by the second inclined portion FA2 in the stacking direction T is greater than the thickness Tc of the dielectric layer 20 disposed between the inner electrode layers 30 in the stacking direction T. More preferably, the height difference distance ls2 between the second region EA2 and the first central region EA0 generated by the second inclined portion FA2 in the stacking direction T is greater than the sum Tt (=Te+Tc) of the thickness Te of the inner electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. More preferably, the height difference distance ls2 between the second region EA2 and the first central region EA0 generated by the second inclined portion FA2 in the stacking direction T is more than twice the sum Tt of the thickness Te of the inner electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Furthermore, the height difference distance ls2 between the second region EA2 and the first central region EA0 generated by the second inclined portion FA2 in the stacking direction T can also be more than 3 times the sum of the thickness Te of the stacking direction T of the internal electrode layer 30 and the thickness Tc of the stacking direction T of the dielectric layer 20.

[0157] like Figure 2BAs shown, the height difference distance ls3 between the third region EB1 and the second central region EB0 generated by the third inclined portion FB1 in the stacking direction T is greater than the thickness Tc of the dielectric layer 20 disposed between the inner electrode layers 30 in the stacking direction T. More preferably, the height difference distance ls3 between the third region EB1 and the second central region EB0 generated by the third inclined portion FB1 in the stacking direction T is greater than the sum Tt (=Te+Tc) of the thickness Te of the inner electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. More preferably, the height difference distance ls3 between the third region EB1 and the second central region EB0 generated by the third inclined portion FB1 in the stacking direction T is more than twice the sum Tt of the thickness Te of the inner electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Furthermore, the height difference distance ls3 between the third region EB1 and the second central region EB0 generated by the third inclined portion FB1 in the stacking direction T can also be more than 3 times the sum of the thickness Te of the stacking direction T of the internal electrode layer 30 and the thickness Tc of the stacking direction T of the dielectric layer 20.

[0158] like Figure 2B As shown, the height difference distance ls4 between the fourth region EB2 and the second central region EB0 generated by the fourth inclined portion FB2 in the stacking direction T is greater than the thickness Tc of the dielectric layer 20 disposed between the inner electrode layers 30 in the stacking direction T. More preferably, the height difference distance ls4 between the fourth region EB2 and the second central region EB0 generated by the fourth inclined portion FB2 in the stacking direction T is greater than the sum Tt (=Te+Tc) of the thickness Te of the inner electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer in the stacking direction T. More preferably, the height difference distance ls4 between the fourth region EB2 and the second central region EB0 generated by the fourth inclined portion FB2 in the stacking direction T is more than twice the sum Tt of the thickness Te of the inner electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Furthermore, the height difference distance ls4 between the fourth region EB2 and the second central region EB0 generated by the fourth inclined portion FB2 can also be more than 3 times the sum of the thickness Te of the stacking direction T of the internal electrode layer 30 and the thickness Tc of the stacking direction T of the dielectric layer 20.

[0159] Furthermore, the thickness Te of the stacking direction T of the aforementioned internal electrode layer 30 is the thickness of the internal electrode layer 30 in the stacking direction T at the first central region EA0 and the second central region EB0. The thickness Tc of the stacking direction T of the dielectric layer 20 is the thickness of the dielectric layer 20 disposed between the first central region EA0 and the second central region EB0 in the stacking direction T.

[0160] Thus, the thickness of the internal electrode layer 30 in the first central region EA0 and the second central region EB0 can be thickened using the difference in height generated by the inclined portions, and thus the coverage factor can be sufficiently increased, and the capacitance can be further increased without increasing the size of the multilayer ceramic capacitor 1.

[0161] The difference in height in the stacking direction T between the first region EA1 generated by the first inclined portion FA1 and the first central region EA0 can be 1.6 μm or more, or 1.6 μm or more and 16 μm or less. For example, it can be 2.9 μm or more and 14.8 μm or less. The difference in height in the stacking direction T between the second region EA2 generated by the second inclined portion FA2 and the first central region EA0 can be 1.6 μm or more, or 1.6 μm or more and 16 μm or less. For example, it can be 2.9 μm or more and 14.8 μm or less. The difference in height in the stacking direction T between the third region EB1 generated by the third inclined portion FB1 and the second central region EB0 can be 1.6 μm or more, or 1.6 μm or more and 16 μm or less. For example, it can be 2.9 μm or more and 14.8 μm or less. The difference in height in the stacking direction T between the fourth region EB2 generated by the fourth inclined portion FB2 and the second central region EB0 can be 1.6 μm or more, or 1.6 μm or more and 16 μm or less. For example, it can be 2.9 μm or more and 14.8 μm or less.

[0162] The first internal electrode layer 31 also has a fifth inclined portion FA3 at the first lead-out portion D1. The second internal electrode layer 32 also has a sixth inclined portion FB3 at the second lead-out portion D2.

[0163] Thus, the distance of the path of penetration of moisture from the outside can be ensured to be long, and thus the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1, and the moisture resistance can also be ensured.

[0164] Moisture such as plating solution can penetrate from the interface between the multilayer body 10 and the external electrode layer. By having the fifth inclined portion FA3 and the sixth inclined portion FB3, the distance of the path of penetration from the interface to the end of the internal electrode layer 30 can be made long. Thus, the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1, and the moisture resistance can also be ensured.

[0165] Furthermore, moisture such as plating solution may seep in from the surface of the outer electrode 40 through its thickness direction. By having the fifth inclined portion FA3 and the sixth inclined portion FB3, the end of the inner electrode layer 30 can be positioned near the center of the stacked ceramic capacitor 10, where the thickness of the outer electrode 40 in the length direction L typically tends to increase. Therefore, capacitance can be increased without increasing the size of the stacked ceramic capacitor 1, and moisture resistance can also be ensured.

[0166] Furthermore, by having the fifth inclined portion FA3 and the sixth inclined portion FB3, the distance from the end of the inner electrode layer 30 to the opposing portion of the inner electrode layer 30 can be increased. This increases the distance of the moisture penetration path up to the opposing portion of the inner electrode layer 30. Therefore, capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1, and moisture resistance can also be ensured.

[0167] The tilt angle θ of the first inclined portion FA1 and the second inclined portion FA2 is smaller than the tilt angle θ2 of the fifth inclined portion FA3. That is, the tilt angle θ of the fifth inclined portion FA3 is larger than that of the first inclined portion FA1 and the second inclined portion FA2.

[0168] The tilt angle θ2 of the fifth inclined part FA3 relative to the first central region EA0 or the first region EA1 can be, for example, 10° or more, or 15° or more.

[0169] The tilt angle θ of the third inclined portion FB1 and the fourth inclined portion FB2 is smaller than the tilt angle θ2 of the sixth inclined portion FB3. That is, the tilt angle θ2 of the sixth inclined portion FB3 is larger than the tilt angle θ of the third inclined portion FB1 and the fourth inclined portion FB2.

[0170] The tilt angle θ2 of the sixth inclined part FB3 relative to the second central region EB0 or ​​the third region EB1 can be, for example, 10° or more, or 15° or more.

[0171] In addition, Figure 2B In the above example, the tilt angle θ2 of the sixth tilted portion FB3 in the second inner electrode layer 32 is shown as a representative of the tilt angle θ2. This tilt angle θ2 is relative to the second central region EB0 and the third region EB1.

[0172] Therefore, the distance of the penetration path of external moisture can be ensured to be longer, thus increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1 and also ensuring moisture resistance.

[0173] In addition, such as Figure 2A as well as Figure 2BAs shown, the laminate 10 has an exposed portion Ep exposed from the first external electrode 40A and the second external electrode 40B, a first covered portion Cl covered by the first external electrode 40A, and a second covered portion C2 covered by the second external electrode 40B. The distance LI of the length direction L of the exposed portion Ep exposed from the first external electrode 40A and the second external electrode 40B corresponds to the distance LI between the first external electrode 40A and the second external electrode 40B.

[0174] In the present embodiment, the distance TO of the length direction L of the exposed portion Ep at the center is longer than the maximum distance Tl of the maximum value of the distance of the length direction T of the surface on the first main surface TS1 side and the surface on the second main surface TS2 side as the first covered portion Cl. Also, in the present embodiment, the distance TO of the length direction L of the exposed portion Ep at the center is longer than the maximum distance Tl of the maximum value of the distance of the length direction T of the surface on the first main surface TS1 side and the surface on the second main surface TS2 side as the second covered portion C2. In addition, in the present embodiment, the distance TO of the length direction L of the exposed portion Ep at the center becomes the maximum distance of the length direction T of the exposed portion Ep of the laminate 10.

[0175] Thus, it is possible to suppress the size of the laminate ceramic capacitor 1 from becoming large, and to increase the thickness of the internal electrode layer 30 of the first central region EA0 and the second central region EB0 to improve the coverage ratio, thereby improving the capacitance.

[0176] The distance TO of the length direction L of the exposed portion Ep at the center is preferably 103.2% or less of the maximum distance Tl of the length direction T of the surface on the first main surface TS1 side and the surface on the second main surface TS2 side as the first covered portion Cl. For example, the distance TO of the length direction L of the exposed portion Ep at the center can also be 100.6% or more and 103.2% or less of the maximum distance Tl of the length direction T of the surface on the first main surface TS1 side and the surface on the second main surface TS2 side as the first covered portion Cl. More preferably, the distance TO of the length direction L of the exposed portion Ep at the center can also be 100.6% or more and 102.7% or less of the maximum distance Tl of the length direction T of the surface on the first main surface TS1 side and the surface on the second main surface TS2 side as the first covered portion Cl. In addition, in the present embodiment, the distance of the length direction T of the plane portion PA1 and the plane portion PB1 to be described later becomes the above-mentioned maximum distance Tl.

[0177] The distance T0 in the lamination direction T at the center of the exposed portion Ep along the length L is preferably 103.2% or less of the maximum distance T1 in the lamination direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second covered portion C2. For example, the distance T0 in the lamination direction T at the center of the exposed portion Ep along the length L may also be 100.6% or more and 103.2% or less of the maximum distance T1 in the lamination direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second covered portion C2. More preferably, the distance T0 in the lamination direction T at the center of the exposed portion Ep along the length L may also be 100.6% or more and 102.7% or less of the maximum distance T1 in the lamination direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second covered portion C2. In addition, in this embodiment, the distance in the lamination direction T connecting the planar portion PA2 and the planar portion PB2, described later, is the maximum distance T1 mentioned above.

[0178] The distance T0 at the center of the stacking direction T along the length L of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first external electrode 40A. Furthermore, the distance T0 at the center of the stacking direction T along the length L of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second external electrode 40B.

[0179] Therefore, it is possible to suppress the increase in size of the multilayer ceramic capacitor 1 and increase the thickness of the internal electrode layer 30 of the first central region EA0 and the second central region EB0 to improve the coverage and thus improve the capacitance.

[0180] Furthermore, the ratio of the thickness of the first central region EA0 of the first internal electrode layer 31 in the stacking direction T to the thickness of the first region EA1 in the stacking direction T can be set to be greater than the ratio of the distance T0 of the stacking direction T at the center of the exposed portion Ep in the length direction L of the laminate 10 to the maximum distance T1 of the stacking direction T of the first covered portion C1 of the laminate 10. Similarly, the ratio of the thickness of the second central region EB0 of the second internal electrode layer 32 in the stacking direction T to the thickness of the third region EB1 in the stacking direction T can be set to be greater than the ratio of the distance T0 of the stacking direction T at the center of the exposed portion Ep in the length direction L of the laminate 10 to the maximum distance T1 of the stacking direction T of the second covered portion C2 of the laminate 10.

[0181] like Figure 2A As shown, the first main surface TS1 has a first exposed surface EpsA exposed from the first external electrode 40A and the second external electrode 40B, a first covered surface C1sA covered by the first external electrode 40A, and a second covered surface C2sA covered by the second external electrode 40B.

[0182] As Figure 1 and Figure 2A shown, the first exposed surface EpsA has a first flat surface PA0 parallel to the stacking direction T, a first inclined surface FC1 linking the first flat surface PA0 and a first covered surface C1sA, and a second inclined surface FC2 linking the first flat surface PA0 and a second covered surface C2sA. In the present embodiment, a flat portion PA1 is formed on the stacking body central side of the first covered surface C1sA, and the first inclined surface FC1 links the first flat surface PA0 and the flat portion PA1. Further, a flat portion PA2 is formed on the stacking body central side of the second covered surface C2sA, and the second inclined surface FC2 links the first flat surface PA0 and the flat portion PA2. That is, the first major surface TS1 of the present embodiment has the flat portion PA1 on the first end surface LS1 side, the flat portion PA2 on the second end surface LS2 side, the first flat surface PA0 disposed between the flat portion PA1 and the flat portion PA2 and rising from the flat portion PA1 and the flat portion PA2, the first inclined surface FC1 linking the first flat surface PA0 and the flat portion PA1, and the second inclined surface FC2 linking the first flat surface PA0 and the flat portion PA2.

[0183] As Figure 2A shown, the second major surface TS2 has a second exposed surface EpsB exposed from the first external electrode 40A and the second external electrode 40B, a third covered surface C1sB covered by the first external electrode 40A, and a fourth covered surface C2sB covered by the second external electrode.

[0184] The second exposed surface EpsB has a second flat surface PB0 parallel to the stacking direction T, a third inclined surface FC3 linking the second flat surface PB0 and the third covered surface C1sB, and a fourth inclined surface FC4 linking the second flat surface PB0 and the fourth covered surface C2sB. In the present embodiment, a flat portion PB1 is formed on the stacking body central side of the third covered surface C1sB, and the third inclined surface FC3 links the second flat surface PB0 and the flat portion PB1. Further, a flat portion PB2 is formed on the stacking body central side of the fourth covered surface C2sB, and the fourth inclined surface FC4 links the second flat surface PB0 and the flat portion PB2. That is, the second major surface TS2 of the present embodiment has the flat portion PB1 on the first end surface LS1 side, the flat portion PB2 on the second end surface LS2 side, the second flat surface PB0 disposed between the flat portion PB1 and the flat portion PB2 and rising from the flat portion PB1 and the flat portion PB2, the third inclined surface FC3 linking the second flat surface PB0 and the flat portion PB1, and the fourth inclined surface FC4 linking the second flat surface PB0 and the flat portion PB2.

[0185] Thus, it becomes easy to secure the areas of the first central region EA0 and the second central region EB0 with high coverage rates in correspondence with the first flat surface PA0 or the second flat surface PB0, and it is possible to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1. Furthermore, by forming the flat surfaces, it is possible to suppress adsorption failure at the time of mounting.

[0186] The distance Lt1 in the length direction L of the first inclined surface FC1 and the distance Lt2 in the length direction L of the second inclined surface FC2 are shorter than the distance Lt0 in the length direction L of the first flat surface PA0. The distance Lt1 in the length direction L of the third inclined surface FC3 and the distance Lt2 in the length direction L of the fourth inclined surface FC4 are shorter than the distance Lt0 in the length direction L of the second flat surface PB0.

[0187] Thus, it becomes easy to secure the areas of the first central region EA0 and the second central region EB0 with high coverage rates in correspondence with the first flat surface PA0 or the second flat surface PB0, and it is possible to further increase the capacitance without increasing the size of the multilayer ceramic capacitor 1. Furthermore, by securing the areas of the flat surfaces, it is possible to suppress adsorption failure at the time of mounting.

[0188] In addition, in the present embodiment, the distance Lt0 of the first flat surface PA0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B in the length direction L. Furthermore, the distance Lt0 of the second flat surface PB0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B in the length direction L. As such, it is preferable that the distance Lt0 in the length direction L of the first flat surface PA0 and the second flat surface PB0 be disposed within the range of the distance L1 between the first external electrode 40A and the second external electrode 40B in the length direction L. In addition, the end portion 40AE of the first external electrode 40A can be located at the first inclined surface FC1 and the third inclined surface FC3, or at the flat surface portion PA1 and the flat surface portion PB1 on the first end surface LSI side from the first inclined surface FC1 and the third inclined surface FC3. The end portion 40BE of the second external electrode 40B can be located at the second inclined surface FC2 and the fourth inclined surface FC4, or at the flat surface portion PA2 and the flat surface portion PB2 on the second end surface LS2 side from the second inclined surface FC2 and the fourth inclined surface FC4. In the present embodiment, the end portion 40AE of the first external electrode 40A is located near the boundary portion of the first inclined surface FC1 and the flat surface portion PA1, and near the boundary portion of the third inclined surface FC3 and the flat surface portion PB1. Furthermore, the end portion 40BE of the second external electrode 40B is located near the boundary portion of the second inclined surface FC2 and the flat surface portion PA2, and near the boundary portion of the fourth inclined surface FC4 and the flat surface portion PB2.

[0189] Thus, it is possible to suppress the size of the multilayer ceramic capacitor 1 from becoming large, and to increase the thickness of the internal electrode layer 30 in the first central region EA0 and the second central region EB0 to improve the coverage ratio, thereby improving the capacitance.

[0190] The inclination angle φ of the first inclined surface FC1 with respect to the first flat surface PA0 is preferably 1° or more. For example, the inclination angle φ of the first inclined surface FC1 with respect to the first flat surface PA0 can also be 1° or more and 10° or less. More preferably, the inclination angle φ of the first inclined surface FC1 with respect to the first flat surface PA0 can also be 2° or more and 5° or less.

[0191] The inclination angle φ of the second inclined surface FC2 with respect to the first flat surface PA0 is preferably 1° or more. For example, the inclination angle φ of the second inclined surface FC2 with respect to the first flat surface PA0 can also be 1° or more and 10° or less. More preferably, the inclination angle φ of the second inclined surface FC2 with respect to the first flat surface PA0 can also be 2° or more and 5° or less.

[0192] The inclination angle φ of the third inclined surface FC3 with respect to the second flat surface PB0 is preferably 1° or more. For example, the inclination angle φ of the third inclined surface FC3 with respect to the second flat surface PB0 can also be 1° or more and 10° or less. More preferably, the inclination angle φ of the third inclined surface FC3 with respect to the second flat surface PB0 can also be 2° or more and 5° or less.

[0193] The inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 is preferably 1° or more. For example, the inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 can also be 1° or more and 10° or less. More preferably, the inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 can also be 2° or more and 5° or less.

[0194] In addition, in Figure 2A In the above, as a representative of the inclination angle φ, the inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 in the second main surface TS2 is shown.

[0195] Thus, it is possible to suppress the size of the multilayer ceramic capacitor 1 from becoming large, and to increase the thickness of the internal electrode layer 30 of the first central region EA0 and the second central region EB0 to improve the coverage ratio, thereby increasing the capacitance. Specifically, by setting the inclination angle φ described above to 1° or more, preferably 2° or more, it is possible to secure a region for thickening the thickness of the internal electrode layer 30 of the first central region EA0 and the second central region EB0. Further, by setting the inclination angle φ described above to 10° or less, preferably 5° or less, it is possible to suppress the surface of the laminate 10 from expanding too much in the stacking direction T so as to protrude outward more than the surface of the external electrode 40. More specifically, by setting the inclination angle φ to the range described above, it becomes easy to set the relationship between the thickness of the first central region EA0 and the second central region and the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 within the range of the present embodiment. Further, by setting the inclination angle φ to the range described above, it becomes easy to set the relationship between the distance TO at the center of the exposed portion of the laminate 10 and the maximum distance T1 at the covered portion of the laminate within the range of the present embodiment.

[0196] The first flat surface PA0 is preferably substantially parallel to a surface orthogonal to the stacking direction T. The first flat surface PA0 and the flat portion PA1 and the flat portion PA2 are preferably substantially parallel. More preferably, the first flat surface PA0 and the flat portion PA1 and the flat portion PA2 are substantially parallel to a surface orthogonal to the stacking direction T.

[0197] The second flat surface PB0 is preferably substantially parallel to a surface orthogonal to the stacking direction T. The second flat surface PB0 and the flat portion PB1 and the flat portion PB2 are preferably substantially parallel. More preferably, the second flat surface PB0 and the flat portion PB1 and the flat portion PB2 are substantially parallel to a surface orthogonal to the stacking direction T.

[0198] Thus, as the multilayer ceramic capacitor 1, it is possible to suppress the formation of a portion in which the size locally becomes large, and to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0199] In addition, as Figure 2AThe height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 (the single-side expansion size of the laminate) is preferably smaller than the thickness tg of the first external electrode 40A and the second external electrode 40B arranged on the first main surface TS1 in the stacking direction T. The height tf of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 (the single-side expansion size of the laminate) is preferably smaller than the thickness tg of the first external electrode 40A and the second external electrode 40B arranged on the second main surface TS2 in the stacking direction T.

[0200] Thus, the size of the laminate ceramic capacitor 1 can be suppressed from increasing and the capacitance can be increased.

[0201] The height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is preferably 2.9 μm or more and 14.8 μm or less. The height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 can also be 2.9 μm or more and 12.6 μm or less. The height tf of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 is preferably 2.9 μm or more and 14.8 μm or less. The height tf of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 can also be 2.9 μm or more and 12.6 μm or less.

[0202] The height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is larger than the thickness Tc of the dielectric layer 20 arranged between the internal electrode layers 30 in the stacking direction T. More preferably, the height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is larger than the sum Tt (= Te + Tc) of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Further preferably, the height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is 2 times or more of the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Moreover, the height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 can also be 3 times or more of the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0203] The protrusion height tf of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 is greater than the thickness Tc of the dielectric layer 20 in the stacking direction T. More preferably, the protrusion height tf of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 is greater than the sum Tt (= Te + Tc) of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Further preferably, the protrusion height tf of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 is two times or more the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Furthermore, the protrusion height tf of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 can be three times or more the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0204] Thus, the difference in height generated by the inclined surfaces can be effectively utilized to ensure a region in which the thickness of the internal electrode layer 30 of the first central region EA0 and the second central region EB0 is thickened, thereby sufficiently improving the coverage ratio, and thus the capacitance can be further improved without increasing the size of the multilayer ceramic capacitor 1.

[0205] The thickness t01 in the stacking direction T in the first flat surface PA0 region of the first main surface side outer layer portion 12 is smaller than the thickness t11 in the stacking direction T in the first covered surface C1sA region of the first main surface side outer layer portion 12 and the thickness t21 in the stacking direction T in the second covered surface C2sA region of the first main surface side outer layer portion 12.

[0206] The thickness t02 in the stacking direction T in the second flat surface PB0 region of the second main surface side outer layer portion 13 is smaller than the thickness t12 in the stacking direction T in the third covered surface C1sB region of the second main surface side outer layer portion 13 and the thickness t22 in the stacking direction T in the fourth covered surface C2sB region of the second main surface side outer layer portion 13.

[0207] Thus, by improving the capacitance without increasing the size of the multilayer ceramic capacitor 1 and ensuring a longer distance between the external electrode 40 and the internal electrode layer 30, the concentration of the electric field can be suppressed, and thus the decrease in the reliability of the multilayer ceramic capacitor 1 due to electrolytic concentration can be suppressed.

[0208] Further, by ensuring the distance of the thicknesses t11, t21, t12, t22 to be long, even if a crack of the laminate 10 is assumed to occur in the vicinity of the end of the external electrode 40 such as in the vicinity of the boundary of the exposed portion Ep and the 1st covering portion C1, the 2nd covering portion C2 of the laminate 10, it is possible to suppress the crack from reaching the internal electrode.

[0209] Further, in the present embodiment, by having the inclined surface described above, the flat surface protrusion that is a part of the surface of the laminate 10 is arranged on both the 1st main surface TS1 and the 2nd main surface TS2, but it is also possible to arrange the flat surface protrusion that is a part of the surface of the laminate 10 on either one of the 1st main surface TS1 and the 2nd main surface TS2.

[0210] Further, as shown in Figure 2A , Figure 2B , the thickness of the length direction L at the center of the stacking direction T of the 1st external electrode 40A is thicker than the thickness of the length direction L on the 1st main surface TS1 side of the stacking direction T of the 1st external electrode 40A and the thickness of the length direction L on the 2nd main surface TS2 side of the stacking direction T of the 1st external electrode 40A. Further, as shown in Figure 4A , Figure 4B , the thickness of the length direction L at the center of the width direction W of the 1st external electrode 40A is thicker than the thickness of the length direction L on the 1st side surface WS1 side of the width direction W of the 1st external electrode 40A and the thickness of the length direction L on the 2nd side surface WS2 side of the width direction W of the 1st external electrode 40A.

[0211] Further, as shown in Figure 2A , Figure 2B , the thickness of the length direction L at the center of the stacking direction T of the 2nd external electrode 40B is thicker than the thickness of the length direction L on the 1st main surface TS1 side of the stacking direction T of the 2nd external electrode 40B and the thickness of the length direction L on the 2nd main surface TS2 side of the stacking direction T of the 2nd external electrode 40B. Further, as shown in Figure 4A , Figure 4B , the thickness of the length direction L at the center of the width direction W of the 2nd external electrode 40B is thicker than the thickness of the length direction L on the 1st side surface WS1 side of the width direction W of the 2nd external electrode 40B and the thickness of the length direction L on the 2nd side surface WS2 side of the width direction W of the 2nd external electrode 40B.

[0212] Thus, it is possible to ensure the distance of the immersion path of moisture from the outside to be longer, and thus it is possible to improve the capacitance without increasing the size of the laminate ceramic capacitor 1 and also to ensure the moisture resistance.

[0213] The first internal electrode layer 31 of this embodiment preferably has the above-described first central region EA0 having a higher coverage ratio and a thicker thickness than the first lead-out portion D1, the first region EA1, and the second region EA2 in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111. However, the first internal electrode layer 31 can have the above-described first central region EA0 having a higher coverage ratio and a thicker thickness than the first lead-out portion D1, the first region EA1, and the second region EA2 in at least either one of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113. Thereby, such an effect that the capacitance is increased without increasing the size of the multilayer ceramic capacitor 1 can also be obtained.

[0214] The second internal electrode layer 32 of this embodiment preferably has the above-described second central region EB0 having a higher coverage ratio and a thicker thickness than the second lead-out portion D2, the third region EB1, and the fourth region EB2 in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111. However, the second internal electrode layer 32 can have the above-described second central region EB0 having a higher coverage ratio and a thicker thickness than the second lead-out portion D2, the third region EB1, and the fourth region EB2 in at least either one of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113. Thereby, such an effect that the capacitance is increased without increasing the size of the multilayer ceramic capacitor 1 can also be obtained.

[0215] In addition, in this embodiment, the first inclined portion FA1, the second inclined portion FA2, the third inclined portion FB1, the fourth inclined portion FB2, the fifth inclined portion FA3, and the sixth inclined portion FB3 are arranged in the first main surface side inner layer portion 112 and the second main surface side inner layer portion 113. However, the first inclined portion FA1, the second inclined portion FA2, the third inclined portion FB1, the fourth inclined portion FB2, the fifth inclined portion FA3, and the sixth inclined portion FB3 can be arranged in at least either one of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113.

[0216] The first internal electrode layer 31 of the present embodiment preferably has the above-described first central region EA0 having a higher coverage ratio and a thicker thickness than the first lead-out portion D1, the first region EA1, and the second region EA2 in the first side surface side opposing electrode portion 112E, the second side surface side opposing electrode portion 113E, and the central opposing electrode portion 111E. The present disclosure is not limited thereto, but by having the above-described first central region EA0 having a higher coverage ratio and a thicker thickness than the first lead-out portion D1, the first region EA1, and the second region EA2 in the first side surface side opposing electrode portion 112E and the second side surface side opposing electrode portion 113E in addition to the central opposing electrode portion 111E, it is possible to secure the area of the first central region EA0 having a higher coverage ratio, and thus it is possible to further increase the capacitance without increasing the size of the multilayer ceramic capacitor 1. Alternatively, it is also possible to have the above-described first central region EA0 having a higher coverage ratio and a thicker thickness than the first lead-out portion D1, the first region EA1, and the second region EA2 in at least the central opposing electrode portion 111E.

[0217] The second internal electrode layer 32 of the present embodiment preferably has the above-described second central region EB0 having a higher coverage ratio and a thicker thickness than the second lead-out portion D2, the third region EB1, and the fourth region EB2 in the first side surface side opposing electrode portion 112E, the second side surface side opposing electrode portion 113E, and the central opposing electrode portion 111E. The present disclosure is not limited thereto, but it is also possible to have the above-described second central region EB0 having a higher coverage ratio and a thicker thickness than the second lead-out portion D2, the third region EB1, and the fourth region EB2 in the first side surface side opposing electrode portion 112E and the second side surface side opposing electrode portion 113E in addition to the central opposing electrode portion 111E. It is possible to secure the area of the second central region EB0 having a higher coverage ratio, and thus it is possible to further increase the capacitance without increasing the size of the multilayer ceramic capacitor 1. Alternatively, it is also possible to have the above-described second central region EB0 having a higher coverage ratio and a thicker thickness than the second lead-out portion D2, the third region EB1, and the fourth region EB2 in at least the central opposing electrode portion 111E.

[0218] Figures 5-7 FIG. 6 is one example of a photograph showing a part of the cross section of the multilayer body 10.

[0219] Figure 5 FIG. 6 is one example of a photograph showing a part of the cross section of the multilayer body 10. Figure 5 FIG. 6 is one example of a photograph showing a part of the cross section of the multilayer body 10. Figure 2B FIG. 6 is one example of a photograph showing a part of the cross section of the multilayer body 10. Figure 2B The upper right region, the lower right region, and the lower left region of the multilayer body 10 in FIG. 6 substantially become the same as the upper right region, the lower right region, and the lower left region of the multilayer body 10 in FIG. 5. Figure 5The right upper region shown is a structure that is left-right symmetrical, up-down symmetrical, and rotationally symmetrical. Thus, the photograph of Figure 5 is used to explain the regions. In addition, Figure 5 is a cross-sectional photograph of the laminate 10 in a state in which the external electrode 40 is not provided.

[0220] Figure 6 is a photograph of a portion, VI portion, of the photograph of Figure 5 that contains the first central region EA0 of the first internal electrode layer 31 and the second central region EB0 of the second internal electrode layer 32. Figure 7 is a photograph of a portion, VII portion, of the photograph of Figure 5 that contains the second region EA2 of the first internal electrode layer 31 and the third region EB1 of the second internal electrode layer 32.

[0221] From the optical microscope photograph of Figure 5 , it is confirmed that the laminate 10 has the inner layer portion 11 and the first main surface side outer layer portion 12 composed of the dielectric layer 20.

[0222] From the optical microscope photograph of Figure 5 , in the inner layer portion 11, it is confirmed that the portion in which the first internal electrode layer 31 and the second internal electrode layer 32, which are internal electrode layers 30, are provided. Moreover, from the optical microscope photographs of Figure 6 , Figure 7 , it is confirmed that the dielectric layer 20 is provided between the plurality of internal electrode layers 30.

[0223] From the optical microscope photograph of Figure 5 , it is confirmed that the laminate 10 has regions (EA, EB regions) in which the first opposing portion EA of the first internal electrode layer 31 and the second opposing portion EB of the second internal electrode layer 32 are present, and a region (D2 region) in which the second lead-out portion D2 of the second internal electrode layer 32 is present.

[0224] From the optical microscope photograph of Figure 5 , it is confirmed that the laminate 10 has a region in which the first central region EA0 of the first internal electrode layer 31 and the second central region EB0 of the second internal electrode layer 32 are present, which is shown by the range of the distance Le0, a region in which the second region EA2 of the first internal electrode layer 31 and the third region EB1 of the second internal electrode layer 32 are present, which is shown by the range of the distance Le2, and a region in which the second inclined portion FA2 of the first internal electrode layer 31 and the third inclined portion FB1 of the second internal electrode layer 32 are present, which is shown by the range of the distance Le4. Furthermore, it is confirmed that the sixth inclined portion FB3 is present in the region of the second lead-out portion D2 of the second internal electrode layer 32.

[0225] Further, according to Figure 5 the optical microscope photograph, it is confirmed that the first main surface TS1 of the laminate 10 has the first flat surface PA0 parallel to the stacking direction T, the flat surface part PA2, and the second inclined surface FC2 connecting the first flat surface PA0 and the flat surface part PA2.

[0226] Here, the coverage of the first central region EA0 and the second central region EB0 and the coverage of the second region EA2 and the third region EB1 are compared using Figure 6 , Figure 7 In Figure 6 , Figure 7 , the black linear portions extending in the left-right direction show the dielectric layer 20, and the white linear portions extending in the left-right direction show the internal electrode layer 30. Further, the black portions existing in the middle of the white linear portions extending in the left-right direction show the void portions V in which the metal material does not exist. Thus, the more the white portions, the higher the coverage. In comparison with Figure 7 , it is confirmed that the void portions V are less in Figure 6 . Therefore, it is confirmed that the coverage of the first central region EA0 and the second central region EB0 shown in Figure 6 is higher than the coverage of the second region EA2 and the third region EB1 shown in Figure 7 .

[0227] <Measurement of Various Parameters>

[0228] Hereinafter, the measurement method of various parameters will be described. The various parameters can be measured by the following method.

[0229] <Measurement Method of Thickness of Internal Electrode Layer and Dielectric Layer>

[0230] Hereinafter, the measurement method of the thickness of the stacking direction T of the internal electrode layer 30 of the laminate ceramic capacitor 1 will be described.

[0231] First, the laminate ceramic capacitor 1 is polished from the first side surface WS1 side or the second side surface WS2 side, whereby the LT cross section of the laminate 10 exposing the opposing electrode part 11E is exposed. As needed, the cross section exposing the observation position is subjected to etching treatment, and the internal electrode layer 30 stretched by polishing is removed. The measurement points M1 to M6 shown in Figure 8 are observed using SEM (scanning electron microscope) among the exposed cross sections. Figure 8is a drawing showing one example of an LT cross section of the multilayer ceramic capacitor 1, and is a drawing showing measurement points when the thickness of the internal electrode layer 30 and the thickness of the dielectric layer 20 are measured. Also, for example, in the case where only the first main surface side inner layer portion 112 has the above-described first central region EA0 and the second central region EB0, which have a high coverage ratio and a thick thickness, the measurement points M1 to M3 are observed using an SEM.

[0232] The measurement points M1 to M3 are set in the first main surface side inner layer portion 112. The measurement point M1 is a portion including the first region EA1 of the first internal electrode layer 31 and the fourth region EB2 of the second internal electrode layer 32. The measurement point M2 is a portion including the first central region EA0 of the first internal electrode layer 31 and the second central region EB0 of the second internal electrode layer 32. The measurement point M3 is a portion including the second region EA2 of the first internal electrode layer 31 and the third region EB1 of the second internal electrode layer 32.

[0233] The measurement points M4 to M6 are set in the second main surface side inner layer portion 113. The measurement point M4 is a portion including the first region EA1 of the first internal electrode layer 31 and the fourth region EB2 of the second internal electrode layer 32. The measurement point M5 is a portion including the first central region EA0 of the first internal electrode layer 31 and the second central region EB0 of the second internal electrode layer 32. The measurement point M6 is a portion including the second region EA2 of the first internal electrode layer 31 and the third region EB1 of the second internal electrode layer 32.

[0234] The measurement points M1 and M4 are set at the center positions of the distances Le1 shown in Figure 2B , Figure 8 The measurement points M2 and M5 are set at the center positions of the distances Le0 shown in Figure 2B , Figure 8 The measurement points M3 and M6 are set at the center positions of the distances Le2 shown in Figure 2B , Figure 8 .

[0235] The observation magnification when each measurement point is observed is a magnification at which 4 layers of the dielectric layer 20 and 5 layers of the internal electrode layer 30 can be observed, and is set to a magnification at which the dielectric layer 20 and the internal electrode layer 30 can be clearly distinguished. Figure 9 is a drawing in which an example of an SEM-based enlarged image of an exposed inner layer portion cross section at a measurement point is visualized.

[0236] When the thickness of the internal electrode layer 30 of the multilayer ceramic capacitor 1 is measured, first, as shown in Figure 9As shown, in the magnified image of the cross-section of the multilayer ceramic capacitor 1, five straight lines La to Le, extending in the stacking direction of the multilayer 10, are drawn at equal intervals with a spacing S. The spacing S can be determined to be 5 to 10 times the thickness of the internal electrode layer 30 to be measured. For example, when measuring an internal electrode with a thickness of approximately 0.5 μm, the spacing S is set to 2.5 μm. Next, the thickness of the internal electrode layer 30 is measured on each of the straight lines La to Le. However, if the internal electrode layer is missing on each of the straight lines La to Le, causing the dielectric layer 20 sandwiching the internal electrode layer 30 to be connected to each other, or if the magnified image at the measurement position is unclear, a new straight line is drawn, and the thickness of the internal electrode layer 30 is measured.

[0237] For example, when measuring the thickness of the internal electrode layer 30, such as Figure 9 As shown, the thicknesses d1, d2, d3, d4, and d5 on the straight line La, Lb, Lc, Ld, and Le are measured. Furthermore, for the measurement points in the first main surface inner layer 112 and the second main surface inner layer 113, the thickness of each of the five internal electrode layers 30 is measured using the method described above, and the average value is taken as the thickness of the internal electrode layer 30 in this embodiment. For example, when measuring the thickness of the first central region EA0 and the second central region EB0, the thicknesses of 25 points (5 x 5 layers) are measured at measurement point M2, and the thicknesses of 25 points (5 x 5 layers) are measured at measurement point M5, and the average value of these 50 points is taken as the thickness of the first central region EA0 and the second central region EB0 in this embodiment. For example, when measuring the thickness of region EA1, region EA2, region EB1, and region EB2, the thickness of 25 points at 5 locations × 5 layers is measured at measurement points M1, M3, M4, and M6 respectively, and the average value of the total 100 points is taken as the thickness of region EA1, region EA2, region EB1, and region EB2 in this embodiment.

[0238] Furthermore, the thickness of the dielectric layer 20 is also measured using the same method as that used for the inner electrode layer 30. When measuring the thickness of the dielectric layer 20, such as... Figure 9 As shown, the thicknesses D1, D2, D3, D4, and D5 on the straight line La, Lb, Lc, Ld, and Le are measured.

[0239] Furthermore, the thickness of each of the four dielectric layers 20 is measured at the measurement points in the first main surface inner layer 112 and the second main surface inner layer 113 using the method described above, and the average value is taken as the thickness of the dielectric layer 20 in this embodiment. The thickness of the dielectric layer 20 can be measured in the regions corresponding to the first central region EA0 and the second central region EB0, the regions corresponding to the first region EA1 and the fourth region EB2, and the regions corresponding to the second region EA2 and the third region EB1.

[0240] It can be repeatedly ground and measured at six locations: the center position of the width direction W of the first side-side opposing electrode 112E, the center position of the width direction W of the central opposing electrode 111E, and the center position of the width direction W of the second side-side opposing electrode 113E, respectively, at measurement points M1 to M6.

[0241] In addition, additional measurement points are added depending on the object to be measured. For example, if it is desired to measure the thickness of the internal electrode layer 30 in the first lead-out portion D1 and the second lead-out portion D2 in the stacking direction T, a portion including the object to be measured is added as a measurement point. In this case, the measurement is performed using the same method as described above.

[0242] <Methods for measuring coverage>

[0243] A method for measuring the coverage of the internal electrode layer 30 relative to the dielectric layer 20, known as the coverage ratio, will be described. Furthermore, the measurement of coverage in this method is also referred to as the measurement of line coverage.

[0244] In the aforementioned exposed LT profile, line coverage was measured using an optical microscope. The measurement points for line coverage were based on... Figure 8 The measurement points M1 to M6 are shown. However, the magnification for observing each measurement point is set to 1000x.

[0245] like Figure 6 , Figure 7 As shown, the internal electrode layer 30 has regions containing conductive components and regions without conductive components, such as the void portion V. Regarding line coverage, in Figure 6 , Figure 7In the optical microscope image shown, the length of the length direction L of the region occupied by the conductive component actually constituting the internal electrode layer 30 is calculated with respect to the length of the length direction L of the internal electrode layer 30 regardless of the presence or absence of the conductive component, that is, the length of the length direction L excluding the region in which the conductive component is not present is calculated with respect to the length of the length direction L of the internal electrode layer 30 regardless of the presence or absence of the conductive component. Also, with respect to the measurement points in the internal layer portion 112 on the first main surface side and the measurement points in the internal layer portion 113 on the second main surface side, the coverage of the internal electrode layer 30 is measured respectively, and the average thereof is taken as the coverage of the internal electrode layer 30 in the present embodiment. For example, in measuring the coverage of the first central region EA0 and the second central region EB0, with respect to the measurement point M2 and the measurement point M5, the coverage of the internal electrode layer 30 is measured respectively, and the average thereof is taken as the coverage of the first central region EA0 and the second central region EB0 in the present embodiment. For example, in measuring the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2, at the measurement points M1, M3, M4, M6, the coverage of the internal electrode layer 30 is measured respectively, and the average thereof is taken as the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 in the present embodiment.

[0246] In addition, depending on the measurement object to be measured, a measurement point is added. For example, in the case where the coverage of the first lead-out portion D1 and the second lead-out portion D2 is to be measured, a portion including the measurement object is added as a measurement point. In this case, measurement is also performed by the same method as the above-described method.

[0247] <Measurement method of distance and angle>

[0248] Measurement of various distances and angles is performed using the exposed LT profile described above. Measurement of distances and angles is performed using a digital microscope.

[0249] <Manufacturing method>

[0250] Next, the manufacturing method of the multilayer ceramic capacitor 1 of the present embodiment will be described. The manufacturing method of the multilayer ceramic capacitor 1 of the present embodiment is not limited as long as the above-described requirements are satisfied. However, the preferred manufacturing method has the following processes. Details of each process will be described below.

[0251] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode layer 30 include a binder and a solvent. The binder and the solvent can also be publicly known binders and solvents.

[0252] On a dielectric sheet, conductive paste for the inner electrode layer 30 is printed in a given pattern, for example, by screen printing, gravure printing, or the like. Thus, a dielectric sheet having a pattern of the first inner electrode layer 31 and a pattern of the second inner electrode layer 32 is prepared. Furthermore, the printing method is not limited to screen printing, etc.

[0253] Here, utilizing Figure 10 , Figure 11 The printing method for printing conductive paste for the internal electrode layer 30 onto the dielectric sheet is described.

[0254] like Figure 11 As shown, the dielectric sheet printed with the pattern of the internal electrode layer 30 is composed of a ceramic green sheet G and conductive pastes P1 and P2 disposed on the ceramic green sheet G. Conductive pastes P1 and P2 are formed by the hollow portions of screen S1 and screen S2.

[0255] First, such as Figure 10 As shown, conductive paste P1 is disposed on a ceramic green sheet G using a screen S1 having a hollow portion formed by a pattern corresponding to the outer shape of the first internal electrode layer 31 and the second internal electrode layer 32.

[0256] Next, as Figure 11 As shown, conductive paste P2 is screen-printed onto conductive paste P1 using a screen S2 having hollow portions formed by patterns corresponding to the first central region EA0 and the second central region EB0. Consequently, the portions corresponding to the first central region EA0 and the second central region EB0 are thicker than the other regions.

[0257] Specifically, the portions corresponding to the first central region EA0 and the second central region EB0 are thicker than the portions corresponding to the first lead-out section D1, the second lead-out section D2, the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. Therefore, the first central region EA0 and the second central region EB0 become high-coverage regions with higher coverage than the first lead-out section D1, the second lead-out section D2, the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. Furthermore, the first lead-out section D1 and the second lead-out section D2 have substantially the same thickness and substantially the same coverage as the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2.

[0258] Here, for example Figure 11The right side portion of the conductive paste P1 and the conductive paste P2 shown is a portion P31 that becomes the first internal electrode layer 31 of the multilayer ceramic capacitor, and the left side portion is a portion P32 that becomes the second internal electrode layer 32 of another multilayer ceramic capacitor. The dielectric sheet is prepared like this.

[0259] The dielectric sheet on which the pattern of the internal electrode layer 30 is not printed is laminated for a given number of sheets, thereby forming a portion P12 that becomes the first main surface side outer layer portion 12 on the first main surface TS1 side.

[0260] Next, as shown in FIG. 6, a dielectric sheet on which the internal electrode layer 30 is printed is laminated on the surface of the portion P12 that becomes the first main surface side outer layer portion 12, thereby forming a portion P12 that becomes the first main surface side outer layer portion 12 on the first main surface TS1 side. Figure 12 Figure 11 The dielectric sheet on which the internal electrode layer 30 is printed is laminated on the surface of the portion P12 that becomes the first main surface side outer layer portion 12, thereby forming a portion P12 that becomes the first main surface side outer layer portion 12 on the first main surface TS1 side. Figure 12 If the portion surrounded by C in FIG. 7 is focused on, the dielectric sheet G1 on which the conductive paste P31 that becomes the first internal electrode layer 31 is arranged and the dielectric sheet G2 on which the conductive paste P32 that becomes the second internal electrode layer 32 is arranged are alternately laminated in this order. In addition, the portion of C in FIG. 7 is cut out in the subsequent process to constitute one multilayer chip. Figure 12

[0261] By laminating the dielectric sheet on which the pattern of the internal electrode layer 30 is not printed for a given number of sheets on the surface of the portion P11 that becomes the inner layer portion 11, a portion P13 that becomes the second main surface side outer layer portion 13 on the second main surface TS2 side is formed. Thus, a laminated sheet is produced.

[0262] By pressing the laminated sheet in the height direction by isostatic pressing or the like, a laminated block is produced.

[0263] By cutting the laminated block to a given size, a multilayer chip is cut out. At this time, the corners and the edge portions of the multilayer chip can be rounded by barrel polishing or the like.

[0264] By firing the multilayer chip, a multilayer body 10 is produced. The firing temperature also depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower. Here, by adjusting the thickness of the conductive paste for the internal electrode layer 30 according to the region and adjusting the pressing conditions and the firing conditions, a multilayer body 10 having the configuration of the internal electrode layer 30 and the surface shapes of the first main surface TS1 and the second main surface TS2 of the present embodiment can be obtained. For example, by adjusting the application state including the thickness of the conductive paste for the internal electrode layer 30 and the pressing conditions, a tilted portion such as the first tilted portion FA1 having a decreasing thickness can be formed, and the internal electrode layer 30 of the present embodiment can be obtained.

[0265] ​​A conductive paste that becomes the base electrode layer is applied to both end surfaces of the laminate 10.

[0266] In the present embodiment, the conductive paste is also applied to the first main surface TS1 and the second main surface TS2 and the first side surface WS1 and the second side surface WS2 of the laminate 10. At this time, the conductive paste is applied so that the distance L1 between the first external electrode 40A and the second external electrode 40B is longer than the distance Lt0 in the length direction L of the first central region EA0 and the second central region EB0.

[0267] One example of a more specific manufacturing method will be described. The first flat surface PA0 and the second flat surface PB0 are present on the first main surface TS1 or the second main surface TS2 of the laminate 10 in correspondence with the positions of the first central region EA0 and the second central region EB0. Further, the first inclined surface FC1, the second inclined surface FC2, the third inclined surface FC3, and the fourth inclined surface FC4 are formed around them. Furthermore, the flat surface portions PA1, PA2, PB1, and PB2 are formed on the end surface side of each of the inclined surfaces.

[0268] Therefore, for example, the conductive paste is applied to the flat surface portions PA1, PA2, PB1, and PB2 on the end surface side of each of the inclined surfaces. The conductive paste is applied to the laminate 10 as described above, whereby the conductive paste is applied so that the distance L1 between the first external electrode 40A and the second external electrode 40B is longer than the distance Lt0 in the length direction L of the first central region EA0 and the second central region EB0. In addition, the conductive paste can also be applied to a part of the end surface side of the first inclined surface FC1, the second inclined surface FC2, the third inclined surface FC3, and the fourth inclined surface FC4.

[0269] In addition, the above is one example of a manufacturing method, and is not limited thereto. Further, the base electrode layer can also be removed and adjusted after the firing process.

[0270] In the present embodiment, the base electrode layer is a fired layer. A conductive paste containing a glass component and a metal is applied to the laminate 10, for example, by a method such as dipping. Then, a firing process is performed, and the base electrode layer is formed. The temperature of the firing process at this time is preferably 700°C or higher and 900°C or lower.

[0271] In addition, in the case where the laminate chip before firing and the conductive paste applied to the laminate chip are simultaneously fired, the fired layer is preferably formed by firing a paste to which a ceramic material is added instead of a glass component. At this time, as the added ceramic material, it is particularly preferable to use the same kind of ceramic material as the dielectric layer 20. In this case, the conductive paste is applied to the laminate chip before firing, and the laminate chip and the conductive paste applied to the laminate chip are simultaneously fired, thereby forming the laminate 10 in which the fired layer is formed.

[0272] Then, a plating layer is formed on the surface of the base electrode layer. In the present embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Further, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In the present embodiment, as the plating layer, a Ni plating layer and a Sn plating layer are formed. When plating treatment is performed, either electrolytic plating or electroless plating can be employed. However, with electroless plating, in order to increase the plating deposition rate, pretreatment using a catalyst or the like is required, and thus there is a disadvantage in that the process is complicated. Therefore, electrolytic plating is generally preferred. The Ni plating layer and the Sn plating layer are formed in sequence, for example, by barrel plating.

[0273] In addition, in the case where a conductive resin layer is provided as the base electrode layer, the conductive resin layer can be configured to cover the fired layer. In the case where a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and a metal component is applied to the fired layer, and then heat treatment is performed at a temperature of 250 to 550°C or higher. Thereby, the thermosetting resin is thermoset, and thus the conductive resin layer is formed. The atmosphere at the time of the heat treatment is preferably a N2 atmosphere. Further, in order to prevent scattering of the resin and oxidation of the various metal components, the oxygen concentration is preferably 100 ppm or lower.

[0274] By such a manufacturing process, the multilayer ceramic capacitor 1 can be manufactured.

[0275] <2nd Embodiment>

[0276] The multilayer ceramic capacitor 1 according to the first embodiment increases the size in the stacking direction T of the internal electrode layer 30 in order to increase the capacitance without increasing the size of the multilayer ceramic capacitor. More specifically, the first internal electrode layer 31 has the above-described first central region EA0 having a high coverage ratio and a thick thickness compared to the first lead D1, the first region EA1, and the second region EA2, at least in either one of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113, and the second internal electrode layer 32 has the above-described second central region EB0 having a high coverage ratio and a thick thickness compared to the second lead D2, the third region EB1, and the fourth region EB2, at least in either one of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113.

[0277] In the present embodiment, in order to further increase the capacitance without increasing the size of the multilayer ceramic capacitor, the size of the width direction W of the internal electrode layer 30 is increased. Specifically, the first internal electrode layer 31 has a first central region EA0 that is longer in the width direction W than the first lead-out portion D1, the first region EA1, and the second region EA2, and a second central region EB0 that is longer in the width direction W than the second lead-out portion D2, the third region EB1, and the fourth region EB2. The distance in the width direction W of at least the first central region EA0 is longer than the distance in the width direction W of the first lead-out portion D1, and the distance in the width direction W of the second central region EB0 is longer than the distance in the width direction W of the second lead-out portion D2. According to such a structure, the effects of the present disclosure can be more effectively obtained.

[0278] Hereinafter, the multilayer ceramic capacitor 1 according to the second embodiment will be described with reference to Figures 2A-3 , Figures 13-14B In the following description, with respect to the same structure as the first embodiment, sometimes the description is made by using the drawings used in the description of the first embodiment. Further, sometimes the reference numerals used in the description of the first embodiment are annotated and detailed description is omitted. Figure 13 is a perspective view of the multilayer ceramic capacitor according to the second embodiment. Figure 14A is a view of the multilayer ceramic capacitor according to the second embodiment, which corresponds to Figure 4A . Figure 14B is a view of the multilayer ceramic capacitor according to the second embodiment, which corresponds to Figure 4B .

[0279] As shown in Figure 2A , Figure 2B , and Figure 3 , the multilayer body 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0280] The inner layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers alternately stacked in the stacking direction T.

[0281] Further, the thickness of the inner layer portion 11 in the stacking direction T varies along the length direction L in conjunction with the shape of the internal electrode layer 30 located closest to the first main surface TS1 side and the shape of the internal electrode layer 30 located closest to the second main surface TS2 side. The size of the width direction W of the inner layer portion 11 varies along the shape of the end of the first side surface WS1 side of the plurality of internal electrode layers 30 and the shape of the end of the second side surface WS2 side of the plurality of internal electrode layers 30 throughout the entire length of the length direction L of the inner layer portion 11.

[0282] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 as a plurality of first internal conductor layers, and a plurality of second internal electrode layers 32 as a plurality of second internal conductor layers.

[0283] As shown in Figure 2A , Figure 14A , the first internal electrode layer 31 has the first opposing portion EA and the first lead-out portion D1. As shown in Figure 2A , Figure 14B , the second internal electrode layer 32 has the second opposing portion EB and the second lead-out portion D2.

[0284] The width direction W dimension of the first central region EA0 among the first opposing portion EA is formed to be larger than the width direction W dimension of the first lead-out portion D1. The width direction W dimension of the second central region EB0 among the second opposing portion EB is formed to be larger than the width direction W of the second lead-out portion D2.

[0285] The width direction W dimension of the first central region EA0 among the first opposing portion EA is formed to be larger than the width direction W dimension of the first region EA1 and the second region EA2. The width direction W dimension of the second central region EB0 among the second opposing portion EB is formed to be larger than the width direction W dimension of the third region EB1 and the fourth region EB2.

[0286] In addition, the laminate 10 has the opposing electrode portion 11E. The opposing electrode portion 11E is a portion in which the first opposing portion EA of the first internal electrode layer 31 and the second opposing portion EB of the second internal electrode layer 32 are opposed to each other. The opposing electrode portion 11E is configured as a part of the inner layer portion 11. In Figure 14A and Figure 14B , the range of the width direction W and the length direction L of the opposing electrode portion 11E is shown. The width direction W dimension of the opposing electrode portion 11E varies along the shape of the end of the first side surface WS1 side of the plurality of internal electrode layers 30 and the shape of the end of the second side surface WS2 side of the plurality of internal electrode layers 30 throughout the length direction L full length of the opposing electrode portion 11E.

[0287] In addition, the laminate 10 has a side surface side outer layer portion. The side surface side outer layer portion has a first side surface side outer layer portion WG1 and a second side surface side outer layer portion WG2.

[0288] The width direction W dimension of the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 is formed to be substantially fixed throughout the length direction L full length, regardless of the shape of the end of the first side surface WS1 side of the plurality of internal electrode layers 30 and the shape of the end of the second side surface WS2 side of the plurality of internal electrode layers 30. However, the width direction W dimension of the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 can also be substantially fixed without being throughout the length direction L full length.

[0289] Further, the shapes of the 1st-side-outer-layer portion WG1 and the 2nd-side-outer-layer portion WG2 are formed along the shape of the end of the 1st side WS1 side of the plurality of internal electrode layers 30 and the shape of the end of the 2nd side WS2 side of the plurality of internal electrode layers 30 throughout the entire length in the length direction L. Therefore, the shape of a portion of the 1st-side-outer-layer portion WG1 and the 2nd-side-outer-layer portion WG2 is curved in the width direction W.

[0290] As shown in FIG. 1, the internal electrode layer 30 has a plurality of internal electrode layers 30A and 30B. The internal electrode layer 30A is a portion of the internal electrode layer 30 on the 1st side WS1 side. The internal electrode layer 30B is a portion of the internal electrode layer 30 on the 2nd side WS2 side. Figures 2A-3 As shown in FIG. 1, the internal electrode layer 30 has a plurality of internal electrode layers 30A and 30B. The internal electrode layer 30A is a portion of the internal electrode layer 30 on the 1st side WS1 side. The internal electrode layer 30B is a portion of the internal electrode layer 30 on the 2nd side WS2 side.

[0291] As shown in FIG. 1, the internal electrode layer 30 has a plurality of internal electrode layers 30A and 30B. The internal electrode layer 30A is a portion of the internal electrode layer 30 on the 1st side WS1 side. The internal electrode layer 30B is a portion of the internal electrode layer 30 on the 2nd side WS2 side. Figure 3 , Figure 14A , Figure 14B As shown in FIG. 1, the internal electrode layer 30 has a plurality of internal electrode layers 30A and 30B. The internal electrode layer 30A is a portion of the internal electrode layer 30 on the 1st side WS1 side. The internal electrode layer 30B is a portion of the internal electrode layer 30 on the 2nd side WS2 side.

[0292] The 1st-side-counter-electrode portion 112E is a portion of the counter-electrode portion 11E on the 1st side WS1 side. The regions of the 1st-side-counter-electrode portion 112E corresponding to the 1st central region EA0 and the 2nd central region EB0 are configured to be widened toward the 1st side WS1 side in the width direction W. The regions of the 2nd-side-counter-electrode portion 113E corresponding to the 1st central region EA0 and the 2nd central region EB0 are configured to be widened toward the 2nd side WS2 side in the width direction W.

[0293] Further, only one of the 1st-side-counter-electrode portion 112E and the 2nd-side-counter-electrode portion 113E can be configured to be widened toward the 1st side WS1 side or the 2nd side WS2 side in the regions corresponding to the 1st central region EA0 and the 2nd central region EB0.

[0294] Next, details of the internal electrode layer 30 will be described. Figure 2B , Figures 14A-14B Next, details of the internal electrode layer 30 will be described.

[0295] The first opposing portion EA has a first region EA1, a second region EA2, and a first central region EA0. The first region EA1 is disposed on the first end surface LSI side. The second region EA2 is disposed on the second end surface LS2 side. The first central region EA0 is located between the first region EA1 and the second region EA2. The coverage ratio of the first central region EA0 is higher than the coverage ratio of the first region EA1 and the second region EA2. Further, as shown in Figure 2B the first central region EA0 is disposed more outward of the laminate 10 than the first region EA1 and the second region EA2. Also, the coverage ratio of the first central region EA0, which is the first high-coverage region, is higher than the coverage ratio of the first lead-out portion D1. The first central region EA0 is disposed more outward of the laminate 10 than the first lead-out portion D1.

[0296] Specifically, in the first main surface side inner layer portion 112, the first central region EA0 of the first internal electrode layer 31 is disposed more on the first main surface TS1 side of the laminate 10 than the first lead-out portion D1, the first region EA1, and the second region EA2. Further, in the present embodiment, in the second main surface side inner layer portion 113, the first central region EA0 of the first internal electrode layer 31 is disposed more on the second main surface TS2 side of the laminate 10 than the first lead-out portion D1, the first region EA1, and the second region EA2. Alternatively, in at least either the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113, the first central region EA0 can be disposed more outward of the laminate 10 than the first lead-out portion D1, the first region EA1, and the second region EA2.

[0297] Further, as shown in Figure 14A , Figure 14B the distance TE0 in the width direction W of the first central region EA0 is longer than the distance TE1 in the width direction W of the first region EA1 and the second region EA2. Specifically, in the width direction W, a portion on the first side surface WS1 side among the first central region EA0 is disposed more outward of the laminate 10 than the end on the first side surface WS1 side among the first region EA1 and the second region EA2. Further, in the width direction W, a portion on the second side surface WS2 side among the first central region EA0 is disposed more outward of the laminate 10 than the end on the second side surface WS2 side among the first region EA1 and the second region EA2. Further, the distance TE0 in the width direction W of the first central region EA0 is longer than the distance TE1 in the width direction W of the first lead-out portion D1. The distance TE1 in the width direction W of the first lead-out portion D1 can be the same as the distance TE1 in the width direction W of the first region EA1 and the second region EA2.

[0298] In addition, it can also be that only either one of a portion of the first side surface WS1 side and a portion of the second side surface WS2 side in the first central region EA0 is disposed on the outside of the laminate 10 compared to the end of the first side surface WS1 side or the end of the second side surface WS2 side in the first region EA1 and the second region EA2.

[0299] The second opposing portion EB has a third region EB1, a fourth region EB2, and a second central region EB0. The third region EB1 is disposed on the second end surface LS2 side. The fourth region EB2 is disposed on the first end surface LSI side. The second central region EB0 is located between the third region EB1 and the fourth region EB2. The coverage of the second central region EB0 is higher than the coverage of the third region EB1 and the fourth region EB2. Further, as shown in FIG. 2, the second central region EB0 is disposed more on the outside of the laminate 10 compared to the third region EB1 and the fourth region EB2. Also, the coverage of the second central region EB0 as the second high-coverage region is higher than the coverage of the second lead-out portion D2. The second central region EB0 is disposed more on the outside of the laminate 10 compared to the second lead-out portion D2. Figure 2B

[0300] Specifically, in the first main surface side inner layer portion 112, the second central region EB0 of the second internal electrode layer 32 is disposed more on the first main surface TS1 side of the laminate 10 compared to the second lead-out portion D2, the third region EB1, and the fourth region EB2. Further, in the present embodiment, in the second main surface side inner layer portion 113, the second central region EB0 of the second internal electrode layer 32 is disposed more on the second main surface TS2 side of the laminate 10 compared to the second lead-out portion D2, the third region EB1, and the fourth region EB2. In addition, it can also be that, in at least either one of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113, the second central region EB0 is disposed more on the outside of the laminate 10 compared to the second lead-out portion D2, the third region EB1, and the fourth region EB2.

[0301] Further, as shown in FIG. 2, Figure 14A Figure 14B ​​As shown, the distance TEO of the second central region EB0 in the width direction W is longer than the distance TE1 of the third region EB1 and the fourth region EB2 in the width direction W. Specifically, in the width direction W, a portion of the first side surface WS1 side in the second central region EB0 is disposed outside the laminate 10 compared to the end of the first side surface WS1 side in the third region EB1 and the fourth region EB2. Further, in the width direction W, a portion of the second side surface WS2 side in the second central region EB0 is disposed outside the laminate 10 compared to the end of the second side surface WS2 side in the third region EB1 and the fourth region EB2. The distance TEO of the second central region EB0 in the width direction W is longer than the distance TE1 of the second lead portion D2 in the width direction W. The distance TE1 of the second lead portion D2 in the width direction W can also be the same as the distance TE1 of the third region EB1 and the fourth region EB2 in the width direction W.

[0302] In addition, it can also be that only either of the portion of the first side surface WS1 side and the portion of the second side surface WS2 side in the second central region EB0 is disposed outside the laminate 10 compared to the end of the first side surface WS1 side or the end of the second side surface WS2 side in the third region EB1 and the fourth region EB2.

[0303] Thus, the area of the opposing electrode portion 11E can be ensured to be large, and further, the areas of the first central region EA0 and the second central region EB0, which have high coverage, can be appropriately ensured, and thus the capacitance can be increased.

[0304] Further, as shown in FIG. 1, the laminate 10 has a first external electrode 40A and a second external electrode 40B. The first external electrode 40A is disposed on the first surface 10S1 side of the laminate 10. The second external electrode 40B is disposed on the second surface 10S2 side of the laminate 10. Figure 2A Figure 2B As shown, the laminate 10 has an exposed portion Ep that is exposed from the first external electrode 40A and the second external electrode 40B, a first covered portion C1 that is covered by the first external electrode 40A, and a second covered portion C2 that is covered by the second external electrode 40B.

[0305] In the present embodiment, the distance T0 of the laminate direction T at the center of the length direction L of the exposed portion Ep is longer than the maximum distance T1 that is the maximum value of the distance of the laminate direction T of the surface on the first main surface TS1 side and the surface on the second main surface TS2 side that connects the first external electrode 40A. Further, in the present embodiment, the distance T0 of the laminate direction T at the center of the length direction L of the exposed portion Ep is longer than the maximum distance T1 that is the maximum value of the distance of the laminate direction T of the surface on the first main surface TS1 side and the surface on the second main surface TS2 side that connects the second external electrode 40B. In addition, in the present embodiment, the distance T0 of the laminate direction T at the center of the length direction L of the exposed portion Ep becomes the maximum distance of the laminate direction T at the exposed portion Ep of the laminate 10.

[0306] ​The distance TW0 in the width direction W at the center of the exposed portion Ep along the length direction L is longer than the maximum distance TW1 in the width direction W of the surface connecting the first side WS1 and the second side WS2 of the first covered portion C1. The distance TW0 in the width direction W at the center of the exposed portion Ep along the length direction L is also longer than the maximum distance TW1 in the width direction W of the surface connecting the first side WS1 and the second side WS2 of the second covered portion C2. Furthermore, in this embodiment, the distance TW0 in the width direction W at the center of the exposed portion Ep along the length direction L is the maximum distance in the width direction W at the exposed portion Ep of the laminate 10.

[0307] Therefore, the area of ​​the counter electrode portion 11E can be ensured to be large, thereby ensuring the area of ​​the first central region EA0 and the second central region EB0 with high coverage, thus improving the capacitance.

[0308] The distance T0 at the center of the stacking direction T along the length L of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first external electrode 40A. Furthermore, the distance T0 at the center of the stacking direction T along the length L of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second external electrode 40B.

[0309] The distance TW0 at the center of the exposed portion Ep in the length direction L is shorter than the maximum value TW2 of the width direction W of the surface of the first external electrode 40A connecting the first side surface WS1 and the second side surface WS2. Furthermore, the distance TW0 at the center of the exposed portion Ep in the length direction L is shorter than the maximum value TW2 of the width direction W of the surface of the second external electrode 40B connecting the first side surface WS1 and the second side surface WS2.

[0310] Therefore, the area of ​​the counter electrode portion 11E can be ensured to be large, thereby ensuring the area of ​​the first central region EA0 and the second central region EB0 with high coverage, thus improving the capacitance.

[0311] like Figure 2A As shown, the first main surface TS1 has a first exposed surface EpsA exposed from the first external electrode 40A and the second external electrode 40B, a first covered surface C1sA covered by the first external electrode 40A, and a second covered surface C2sA covered by the second external electrode 40B.

[0312] like Figure 1 as well as Figure 2AAs shown, the first exposed surface EpsA has a first flat surface PA0 parallel to the stacking direction T, a first inclined surface FC1 linking the first flat surface PA0 and a first covered surface C1sA, and a second inclined surface FC2 linking the first flat surface PA0 and a second covered surface C2sA. In the present embodiment, a flat portion PA1 is formed on the stacking body central side of the first covered surface C1sA, and the first inclined surface FC1 links the first flat surface PA0 and the flat portion PA1. Further, a flat portion PA2 is formed on the stacking body central side of the second covered surface C2sA, and the second inclined surface FC2 links the first flat surface PA0 and the flat portion PA2.

[0313] That is, the first main surface TS1 of the present embodiment has the flat portion PA1 on the first end surface LSI side, the flat portion PA2 on the second end surface LS2 side, the first flat surface PA0 disposed between the flat portion PA1 and the flat portion PA2 and rising from the flat portion PA1 and the flat portion PA2, the first inclined surface FC1 linking the first flat surface PA0 and the flat portion PA1, and the second inclined surface FC2 linking the first flat surface PA0 and the flat portion PA2.

[0314] As shown, the second main surface TS2 has a second exposed surface EpsB exposed from the first external electrode 40A and the second external electrode 40B, a third covered surface C1sB covered by the first external electrode 40A, and a fourth covered surface C2sB covered by the second external electrode. Figure 2A

[0315] The second exposed surface EpsB has a second flat surface PB0 parallel to the stacking direction T, a third inclined surface FC3 linking the second flat surface PB0 and the third covered surface C1sB, and a fourth inclined surface FC4 linking the second flat surface PB0 and the fourth covered surface C2sB. In the present embodiment, a flat portion PB1 is formed on the stacking body central side of the third covered surface C1sB, and the third inclined surface FC3 links the second flat surface PB0 and the flat portion PB1. Further, a flat portion PB2 is formed on the stacking body central side of the fourth covered surface C2sB, and the fourth inclined surface FC4 links the second flat surface PB0 and the flat portion PB2.

[0316] That is, the second main surface TS2 of the present embodiment has the flat portion PB1 on the first end surface LSI side, the flat portion PB2 on the second end surface LS2 side, the second flat surface PB0 disposed between the flat portion PB1 and the flat portion PB2 and rising from the flat portion PB1 and the flat portion PB2, the third inclined surface FC3 linking the second flat surface PB0 and the flat portion PB1, and the fourth inclined surface FC4 linking the second flat surface PB0 and the flat portion PB2.

[0317] As shown, the second main surface TS2 has a second exposed surface EpsB exposed from the first external electrode 40A and the second external electrode 40B, a third covered surface C1sB covered by the first external electrode 40A, and a fourth covered surface C2sB covered by the second external electrode. Figure 14A and​Figure 14B As shown, the first side WS1 has a first side exposed surface EWpsA exposed from the first external electrode 40A and the second external electrode 40B, a first side covered surface CW1sA covered by the first external electrode 40A, and a second side covered surface CW2sA covered by the second external electrode 40B.

[0318] The first side exposed surface EWpsA has a first side flat surface PWA0 parallel to the width direction W, a first side inclined surface FWC1 connecting the first side flat surface PWA0 and the first side covered surface CW1sA, and a second side inclined surface FWC2 connecting the first side flat surface PWA0 and the second side covered surface CW2sA.

[0319] In this embodiment, a planar portion PWA1 is formed on the central side of the laminate of the first side-covered surface CW1sA, and the first side-inclined surface FWC1 connects the first side-flat surface PWA0 and the planar surface PWA1. Furthermore, a planar portion PWA2 is formed on the central side of the laminate of the second side-covered surface CW2sA, and the second side-inclined surface FWC2 connects the first side-flat surface PWA0 and the planar surface PWA2.

[0320] That is, the first side surface WS1 of this embodiment has a planar portion PWA1 on the first end surface LS1 side, a planar portion PWA2 on the second end surface LS2 side, a first side surface flat surface PWA0 disposed between the planar portion PWA1 and the planar portion PWA2 and raised from the planar portion PWA1 and the planar portion PWA2, a first side surface inclined surface FWC1 connecting the first side surface flat surface PWA0 and the planar surface PWA1, and a second side surface inclined surface FWC2 connecting the first side surface flat surface PWA0 and the planar surface PWA2.

[0321] like Figure 14A as well as Figure 14B As shown, the second side WS2 has a second side exposed surface EWpsB exposed from the first external electrode 40A and the second external electrode 40B, a third side covered surface CW1sB covered by the first external electrode 40A, and a fourth side covered surface CW2sB covered by the second external electrode 40B.

[0322] The 2nd-side surface side exposed surface EWpsB has a 2nd-side surface side flat surface PWB0 parallel to the width direction W, a 3rd-side surface side inclined surface FWC3 connecting the 2nd-side surface side flat surface PWB0 and the 3rd-side surface side covered surface CW1sB, and a 4th-side surface side inclined surface FWC4 connecting the 2nd-side surface side flat surface PWB0 and the 4th-side surface side covered surface CW2sB. In the present embodiment, a flat portion PWB1 is formed on the laminate central side of the 3rd-side surface side covered surface CW1sB, and the 3rd-side surface side inclined surface FWC3 connects the 2nd-side surface side flat surface PWB0 and the flat portion PWB1. Further, a flat portion PWB2 is formed on the laminate central side of the 4th-side surface side covered surface CW2sB, and the 4th-side surface side inclined surface FWC4 connects the 2nd-side surface side flat surface PWB0 and the flat portion PWB2.

[0323] That is, the 2nd-side surface WS2 of the present embodiment has a flat portion PWB1 on the 1st-end surface LS1 side, a flat portion PWB2 on the 2nd-end surface LS2 side, a 2nd-side surface side flat surface PWB0 disposed between the flat portion PWB1 and the flat portion PWB2 and rising from the flat portion PWB1 and the flat portion PWB2, a 3rd-side surface side inclined surface FWC3 connecting the 2nd-side surface side flat surface PWB0 and the flat portion PWB1, and a 4th-side surface side inclined surface FWC4 connecting the 2nd-side surface side flat surface PWB0 and the flat portion PWB2.

[0324] Thus, the area of the opposing electrode portion 11E can be ensured to be large, and further, the areas of the 1st-central region EA0 and the 2nd-central region EB0, which have high coverage, can be appropriately ensured, so that the capacitance can be increased. Further, by forming the flat surfaces, it is possible to suppress attachment failure at the time of mounting.

[0325] The length direction L distance Lt1 of the 1st-inclined surface FC1 and the length direction L distance Lt2 of the 2nd-inclined surface FC2 are shorter than the length direction L distance Lt0 of the 1st-flat surface PA0. The length direction L distance Lt1 of the 3rd-inclined surface FC3 and the length direction L distance Lt2 of the 4th-inclined surface FC4 are shorter than the length direction L distance Lt0 of the 2nd-flat surface PB0.

[0326] The length direction L distance Lwt1 of the 1st-side surface side inclined surface FWC1 and the length direction L distance Lwt2 of the 2nd-side surface side inclined surface FWC2 are shorter than the length direction L distance Lwt0 of the 1st-side surface side flat surface PWA0. The length direction L distance Lwt1 of the 3rd-side surface side inclined surface FWC3 and the length direction L distance Lwt2 of the 4th-side surface side inclined surface FWC4 are shorter than the length direction L distance Lwt0 of the 2nd-side surface side flat surface PWB0.

[0327] Thus, the area of the opposing electrode portion 11E can be ensured to be large, and further, the areas of the first central region EA0 and the second central region EB0, which have high coverage, can be appropriately ensured, and thus the capacitance can be increased. Further, by ensuring the area of the flat surface, the adhesion failure at the time of mounting can be suppressed.

[0328] Further, in the present embodiment, in the length direction L, the distance Lt0 of the first flat surface PA0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. Further, in the length direction L, the distance Lt0 of the second flat surface PB0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. In this way, it is preferable that the distance Lt0 of the length direction L of the first flat surface PA0 and the second flat surface PB0 be arranged within the distance L1 between the first external electrode 40A and the second external electrode 40B in the length direction L.

[0329] Further, the end portion 40AE of the first external electrode 40A can be positioned at the first inclined surface FC1 and the third inclined surface FC3, or at the planar portion PA1 and the planar portion PB1 on the first end surface LS1 side from the first inclined surface FC1 and the third inclined surface FC3. The end portion 40BE of the second external electrode 40B can be positioned at the second inclined surface FC2 and the fourth inclined surface FC4, or at the planar portion PA2 and the planar portion PB2 on the second end surface LS2 side from the second inclined surface FC2 and the fourth inclined surface FC4.

[0330] In the present embodiment, the end portion 40AE of the first external electrode 40A is positioned near the boundary portion of the first inclined surface FC1 and the planar portion PA1, and near the boundary portion of the third inclined surface FC3 and the planar portion PB1. Further, the end portion 40BE of the second external electrode 40B is positioned near the boundary portion of the second inclined surface FC2 and the planar portion PA2, and near the boundary portion of the fourth inclined surface FC4 and the planar portion PB2.

[0331] Further, in the present embodiment, in the length direction L, the distance Lwto of the first side surface side flat surface PWA0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. Further, in the length direction L, the distance Lwto of the second side surface side flat surface PWB0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. In this way, it is preferable that the distance Lwto of the length direction L of the first side surface side flat surface PWA0 and the second side surface side flat surface PWB0 be arranged within the distance L1 between the first external electrode 40A and the second external electrode 40B in the length direction L.

[0332] Further, the end portion 40AE of the first external electrode 40A can be positioned on the first side surface side inclined surface FWC1 and the third side surface side inclined surface FWC3, or on the planar portion PWA1 and the planar portion PWB1 on the first end surface LSI side than the first side surface side inclined surface FWC1 and the third side surface side inclined surface FWC3. The end portion 40BE of the second external electrode 40B can be positioned on the second side surface side inclined surface FWC2 and the fourth side surface side inclined surface FWC4, or on the planar portion PWA2 and the planar portion PWB2 on the second end surface LS2 side than the second side surface side inclined surface FWC2 and the fourth side surface side inclined surface FWC4.

[0333] In the present embodiment, the end portion 40AE of the first external electrode 40A is positioned near the boundary portion of the first side surface side inclined surface FWC1 and the planar portion PWA1, and near the boundary portion of the third side surface side inclined surface FWC3 and the planar portion PWB1. Further, the end portion 40BE of the second external electrode 40B is positioned near the boundary portion of the second side surface side inclined surface FWC2 and the planar portion PWA2, and near the boundary portion of the fourth side surface side inclined surface FWC4 and the planar portion PWB2.

[0334] Thus, the area of the opposing electrode portion 11E can be ensured to be large, and further, the areas of the first central region EA0 and the second central region EB0, which have high coverage, can be appropriately ensured, and thus the capacitance can be increased.

[0335] The first flat surface PA0 is preferably substantially parallel to a surface orthogonal to the stacking direction T. The first flat surface PA0 and the planar portion PA1 and the planar portion PA2 are preferably substantially parallel. More preferably, the first flat surface PA0 and the planar portion PA1 and the planar portion PA2 are substantially parallel to a surface orthogonal to the stacking direction T.

[0336] The second flat surface PB0 is preferably substantially parallel to a surface orthogonal to the stacking direction T. The second flat surface PB0 and the planar portion PB1 and the planar portion PB2 are preferably substantially parallel. More preferably, the second flat surface PB0 and the planar portion PB1 and the planar portion PB2 are substantially parallel to a surface orthogonal to the stacking direction T.

[0337] Further, in the present embodiment, the flat surfaces are protruded as a part of the surface of the laminate 10 on both the first main surface TS1 and the second main surface TS2 by having the above-described inclined surfaces, but the flat surfaces can be protruded as a part of the surface of the laminate 10 on either one of the first main surface TS1 and the second main surface TS2.

[0338] The first side surface flat surface PWA0 is preferably substantially parallel to a surface orthogonal to the width direction W. The first side surface flat surface PWA0 and the flat surface portion PWA1 and the flat surface portion PWA2 are preferably substantially parallel. More preferably, the first side surface flat surface PWA0 and the flat surface portion PWA1 and the flat surface portion PWA2 and the surface orthogonal to the width direction W are substantially parallel.

[0339] The second side surface flat surface PWB0 is preferably substantially parallel to a surface orthogonal to the width direction W. The second side surface flat surface PWB0 and the flat surface portion PWB1 and the flat surface portion PWB2 are preferably substantially parallel. More preferably, the second side surface flat surface PWB0 and the flat surface portion PWB1 and the flat surface portion PWB2 and the surface orthogonal to the width direction W are substantially parallel.

[0340] In addition, in the present embodiment, the flat surface protrusions as a part of the surface of the laminate 10 are arranged on both the first side surface WS1 and the second side surface WS2 by having the above-described inclined surface, but the flat surface protrusions as a part of the surface of the laminate 10 can also be arranged on either one of the first side surface WS1 and the second side surface WS2.

[0341] Thus, the area of the opposing electrode portion 11E can be ensured to be large, and further, the areas of the first central region EA0 and the second central region EB0, which have high coverage, can be appropriately ensured, and thus the capacitance can be increased.

[0342] The first internal electrode layer 31 of the present embodiment preferably has the above-described first central region EA0 having a high coverage and a thick thickness in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111, as compared to the first lead portion D1, the first region EA1, and the second region EA2.

[0343] However, the first internal electrode layer 31 can also have the above-described first central region EA0 having a high coverage and a thick thickness in at least either one of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113, as compared to the first lead portion D1, the first region EA1, and the second region EA2. Thus, an effect of increasing the capacitance without increasing the size of the laminate ceramic capacitor 1 can also be obtained.

[0344] The second internal electrode layer 32 of the present embodiment preferably has the above-described second central region EB0 having a high coverage and a thick thickness in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111, as compared to the second lead portion D2, the third region EB1, and the fourth region EB2.

[0345] However, the second internal electrode layer 32 can also have the above-described second central region EB0 having a higher coverage ratio and a thicker thickness than the second lead-out portion D2, the third region EB1, and the fourth region EB2 at least in either of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113. Thereby, such an effect of increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1 can also be obtained.

[0346] The first internal electrode layer 31 of the present embodiment preferably has the above-described first central region EA0 having a higher coverage ratio and a thicker thickness than the first lead-out portion D1, the first region EA1, and the second region EA2, and further spreading outward of the laminate 10 in the width direction W in the first side surface side opposing electrode portion 112E, the second side surface side opposing electrode portion 113E, and the central opposing electrode portion 111E.

[0347] The present disclosure is not limited thereto, but by having the above-described first central region EA0 having a higher coverage ratio and a thicker thickness than the first lead-out portion D1, the first region EA1, and the second region EA2, and further spreading outward of the laminate 10 in the width direction W in the first side surface side opposing electrode portion 112E and the second side surface side opposing electrode portion 113E in addition to the central opposing electrode portion 111E, the area of the first central region EA0 having a high coverage ratio can be secured, and thus the capacitance can be further increased without increasing the size of the multilayer ceramic capacitor 1.

[0348] The second internal electrode layer 32 of the present embodiment preferably has the above-described second central region EB0 having a higher coverage ratio and a thicker thickness than the second lead-out portion D2, the third region EB1, and the fourth region EB2, and further spreading outward of the laminate 10 in the width direction W in the first side surface side opposing electrode portion 112E, the second side surface side opposing electrode portion 113E, and the central opposing electrode portion 111E.

[0349] The present disclosure is not limited thereto, but by having the above-described second central region EB0 having a higher coverage ratio and a thicker thickness than the second lead-out portion D2, the third region EB1, and the fourth region EB2, and further spreading outward of the laminate 10 in the width direction W in the first side surface side opposing electrode portion 112E and the second side surface side opposing electrode portion 113E in addition to the central opposing electrode portion 111E, the area of the second central region EB0 having a high coverage ratio can be secured, and thus the capacitance can be further increased without increasing the size of the multilayer ceramic capacitor 1.

[0350] <Manufacturing method>

[0351] Next, the manufacturing method of the multilayer ceramic capacitor 1 according to the second embodiment will be described. Regarding the multilayer ceramic capacitor 1 of this embodiment, the manufacturing method is not limited as long as the above-described requirements are met. However, a preferred manufacturing method includes the following steps. Details of each step will be described below.

[0352] Prepare the dielectric sheet for dielectric layer 20 and the conductive paste for internal electrode layer 30.

[0353] On the dielectric sheet, conductive paste for the inner electrode layer 30 is printed in a given pattern, for example, by screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern of the first inner electrode layer 31 and a pattern of the second inner electrode layer 32 is prepared.

[0354] like Figure 11 As shown, the dielectric sheet printed with the pattern of the internal electrode layer 30 is composed of a ceramic green sheet G and conductive pastes P1 and P2 disposed on the ceramic green sheet G. Conductive pastes P1 and P2 are formed by the hollow portions of screen S1 and screen S2.

[0355] The hollow portion of the wire mesh S1 has a portion corresponding to the first region EA1, a portion corresponding to the first central region EA0, and a portion corresponding to the second region EA2, or a portion corresponding to the third region EB1, a portion corresponding to the second central region EB0, and a portion corresponding to the fourth region EB2.

[0356] The hollow portion of wire mesh S1 has a portion corresponding to the first central region EA0 whose width-direction distance is longer than the width-direction distances of the portions corresponding to the first region EA1 and the second region EA2. The hollow portion of wire mesh S1 also has a portion corresponding to the second central region EB0 whose width-direction distance is longer than the width-direction distances of the portions corresponding to the third region EB1 and the fourth region EB2. The hollow portion of wire mesh S2 has a portion corresponding to either the first central region EA0 or the second central region EB0.

[0357] Thus, as described above, conductive paste P1 and conductive paste P2 are formed by the hollow portion of screen S1 and the hollow portion of screen S2, and the portions corresponding to the first central region EA0 and the second central region EB0 are wider in the width direction W compared to other regions.

[0358] First, such as Figure 10 As shown, conductive paste P1 is disposed on a ceramic green sheet G using a screen S1 having a hollow portion formed by a pattern corresponding to the outer shape of the first internal electrode layer 31 and the second internal electrode layer 32.

[0359] Next, asFigure 11 As shown, conductive paste P2 is screen-printed onto conductive paste P1 using a screen S2 having hollow portions formed by patterns corresponding to the first central region EA0 and the second central region EB0. Consequently, the portions corresponding to the first central region EA0 and the second central region EB0 are thicker and wider in the width direction W compared to the other regions.

[0360] Specifically, the portions corresponding to the first central region EA0 and the second central region EB0 are wider and thicker in the width direction W compared to the portions corresponding to the first lead-out portion D1, the second lead-out portion D2, the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. Therefore, the first central region EA0 and the second central region EB0 become high-coverage regions that are wider and have higher coverage in the width direction W compared to the first lead-out portion D1, the second lead-out portion D2, the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. Furthermore, the first lead-out portion D1 and the second lead-out portion D2 have substantially the same thickness and substantially the same coverage as the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2.

[0361] A given number of dielectric sheets with unprinted internal electrode layer 30 patterns are stacked to form part P12, which becomes the outer layer 12 of the first main surface side on the first main surface TS1 side.

[0362] Next, as Figure 12 As shown, layers are sequentially stacked on the surface of portion P12, which becomes the outer layer 12 of the first main surface side. Figure 11 The screen-printed dielectric sheet shown is thus formed as part P11 of the inner layer 11. Here, if we focus on... Figure 12 To explain the portion enclosed by C, a dielectric sheet G1, which is a conductive paste P31 serving as the first internal electrode layer 31, and a dielectric sheet G2, which is a conductive paste P32 serving as the second internal electrode layer 32, are alternately stacked in sequence. Furthermore, regarding... Figure 12 The C portion is cut out in subsequent processes to form a stacked piece.

[0363] By laminating a given number of dielectric sheets with unprinted internal electrode layer 30 patterns onto the surface of the portion P11 that becomes the inner layer 11, a portion P13 that becomes the outer layer 13 of the second main surface TS2 side is formed. Thus, a laminated sheet is manufactured.

[0364] Laminated blocks are produced by pressing laminated sheets in the height direction using methods such as isostatic pressing.

[0365] The laminated chip is cut to a given size, thereby cutting out the laminated chip. Here, by cutting the two end face sides among the side faces of the laminated chip by barrel grinding or the like, the portions corresponding to the first central region EA0 and the second central region EB0 are made relatively wide in the width direction.

[0366] Specifically, by performing mask application and barrel grinding or the like at the same time, the portions corresponding to the first lead-out portion D1, the portions corresponding to the first region EA1 or the third region EB1, the portions corresponding to the second region EA2 and the fourth region EB2, and the portions corresponding to the second lead-out D2 are cut out of the side faces of the laminated chip. The portions corresponding to the first central region EA0 and the second central region EB0 are made wide in the width direction with respect to the portions corresponding to the first lead-out portion D1, the portions corresponding to the first region EA1 or the third region EB1, the portions corresponding to the second region EA2 and the fourth region EB2, and the portions corresponding to the second lead-out D2. At this time, the corner portions and the ridge line portions of the laminated chip can also be rounded by barrel grinding or the like.

[0367] In addition, the details of the subsequent manufacturing method are the same as in the first embodiment, and thus the description is omitted. Through such a manufacturing process, the laminated ceramic capacitor 1 can be manufactured.

[0368] <Experimental Examples>

[0369] Next, experimental examples performed on the laminated ceramic capacitor 1 according to the first embodiment with respect to the laminated ceramic capacitor 1 representing the present disclosure are described. Seven batches of laminated ceramic capacitors produced by adjusting the thickness and coverage of the first central region EA0 and the second central region EB0 were produced as samples for experimental examples 1 to 7, according to the manufacturing method described in the first embodiment. In addition, as a sample for a comparative example, a sample having the same thickness and coverage of the internal electrode layer was produced. Then, using the produced samples, evaluation of the static capacitance and mounting evaluation were performed. With respect to the thickness and coverage of the internal electrode layer, the evaluation results, and the like of each experimental example and the comparative example, Table 1 described later is referred to. In addition, the thickness and coverage of the lead-out portion of the internal electrode layer were designed to be the same as the opposing portion end region.

[0370] First, according to the manufacturing method described in the present embodiment, laminated ceramic capacitors of the following specifications were produced as samples for experimental examples.

[0371] • Size of laminated ceramic capacitor: 1608 size

[0372] • Capacitance: 22 μF

[0373] • Rated voltage: 25 V

[0374] • Dielectric layer: BaTi03 (thickness of dielectric layer: 1 μm)

[0375] • Internal electrode layer: Ni

[0376] • Base electrode layer: Electrode containing conductive metal (Cu) and glass component (thickness of base electrode layer disposed on the 1st end surface and the 2nd end surface: 36 μm, thickness of base electrode layer disposed on the 1st main surface, the 2nd main surface, the 1st side surface, and the 2nd side surface: 9 μm)

[0377] • Plating layer: Two layers of Ni plating layer (2 μm) and Sn plating layer (4 μm) were formed

[0378] • Internal electrode layer: Ni

[0379] • Number of stacked sheets: 550 sheets

[0380] • Proportion of central region (high coverage region) at the opposing portion: 75%

[0381] Here, each batch was a batch manufactured according to different manufacturing conditions, and the thickness and coverage of the 1st central region EA0 and the 2nd central region EB0 were adjusted respectively. According to each of the experimental examples and the comparative examples, the necessary number of samples for each evaluation were produced. Furthermore, according to each of the experimental examples and the comparative examples, five samples for the measurement of the size, thickness, and coverage of the internal electrode layer were produced, and the average of the measured values of the size, thickness, and coverage of the internal electrode layer of the five samples was calculated as the size, thickness, and coverage of the internal electrode layer of each of the experimental examples and the comparative examples.

[0382] <Measurement method of electrostatic capacitance>

[0383] The electrostatic capacitance obtained under the conditions of a frequency of 120 Hz and an applied voltage of 0.5 Vrms was measured using a C meter. According to each of the experimental examples and the comparative examples, 50 samples were evaluated, and the average thereof was taken as the electrostatic capacitance of each of the experimental examples and the comparative examples.

[0384] <Mounting evaluation>

[0385] The occurrence rate of adsorption failure caused by a mounter of a mounting machine when mounting the multilayer ceramic capacitor on a mounting substrate was evaluated. According to each of the experimental examples and the comparative examples, 50 samples were evaluated.

[0386] In Table 1, the measurement results and the evaluation results of the experimental examples 1 to 7 and the comparative examples are shown.

[0387] [Table 1]

[0388]

[0389] In Table 1, the measurement results are described in the central region thickness te0, the opposing portion end region thickness te1, the thickness ratio te0 / te1, the central region coverage Ce0, the opposing portion end region coverage Ce1, the coverage difference Ce0-Ce1, the laminate expansion size (one side), the laminate expansion ratio, and the main surface side thickness of the external electrode. The evaluation results are described in the static capacitance, the static capacitance evaluation results, the size evaluation results, the occurrence rate of adsorption failure in the mounting evaluation, the adsorption failure evaluation results, and the comprehensive evaluation.

[0390] In Table 1, the central region thickness te0 is the average of the measurement results of the thicknesses of the 1st central region EA0 and the 2nd central region EB0. The opposing portion end region thickness te1 is the average of the measurement results of the thicknesses of the 1st region EA1, the 2nd region EA2, the 3rd region EB1, and the 4th region EB2. The thickness ratio is the value obtained by dividing the central region thickness te0 by the opposing portion end region thickness te1.

[0391] In Table 1, the central region coverage Ce0 is the average of the measurement results of the coverages of the 1st central region EA0 and the 2nd central region EB0. The opposing portion end region coverage Ce1 is the average of the measurement results of the coverages of the 1st region EA1, the 2nd region EA2, the 3rd region EB1, and the 4th region EB2. The coverage difference is the value obtained by subtracting the opposing portion end region coverage Ce1 from the central region coverage Ce0, and is expressed in percentage points (%pt).

[0392] In Table 1, the expansion size (one side) of the laminate is the average of the protrusion height tf of the 1st flat surface PA0 formed by the 1st inclined surface FC1 and the 2nd inclined surface FC2 and the protrusion height tf of the 2nd flat surface PB0 formed by the 3rd inclined surface FC3 and the 4th inclined surface FC4. The laminate expansion ratio is the value obtained by dividing the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep of the laminate 10 by the maximum distance T1 in the stacking direction T of the surfaces (flat surface portions PA1, flat surface portions PA2) on the side of the 1st main surface TS1 and the surfaces (flat surface portions PB1, flat surface portions PB2) on the side of the 2nd main surface TS2 of the 1st covering portion C1 and the 2nd covering portion C2. In the present experimental example, the average of the aforementioned maximum distance T1 is 930 μm. The main surface side thickness of the external electrode is the average of the thickness of the 1st external electrode disposed on the 1st main surface TS1, the thickness of the 2nd external electrode disposed on the 1st main surface TS1, the thickness of the 1st external electrode disposed on the 2nd main surface TS2, and the thickness of the 2nd external electrode disposed on the 2nd main surface TS2.

[0393] In Table 1, in the item of electrostatic capacitance, the electrostatic capacitance of the multilayer ceramic capacitor measured by the above-described measurement method of electrostatic capacitance is shown. In the item of electrostatic capacitance evaluation result, in the present experimental examples, the evaluation result is set to O in the case where it is 22.0 μF or more, and the evaluation result is set to X in the case where it is less than 22.0 μF.

[0394] In Table 1, in the item of size evaluation result, the evaluation result is set to Δ in the case where the thickness of the first central region EA0 and the second central region EB0 is increased so that the first flat surface PA0 and the second flat surface PB0 protrude outward in the stacking direction T than the first external electrode 40A or the second external electrode 40B, and the evaluation result is set to O in the case where they do not protrude outward.

[0395] In Table 1, in the item of occurrence rate of adsorption failure in mounting evaluation, the occurrence rate of adsorption failure caused by the mounters of the mounting machine at the time of mounting of 50 multilayer ceramic capacitors of each of the comparative example, the experimental examples 1 to 7 is described. In the item of adsorption failure evaluation result, the evaluation result is set to O in the case where the number of samples in which adsorption failure occurs is one or less out of 50, the evaluation result is set to Δ in the case where the number of samples in which adsorption failure occurs is two or more and 15 or less, and the evaluation result is set to X in the case where the number of samples in which adsorption failure occurs is more than 15. In the present experimental examples, the number of samples in which adsorption failure occurs is 15 or less in any of the experimental examples.

[0396] In Table 1, in the item of comprehensive evaluation, the evaluation result is set to Δ (tolerable) in the case where any of the evaluation results contains Δ (tolerable), the evaluation result is set to X (not good) in the case where any of the evaluation results contains X (not good), and the evaluation result is set to O (good) in the case where any of the evaluation results is O (good).

[0397] It can be confirmed that the coverage difference is 2.2 percent or more, the electrostatic capacitance is 22.0 μF or more, and the effect of increasing the capacitance can be obtained. According to the tendency obtained from the results, for example, if the coverage difference is 3.0 percent or more, a higher effect on the increase in capacitance can be expected, and if the coverage difference is 4.0 percent or more, a further higher effect on the increase in capacitance can be expected. According to the tendency of the evaluation results of the comparative example and each of the experimental examples, the effect of the present embodiment can be obtained by making the central region coverage Ce0 higher than the opposing portion end region coverage Ce1, and it can be confirmed that the higher the central region coverage Ce0 is made higher than the opposing portion end region coverage Ce1, the higher the electrostatic capacitance is increased.

[0398] It was confirmed that the thickness ratio was 101.6% or more, the electrostatic capacitance was 22.0 μF or more, and the effect of increasing the capacitance was obtained. From the tendency obtained from the results, it was predicted that the thickness ratio was more preferably 102% or more, and further preferably 103% or more. Thus, the coverage of the central portion was increased, and the capacitance was increased. In addition, the thickness ratio can be 111.3% or less, or 109.8% or less. From the tendency of the evaluation results of the comparative example and each of the experimental examples, the effect of the present embodiment was obtained by making the central region thickness te0 higher than the opposing portion end region thickness te1, and it was confirmed that the electrostatic capacitance was increased more as the central region thickness te0 was made higher than the opposing portion end region thickness te1.

[0399] In addition, if the thickness ratio exceeds 109.8%, the effect of increasing the capacitance becomes limited. Furthermore, if the thickness ratio becomes too high, the size of the central region of the laminate becomes large, the expanded size (one side) of the laminate approaches the thickness of the main surface side of the external electrode, and thus it becomes difficult to reduce the size of the entire multilayer ceramic capacitor 1, and it becomes easy to cause suction failure in mounting evaluation. Thus, if the thickness ratio becomes too high, the effect of increasing the capacitance is reduced, and depending on the size of the product and the thickness of the external electrode, it becomes difficult to use.

[0400] Here, in the samples of the comparative example, the first inclined portion FA1, the second inclined portion FA2, and the third inclined portion FB1 and the fourth inclined portion FB2 of the present embodiment were not confirmed, and on the other hand, in the samples of the experimental examples 1 to 7, the first inclined portion FA1, the second inclined portion FA2, and the third inclined portion FB1 and the fourth inclined portion FB2 of the present embodiment were confirmed. By being configured in this way, good evaluation results were obtained in the above evaluation.

[0401] In addition, in the samples of the experimental examples 1 to 7, it was confirmed that the distance of the first central region EA0 and the second central region EB0 in the length direction L was shorter than the distance between the first external electrode 40A and the second external electrode 40B. By being configured in this way, good evaluation results were obtained in the above evaluation.

[0402] In addition, in the samples of the experimental examples 1 to 7, it was confirmed that the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep of the laminate 10 was longer than the maximum distance T1 in the stacking direction T of the connecting first main surface TS1 side surface and the second main surface TS2 side surface of the first covering portion C1 and the second covering portion C2. By being configured in this way, good evaluation results were obtained in the above evaluation.

[0403] Further, in the samples of Experimental Examples 1 to 6, it was confirmed that the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep of the laminate 10 was shorter than the maximum distance T2 in the stacking direction T of the surface on the side of the first main face TS1 and the surface on the side of the second main face TS2 of the first external electrode 40A and the second external electrode 40B. By providing such a structure, more favorable evaluation results were obtained in the above evaluation. The expansion size (one side) of the laminate is preferably smaller than the thickness of the main face side of the external electrode.

[0404] The laminate ceramic capacitor 1 according to the above-described embodiment has the following effects. In a general laminate ceramic capacitor, a space exists between a portion between an imaginary plane connecting the surface of the first external electrode and the surface of the second external electrode and the surface of the laminate. This space is a space that necessarily exists as long as the external electrode has a side surface thickness, but does not contribute to the capacitance density.

[0405] As one of the methods of increasing the electrostatic capacitance, a method of increasing the coverage of the internal electrode layer to increase the net effective area can be considered. Here, the coverage of the internal electrode layer has a positive correlation with the thickness of the internal electrode layer, and thus the thickness of the internal electrode layer needs to be increased to increase the coverage. Thus, in order to design the laminate with the same size in the stacking direction T, the number of pieces of the internal electrode layer needs to be reduced in correspondence with the amount of increase in the thickness of the internal electrode layer. Therefore, the effect of increasing the electrostatic capacitance due to the increase in the thickness of the internal electrode layer is canceled out by the reduction in the number of pieces of the internal electrode layer.

[0406] According to the present disclosure, it is possible to provide a laminate ceramic capacitor that can effectively utilize the space existing in a portion between an imaginary plane connecting the surface of the first external electrode and the surface of the second external electrode and the surface of the laminate to increase the electrostatic capacitance without increasing the size of the laminate ceramic capacitor 1.

[0407] (1) The multilayer ceramic capacitor 1 of the present disclosure has: a laminate 10 including a plurality of dielectric layers 20 laminated, and including a first main surface TS1 and a second main surface TS2 opposed in a lamination direction T, a first side surface WS1 and a second side surface WS2 opposed in a width direction W orthogonal to the lamination direction T, and a first end surface LS1 and a second end surface LS2 opposed in a length direction L orthogonal to the lamination direction T and the width direction W; a first internal electrode layer 31 disposed on the dielectric layers 20 and exposed at the first end surface LS1; a second internal electrode layer 32 disposed on the dielectric layers 20 and exposed at the second end surface LS2; a first external electrode 40A disposed on the first end surface LS1 and connected to the first internal electrode layer 31; and a second external electrode 40B disposed on the second end surface LS2 and connected to the second internal electrode layer 32, the first internal electrode layer 31 has a first opposing portion EA opposed to the second internal electrode layer 32, and a first lead-out portion D1 led out from the first opposing portion EA to the first end surface LS1 side, the second internal electrode layer 32 has a second opposing portion EB opposed to the first internal electrode layer 31, and a second lead-out portion D2 led out from the second opposing portion EB to the second end surface LS2 side, the first opposing portion EA has: a first high-coverage-area EA0 that is an area disposed more outward of the laminate 10 in the lamination direction T than the first lead-out portion D1 and has a higher coverage than the first lead-out portion D1, and the second opposing portion EB has: a second high-coverage-area EB0 that is an area disposed more outward of the laminate 10 in the lamination direction T than the second lead-out portion D2 and has a higher coverage than the second lead-out portion D2.

[0408] Thus, the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1.

[0409] (2) In the multilayer ceramic capacitor 1 of (1), the distance TE0 in the width direction W of the first high-coverage-area EA0 is longer than the distance TE1 in the width direction W of the first lead-out portion D1, and the distance TE0 in the width direction W of the second high-coverage-area EB0 is longer than the distance TE1 in the width direction W of the second lead-out portion D2.

[0410] Thus, even in the width direction W, the high-coverage-area can be ensured wider, and the capacitance can be further increased without increasing the size of the multilayer ceramic capacitor 1.

[0411] (3) In the multilayer ceramic capacitor 1 of (2), the stack 10 has an exposed portion Ep exposed from the first external electrode 40A and the second external electrode 40B, a first covered portion C1 covered by the first external electrode 40A, and a second covered portion C2 covered by the second external electrode 40B, a distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep is longer than a maximum distance T1 in the stacking direction T of a surface on the side of the first main face TS1 and a surface on the side of the second main face TS2 of the first covered portion C1 and the second covered portion C2, and shorter than a maximum distance T2 in the stacking direction T of a surface on the side of the first main face TS1 and a surface on the side of the second main face TS2 of the first external electrode 40A and the second external electrode 40B, and a distance TW0 in the width direction W at the center in the length direction L of the exposed portion Ep is longer than a maximum distance TW1 in the width direction W of a surface on the side of the first side face WS1 and a surface on the side of the second side face WS2 of the first covered portion C1 and the second covered portion C2, and shorter than a maximum distance TW2 in the width direction W of a surface on the side of the first side face WS1 and a surface on the side of the second side face WS2 of the first external electrode 40A and the second external electrode 40B.

[0412] Thus, it is possible to ensure a wider high-coverage-area region and further improve the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0413] (4) In the multilayer ceramic capacitor 1 of any one of (1) to (3), the first main face TS1 has a first exposed face EpsA exposed from the first external electrode 40A and the second external electrode 40B, a first covered face C1sA covered by the first external electrode 40A, and a second covered face C2sA covered by the second external electrode 40B, and the first exposed face EpsA has a first flat face PA0 parallel to the stacking direction T, a first inclined face FC1 connecting the first flat face PA0 and the first covered face C1sA, and a second inclined face FC2 connecting the first flat face PA0 and the second covered face C2sA.

[0414] Thus, it is possible to easily ensure the areas of the first high-coverage-area region EA0 and the second high-coverage-area region EB0 having high coverage corresponding to the first flat face PA0, and to improve the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0415] (5) In the multilayer ceramic capacitor of (4), a distance Lt1 in the length direction L of the first inclined face FC1 and a distance Lt2 in the length direction L of the second inclined face FC2 are shorter than a distance Lt0 in the length direction L of the first flat face PA0.

[0416] Thus, it becomes easy to ensure the areas of the first high coverage area EA0 and the second high coverage area EB0 with high coverage corresponding to the first flat surface PA0, and it is possible to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0417] (6) In the multilayer ceramic capacitor of (2) or (3), the first side surface WS1 has a first side surface side exposed surface EWpsA exposed from the first external electrode 40A and the second external electrode 40B, a first side surface side covered surface CW1sA covered by the first external electrode 40A, and a second side surface side covered surface CW2sA covered by the second external electrode 40B, and the first side surface side exposed surface EWpsA has a first side surface side flat surface PWA0 parallel to the stacking direction T, a first side surface side inclined surface FWC1 connecting the first side surface side flat surface PWA0 and the first side surface side covered surface CW1sA, and a second side surface side inclined surface FWC2 connecting the first side surface side flat surface PWA0 and the second side surface side covered surface CW2sA.

[0418] Thus, even in the width direction W, it becomes easy to ensure the areas of the first high coverage area EA0 and the second high coverage area EB0 with high coverage corresponding to the first side surface side flat surface PWA0, and it is possible to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0419] (7) In the multilayer ceramic capacitor 1 of (6), the length direction L distance Lwt1 of the first side surface side inclined surface FWC1 and the length direction L distance Lwt2 of the second side surface side inclined surface FWC2 are shorter than the length direction L distance Lwt0 of the first side surface side flat surface PWA0.

[0420] Thus, even in the width direction W, it becomes easy to ensure the areas of the first high coverage area EA0 and the second high coverage area EB0 with high coverage corresponding to the first side surface side flat surface PWA0, and it is possible to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0421] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the first opposing portion EA has a first region EA1 that is a region on the first end surface LSI side, a second region EA2 that is a region on the second end surface LS2 side, and a first central region EA0 that is a region between the first region EA1 and the second region EA2 and is a region that is disposed more outward of the multilayer body 10 in the stacking direction T than the first region EA1 and the second region EA2 and has a higher coverage ratio than the first region EA1 and the second region EA2, the second opposing portion EB has a third region EB1 that is a region on the second end surface LS2 side, a fourth region EB2 that is a region on the first end surface LSI side, and a second central region EB0 that is a region between the third region EB1 and the fourth region EB2 and is a region that is disposed more outward of the multilayer body 10 in the stacking direction T than the third region EB1 and the fourth region EB2 and has a higher coverage ratio than the third region EB1 and the fourth region EB2, the first internal electrode layer 31 further has a first inclined portion FA1 that links the first region EA1 and the first central region EA0 and a second inclined portion FA2 that links the second region EA2 and the first central region EA0, and the second internal electrode layer 32 further has a third inclined portion FB1 that links the third region EB1 and the second central region EB0 and a fourth inclined portion FB2 that links the fourth region EB2 and the second central region EB0.

[0422] Thus, it is possible to provide a multilayer ceramic capacitor that can increase the capacitance without increasing the size of the multilayer ceramic capacitor.

[0423] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the first central region EA0 is shorter in the length direction L than the distance LI between the first external electrode 40A and the second external electrode 40B, and the second central region EB0 is shorter in the length direction L than the distance LI between the first external electrode 40A and the second external electrode 40B.

[0424] Thus, it is possible to provide a multilayer ceramic capacitor that can increase the capacitance without increasing the size of the multilayer ceramic capacitor.

[0425] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the multilayer body 10 has an exposed portion Ep exposed from the first external electrode 40A and the second external electrode 40B, a first covered portion C1 covered by the first external electrode 40A, and a second covered portion C2 covered by the second external electrode 40B, a distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep is longer than a maximum distance T1 in the stacking direction T of a side surface of the first main surface TS1 and a side surface of the second main surface TS2 of the first covered portion C1 and the second covered portion C2, and is shorter than a maximum distance T2 in the stacking direction T of a side surface of the first main surface TS1 and a side surface of the second main surface TS2 of the first external electrode 40A and the second external electrode 40B.

[0426] Thus, it is possible to provide a multilayer ceramic capacitor capable of increasing the capacitance without increasing the size of the multilayer ceramic capacitor.

[0427] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the first main surface TS1 has a first exposed surface EpsA exposed from the first external electrode 40A and the second external electrode 40B, a first covered surface C1sA covered by the first external electrode 40A, and a second covered surface C2sA covered by the second external electrode 40B, the first exposed surface EpsA has a first flat surface PA0 parallel to the stacking direction T, a first inclined surface FC1 connecting the first flat surface PA0 and the first covered surface C1sA, and a second inclined surface FC2 connecting the first flat surface PA0 and the second covered surface C2sA.

[0428] Thus, it is possible to ensure the areas of the first central region EA0 and the second central region EB0 having high coverage rates in correspondence with the first flat surface PA0, and to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0429] Further, in the multilayer ceramic capacitor 1 of the present disclosure, a distance Lt1 in the length direction L of the first inclined surface FC1 and a distance Lt2 in the length direction L of the second inclined surface FC2 are shorter than a distance Lt0 in the length direction L of the first flat surface PA0.

[0430] Thus, it is possible to ensure the areas of the first central region EA0 and the second central region EB0 having high coverage rates in correspondence with the first flat surface PA0, and to further increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0431] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the first internal electrode layer 31 further has a fifth inclined portion FA3 at the first lead-out portion D1, and the second internal electrode layer 32 further has a sixth inclined portion FB3 at the second lead-out portion D2.

[0432] Thus, the distance of the penetration path of moisture from the outside can be ensured to be long, so the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1 and the moisture resistance can also be ensured.

[0433] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the inclination angle θ of the first and second inclined portions FA1 and FA2 is smaller than the inclination angle θ2 of the fifth inclined portion FA3, and the inclination angle θ of the third and fourth inclined portions FB1 and FB2 is smaller than the inclination angle θ2 of the sixth inclined portion FB3.

[0434] Thus, the distance of the penetration path of moisture from the outside can be ensured to be longer, so the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1 and the moisture resistance can also be ensured.

[0435] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the step distance Isi between the first region EA1 and the first central region EA0 generated by the first inclined portion FA1 is larger than the thickness Tc of the dielectric layer 20 in the stacking direction T arranged between the first and second internal electrode layers 31 and 32, and the step distance Is3 between the third region EB1 and the second central region EB0 generated by the third inclined portion FB1 is larger than the thickness Tc of the dielectric layer 20 in the stacking direction T arranged between the first and second internal electrode layers 31 and 32.

[0436] Thus, the step distance Isi between the first region EA1 and the first central region EA0 generated by the first inclined portion FA1 is larger than the thickness Tc of the dielectric layer 20 in the stacking direction T arranged between the first and second internal electrode layers 31 and 32, and the step distance Is3 between the third region EB1 and the second central region EB0 generated by the third inclined portion FB1 is larger than the thickness Tc of the dielectric layer 20 in the stacking direction T arranged between the first and second internal electrode layers 31 and 32.

[0437] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the step distance Isi between the first region EA1 and the first central region EA0 generated by the first inclined portion FA1 is larger than the thickness Tc of the dielectric layer 20 in the stacking direction T arranged between the first and second internal electrode layers 31 and 32, and the step distance Is3 between the third region EB1 and the second central region EB0 generated by the third inclined portion FB1 is larger than the thickness Tc of the dielectric layer 20 in the stacking direction T arranged between the first and second internal electrode layers 31 and 32.

[0438] Thus, the step distance Isi between the first region EA1 and the first central region EA0 generated by the first inclined portion FA1 is larger than the thickness Tc of the dielectric layer 20 in the stacking direction T arranged between the first and second internal electrode layers 31 and 32, and the step distance Is3 between the third region EB1 and the second central region EB0 generated by the third inclined portion FB1 is larger than the thickness Tc of the dielectric layer 20 in the stacking direction T arranged between the first and second internal electrode layers 31 and 32.

[0439] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the first central region EA0, the first region EA1, and the second region EA2 have portions substantially parallel to a plane orthogonal to the stacking direction T, and the second central region EB0, the third region EB1, and the fourth region EB2 have portions substantially parallel to a plane orthogonal to the stacking direction T.

[0440] Thus, it is possible to suppress formation of a portion in which the size locally increases, and to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0441] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the distance Le3 in the length direction L of the first inclined portion FA1 and the distance Le4 in the length direction L of the second inclined portion FA2 are shorter than the distance Le0 in the length direction L of the first central region EA0, and the distance Le4 in the length direction L of the third inclined portion FB1 and the distance Le3 in the length direction L of the fourth inclined portion FB2 are shorter than the distance Le0 in the length direction L of the second central region EB0.

[0442] Thus, it is possible to secure the areas of the first central region EA0 and the second central region EB0 in which the coverage is high, and thus to further increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0443] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the thickness of the first inclined portion FA1 decreases as it approaches the first end surface LS1, the thickness of the second inclined portion FA2 decreases as it approaches the second end surface LS2, the thickness of the third inclined portion FB1 decreases as it approaches the second end surface LS2, and the thickness of the fourth inclined portion FB2 decreases as it approaches the first end surface LS1.

[0444] If there is a portion in which the thickness of the internal electrode layer 30 sharply changes, it is possible that a portion in which the distance between the internal electrode layers sandwiching the dielectric layer 20 locally becomes short will be formed. In this case, the electric field concentrates in this portion, and thus the reliability of the multilayer ceramic capacitor 1 can decrease. If the above-described structure is employed, it is possible to suppress formation of a portion in which the distance between the internal electrode layers locally becomes short in the vicinity of the inclined portion, and thus to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1, and to suppress a decrease in the reliability of the multilayer ceramic capacitor 1 due to electrolytic concentration. Further, it is possible to prevent stress concentration at the inclined portion, and thus to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1, and to further suppress generation of cracks in the multilayer body.

[0445] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the thickness of the first central region EA0 and the second central region EB0 is 101.6% or more and 111.3% or less of the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2, and the difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is 2.2 percentage points or more.

[0446] Thus, it is possible to provide a multilayer ceramic capacitor 1 capable of increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0447] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the thickness of the first central region EA0 and the second central region EB0 is 101.6% or more and 109.8% or less of the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2.

[0448] Thus, it is possible to provide a multilayer ceramic capacitor 1 capable of increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0449] Further, in the multilayer ceramic capacitor 1 of the present disclosure, the difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is 2.2 percentage points or more and 11.4 percentage points or less.

[0450] Thus, it is possible to provide a multilayer ceramic capacitor 1 capable of increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0451] The present application is not limited to the structure of the above-described embodiments, and can be appropriately changed and applied within the scope of the gist of the present application. In addition, the present application also includes a combination of two or more of the preferred structures described in the above-described embodiments.

[0452] Explanation of Reference Signs

[0453] 1: Multilayer ceramic capacitor

[0454] 10: Multilayer body

[0455] 20: Dielectric layer

[0456] 31: First internal electrode layer

[0457] 32: Second internal electrode layer

[0458] 40A: First external electrode

[0459] 40B: 2nd external electrode

[0460] D1: 1st lead-out portion

[0461] D2: 2nd lead-out portion

[0462] EA: 1st opposing portion

[0463] EA0: 1st central region (1st high coverage region)

[0464] EA1: 1st region

[0465] EA2: 2nd region

[0466] EB: 2nd opposing portion

[0467] EB0: 2nd central region (2nd high coverage region)

[0468] EB1: 3rd region

[0469] EB2: 4th region

[0470] L: length direction

[0471] LS1: 1st end surface

[0472] LS2: 2nd end surface

[0473] T: stacking direction

[0474] TS1: 1st main surface

[0475] TS2: 2nd main surface

[0476] W: width direction

[0477] WS1: 1st side surface

[0478] WS2: 2nd side surface

Claims

1. A multilayer ceramic capacitor, comprising: a multilayer body including a plurality of dielectric layers stacked in a stacking direction, and including a first main surface and a second main surface opposed in the stacking direction, a first side surface and a second side surface opposed in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposed in a length direction orthogonal to the stacking direction and the width direction; a first internal electrode layer disposed on the dielectric layers and exposed at the first end surface; a second internal electrode layer disposed on the dielectric layers and exposed at the second end surface; a first external electrode disposed on the first end surface and connected to the first internal electrode layer; and a second external electrode disposed on the second end surface and connected to the second internal electrode layer, wherein the first internal electrode layer has a first opposing portion opposed to the second internal electrode layer, and a first lead-out portion led out from the first opposing portion toward the first end surface side, the second internal electrode layer has a second opposing portion opposed to the first internal electrode layer, and a second lead-out portion led out from the second opposing portion toward the second end surface side, the first opposing portion has a first high-coverage-area region that is disposed more outward of the multilayer body in the stacking direction than the first lead-out portion and has a higher coverage than the first lead-out portion, and the second opposing portion has a second high-coverage-area region that is disposed more outward of the multilayer body in the stacking direction than the second lead-out portion and has a higher coverage than the second lead-out portion.

2. The multilayer ceramic capacitor according to claim 1, wherein a distance in the width direction of the first high-coverage-area region is longer than a distance in the width direction of the first lead-out portion, and a distance in the width direction of the second high-coverage-area region is longer than a distance in the width direction of the second lead-out portion.

3. The multilayer ceramic capacitor according to claim 2, wherein the multilayer body has an exposed portion exposed from the first external electrode and the second external electrode, a first covered portion covered by the first external electrode, and a second covered portion covered by the second external electrode, a distance in the stacking direction at a length direction center of the exposed portion is longer than a maximum distance in the stacking direction of surfaces connecting the first main surface side and the second main surface side of the first covered portion and the second covered portion, and shorter than a maximum distance in the stacking direction of surfaces connecting the first main surface side and the second main surface side of the first external electrode and the second external electrode, and a distance in the width direction at the length direction center of the exposed portion is longer than a maximum distance in the width direction of surfaces connecting the first side surface side and the second side surface side of the first covered portion and the second covered portion, and shorter than a maximum distance in the width direction of surfaces connecting the first side surface side and the second side surface side of the first external electrode and the second external electrode.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The first main surface has a first exposed surface exposed from the first external electrode and the second external electrode, a first covered surface covered by the first external electrode, and a second covered surface covered by the second external electrode, the first exposed surface has a first flat surface parallel to the stacking direction, a first inclined surface linking the first flat surface and the first covered surface, and a second inclined surface linking the first flat surface and the second covered surface.

5. The multilayer ceramic capacitor according to claim 4, wherein The distance in the length direction of the first inclined surface and the distance in the length direction of the second inclined surface are shorter than the distance in the length direction of the first flat surface.

6. The multilayer ceramic capacitor according to claim 2 or 3, wherein The first side surface has a first side surface exposed surface exposed from the first external electrode and the second external electrode, a first side surface covered surface covered by the first external electrode, and a second side surface covered surface covered by the second external electrode, The first side surface exposed surface has a first side surface flat surface parallel to the stacking direction, a first side surface inclined surface linking the first side surface flat surface and the first side surface covered surface, and a second side surface inclined surface linking the first side surface flat surface and the second side surface covered surface.

7. The multilayer ceramic capacitor according to claim 6, wherein The distance in the length direction of the first side surface inclined surface and the distance in the length direction of the second side surface inclined surface are shorter than the distance in the length direction of the first side surface flat surface.

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