Semiconductor device
By setting a high impurity concentration barrier layer at the diode region boundary in the RC-IGBT structure, the carrier discharge during turn-off is reduced, which solves the problems of switching losses and thermal damage during IGBT turn-off and expands the reverse bias safe operation area.
Patent Information
- Application Number
- CN202480018623.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-04-12
- Filing Date
- 2024-01-31
- Publication Date
- 2025-11-07
AI Technical Summary
In the existing RC-IGBT structure, the accumulation of charge carriers during IGBT turn-off leads to increased switching losses, increased risk of thermal damage, and narrowing of the reverse bias safe operating area (RBSOA).
An IGBT element and a diode region are disposed on the same semiconductor substrate. The boundary region between the diode region and the transistor region has a barrier layer with a high impurity concentration, while the boundary region does not have a barrier layer with a high impurity concentration, thereby increasing the contact area between the diode region and the transistor region.
By reducing carrier discharge during turn-off, switching losses are reduced, the reverse bias safe operating area (RBSOA) is expanded, and thermal damage to components is prevented.
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Figure CN120917893A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor device. BACKGROUND
[0002] As a technology related to a semiconductor device of an RC-IGBT structure in which an Insulated Gate Bipolar Transistor (IGBT) and a freewheeling diode are provided on the same substrate, there is a technology disclosed in Patent Literature 1. In Patent Literature 1, it is described that "in a semiconductor substrate, a protection ring of a second conductivity type to which a voltage of the same potential as an anode layer of a diode region is applied is formed in an outer peripheral region surrounding an element region in which an IGBT region and the diode region are formed. When a minimum value of a distance between a cathode layer and the protection ring in a case of being projected onto a plane parallel to a surface of the semiconductor substrate is set to L, and a thickness of the semiconductor substrate is set to d, the cathode layer and the protection ring are formed at a position satisfying L / d ≥ 1.5. Thereby, it is possible to suppress injection of a large amount of carriers from the protection ring to a drift layer, and when the diode region is switched to a reverse bias, it is possible to suppress inflow of a large amount of holes to the anode layer. As a result, it is possible to achieve further improvement of a recovery withstand amount of the diode."
[0003] PRIOR ART DOCUMENTS
[0004] PATENT LITERATURE
[0005] Patent Literature 1: Japanese Patent Application Publication No. 2017-224685 SUMMARY
[0006] PROBLEMS TO BE SOLVED BY THE INVENTION
[0007] However, in the semiconductor device of the above-described structure, in a case where the IGBT is caused to perform an on operation, a conductivity modulation obtained by causing a minority carrier to be accumulated in the IGBT region makes it possible to perform another operation of a high withstand voltage and a low on resistance. However, in an off operation of the IGBT, the carrier accumulated in the IGBT region becomes a main cause of thermal destruction of the element due to an increase in switching loss, and narrows a Reverse Bias Safe Operating Area (RBSOA).
[0008] Therefore, an object of the present application is to provide a semiconductor device of an RC-IGBT structure capable of achieving expansion of a Reverse Bias Safe Operating Area (RBSOA).
[0009] MEANS FOR SOLVING THE PROBLEMS
[0010] To solve the above problems, for example, the structure described in the claims is adopted.
[0011] The present application includes a plurality of means for solving the above problems, and one example is a semiconductor device having: a first-conductivity-type drift layer; a second-conductivity-type body layer formed in a surface layer on one main surface side of the drift layer; a first-conductivity-type first diffusion layer partially formed in a surface layer on one main surface side of the body layer; and a second-conductivity-type second diffusion layer having a higher impurity concentration than a collector layer of the second-conductivity-type formed in a surface layer on the other main surface side of the drift layer and the drift layer, a transistor region in which an IGBT element composed of the first diffusion layer, the body layer, the drift layer, and the collector layer is arranged, and a diode region in which an FWD element composed of the body layer, the drift layer, and the second diffusion layer is arranged are provided on the same semiconductor substrate, the diode region has a first-conductivity-type barrier layer having a higher impurity concentration than the drift layer between the body layer and the drift layer, and an area of the body layer and the drift layer of a boundary region of the diode region with the transistor region is wider than other regions in the diode region.
[0012] Effects of Invention
[0013] According to the present application, a semiconductor device of an RC-IGBT structure capable of achieving an enlarged Reverse Bias Safe Operating Area (RBSOA) can be provided. BRIEF DESCRIPTION OF DRAWINGS
[0014] Figure 1 is a cross-sectional schematic view of the semiconductor device of the first embodiment (1).
[0015] Figure 2 is a cross-sectional schematic view of the semiconductor device of the first embodiment (2).
[0016] Figure 3 is a cross-sectional schematic view of the semiconductor device of the second embodiment. DETAILED DESCRIPTION
[0017] Hereinafter, each embodiment to which the present application is applied will be described in detail based on the drawings. Furthermore, in each embodiment described below, the same reference numerals are assigned to the same constituent elements, and overlapping descriptions will be omitted. In addition, hereinafter, the first-conductivity-type will be described as n-type, and the second-conductivity-type will be described as p-type, but the conductivity types can be reversed.
[0018] FIRST EMBODIMENT
[0019] Figure 1is a cross-sectional view of a semiconductor device 1 of a first embodiment (1). The semiconductor device 1 shown in this figure is a reverse conducting IGBT (RC-IGBT) provided with an insulated gate bipolar transistor (IGBT element 1tr) and a free wheeling diode (FWD element 1d) on the same semiconductor substrate 10. Hereinafter, the semiconductor device 1 will be described in the order of the region structure when the semiconductor substrate 10 is viewed from above, and the cross-sectional structure when the semiconductor substrate 10 is viewed from the cross section.
[0020] <Region structure>
[0021] First, the region structure of the semiconductor device 1 will be described. The semiconductor substrate 10 in which the semiconductor device 1 is provided has a transistor region 10tr in which a plurality of IGBT elements 1tr are arranged, and a diode region 10d in which a plurality of FWD elements 1d are arranged. Here, the transistor region 10tr and the diode region 10d are alternately arranged, for example, along one arrangement direction [x], but are not limited thereto, and can be a structure in which the diode region 10d is island-shapedly arranged in the transistor region 10tr.
[0022] The diode region 10d sets a region adjacent to the transistor region 10tr as a boundary region 10db. Such a boundary region 10db is a region of about 100 μm from the boundary of the transistor region 10tr, and is a range in which the diffusion layer of the diode region 10d can affect the carrier of the transistor region 10tr, as will be described later.
[0023] In such a boundary region 10db, a boundary region FWD element 1db of a structure different from the FWD element 1da provided in the other diode region 10da in the diode region 10d is provided. Hereinafter, the region in the diode region 10d excluding the boundary region 10db will be simply referred to as the diode region 10da. Further, the FWD element 1d provided in the diode region 10da other than the boundary region 10db will be described as simply referred to as the FWD element 1da with respect to the boundary region FWD element 1db.
[0024] Figure 1 A cross-sectional configuration along the arrangement direction [x] between the transistor region 10tr - the boundary region 10db - the diode region 10da is shown, and the cross sections of the IGBT element 1tr of 3-element amount, the boundary region FWD element 1db of 2-element amount, and the FWD element 1da of 3-element part are shown.
[0025] In addition, in the boundary region FWD element 1db, the FWD element 1da is provided with a structure different from the FWD element 1da provided in the diode region 10da other than the boundary region 10db. Figure 1In the embodiment, an example in which two boundary region FWD elements ldb are arranged in the arrangement direction [x] of the boundary region lOdb is shown, but the present embodiment is not limited thereto. The number of boundary region FWD elements ldb arranged in the arrangement direction [x] can be one or more as long as the elements are arranged within the boundary region lOdb having a width of about 100 μm.
[0026] <cross-sectional structure>
[0027] Next, the cross-sectional structure of the semiconductor device 1 will be described. The semiconductor substrate 10 in which the semiconductor device 1 is provided is a substrate having a relatively thin impurity concentration of the first conductivity type, which is an n- substrate in this embodiment. The semiconductor substrate 10 has a plurality of trenches lOa on one main surface (hereinafter referred to as a front surface). Each of the trenches lOa is arranged in a direction perpendicular to the arrangement direction [x] (a depth direction in the drawing) and is arranged corresponding to each element, i.e., each IGBT element ltr and each FWD element ld, with respect to the arrangement direction [x]. These trenches lOa are formed in the same process and can have the same depth.
[0028] In each of the trenches lOa, an electrode pattern 12 is embedded through an insulating film 11 provided on the inner wall of the trench lOa. The insulating film 11 can be a film formed on the inner wall of the trench lOa or a film grown from the inner wall of the trench lOa into the semiconductor substrate 10 by oxidation or nitridation.
[0029] The insulating film 11 in the transistor region lOtr in particular functions as a gate insulating film 11g. In addition, the electrode pattern 12 in the transistor region lOtr is used as a gate electrode 12g. On the other hand, the electrode pattern 12 in the diode region lOd is connected to an emitter electrode 14 described later.
[0030] In addition, an interlayer insulating film 13 is patterned on the front surface of the semiconductor substrate 10 so as to cover the electrode pattern 12. The interlayer insulating film 13 is patterned so as to cover the electrode pattern 12 and expose the semiconductor substrate 10 between the trenches lOa. Further, the emitter electrode 14 is patterned on one main surface of the semiconductor substrate 10 through the interlayer insulating film 13. The emitter electrode 14 is held in a state of being insulated from the electrode pattern 12 in the trench lOa by the interlayer insulating film 13 and, on the other hand, is held in a state of being connected to the semiconductor substrate 10 between the interlayer insulating films 13.
[0031] On the other hand, a collector electrode 15 is patterned on the other main surface (hereinafter referred to as a back surface) of the semiconductor substrate 10.
[0032] Next, the diffusion layer structure inside the semiconductor substrate 10 in the transistor region 10tr, the diode region 10da, and the boundary region 10db will be described. The diffusion layer is a layer having each conductivity type formed by introducing an n-type impurity or a p-type impurity into the n- semiconductor substrate 10. Hereinafter, the n- region in the semiconductor substrate 10 remaining by the formation of the diffusion layer based on the impurity introduction will be particularly referred to as an n- drift layer 100.
[0033] [Transistor region 10tr]
[0034] In the transistor region 10tr, the surface side of the semiconductor substrate 10 in which the trench 10a is provided is covered with a diffusion layer of the p-type (referred to as a p-type body layer 101). The p-type body layer 101 is formed shallower than the above-described trench 10a.
[0035] On the surface side of the p-type body layer 101, at a position in contact with the gate insulating film 11g, an n+ diffusion layer 102 having a width exposed from the interlayer insulating film 13 is provided. The n+ diffusion layer 102 is provided as a first diffusion layer of the n-type (first conductivity type). The n+ diffusion layer 102 is provided with a gap between the adjacently arranged trenches 10a, in a state in which the p-type body layer 101 is exposed on the surface of the semiconductor substrate 10 in the gap. Thereby, the p-type body layer 101 and the n+ diffusion layer 102 are in a state of being connected with the emitter electrode 14 between the trenches 10a.
[0036] Further, between the p-type body layer 101 and the n- drift layer 100, an n-type barrier layer 103 composed of an n-type diffusion layer having a higher n-type impurity concentration than the semiconductor substrate 10 is provided. The n-type barrier layer 103 is formed at a position shallower than the trench 10a and is arranged between the trenches 10a. In the drawing, a structure in which the n-type barrier layer 103 is provided in a manner of blocking the gap between the trenches 10a is shown, but the n-type barrier layer 103 can be arranged at the center between the trenches 10a and provided so as to be apart from the gate insulating film 11g.
[0037] By the above structure, the surface side of the semiconductor substrate 10 in the transistor region 10tr becomes a state in which an MOS type transistor having the n+ diffusion layer 102 as a drain, and the n-type barrier layer 103 and the n- drift layer 100 as a source is arranged.
[0038] On the other hand, in the transistor region 10tr, the back surface side of the semiconductor substrate 10 is provided with a p-type collector layer 104 composed of a p-type diffusion layer as an outermost surface. Further, in the semiconductor substrate 10, between the p-type collector layer 104 and the n- drift layer 100, an n-type buffer layer 105 composed of an n-type diffusion layer is provided. Further, the n-type buffer layer 105 can be provided as needed, or can not be provided.
[0039] By the above structure, in the transistor region 10tr, a state is made in which a PNP bipolar transistor having the n-type barrier layer 103, the n- drift layer 100, and the n-type buffer layer 105 interposed between the p-type body layer 101 and the p-type collector layer 104 is arranged.
[0040] Also, in the transistor region 10tr, a state is made in which the IGBT element 1tr in which a MOS transistor arranged on the surface side of the semiconductor substrate 10 is used as a switching element of the PNP bipolar transistor is arranged.
[0041] The IGBT element 1tr becomes a current conduction state by applying a positive voltage with respect to the emitter electrode 14 to the gate electrode 12g. In this case, electrons gather at the position of the gate electrode 12g along the p-type body layer 101, a channel inverted to n-type is formed, and thus a base current flows through the PNP bipolar transistor. Then, electrons supplied from the emitter electrode 14 reach the collector electrode 15 in the path of the n+ diffusion layer 102, the n-type channel, the n-type barrier layer 103, the n- drift layer 100, the n-type buffer layer 105, and the p-type collector layer 104. In addition, holes supplied from the collector electrode 15 reach the emitter electrode 14 in the path opposite to that of the electrons.
[0042] At this time, by providing the n-type barrier layer 103, movement of holes from the n- drift layer 100 to the p-type body layer 101 is prevented, and holes can be efficiently accumulated in the n- drift layer 100. Thus, a structure is made in which the conductivity modulation effect of the IGBT element 1tr can be reliably obtained, and an increase in on-resistance is suppressed.
[0043] [Diode region 10da]
[0044] In the diode region 10da, the surface side of the semiconductor substrate 10 in which the trench 10a is provided is covered with an anode layer 101' composed of the p-type body layer 101. The anode layer 101' is formed shallower than the trench 10a explained above. In addition, the anode layer 101' is in a state connected to the emitter electrode 14 between the trenches 10a.
[0045] Between the anode layer 101' and the n- drift layer 100, an n-type barrier layer 103' composed of an n-type diffusion layer having a higher impurity concentration than the semiconductor substrate 10 is provided. The n-type barrier layer 103' has the same structure as the n-type barrier layer 103 of the transistor region 10tr, and can be a layer formed in the same process. Thus, the n-type barrier layer 103' is formed at a position shallower than the trench 10a, and is arranged between the trenches 10a. In addition, the n-type barrier layer 103' can be arranged at the center between the trenches 10a, and can be provided separately from the insulating film 11 with respect to the inner wall of the trench 10a.
[0046] On the other hand, in the diode region 10d, on the back surface side of the semiconductor substrate 10, a second diffusion layer of the first conductive type (n-type) having a higher impurity concentration than the drift layer is provided as a cathode layer 106. The back surface side of the semiconductor substrate 10 is covered with the cathode layer 106 composed of the n+ diffusion layer. This cathode layer 106 is provided in ground connection with the collector electrode 15, and becomes in a state of connection with the collector electrode 15. Such a cathode layer 106 can have, for example, the same depth as the p-type collector layer 104 of the transistor region 10tr.
[0047] Further, between the cathode layer 106 and the n- drift layer 100, an n-type buffer layer 105 composed of an n-type diffusion layer provided so as to extend from the transistor region 10tr is provided. The n-type buffer layer 105 has a higher n-type impurity concentration than the n- drift layer 100, and a lower n-type impurity concentration than the cathode layer 106. Further, this n-type buffer layer 105 can be provided as needed, or can not be provided.
[0048] With the above structure, in the diode region 10da, the anode layer 101' is connected to the emitter electrode 14, and the cathode layer 106 is connected to the collector electrode 15, thereby becoming in a state of being provided with an FWD element 1da connected in anti-parallel with respect to the IGBT element 1tr provided in the transistor region 10tr.
[0049] This FWD element 1da is connected in anti-parallel with respect to the IGBT element 1tr, and therefore, in a state in which the IGBT element 1tr is in an on state, a reverse bias is applied to the anode layer 101' and the cathode layer 106, and no current flows. On the other hand, the FWD element 1da becomes a path for releasing a backflow current generated in the IGBT element 1tr in the case where the IGBT element 1tr is turned off, and prevents damage to the IGBT element 1tr.
[0050] Further, in the case where the FWD element 1da becomes in a forward on state due to the flow of the above-mentioned backflow current, the movement of holes from the anode layer 101' to the n- drift layer 100 can be prevented by the n-type barrier layer 103' provided in ground connection with the anode layer 101'.
[0051] [Boundary region 10db]
[0052] The diffusion layer configuration of the semiconductor substrate 10 in the boundary region 10db is different from the diffusion layer configuration in the diode region 10da only in that the n-type barrier layer 103' is not provided. That is, the boundary region FWD element 1db in the boundary region 10db becomes a structure in which the n-type barrier layer 103' is removed from the FWD element 1da provided in the diode region 10da.
[0053] The boundary region FWD element 1db is connected in anti-parallel with respect to the IGBT element 1tr, so in a state in which the IGBT element 1tr is in an on state, the anode layer 101' and the cathode layer 106 are applied with a reverse bias, and no current flows. Furthermore, the FWD element 1d becomes a path that releases a backflow current generated in the IGBT element 1tr that is turned off, in the case in which the IGBT element 1tr is turned off, and prevents damage to the IGBT element 1tr, as with the FWD element 1da.
[0054] <Effects of the First Embodiment>
[0055] The semiconductor device 1 of the first embodiment described above is a structure in which the n-type barrier layer 103' is provided only in the diode region 10da other than the boundary region 10db. Due to this, in the boundary region 10db, there is no region in which the concentration of n-type impurities is higher than the n-drift layer 100 between the p-type anode layer 101' and the n-drift layer 100, and a structure in which the anode layer 101' and the n-drift layer 100 are in contact with a large area is formed. With this structure, the following effects can be obtained.
[0056] Figure 2 is a cross-sectional view of the semiconductor device of the first embodiment (2), and is a schematic view at the time of turning off the IGBT element 1tr from an on state to an off state. As shown in Figure 2 , in a state in which the IGBT element 1tr is turned off, a state in which holes as minority carriers are stored in the n-drift layer 100 of the transistor region 10tr is formed. At this time, the boundary region 10db does not have the n-type barrier layer 103' in which the concentration of n-type impurities is high, and a state in which the p-type anode layer 101' of the region is exposed is formed, so the holes of the n-drift layer 100 are easily discharged from the p-type anode layer 101'.
[0057] Due to this, the total amount of carriers (holes) that are discharged due to dynamic avalanche at the junction of the p-type body layer 101 - n-type barrier layer 103 of the IGBT element 1tr that is turned off can be reduced. Furthermore, the base current that is supplied to the pnpn-type parasitic thyristor that exists in the IGBT element 1tr is reduced, and latch-up damage to the IGBT element 1tr can be prevented. As a result, expansion of the reverse bias safe operating area in the semiconductor device 1 of the RC-IGBT structure can be achieved.
[0058] Further, in the first embodiment described above, the n-type barrier layer 103' is not provided in the boundary region 10db. However, the boundary region 10db can also be configured such that the n-type barrier layer 103' having a shape that is smaller than that of the transistor region 1da is provided, and the area where the anode layer 101' is in contact with the n-drift layer 100 is larger than the transistor region 1da. Even with such a configuration, the effect of expanding the reverse bias safe operating area described above can be achieved.
[0059] Second Embodiment
[0060] Figure 3 is a cross-sectional view of a semiconductor device 2 according to a second embodiment. The semiconductor device 2 according to the second embodiment shown in this figure is different from the semiconductor device 1 according to the first embodiment described above in the depth of the anode layer 101" of the boundary region FWD element 1db" provided in the boundary region 10db, and is otherwise the same as the semiconductor device 1 according to the first embodiment. Figure 1 Figure 2
[0061] The anode layer 101" of the boundary region FWD element 1db" is formed deeper than the anode layer 101' of the diode region 10da. The depth of the anode layer 101" can be deeper than the anode layer 101' of the diode region 10da, but is preferably deeper than the trench 10a.
[0062] Further, as shown in the figure, the anode layer 101" is more preferably formed in a shape that covers the bottom surface of the trench 10a. Such an anode layer 101" can be formed by introducing a p-type impurity deeper than the predetermined depth of the trench 10a into the semiconductor substrate 10 before the trench 10a is formed. Further, in the case where the insulating film 11 is grown from the inner wall of the trench 10a into the semiconductor substrate 10 by oxidation or nitridation, the anode layer 101" can be formed to a depth that takes into account the film thickness of the insulating film 11. Figure 3 Effects of the Second Embodiment
[0063] According to the semiconductor device 2 according to the second embodiment described above, the anode layer 101" of the boundary region 10db is deeper than the anode layer 101' of the diode region 10da. Thus, compared to the configuration of the first embodiment, the boundary between the p-type anode layer 101" and the n-drift layer 100 in the boundary region 10db is closer to the n-drift layer 100 of the transistor region 10tr. Therefore, compared to the configuration of the first embodiment, it is further easy to discharge the holes accumulated in the n-drift layer 100 from the anode layer 101" of the boundary region 10db at the turn-off operation of the IGBT element 1tr.
[0064]
[0065] Further, by setting the shape of the anode layer 101" of the boundary region 10db to a shape that covers the bottom surface of the trench 10a, the boundary between the p-type anode layer 101" and the n- drift layer 100 in the boundary region 10db is enlarged. Thus, the discharge effect of the holes from the n-drift layer 100 at the time of turning off can be more effectively obtained.
[0066] Further, in each of the above-described embodiments, the first conductivity type is set to n-type and the second conductivity type is set to p-type, but the conductivity types can be reversed, in which case, in the description of each of the embodiments, n-type is replaced with p-type, p-type is replaced with n-type, anode is replaced with cathode, electron is replaced with hole, and hole is replaced with electron.
[0067] Further, the present application is not limited to the above-described embodiments and modified examples, but includes various modified examples. For example, the above-described embodiments are examples in which the present application is described in detail in order to easily understand the present application, and are not necessarily limited to having all the structures described. In addition, a part of the structure of one embodiment can be replaced with the structure of another embodiment, and the structure of one embodiment can be added with the structure of another embodiment.
[0068] In addition, with respect to a part of the structure of each of the embodiments, addition, deletion, and replacement of other structures can be performed.
[0069] Symbol explanation
[0070] 1, 2: semiconductor device, 1tr: IGBT element, 1d: FWD element, 1db, 1db": boundary region FWD element, 10: semiconductor substrate, 10a: trench, 10bd: boundary region, 10tr: transistor region, 10d: diode region, 11: insulating film, 12: electrode pattern, 100: n-drift layer, 101: p-type body layer, 101', 101": anode layer (p-type body layer), 102: n+ diffusion layer (first diffusion layer of first conductivity type), 103, 103': n-type barrier layer, 104: p-type collector layer, 106: cathode layer (second diffusion layer of first conductivity type).
Claims
1. A semiconductor device comprising: a drift layer of a first conductivity type; a body layer of a second conductivity type formed on a surface layer on one main surface side of the drift layer; a first diffusion layer of the first conductivity type partially formed on a surface layer on one main surface side of the body layer; and a second diffusion layer of the first conductivity type having a higher impurity concentration than a collector layer of the second conductivity type formed on a surface layer on the other main surface side of the drift layer and the drift layer, a transistor region in which an IGBT element composed of the first diffusion layer, the body layer, the drift layer, and the collector layer is arranged and a diode region in which an FWD element composed of the body layer, the drift layer, and the second diffusion layer is arranged are provided on the same semiconductor substrate, the semiconductor device being characterized in that: the diode region has a barrier layer of the first conductivity type having a higher impurity concentration than the drift layer between the body layer and the drift layer, and an area of the body layer and the drift layer of the boundary region of the diode region with the transistor region is wider than other regions in the diode region.
2. The semiconductor device according to claim 1, wherein: the barrier layer is provided only in regions other than the boundary region in the diode region.
3. The semiconductor device according to claim 1, wherein: the boundary region is a region in a range of 100 μm from the transistor region.
4. The semiconductor device according to claim 1, wherein: the transistor region has the barrier layer between the body layer and the drift layer.
5. The semiconductor device according to claim 1, wherein: the body layer of the boundary region is deeper than other regions.
6. The semiconductor device according to claim 1, wherein: the semiconductor substrate has a trench on one main surface side and an electrode pattern embedded in the trench through an insulating film, and the body layer is deeper than the trench in the boundary region and shallower than the trench in other regions.
7. The semiconductor device according to claim 6, wherein: the body layer is provided so as to cover a bottom surface of the trench in the boundary region.
8. The semiconductor device according to claim 6, wherein: the first diffusion layer is provided so as to contact the insulating film in the trench in the transistor region, and the barrier layer is arranged between the trenches.
Citation Information
Patent Citations
Semiconductor device
JP2017224685A