Semiconductor device
By adjusting the contact layer area distribution near the boundary between the IGBT and diode regions, the carrier injection amount is controlled, thus solving the component damage problem caused by carrier concentration and improving the stability and reliability of semiconductor devices.
Patent Information
- Application Number
- CN202480017078.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-04-06
- Filing Date
- 2024-02-01
- Publication Date
- 2025-11-07
AI Technical Summary
Within the IGBT and diode regions of the same chip, charge carriers tend to concentrate at the boundary, leading to component damage. This is especially true during diode recovery, when charge carriers flow from the diode region into the IGBT region, increasing the risk of component damage.
Near the boundary between the IGBT region and the diode region, the area distribution of the contact layer is adjusted so that the area of the high-concentration contact layer in the diode region is smaller than that far from the boundary, while the area of the low-concentration contact layer in the IGBT region is smaller than that near the boundary. This controls the amount of carrier injection and reduces the concentration of carriers at the boundary.
It effectively suppresses the inflow of charge carriers from the diode region to the IGBT region, avoids damage to the components, and improves the reliability and stability of the semiconductor device.
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Figure CN120917896A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor device. BACKGROUND
[0002] An RC-IGBT (RC: Reverse-Conducting IGBT) in which an IGBT and a diode are built in the same chip can make the terminal regions of the IGBT and the diode common, and thus has an advantage of being able to reduce the chip size. In addition, since the timings of the IGBT and the diode to act are different, respectively, the heat generated by the loss generated in one of the IGBT region and the diode region is dispersed to the other, and the chip as a whole can be cooled, and thus has an advantage of being able to reduce the thermal resistance.
[0003] On the other hand, in the RC-IGBT, at the timing when the IGBT is turned on and the diode changes from being turned on to being turned off, that is, at the time of recovery of the diode, carriers (holes) easily flow from the diode region to the IGBT region, and thus there is a problem that the carriers (holes) concentrate at the boundary portion of the diode region and the IGBT region and the element is destroyed.
[0004] As a semiconductor device that reduces the destruction of such an element, for example, in FIG. 9 of Patent Literature 1, a configuration is described in which, in the IGBT region closest to the boundary of the IGBT region (10) and the diode region (20), a p+ type contact layer (14) is not provided, the surface of an n+ type source layer (13) and a p type base layer (15) constitute a first main surface of a semiconductor substrate, and the n+ type source layer (13) is connected to an active trench gate (11), but is not connected to a boundary trench gate (51).
[0005] PRIOR ART DOCUMENTS
[0006] PATENT LITERATURE
[0007] Patent Literature 1: Japanese Patent Application Laid-Open No. 2022-25674 SUMMARY
[0008] PROBLEMS TO BE SOLVED BY THE INVENTION
[0009] However, if the p+ type contact layer (14) is not provided in the IGBT region of the boundary portion as in Patent Literature 1, there is a possibility that a problem in which the on voltage rises because the holes also hardly flow in the IGBT of the boundary portion at the time of the operation of the IGBT, and a problem in which the IGBT is easily latched occur.
[0010] The present application provides a semiconductor device having an IGBT region and a diode region in the same chip, and is capable of suppressing the inflow of carriers from the diode region to the IGBT region at the time of diode recovery, and concentrating the carriers at the boundary portion so as to prevent the element from being destroyed.
[0011] Means for solving the problem
[0012] To solve the above problem, the semiconductor device of the present application, for example, has an IGBT region and a diode region in the same chip, and is characterized in that the IGBT of the IGBT region has a drift layer of a first conductivity type, a body layer of a second conductivity type, a first contact layer of the second conductivity type connected to the body layer and having a higher impurity concentration than the body layer, and an emitter electrode connected to the first contact layer, the diode of the diode region has a first semiconductor layer of the second conductivity type, a second contact layer of the second conductivity type connected to the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer, and a first electrode connected to the second contact layer and the emitter electrode, the area of the second contact layer of the diode near the boundary portion of the IGBT region and the diode region is smaller than the area of the second contact layer of the diode at a position away from the vicinity of the boundary portion, and the area of the first contact layer of the IGBT near the vicinity of the boundary portion is smaller than the area of the first contact layer of the IGBT at a position away from the vicinity of the boundary portion.
[0013] Effects of the Invention
[0014] According to the present application, in a semiconductor device having an IGBT region and a diode region in the same chip, at the time of diode recovery, the inflow of carriers from the diode region to the IGBT region can be suppressed, and the carriers can be concentrated at the boundary portion so as to prevent the element from being destroyed. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 is a perspective view illustrating the outline structure of the semiconductor device of Embodiment 1.
[0016] Figure 2 is a plan view of the semiconductor device of Embodiment 1.
[0017] Figure 3 is a plan view of the semiconductor device of Embodiment 2.
[0018] Figure 4 is a plan view of the semiconductor device of Embodiment 3.
[0019] Figure 5 is a plan view of the semiconductor device of Embodiment 4. DETAILED DESCRIPTION
[0020] Embodiments of the present application will be described below with reference to the drawings. In the drawings, the same or similar components are denoted by the same reference signs, and repetitive explanations will be omitted.
[0021] Embodiment 1
[0022] Figure 1 is a perspective view illustrating a schematic configuration of the semiconductor device of Embodiment 1. Figure 2 is a plan view of the semiconductor device of Embodiment 1.
[0023] As Figure 1 shown, the semiconductor device 1 is an RC-IGBT having an IGBT region 21 and a diode region 22 in the same chip.
[0024] The IGBT of the IGBT region 21 has a drift layer 2 of a first conductivity type (n-type in the present example), a body layer 3 of a second conductivity type (p-type in the present example), a first contact layer 5 of the second conductivity type connected to the body layer 3 and having a higher impurity concentration than the body layer 3, and an emitter electrode (omitted from the drawing) connected to the first contact layer 5. Further, as will be described later, the conductivity types of the semiconductor layers are not limited to the example shown in the drawing, and the n-type and the p-type can be exchanged. In addition, as will be described later, the impurity concentrations such as n- and p+ are also one example, and can be appropriately changed within a range in which desired operations can be performed. Figure 1 Figure 1 Figure 1
[0025] Further, the IGBT of the IGBT region 21 has a trench gate 6, a gate insulating film 7, an emitter layer 4 of the first conductivity type connected to the body layer 3, a collector layer 9 of the second conductivity type provided on the back surface side as compared with the drift layer 2, and a collector electrode 10 connected to the collector layer 9. The collector electrode 10 is also connected to a second electrode 16 of the diode region 22 to be described later. Furthermore, the IGBT of the IGBT region 21 preferably has a buffer layer 8 of the first conductivity type provided between the drift layer 2 and the collector layer 9 and having a higher impurity concentration than the drift layer 2.
[0026] The trench gate 6 and the gate insulating film 7 are formed in a trench reaching the drift layer 2 through the body layer 3. The trench gate 6 is formed of, for example, polysilicon. A gate potential G is applied to the trench gate 6.
[0027] The first contact layer 5 is in ohmic contact with the emitter electrode (omitted from the drawing) via a contact hole formed in an interlayer insulating film (omitted from the drawing). An emitter potential E is applied to the first contact layer 5. In addition, the emitter layer 4 is in ohmic contact with the emitter electrode (omitted from the drawing) via a contact hole formed in an interlayer insulating film (omitted from the drawing), or is connected to the emitter electrode (omitted from the drawing) via the first contact layer 5.
[0028] The diode of the diode region 22 has a first semiconductor layer 11 of a second conductivity type, a second contact layer 12 of the second conductivity type connected to the first semiconductor layer 11 and having a higher impurity concentration than the first semiconductor layer 11, and a first electrode (not shown) connected to the second contact layer 12 and an emitter electrode (not shown).
[0029] Further, the diode of the diode region 22 has a drift layer 2 provided on the back surface side of the first semiconductor layer 11, a second semiconductor layer 15 of a first conductivity type provided on the back surface side of the drift layer 2 and having a higher impurity concentration than the drift layer 2, and a second electrode 16 connected to the second semiconductor layer 15.
[0030] Here, as shown in FIG. 1, in a case where the first conductivity type is n-type and the second conductivity type is p-type, the first semiconductor layer 11 is an anode layer, the first electrode (not shown) is an anode electrode, the second semiconductor layer 15 is a cathode layer, and the second electrode 16 is a cathode electrode. Figure 1
[0031] In the diode region 22, no interlayer insulating film is formed, the high-concentration second contact layer 12 is in ohmic contact with the first electrode (not shown), and an anode potential A equal to the emitter potential E is applied to the second contact layer 12. Further, the low-concentration first semiconductor layer 11 is in Schottky junction with the first electrode (not shown).
[0032] Further, in a case where the first conductivity type is p-type and the second conductivity type is n-type, the first semiconductor layer 11 is a cathode layer, the first electrode (not shown) is a cathode electrode, the second semiconductor layer 15 is an anode layer, and the second electrode 16 is an anode electrode.
[0033] Further, it is preferable that the buffer layer 8 is also formed in the diode region 22.
[0034] It is preferable that a trench reaching the drift layer 2 through the first semiconductor layer 11 is formed in the diode region 22, and that a diode region trench electrode 13 and a diode region trench insulating film 14 are formed in the trench. The diode region trench electrode 13 is formed of, for example, polysilicon. It is preferable that the diode region trench electrode 13 is applied with an anode potential A equal to the emitter potential E.
[0035] In the semiconductor device 1 of the present embodiment, the injection amount of carriers (holes when the first conductivity type is n-type and the second conductivity type is p-type, as shown in FIG. 1) at the time of diode conduction can be controlled by the ratio of the high-concentration second contact layer 12 formed on the surface to the low-concentration first semiconductor layer 11. When the second contact layer 12 is greater, more carriers are injected, and when the first semiconductor layer 11 is greater, the injection of carriers can be suppressed. Figure 1
[0036] Therefore, the semiconductor device 1 of the present embodiment makes the area of the second contact layer 12 of the diode near the boundary portion 24 of the boundary portion 23 between the IGBT region 21 and the diode region 22 smaller than the area of the second contact layer 12 of the diode at a position farther than the boundary portion near 24. Thus, the carrier injection amount at the time of conduction of the diode at the boundary portion near 24 is smaller than the carrier injection amount of the diode at a position farther than the boundary portion near 24, and even if the carriers at the boundary portion near 24 flow to the IGBT region 21 side at the time of recovery of the diode, the carrier injection amount can be suppressed, so at the time of recovery of the diode, the flow of carriers from the diode region 22 to the IGBT region 21 can be suppressed, and the carriers can be concentrated at the boundary portion 23, and the element can be destroyed.
[0037] In addition to this, the semiconductor device 1 of the present embodiment makes the area of the first contact layer 5 of the IGBT near the boundary portion 25 of the boundary portion 23 between the IGBT region 21 and the diode region 22 smaller than the area of the first contact layer 5 of the IGBT at a position farther than the boundary portion near 25. Also at the time of conduction of the diode, holes as carriers are injected from the first contact layer 5 of the boundary portion near 25 in the IGBT region 21 to the boundary portion near 24, so by reducing the area of the first contact layer 5 of the boundary portion near 25, the carrier injection amount from the boundary portion near 25 to the boundary portion near 24 can be reduced, so at the time of recovery of the diode, the concentration of carriers at the boundary portion 23 can be suppressed, and the element can be destroyed.
[0038] In addition, in the Figure 1 In the present embodiment, the drift layer 2 is n-type of low concentration, the body layer 3 and the first semiconductor layer 11 are p-type of low concentration, the emitter layer 4 and the second semiconductor layer 15 are n+ type of high concentration, the first contact layer 5 and the second contact layer 12 are p+ type of high concentration, and the others are n-type or p-type, but not limited thereto, and can be appropriately changed within a range in which desired operation can be performed.
[0039] In addition, in the case where the first conductive type is p-type and the second conductive type is n-type, the carriers are electrons instead of holes, so the description of the holes related to the carriers can be replaced with electrons.
[0040] Embodiment 2
[0041] Figure 3 A plan view of the semiconductor device of Embodiment 2.
[0042] Example 2 is a modification of Example 1. The semiconductor device 1 of the present embodiment differs from that of Example 1 in that the area of the first contact layer 5 near the boundary portion 25 is made smaller than the area of the second contact layer 12 near the boundary portion 24. There is a npn parasitic transistor with the first contact layer 5 as the base in the IGBT, and when the carriers, i.e. holes, flowing into the vicinity of the boundary portion 25 at the time of diode recovery are extracted from the first contact layer 5, the parasitic transistor operates, so the IGBT is more likely to be destroyed than the diode. Therefore, by making the area of the first contact layer 5 near the boundary portion 25 smaller than the area of the second contact layer 12 near the boundary portion 24, the carriers flowing in at the time of diode recovery are more likely to be extracted near the boundary portion 24 than near the boundary portion 25, so the carriers flowing in near the boundary portion 25 can be reduced, whereby the operation of the parasitic transistor can be suppressed, and the destruction of the element can be suppressed. The same as Example 1 except for this is omitted from the description.
[0043] Example 3
[0044] Figure 4 is a plan view of the semiconductor device of Example 3.
[0045] Example 3 is a modification of Example 1. The semiconductor device 1 of the present embodiment differs from that of Example 1 in that the area of the second contact layer 12 near the boundary portion 24 gradually decreases as it approaches the boundary portion 23. Thereby, the carriers can be injected to some extent in the portion away from the boundary portion 23 in the vicinity of the boundary portion 24 to lower the forward voltage, and the concentration of carriers at the boundary portion 23 can be suppressed.
[0046] Further, the semiconductor device 1 of the present embodiment also differs from that of Example 1 in that the area of the first contact layer 5 near the boundary portion 25 gradually decreases as it approaches the boundary portion 23. Thereby, the carriers can be injected to some extent in the portion away from the boundary portion 23 in the vicinity of the boundary portion 25 to suppress the rise in the on-voltage at the time of IGBT operation, and the injection of carriers from the vicinity of the boundary portion 25 to the vicinity of the boundary portion 24 at the time of diode conduction can be suppressed, and the concentration of carriers at the boundary portion 23 at the time of diode recovery can be suppressed.
[0047] In addition, in Figure 4 , both the vicinity of the boundary portion 24 and the vicinity of the boundary portion 25 are changed from Example 1, but not limited thereto, and the structure of the present embodiment can be applied to only one of the vicinity of the boundary portion 24 and the vicinity of the boundary portion 25. In addition, Example 3 can be applied to Example 2. The same as Example 1 except for this is omitted from the description.
[0048] Example 4
[0049] Figure 5 is a plan view of the semiconductor device of Example 4.
[0050] Example 4 is a modification of Example 3. The semiconductor device 1 of the present embodiment is different from Example 3 in that the second contact layer 12 is not provided in the region of the diode region 22 that borders the boundary portion 23. Thus, as in Example 3, a certain degree of carriers is injected in the portion away from the boundary portion 23 in the vicinity of the boundary portion 24, and the effect of suppressing the concentration of carriers at the boundary portion 23 can be improved compared to Example 3.
[0051] Here, in the present embodiment, the first contact layer 5 borders the boundary portion 23 in the vicinity of the boundary portion 25. If the first contact layer 5 is not provided in the vicinity of the boundary portion 25, the on-voltage at the time of IGBT operation will increase, and thus the first contact layer 5 is retained in order to avoid this. The same as Example 3 except for this, and thus the description is omitted.
[0052] In addition, the structure of Example 4 can also be applied to Example 1 or Example 2. In this case, the effect of lowering the forward voltage is weaker than Example 3, but the effect of suppressing the concentration of carriers at the boundary portion 23 can be improved compared to Example 1 or Example 2.
[0053] The above describes the embodiments of the present application, but the present application is not limited to the structures described in the embodiments, and various changes can be made within the scope of the technical idea of the present application. In addition, a part or all of the structures described in each of the embodiments can be combined and applied.
[0054] Explanation of Symbols
[0055] 1: semiconductor device, 2: drift layer, 3: body layer, 4: emitter layer, 5: first contact layer, 6: trench gate, 7: gate insulating film, 8: buffer layer, 9: collector layer, 10: collector, 11: first semiconductor layer, 12: second contact layer, 13: diode region trench electrode, 14: diode region trench insulating film, 15: second semiconductor layer, 16: second electrode, 21: IGBT region, 22: diode region, 23: boundary portion, 24: vicinity of boundary portion, 25: vicinity of boundary portion, G: gate potential, E: emitter potential, A: anode potential.
Claims
1. A semiconductor device having an IGBT region and a diode region in the same chip, the semiconductor device characterized by, an IGBT of the IGBT region having a drift layer of a first conductivity type, a body layer of a second conductivity type, a first contact layer of the second conductivity type connected to the body layer and having a higher impurity concentration than the body layer, and an emitter electrode connected to the first contact layer, a diode of the diode region having a first semiconductor layer of the second conductivity type, a second contact layer of the second conductivity type connected to the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer, and a first electrode connected to the second contact layer and the emitter electrode, an area of the second contact layer of the diode near a boundary portion near the boundary portion of the IGBT region and the diode region is smaller than an area of the second contact layer of the diode at a position farther than the boundary portion, an area of the first contact layer of the IGBT near the boundary portion is smaller than an area of the first contact layer of the IGBT at a position farther than the boundary portion.
2. The semiconductor device according to claim 1, characterized in that, the area of the first contact layer near the boundary portion is smaller than the area of the second contact layer near the boundary portion.
3. The semiconductor device according to claim 1, characterized in that, the area of the first contact layer near the boundary portion gradually decreases as it approaches the boundary portion.
4. The semiconductor device according to claim 1, characterized in that, the area of the second contact layer near the boundary portion gradually decreases as it approaches the boundary portion.
5. The semiconductor device according to claim 1, characterized in that, the second contact layer is not provided in a region of the diode region that borders the boundary portion.
6. The semiconductor device according to claim 1, characterized in that, the diode has: the drift layer provided at a position farther from a back surface side than the first semiconductor layer, a second semiconductor layer of the first conductivity type provided farther from the back surface side than the drift layer and having a higher impurity concentration than the drift layer, and a second electrode connected to the second semiconductor layer.
7. The semiconductor device according to claim 6, characterized in that, the IGBT has: a trench gate, a gate insulating film, an emitter layer of the first conductivity type connected to the body layer, a collector layer of the second conductivity type provided farther from the back surface side than the drift layer, and a collector electrode connected to the collector layer and the second electrode. a buffer layer of the first conductivity type provided between the drift layer and the collector layer and having a higher impurity concentration than the drift layer.
9. The semiconductor device according to claim 1, characterized in that, 8. The semiconductor device according to claim 7, wherein the first conductivity type is n-type, the second conductivity type is p-type, the first semiconductor layer is an anode layer, and the first electrode is an anode electrode.
Citation Information
Patent Citations
Semiconductor device
JP2022025674A