Semiconductor device

Abstract

The purpose of the present invention is to facilitate planarization of an insulating film that covers a semiconductor chip bonded to the rear surface side of an imaging element. The semiconductor device has a first semiconductor substrate, a second semiconductor substrate, and a cover member. A second semiconductor substrate of the semiconductor device is bonded to a first semiconductor substrate of the semiconductor device, and a protruding portion is provided on a surface different from the bonding surface. A cover member in a semiconductor device covers a second semiconductor substrate bonded to a first semiconductor substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] A semiconductor device using a semiconductor chip including a logic circuit that processes an image signal is stacked on an imaging element in which pixels that generate an image signal in accordance with incident light are arranged in a two-dimensional matrix. As the imaging element used in such a semiconductor device, a back-illuminated type imaging element is applied in which a back surface side of a semiconductor substrate is irradiated with incident light. A front surface side of the semiconductor chip is bonded to and stacked on a front surface side of the imaging element. In a method of connecting the imaging element and the semiconductor chip, a Cu-Cu connection is used in which copper (Cu) pads arranged in respective wiring regions are bonded to each other to obtain an electrical connection.

[0003] Meanwhile, for example, a process in which a color filter or an on-chip lens that collects incident light is arranged on a back surface side of the imaging element is required. Therefore, a semiconductor device (a solid-state imaging device) has been proposed that generates by adhering a support substrate such as a silicon wafer to a back surface side of a semiconductor chip that is bonded to a front surface side of an imaging element and inverting the support substrate, and performing a process on a back surface side of the imaging element (for example, see Patent Literature 1).

[0004] Prior Art Documents

[0005] Patent Literature

[0006] Document 1: WO 2019 / 087764 A SUMMARY

[0007] Technical Problem

[0008] In the above-described conventional technology, an oxide film for adhering a support substrate is formed on a back surface side of a semiconductor chip. By planarizing the oxide film and thermocompression bonding the support substrate, the semiconductor chip and the support substrate are bonded via the oxide film. However, since the area of the semiconductor chip is smaller than the area of the imaging element, there is a region on the back surface side of the imaging element in which the semiconductor chip is not disposed. Therefore, there is a problem that a relatively large step is formed in the oxide film that covers the semiconductor chip, making it difficult to planarize the oxide film.

[0009] Therefore, the present disclosure proposes a semiconductor device that easily performs planarization of an insulating film that covers a semiconductor chip bonded to a back surface side of an imaging element.

[0010] Solution to Problem

[0011] A semiconductor device according to the present disclosure includes a first semiconductor substrate, a second semiconductor substrate joined to the first semiconductor substrate and including a protruding portion on a surface different from a joining surface, and a cover member covering the second semiconductor substrate joined to the first semiconductor substrate. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a view showing a configuration example of a semiconductor device according to a first embodiment of the present disclosure.

[0013] Figure 2 is a cross-sectional view showing a configuration example of a semiconductor device according to the first embodiment of the present disclosure.

[0014] Figure 3A is a view showing a configuration example of a cover member in a conventional technique.

[0015] Figure 3B is a view showing a configuration example of a cover member in a conventional technique.

[0016] Figure 4 is a view showing a configuration example of a protruding portion according to the first embodiment of the present disclosure.

[0017] Figure 5 is a view showing an example of a shape of a protruding portion according to the first embodiment of the present disclosure.

[0018] Figure 6A is a graph showing a relationship between a step of a material film and a shape of a protruding portion according to the first embodiment of the present disclosure.

[0019] Figure 6B is a graph showing a relationship between a polishing rate of a material film and a shape of a protruding portion according to the first embodiment of the present disclosure.

[0020] Figure 7A is a view showing an example of a manufacturing method of a semiconductor chip according to the first embodiment of the present disclosure.

[0021] Figure 7B is a view showing an example of a manufacturing method of a semiconductor chip according to the first embodiment of the present disclosure.

[0022] Figure 7C is a view showing an example of a manufacturing method of a semiconductor chip according to the first embodiment of the present disclosure.

[0023] Figure 7D is a view showing an example of a manufacturing method of a semiconductor chip according to the first embodiment of the present disclosure.

[0024] Figure 7Eis a view showing an example of a manufacturing method of a semiconductor chip according to the first embodiment of the present application.

[0025] Figure 8A is a view showing an example of a manufacturing method of a semiconductor device according to the first embodiment of the present disclosure.

[0026] Figure 8B is a view showing an example of a manufacturing method of a semiconductor device according to the first embodiment of the present disclosure.

[0027] Figure 8C is a view showing an example of a manufacturing method of a semiconductor device according to the first embodiment of the present disclosure.

[0028] Figure 8D is a view showing an example of a manufacturing method of a semiconductor device according to the first embodiment of the present disclosure.

[0029] Figure 8E is a view showing an example of a manufacturing method of a semiconductor device according to the first embodiment of the present disclosure.

[0030] Figure 8F is a view showing an example of a manufacturing method of a semiconductor device according to the first embodiment of the present disclosure.

[0031] Figure 8G is a view showing an example of a manufacturing method of a semiconductor device according to the first embodiment of the present disclosure.

[0032] Figure 8H is a view showing an example of a manufacturing method of a semiconductor device according to the first embodiment of the present disclosure.

[0033] Figure 9A is a view showing another configuration example of a protruding portion according to the first embodiment of the present disclosure.

[0034] Figure 9B is a view showing another configuration example of a protruding portion according to the first embodiment of the present disclosure.

[0035] Figure 10A is a view showing a configuration example of a protruding portion according to the second embodiment of the present disclosure.

[0036] Figure 10B is a view showing a configuration example of a protruding portion according to the second embodiment of the present disclosure.

[0037] Figure 11A is a view showing an example of a manufacturing method of a semiconductor chip according to the second embodiment of the present disclosure.

[0038] Figure 11Bis a view showing an example of a manufacturing method of a semiconductor chip according to the second embodiment of the present disclosure.

[0039] Figure 11C is a view showing an example of a manufacturing method of a semiconductor chip according to the second embodiment of the present application.

[0040] Figure 12A is a view showing another configuration example of a protruding portion according to the second embodiment of the present disclosure.

[0041] Figure 12B is a view showing another configuration example of a protruding portion according to the second embodiment of the present disclosure.

[0042] Figure 13 is a view showing a configuration example of a protruding portion according to the third embodiment of the present disclosure.

[0043] Figure 14A is a view showing an example of a manufacturing method of a semiconductor chip according to the third embodiment of the present disclosure.

[0044] Figure 14B is a view showing an example of a manufacturing method of a semiconductor chip according to the third embodiment of the present disclosure.

[0045] Figure 15 is a view showing a configuration example of a semiconductor device according to the fourth embodiment of the present disclosure.

[0046] Figure 16 is a view showing another configuration example of a semiconductor device according to the fourth embodiment of the present disclosure.

[0047] Figure 17 is a view showing another configuration example of a semiconductor device according to the fourth embodiment of the present disclosure.

[0048] Figure 18 is a view showing another configuration example of a semiconductor device according to the fourth embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Descriptions will be given in the following order. In addition, in each of the following embodiments, the same parts are labeled with the same reference numerals and overlapping descriptions are omitted.

[0050] 1. First Embodiment

[0051] 2. Second Embodiment

[0052] 3. Third Embodiment

[0053] 4. Fourth Embodiment

[0054] (1. First Embodiment)

[0055] [Configuration of Semiconductor Device]

[0056] Figure 1 is a view showing a configuration example of a semiconductor device according to the first embodiment of the present disclosure. Figure 1 is a view showing a configuration example of a semiconductor device 10. Figure 1 The semiconductor device 10 in FIG. 1 illustrates an example in which semiconductor chips 20 and 21 are stacked on the front surface side of an imaging element 100 that performs imaging of an object and generates an image signal, and further a third semiconductor substrate 350 is stacked. The third semiconductor substrate 350 corresponds to the above-described support substrate. Figure 1 The broken line in FIG. 1 indicates the shape of the third semiconductor substrate 350. The semiconductor chip 20, for example, corresponds to a semiconductor chip including a circuit that processes an image signal generated by the imaging element 100. Further, the semiconductor chip 21 corresponds to a semiconductor chip including, for example, a circuit that performs artificial intelligence (AI) processing. By stacking the semiconductor chip 20 or the like on the imaging element 100, miniaturization of the semiconductor device 10 can be achieved. Note that, in the following description, the semiconductor chip 20 and the semiconductor chip 21 are collectively referred to as a semiconductor chip 20A. Figure 1 The imaging element 100 in FIG. 1 includes a first semiconductor substrate 110.

[0057] [Configuration of Cross Section of Semiconductor Device]

[0058] Figure 2 is a cross-sectional view showing a configuration example of a semiconductor device according to the first embodiment of the present disclosure. Figure 2 is a schematic cross-sectional view showing a configuration example of a semiconductor device 10. Figure 2 The semiconductor device 10 in FIG. 2 includes the imaging element 100, the semiconductor chip 20, a cover member 330, and the third semiconductor substrate 350.

[0059] The imaging element 100 includes the first semiconductor substrate 110, a wiring region 120, a color filter 191, and an on-chip lens 192.

[0060] The first semiconductor substrate 110 is a semiconductor substrate in which a plurality of pixels including a photoelectric conversion unit that performs photoelectric conversion of incident light are arranged. The first semiconductor substrate can be made of, for example, silicon (Si).

[0061] The wiring region 120 is a region formed on the surface side of the first semiconductor substrate 110 and configured with a wiring. The wiring region 120 includes an insulating layer 121 and a wiring 122. The wiring 122 is a conductor that transmits an electric signal. The wiring 122 can be made of copper (Cu) or tungsten (W). The insulating layer 121 insulates the wiring 122 or the like. The insulating layer 121 can be made of, for example, SiO2. In addition, the insulating layer 121 constitutes an oxide film bonding layer for bonding with an insulating layer 221 of a wiring region 220 of a second semiconductor substrate 210 described later. A pad 125 is arranged on the front surface of the insulating layer 121. The pad 125 is an electrode having a shape embedded in the insulating layer 121. The pad 125 can be made of Cu. The pad 125 is a pad that is bonded with a pad 225 in the wiring region 220 of the second semiconductor substrate 210.

[0062] The color filter 191 is an optical filter that transmits light of a predetermined wavelength among incident light. In addition, the on-chip lens 192 is a lens that collects incident light.

[0063] The semiconductor chip 20 includes a second semiconductor substrate 210, a wiring region 220, and a protruding portion 250.

[0064] The second semiconductor substrate 210 is a semiconductor substrate in which a circuit that processes an image signal generated by the imaging element 100 is arranged. The second semiconductor substrate 210 can be made of, for example, Si.

[0065] The wiring region 220 is formed on the front surface side of the second semiconductor substrate 210 and includes a wiring 222 and an insulating layer 221. Similar to the insulating layer 121, the insulating layer 221 can be made of SiO2. In addition, a pad 225 having a shape embedded in the front surface of the insulating layer 221 is arranged in the wiring region 220. When the semiconductor chip 20 is bonded to the imaging element 100, the insulating layers 121 and 221 adhere and are bonded. At this time, the pads 125 and 225 are bonded and used for signal transmission between the imaging element 100 and the semiconductor chip 20. This connection method is called Cu-Cu connection.

[0066] The protruding portion 250 is a protruding region arranged on the back surface side of the second semiconductor substrate 210. The protruding portion 250 moderates a step formed when a cover member 330 described later is arranged on the back surface side of the semiconductor chip 20. Figure 2 An example in which a plurality of protruding portions 250 are arranged is shown.

[0067] Figure 2 The protruding portion 250 in the semiconductor chip 20 can include a member having a higher thermal conductivity than the thermal conductivity of the second semiconductor substrate 210. Specifically, the protruding portion 250 can be made of silicon carbide (SiC), aluminum nitride (AlN), and silicon nitride (SiN).

[0068] Further, Figure 2 The protrusions 250 in the second semiconductor substrate 210 can also include a member that suppresses etching of the second semiconductor substrate 210 when dry etching the covering member 330. The member that suppresses etching of the second semiconductor substrate 210 is also referred to as an etching stopper. Specifically, the protrusions 250 can be made of aluminum oxide (Al2O3), SiC, AlN, and SiN.

[0069] The covering member 330 covers the back surface side of the semiconductor chip 20. Figure 2 The covering member 330 in the second semiconductor substrate 210 also covers the rear surface and the side surface of the second semiconductor substrate 210 and the wiring region 120 on the front surface side of the first semiconductor substrate 110. The covering member 330 can be made of, for example, an inorganic material such as SiO2, SiON, SiCHO, SiN, and spin-on-glass (SOG) or an organic material such as silicone resin, siloxane resin, and polyimide resin.

[0070] The third semiconductor substrate 350 is a substrate that is stacked on the rear surface side of the semiconductor chip 20 and supports the imaging element 100 and the semiconductor chip 20. A silicon wafer or the like can be applied to the third semiconductor substrate 350. Figure 2 The third semiconductor substrate 350 in the second semiconductor substrate 210 is joined to the rear surface side of the semiconductor chip 20 via the covering member 330.

[0071] Figure 3A and Figure 3B are views that show an example of a configuration of a covering member in a conventional technology. Figure 3A A state in which a material film 401 of the covering member 330 is formed by chemical vapor deposition (CVD) or the like in a state in which a plurality of second semiconductor substrates 210 are joined to the semiconductor substrate 400 is shown. As shown in Figure 3A A large step is formed on the surface of the material film 401. Next, the surface of the material film 401 is polished by chemical mechanical polishing (CMP) or the like, and the surface of the material film 401 is planarized to join the third semiconductor substrate 350.

[0072] Figure 3B The covering member 330 after planarization is shown. Figure 3B An example in which planarization cannot be performed due to a step portion and a bulge occurs in the vicinity of the second semiconductor substrate 210 is shown. In a case in which planarization of the covering member 330 is insufficient, the joining strength of the third semiconductor substrate 350 decreases. As described above, because of the step formed by the second semiconductor substrate 210, it is difficult to planarize the covering member 330.

[0073] [Structure of protrusions]

[0074] Figure 4 is a view that shows a configuration example of protrusions according to the first embodiment of the present disclosure.Figure 4 is a plan view showing a configuration example of the protrusion portion 250. Figure 4 An arrangement example of the protrusions 250 arranged on the rear surface of the second semiconductor substrate 210 of the semiconductor chip 20 is shown. Figure 4 Examples in which the protrusion portions 250 each have a rectangular shape in a plan view are shown. Further, Figure 4 An example in which the protrusion portions 250 are arranged in 3 rows and 3 columns is shown.

[0075] [Shape of protrusion portion]

[0076] Figure 5 is a view showing an example of the shape of the protrusion portion according to the first embodiment of the present disclosure. Figure 5 A state in which the material film 401 of the cover member 330 is arranged on the second semiconductor substrate 210 bonded to the first semiconductor substrate 110 is shown. In Figure 5 In the drawing, "a" indicates the height from the bonding surface of the second semiconductor substrate 210, that is, the thickness of the second semiconductor substrate 210 including the wiring region 120. Further, "b" indicates the height of the protrusion portion 250. Further, "c" indicates the width of the protrusion portion 250. Further, "d" indicates the distance to the adjacent protrusion portion 250. Further, "Ah" indicates the step of the material film 401 in the vicinity of the protrusion portion 250.

[0077] As Figure 5 shown, by arranging a plurality of protrusions 250 on the front surface side of the second semiconductor substrate 210, the material film 401 between the protrusion portions 250 can be thinned. This is because the step coverage of the material film 401 formed by CVD or the like deteriorates. Note that the protrusion portion 250 can have a shape in which the height (b) is smaller than the height (a) from the bonding surface of the second semiconductor substrate 210.

[0078] Figure 6A is a graph showing the relationship between the step of the material film and the shape of the protrusion according to the first embodiment of the present disclosure. Figure 6A is a graph showing the relationship between (Ah) in Figure 5 and the ratio (b / d) of the height of the protrusion portion 250 and the distance to the adjacent protrusion portion 250. Figure 6A The horizontal axis in indicates the ratio (b / d). Further, Figure 6A The vertical axis in indicates the step (Ah) in Figure 5 . The unit is [pm]. As Figure 6A shown, the step (Ah) can be reduced in a region in which the ratio (b / d) is less than 0.01.

[0079] Figure 6B is a graph showing the relationship between the polishing rate of the material film and the shape of the protrusion portion according to the first embodiment of the present disclosure.Figure 6B is a graph showing a relationship between a polishing rate of the material film 401 in the CMP and a width (c) of the protrusion 250 in the CMP. Figure 5 Figure 6B The horizontal axis in the graph of FIG. 25 indicates the width (c). The unit is [pm]. Figure 6B The vertical axis in the graph of FIG. 25 indicates the polishing rate. The unit is [nm / s]. As shown in FIG. 25, the polishing rate decreases when the width (c) of the protrusion 250 exceeds 500 pm. Therefore, the width (c) of the protrusion 250 is preferably 500 pm or less. Figure 6B

[0080] [Method for manufacturing semiconductor chip]

[0081] Figure 7A to Figure 7E is a view showing an example of a method for manufacturing a semiconductor chip according to the first embodiment of the present disclosure. Figure 7A to Figure 7E is a view showing an example of a process of manufacturing a semiconductor chip 20. First, an insulating layer 221 is arranged on a semiconductor substrate 403 that is a raw substrate of a second semiconductor substrate 210 (a) as a first semiconductor substrate 110. Next, the back surface side of the semiconductor substrate 403 is thinned (b) with the back surface side grounded. Next, a material film 404 of a protrusion 250 is arranged on the back surface side of the semiconductor substrate 403 (c). Next, the material film 404 is etched to form the protrusion 250 (d). Next, the semiconductor substrate 403 is dicing processed to be singulated (e). Thus, the semiconductor chip 20 can be formed. Figure 7A Figure 7B Figure 7C Figure 7D Figure 7E

[0082] [Method for manufacturing semiconductor device]

[0083] Figure 8A to Figure 8H is a view showing an example of a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. Figure 8A to Figure 8H is a view showing an example of a process of manufacturing a semiconductor device 10. First, an insulating layer 121 is formed on a semiconductor substrate 400 that is a raw substrate of a first semiconductor substrate 110 (a). Next, a semiconductor chip 20 is arranged (b). Next, a material film 401 of a covering member 330 is arranged (c). Next, the material film 401 is polished and planarized (d). Next, the semiconductor substrate 400 is inverted and bonded to a third semiconductor substrate 350 (e). Next, the semiconductor substrate 400 is polished to be thinned (f). Thus, the semiconductor device 10 can be formed. Figure 8A Figure 8B Figure 8C Figure 8D Figure 8E Figure 8F ​​​​​​​​​​​​Next, the color filter 191 and the on-chip lens 192 are arranged on the rear surface side of the semiconductor substrate 400. Figure 8G Next, the semiconductor substrate 400 and the third semiconductor substrate 350 are diced to achieve monolithic assembly. Figure 8H As a result, semiconductor devices 10 can be manufactured.

[0084] [Another structure of the protrusion]

[0085] Figure 9A and Figure 9B This is a view showing another configuration example of the protrusion according to the first embodiment of the present disclosure. Figure 9A It shows something similar to Figure 4 A plan view of a configuration example of the protrusion 250. Figure 9A The protrusion 250 in the middle and Figure 4 The difference in the protrusion 250 is that it is formed into a wall shape along the end of the second semiconductor substrate 210.

[0086] Figure 9B This is a schematic cross-sectional view showing an example of the configuration of the protrusion 250. Figure 9B The image further shows a first semiconductor substrate 110, a cover member 330, and a third semiconductor substrate 350.

[0087] As described above, in the semiconductor device 10 according to the first embodiment of the present disclosure, a protrusion is formed on the rear surface side of the second semiconductor substrate 210, wherein the front surface side of the protrusion is bonded to and stacked on the front surface side of the first semiconductor substrate 110. As a result, the steps of the cover member 330 arranged in a shape covering the rear surface of the second semiconductor substrate 210 can be reduced. Therefore, grinding for planarizing the cover member 330 can be easily performed.

[0088] (2. Second Implementation)

[0089] The semiconductor device 10 according to the first embodiment described above includes a protrusion 250, which includes a component with a thermal conductivity higher than that of the second semiconductor substrate 210 and a component that inhibits the etching of the second semiconductor substrate 210 when the covering component 330 is dry-etched. On the other hand, the semiconductor device 10 according to the second embodiment of this disclosure differs from the semiconductor device 10 of the first embodiment in that it includes a protrusion 250, which includes the same component as the second semiconductor substrate 210.

[0090] [Structure of the protrusion]

[0091] Figure 10A and Figure 10B This is a view showing an example of the configuration of the protrusions according to a second embodiment of the present disclosure.Figure 10A is a plan view showing a configuration example of the protrusion 250 similar to Figure 4 . Figure 10A The protrusion 250 in Figure 4 differs from the protrusion 250 in in that the protrusion 250 includes the same member as the second semiconductor substrate 210 of the semiconductor chip 20.

[0092] Figure 10B is a schematic cross-sectional view showing a configuration example of the protrusion 250 similar to Figure 9B . In Figure 10B , the first semiconductor substrate 110, the cover member 330, and the third semiconductor substrate 350 are further shown. Figure 10B The protrusion 250 in is an example including a portion of the second semiconductor substrate 210.

[0093] [Manufacturing method of semiconductor chip]

[0094] Figure 11A to Figure 11C is a view showing an example of a method of manufacturing a semiconductor chip according to the second embodiment of the present disclosure. Figure 11A to Figure 11C is a view showing an example of a process of manufacturing the semiconductor chip 20 similar to Figure 7A to Figure 7E . Similar to Figure 7A , first, the insulating layer 221 is arranged on a semiconductor substrate 403 that is a raw substrate of the second semiconductor substrate 210 ( Figure 11A ). Next, a portion of the back surface side of the semiconductor substrate 403 is ground to form the protrusion 250 ( Figure 11B ). This can be performed, for example, by forming a scribe slit on the back surface side of the semiconductor substrate 403. Next, the semiconductor substrate 403 is scribed to singulate ( Figure 11C ). Thereby, the semiconductor chip 20 can be formed.

[0095] [Another structure of protrusion]

[0096] Figure 12A and Figure 12B are views showing another configuration example of a protrusion according to the second embodiment of the present disclosure. Figure 12A is a plan view showing a configuration example of the protrusion 250 similar to Figure 9A . Further, Figure 12B is a schematic cross-sectional view showing a configuration example of the protrusion 250 similar to Figure 9B . Figure 12A and Figure 12B The protrusion 250 in Figure 9A and Figure 9B differs from the protrusion 250 in

[0097] Since the configuration of the semiconductor device 10 other than the above is similar to that of the semiconductor device 10 in the first embodiment of the present disclosure, the description thereof will be omitted.

[0098] As described above, the semiconductor device 10 according to the second embodiment of the present disclosure includes the protrusion portion 250 including the same member as the second semiconductor substrate 210. Therefore, it is possible to simplify the process of manufacturing the protrusion portion 250.

[0099] (3. Third Embodiment)

[0100] The semiconductor device 10 according to the above-described second embodiment includes the protrusion portion 250 including the same member as the second semiconductor substrate 210. On the other hand, the semiconductor device 10 according to the third embodiment of the present disclosure is different from the semiconductor device of the above-described second embodiment in that it includes the protrusion portion 250 including a member having a higher thermal conductivity than that of the second semiconductor substrate 210 and a member that suppresses etching of the second semiconductor substrate 210 during dry etching.

[0101] [Structure of protrusion portion]

[0102] Figure 13 is a view showing a configuration example of the protrusion portion according to the third embodiment of the present disclosure. Figure 13 is a schematic cross-sectional view showing a configuration example of the semiconductor chip 22. Figure 13 The semiconductor chip 22 in is an example in which the protrusion portion 250 including a plurality of members is provided. Figure 13 The protrusion portion 250 in is formed by disposing a coating film 255 on the surface of the protrusion portion including a portion of the second semiconductor substrate 210. For example, the coating film 255 can include a member having a higher thermal conductivity than that of the second semiconductor substrate 210. In addition, the coating film 255 can further include, for example, a member that suppresses etching of the second semiconductor substrate 210. In addition, a coating film 255 formed by stacking these components can also be used. In this case, it is preferable to arrange the member that suppresses etching on the surface side.

[0103] [Manufacturing method of semiconductor chip]

[0104] Figure 14A and Figure 14B is a view showing an example of a manufacturing method of a semiconductor chip according to the third embodiment of the present disclosure. Figure 14A and Figure 14B are views showing examples of a process of manufacturing the semiconductor chip 22 similar to Figure 11A to Figure 11C First, the process of forming the protrusion portion 250 is performed. Figure 11A and Figure 11BThe material film 405 of the coating film 255 is arranged on the back surface side of the semiconductor substrate 403 (S4). Next, the semiconductor substrate 403 is diced to be singulated (S5). As a result, the semiconductor chip 22 can be formed. Figure 14A ). Next, the semiconductor substrate 403 is diced to be singulated (S5). As a result, the semiconductor chip 22 can be formed. Figure 14B ). Next, the semiconductor substrate 403 is diced to be singulated (S5). As a result, the semiconductor chip 22 can be formed.

[0105] The configuration of the semiconductor device 10 other than the above is similar to that of the semiconductor device 10 in the second embodiment of the present disclosure, and thus the description thereof will be omitted.

[0106] As described above, the semiconductor device 10 according to the third embodiment of the present disclosure includes the protruding portion 250 including the coating film 255 including the same member as the second semiconductor substrate 210 and the high-thermal-conductivity member.

[0107] (4. Fourth Embodiment)

[0108] A modification of the semiconductor device 10 will be described.

[0109] [Configuration of Semiconductor Device]

[0110] Figure 15 is a view showing a configuration example of a semiconductor device according to the fourth embodiment of the present disclosure. Figure 15 is a schematic cross-sectional view showing a configuration example of the semiconductor device 10 similar to Figure 10B Figure 15 The semiconductor device 10 in (1) shows an example in which a plurality of semiconductor chips (the semiconductor chips 20 and 21) are provided.

[0111] [Another Configuration of Semiconductor Device]

[0112] Figure 16 is a view showing another configuration example of a semiconductor device according to the fourth embodiment of the present disclosure. Figure 16 is a schematic cross-sectional view showing a configuration example of the semiconductor device 10 similar to Figure 15 Figure 16 The semiconductor device 10 in (1) shows an example in which a plurality of semiconductor chips (the semiconductor chips 20 and 21) are provided.

[0113] The storage chip 300 is a semiconductor chip on which a semiconductor storage element is arranged. Figure 16 The storage chip 300 in (1) is an example configured to have the same size as the imaging element 100. The storage chip 300 includes a fourth semiconductor substrate 310 and a wiring region 320. Further, the storage chip 300 is bonded to the front surface side of the imaging element 100. The semiconductor chips 20 and 21 are bonded to the wiring region 320 on the front surface side of the storage chip 300.

[0114] Figure 17 ​​is a view showing another configuration example of a semiconductor device according to the fourth embodiment of the present disclosure. Figure 17 is a schematic cross-sectional view showing a configuration example of a semiconductor device 10 similar to Figure 16 . Figure 17 The semiconductor device 10 in Figure 16 differs from the semiconductor device 10 in

[0115] As shown in Figure 17 , the height of the protruding portion 250 of the semiconductor chip 20 and the protruding portion 251 of the semiconductor chip 21 can be adjusted so as to make the height from the bonding surface to the end portion of the protruding portion uniform. As a result, an increase in the step of the cover member 330 can be prevented.

[0116] Figure 18 is a view showing another configuration example of a semiconductor device according to the fourth embodiment of the present disclosure. Figure 18 is a schematic cross-sectional view showing a configuration example of a semiconductor device 10 similar to Figure 16 . Figure 18 The semiconductor device 10 in Figure 16 differs from the semiconductor device 10 in Figure 13 described in

[0117] The chip 23 is a chip including a member having a higher thermal conductivity than the thermal conductivity of the second semiconductor substrate 210. The chip 23 constitutes a heat dissipation path of the imaging element 100 and the memory chip 300. The heat dissipation capacity of the semiconductor device 10 can be improved by the chip 23 and the semiconductor chip 22.

[0118] Further, by arranging the chip 23 in the blank area, the step of the cover member 330 can be further reduced.

[0119] Since the configuration of the semiconductor device 10 other than the above is similar to that of the semiconductor device 10 in the first embodiment of the present disclosure, the description thereof will be omitted.

[0120] While each of the embodiments of the present disclosure has been described above, the technical scope of the present disclosure is not limited to the above-described each embodiment of the present disclosure itself and various modifications can be made without departing from the spirit of the present disclosure. In addition, components of different embodiments and modified examples can be appropriately combined.

[0121] Note that the effects described in the present specification are merely examples and the disclosure is not limited thereto. That is, of course, additional effects can be provided together with or in the place of the effects indicated in the present specification.

[0122] Note that the present technology can also have the following configurations.

[0123] (1) A semiconductor device comprising:

[0124] a first semiconductor substrate;

[0125] a second semiconductor substrate bonded to the first semiconductor substrate and including a protruding portion on a surface different from a bonding surface; and

[0126] a covering member covering the second semiconductor substrate bonded to the first semiconductor substrate.

[0127] (2) The semiconductor device according to the above (1), wherein the protruding portion includes a member identical to the second semiconductor substrate.

[0128] (3) The semiconductor device according to the above (1), wherein the protruding portion includes a member having a higher thermal conductivity than a thermal conductivity of the second semiconductor substrate.

[0129] (4) The semiconductor device according to the above (1), wherein the protruding portion includes a member that suppresses etching of the second semiconductor substrate.

[0130] (5) The semiconductor device according to the above (1), wherein the protruding portion includes any one of silicon carbide, aluminum nitride, and silicon nitride.

[0131] (6) The semiconductor device according to any one of the above (1) to (5), wherein the protruding portion has a shape having a height smaller than a thickness of the second semiconductor substrate.

[0132] (7) The semiconductor device according to any one of the above (1) to (6), wherein the protruding portion is formed in a wall shape along an end portion of the second semiconductor substrate.

[0133] (8) The semiconductor device according to any one of the above (1) to (5), wherein the second semiconductor substrate includes a plurality of protruding portions.

[0134] (9) The semiconductor device according to the above (8), wherein the protruding portions are formed so that a ratio of a height of one of the protruding portions to a distance to an adjacent other one of the protruding portions is 0.01 or less.

[0135] (10) The semiconductor device according to the above (8), wherein the protruding portions each have a shape having a width of 0.5 mm or less.

[0136] (11) The semiconductor device according to any one of the above (1) to (10), further comprising a plurality of second semiconductor substrates.

[0137] (12) The semiconductor device according to (11) above, wherein the plurality of second semiconductor substrates are formed so that heights from a bonding surface to a top end of the protruding portion are substantially equal to each other when the second semiconductor substrates are bonded to the first semiconductor substrate.

[0138] (13) The semiconductor device according to any one of (1) to (12) above, further comprising a third semiconductor substrate bonded to a surface of the second semiconductor substrate on which the protruding portion is disposed.

[0139] Explanation of Symbols

[0140] 10 Semiconductor device

[0141] 20-22 Semiconductor chip

[0142] 23 Chip

[0143] 100 Imaging element

[0144] 110 First semiconductor substrate

[0145] 210, 230 Second semiconductor substrate

[0146] 250, 251 Protruding portion

[0147] 255 Coating film

[0148] 300 Storage chip

[0149] 310 Fourth semiconductor substrate

[0150] 330 Covering member

[0151] 350 Third semiconductor substrate

Claims

1. A semiconductor device comprising: a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate and including a protruding portion on a surface different from a bonding surface; and a cover member covering the second semiconductor substrate bonded to the first semiconductor substrate.

2. The semiconductor device according to claim 1, wherein The protruding portion includes a member identical to the second semiconductor substrate.

3. The semiconductor device according to claim 1, wherein The protruding portion includes a member having a higher thermal conductivity than the second semiconductor substrate.

4. The semiconductor device according to claim 1, wherein The protruding portion includes a member that suppresses etching of the second semiconductor substrate.

5. The semiconductor device according to claim 1, wherein The protruding portion includes any one of silicon carbide, aluminum nitride, and silicon nitride.

6. The semiconductor device according to claim 1, wherein The protruding portion has a shape with a height smaller than a thickness of the second semiconductor substrate.

7. The semiconductor device according to claim 1, wherein The protruding portion is formed in a wall shape along an end portion of the second semiconductor substrate.

8. The semiconductor device according to claim 1, wherein The second semiconductor substrate includes a plurality of protruding portions.

9. The semiconductor device according to claim 8, wherein The protruding portions are formed so that a ratio of a height of one of the protruding portions to a distance to an adjacent other one of the protruding portions is 0.01 or less.

10. The semiconductor device according to claim 8, wherein The protruding portions each have a shape with a width of 0.5 mm or less.

11. The semiconductor device according to claim 1, further comprising a plurality of the second semiconductor substrates.

12. The semiconductor device according to claim 11, wherein The plurality of the second semiconductor substrates are formed so that heights from a bonding surface to top ends of the protruding portions are substantially equal to each other when the second semiconductor substrates are bonded to the first semiconductor substrate.

13. The semiconductor device according to claim 1, further comprising a third semiconductor substrate bonded to a surface of the second semiconductor substrate on which the protruding portion is disposed.

Images