Silicon carbide substrate and substrate preparation method

Abstract

The invention relates to the technical field of semiconductor single crystal growth, in particular to a silicon carbide substrate and a substrate preparation method, and the method comprises the following steps: sputtering a layer of tungsten-carbon composite film on the growth surface of a 4H-SiC single crystal seed crystal in a magnetron sputtering mode; fixing the seed crystal sputtered with the tungsten-carbon composite film on a crucible cover, and laying a porous silicon carbide composite source material coated with a graphene nano layer at the bottom of a crucible; placing the crucible in a physical vapor transport growth furnace, vacuumizing, filling argon, and then carrying out gradient heating, crystal growth and speed-controlled cooling to obtain a silicon carbide crystal ingot; according to the invention, the crystal defect density of the silicon carbide substrate is obviously reduced, and the crystal quality is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor single crystal growth technology, specifically to a silicon carbide substrate and a substrate preparation method. Background Technology

[0002] In existing technologies for preparing silicon carbide (SiC) single-crystal substrates using the physical vapor transport (PVT) method, two major technical bottlenecks are commonly encountered, severely affecting crystal quality and yield. First, in the initial stage of crystal growth, the interface between the 4H-SiC seed crystal and the nascent crystal is prone to inducing a large number of microtubes and dislocations due to lattice mismatch and microscopic defects on the seed crystal surface. These defects can penetrate the entire ingot, rendering the substrate unusable. Although using an intermediate induction layer is considered a feasible technical approach, traditional induction layers such as pure carbon films have limited ability to suppress interface defects due to their poor lattice matching with SiC. Second, during long-term high-temperature growth, the sublimation process of traditional high-purity SiC powder source materials is difficult to control, often resulting in explosive and unstable sublimation phenomena. This unstable material transport leads to drastic fluctuations in the supersaturation of the gas phase components within the growth chamber. This not only interferes with the stable growth rate of the crystal but also makes it easier to introduce serious defects such as inclusions and dislocation clusters into the crystal, resulting in a substrate with high defect density, high internal stress, and poor crystal structure integrity. Therefore, how to synergistically solve the two major challenges of initial interface defect control and stable material transport is a core technical problem that urgently needs to be solved in the field of large-scale, low-cost preparation of high-quality silicon carbide substrates for power semiconductors. Summary of the Invention

[0003] To achieve the above objectives, the present invention provides a silicon carbide substrate and a method for preparing the substrate, comprising the following steps: A method for preparing a silicon carbide substrate includes the following steps: A tungsten-carbon composite film was sputtered onto the growth surface of a 4H-SiC single crystal seed crystal using magnetron sputtering. The seed crystal sputtered with the tungsten-carbon composite film is fixed to the crucible lid, and a porous silicon carbide composite source material coated with a graphene nanolayer is laid at the bottom of the crucible. The crucible was placed in a physical vapor transport growth furnace, evacuated and then filled with argon gas. Gradient heating, crystal growth and controlled cooling were then performed to obtain silicon carbide ingots. The method for preparing the graphene nanolayer-coated porous silicon carbide composite source material includes: High-purity α-SiC powder was mixed with a binder, granulated by spray drying, and then subjected to gradient heating and high-temperature sintering in an argon atmosphere to obtain porous silicon carbide spherical particles. The porous silicon carbide spherical particles were placed in a fluidized bed reactor and subjected to pulsed chemical vapor deposition using methane as a carbon source to coat the particle surface with a graphene nanolayer. The method for preparing the nano-tungsten / carbon composite target for magnetron sputtering includes: Nano-tungsten powder and graphite powder were mixed with ball milling media and then subjected to planetary ball milling to obtain a mixed slurry; The mixed slurry is vacuum dried to obtain composite powder, and the composite powder is hot-pressed and sintered to obtain the nano-tungsten / carbon composite target.

[0004] Furthermore, the weight ratio of the high-purity α-SiC powder to the polyvinyl alcohol solution as the binder component is (480-520):(18-22).

[0005] Furthermore, the thickness of the graphene nanolayer coated on the particle surface by chemical vapor deposition is 5-10 nanometers.

[0006] Furthermore, the weight ratio of the nano-tungsten powder to the graphite powder is (85-95):(5-15).

[0007] Furthermore, the thickness of the tungsten-carbon composite film formed by magnetron sputtering on the seed crystal growth surface is 25-35 nanometers.

[0008] Furthermore, the gradient heating step includes holding the temperature at 1600°C to allow the tungsten-carbon composite film to react in situ and generate a nano-tungsten carbide induction layer.

[0009] Furthermore, in the crystal growth step, the source region temperature is controlled at 2340-2360℃, the seed crystal region temperature is controlled at 2320-2340℃, and a temperature difference of 15-25℃ is maintained between the source region and the seed crystal region.

[0010] Furthermore, in the controlled-speed cooling step, when the temperature drops below 600℃, the cooling rate is 2-4℃ / minute.

[0011] A silicon carbide substrate prepared by the above-described preparation method.

[0012] An application of silicon carbide substrates in the fabrication of power semiconductor devices.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention significantly reduces the crystal defect density of silicon carbide substrates and improves crystal quality. It achieves this through the synergistic effect of two major technologies: First, a nano-tungsten carbide induction layer is generated on the 4H-SiC seed crystal growth surface by magnetron sputtering of a tungsten-carbon composite film and in-situ reaction. This induction layer provides a growth template with high lattice matching degree and low interface energy with SiC, suppressing the extension of microtubes and dislocations caused by seed crystal-crystal interface defects. Second, a porous silicon carbide composite source material coated with a graphene nanolayer is used. By controlling the SiC sublimation rate at high temperature through the graphene layer, the unstable explosive sublimation of traditional source materials is transformed into a stable and controllable evaporative sublimation, providing a stable gas phase environment for crystal growth and avoiding new defects, inclusions, and dislocation clusters caused by drastic fluctuations in gas phase concentration.

[0014] 2. This invention improves the integrity of the crystal structure and reduces internal stress. Due to the synergistic effect of interface preference and source current stabilization, this invention lays the foundation for low dislocations from the initial growth stage and maintains a stable growth rate throughout the crystal growth process, effectively suppressing the generation of new dislocations and the accumulation of lattice stress. High-resolution X-ray diffraction rocking curve test results show that the full width at half maximum (FWHM) of the substrate in the embodiment of this invention can reach as low as 15.53 arcsec, which is significantly lower than that of the comparative example, indicating that its lattice arrangement is more regular, the crystal structure integrity is higher, and the internal stress is lower.

[0015] 3. This invention improves the surface morphology of the substrate, achieving atomic-level flatness. The prepared silicon carbide bulk crystal has extremely low density of defects such as microtubes, dislocations, and inclusions, resulting in uniform material texture. After chemical mechanical polishing, uniform material removal can be achieved. Atomic force microscopy results show that the root mean square roughness of the substrate in this embodiment can reach as low as 0.12 nm, achieving atomic-level flatness. This contrasts sharply with Comparative Example 2, where unstable ejection of the source material leads to the formation of a large number of micron-sized inclusions in the crystal, resulting in a sharp deterioration of the surface roughness to 0.83 nm. This highly flat surface provides a solid foundation for the subsequent growth of high-quality epitaxial layers and the fabrication of high-performance power devices.

[0016] 4. This invention improves the performance and reliability of power devices and demonstrates promising prospects for industrial applications. The low-defect, high-quality silicon carbide substrates prepared exhibit lower leakage current, higher breakdown voltage, lower switching losses, and higher operational reliability when applied to power devices in fields such as electric vehicle main inverters, photovoltaic inverters, smart grids, high-speed rail transit, and 5G communication base stations. This method has successfully prepared large-size substrates of 6 inches and 8 inches, proving its stability and scalability, which helps to reduce the manufacturing cost per chip and meets the needs of different fields for high-performance silicon carbide devices. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a silicon carbide substrate preparation method according to the present invention; Figure 2 Images showing the morphology and structural characteristics of porous silicon carbide composite source material coated with graphene nanolayers; Figure 3 This is a schematic diagram illustrating the mechanism of interface defect suppression by the nano-tungsten carbide induced layer in SiC crystal growth. Detailed Implementation

[0018] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example

[0019] This embodiment provides a method for preparing a silicon carbide substrate, including the following steps: A method for preparing a nano-tungsten / carbon composite target for magnetron sputtering is described. The method includes mixing nano-tungsten powder and graphite powder with anhydrous ethanol ball milling media at a weight ratio of 90:10, followed by planetary ball milling to obtain a mixed slurry; vacuum drying the mixed slurry to obtain a composite powder; and hot-pressing and sintering the composite powder to obtain the nano-tungsten / carbon composite target. Subsequently, a method for preparing a porous silicon carbide composite source material coated with a graphene nanolayer is described. This method includes mixing high-purity α-SiC powder with a polyvinyl alcohol solution as a binder component at a weight ratio of 500:20, granulating by spray drying, and then performing gradient heating and high-temperature sintering in an argon atmosphere to obtain porous silicon carbide spherical particles; placing the porous silicon carbide spherical particles in a fluidized bed reactor and performing pulsed chemical vapor deposition using methane as a carbon source to coat the particle surface with an 8-nanometer-thick graphene nanolayer. After the raw material preparation is completed, a 30 nm thick tungsten-carbon composite film is sputtered onto the growth surface of the 4H-SiC single crystal seed crystal using magnetron sputtering. The seed crystal with the sputtered tungsten-carbon composite film is fixed to the crucible lid, and the porous silicon carbide composite source material coated with the graphene nanolayer prepared above is laid on the bottom of the crucible. The crucible is placed in a physical vapor transport growth furnace, evacuated, and then filled with argon gas. Gradient heating, crystal growth, and controlled cooling steps are performed. The gradient heating step includes holding at 1600 °C to allow the tungsten-carbon composite film to react in situ and generate a nano-tungsten carbide induction layer. In the crystal growth step... The source region temperature is controlled at 2350℃, the seed region temperature at 2330℃, and a temperature difference of 20℃ is maintained between the source region and the seed region. In the controlled cooling step, when the temperature drops below 600℃, the cooling rate is 3℃ / minute, and a high-quality silicon carbide ingot is finally obtained. The 6-inch silicon carbide substrate prepared in this embodiment has a microtube density of less than 0.1cm⁻² and a growth rate of 320μm / h. When this substrate is used to manufacture high-voltage MOSFETs in the main inverter of electric vehicles, it exhibits a low defect-related leakage current and a high breakdown voltage, which helps to improve the long-term reliability of the inverter module. Example

[0020] This embodiment provides a method for preparing a silicon carbide substrate, including the following steps: A method for preparing a nano-tungsten / carbon composite target for magnetron sputtering is provided. The method includes mixing nano-tungsten powder and graphite powder with anhydrous ethanol ball milling media at a weight ratio of 85:15 and then performing planetary ball milling to obtain a mixed slurry; vacuum drying the mixed slurry to obtain a composite powder; and hot pressing and sintering the composite powder to obtain the nano-tungsten / carbon composite target. A method for preparing porous silicon carbide composite raw material coated with graphene nanolayers includes mixing high-purity α-SiC powder with a polyvinyl alcohol solution as a binder component at a weight ratio of 480:22, granulating by spray drying, and then performing gradient heating and high-temperature sintering in an argon atmosphere to obtain porous silicon carbide spherical particles; placing the porous silicon carbide spherical particles in a fluidized bed reactor and performing pulsed chemical vapor deposition using methane as a carbon source to coat the particle surface with a graphene nanolayer with a thickness of 5 nanometers. After the raw material preparation is completed, a 25 nm thick tungsten-carbon composite film is sputtered onto the growth surface of the 4H-SiC single crystal seed crystal using magnetron sputtering. The seed crystal with the sputtered tungsten-carbon composite film is fixed to the crucible lid, and the porous silicon carbide composite source material coated with the graphene nanolayer prepared above is laid at the bottom of the crucible. The crucible is placed in a physical vapor transport growth furnace, evacuated, and then filled with argon gas. Gradient heating, crystal growth, and controlled cooling steps are performed. The gradient heating step includes holding at a temperature of 1600 °C to allow the tungsten-carbon composite film to react in situ and generate nano-tungsten carbide. In the crystal growth step, the source region temperature is controlled at 2340℃, the seed region temperature at 2325℃, and a temperature difference of 15℃ is maintained between the source region and the seed region. In the controlled cooling step, when the temperature drops below 600℃, the cooling rate is 4℃ / minute, ultimately obtaining a high-quality silicon carbide ingot. The 6-inch silicon carbide substrate prepared in this embodiment has a microtube density of approximately 0.2cm⁻² and a stable growth rate. This substrate is used in photovoltaic inverter power modules, and its low defect level enables the device to operate at higher frequencies, reducing switching losses and thus improving the overall energy conversion efficiency of the photovoltaic system. Example

[0021] This embodiment provides a method for preparing a silicon carbide substrate, including the following steps: A method for preparing a nano-tungsten / carbon composite target for magnetron sputtering is provided. The method includes mixing nano-tungsten powder and graphite powder with anhydrous ethanol ball milling media at a weight ratio of 95:5 and then performing planetary ball milling to obtain a mixed slurry; vacuum drying the mixed slurry to obtain a composite powder; and hot pressing and sintering the composite powder to obtain the nano-tungsten / carbon composite target. A method for preparing porous silicon carbide composite raw material coated with graphene nanolayers includes mixing high-purity α-SiC powder with a polyvinyl alcohol solution as a binder component at a weight ratio of 520:18, granulating by spray drying, and then performing gradient heating and high-temperature sintering in an argon atmosphere to obtain porous silicon carbide spherical particles; placing the porous silicon carbide spherical particles in a fluidized bed reactor and performing pulsed chemical vapor deposition using methane as a carbon source to coat the particle surface with a graphene nanolayer with a thickness of 10 nanometers. After the raw material preparation is completed, a 35 nm thick tungsten-carbon composite film is sputtered onto the growth surface of the 4H-SiC single crystal seed crystal using magnetron sputtering. The seed crystal with the sputtered tungsten-carbon composite film is fixed to the crucible lid, and a porous silicon carbide composite source material coated with the graphene nanolayer prepared above is laid at the bottom of the crucible. The crucible is placed in a physical vapor transport growth furnace, evacuated, and then filled with argon gas. Gradient heating, crystal growth, and controlled-rate cooling steps are then performed. The gradient heating step includes holding the temperature at 1600 °C to allow the tungsten-carbon composite film to react in situ and generate a nano-tungsten carbide induced layer. In the crystal growth step, the source region temperature is controlled at 2360 °C, the seed crystal region temperature is controlled at 2335 °C, and a temperature difference of 25 °C is maintained between the source region and the seed crystal region. In the controlled-rate cooling step, when the temperature drops below 600 °C, the cooling rate is 2 °C / min, finally obtaining a high-quality silicon carbide ingot. The 8-inch silicon carbide substrate prepared in this embodiment has a microtube density controlled at around 0.2 cm⁻² and a high growth rate. This large-size substrate is used in high-voltage direct current transmission converter valve devices in smart grids, which can manufacture more high-power chips on a single wafer, helping to reduce the manufacturing cost per chip while maintaining the high voltage withstand characteristics and low on-resistance of the device. Example

[0022] This embodiment provides a method for preparing a silicon carbide substrate, including the following steps: A method for preparing a nano-tungsten / carbon composite target for magnetron sputtering is described. The method includes mixing nano-tungsten powder and graphite powder with anhydrous ethanol ball milling media at a weight ratio of 88:12, followed by planetary ball milling to obtain a mixed slurry; vacuum drying the mixed slurry to obtain a composite powder; and hot-pressing and sintering the composite powder to obtain the nano-tungsten / carbon composite target. Subsequently, a method for preparing a porous silicon carbide composite source material coated with a graphene nanolayer is described. This method includes mixing high-purity α-SiC powder with a polyvinyl alcohol solution as a binder component at a weight ratio of 490:21, granulating by spray drying, and then performing gradient heating and high-temperature sintering in an argon atmosphere to obtain porous silicon carbide spherical particles; placing the porous silicon carbide spherical particles in a fluidized bed reactor and performing pulsed chemical vapor deposition using methane as a carbon source to coat the particle surface with a 7-nanometer thick graphene nanolayer. After the raw material preparation is completed, a 28 nm thick tungsten-carbon composite film is sputtered onto the growth surface of the 4H-SiC single crystal seed crystal using magnetron sputtering. The seed crystal with the sputtered tungsten-carbon composite film is fixed to the crucible lid, and the porous silicon carbide composite source material coated with the graphene nanolayer prepared above is laid at the bottom of the crucible. The crucible is placed in a physical vapor transport growth furnace, evacuated, and then filled with argon gas. Then, gradient heating, crystal growth, and controlled cooling steps are performed. The gradient heating step includes holding at a temperature of 1600 °C to allow the tungsten-carbon composite film to react in situ and generate a nano-tungsten carbide induced layer. In the long growth step, the source region temperature is controlled at 2355℃, the seed region temperature at 2337℃, and an 18℃ temperature difference is maintained between the source and seed regions. In the controlled cooling step, when the temperature drops below 600℃, the cooling rate is 3.5℃ / minute, ultimately yielding a high-quality silicon carbide ingot. The 6-inch silicon carbide substrate prepared in this embodiment has a microtube density of approximately 0.15 cm⁻², and the growth process is stable. This substrate is used to manufacture IGBT modules in high-speed rail transit traction converters. Its excellent crystal quality ensures the durability of the device under frequent start-stop and high-load impacts, reducing the risk of early failure due to material defects. Example

[0023] This embodiment provides a method for preparing a silicon carbide substrate, including the following steps: A method for preparing a nano-tungsten / carbon composite target for magnetron sputtering is provided. The method includes mixing nano-tungsten powder and graphite powder with anhydrous ethanol ball milling media at a weight ratio of 92:8 and then performing planetary ball milling to obtain a mixed slurry; vacuum drying the mixed slurry to obtain a composite powder; and hot pressing and sintering the composite powder to obtain the nano-tungsten / carbon composite target. A method for preparing porous silicon carbide composite raw materials coated with graphene nanolayers is disclosed. The method includes mixing high-purity α-SiC powder with a polyvinyl alcohol solution as a binder component at a weight ratio of 510:19, granulating by spray drying, and then performing gradient heating and high-temperature sintering in an argon atmosphere to obtain porous silicon carbide spherical particles. The porous silicon carbide spherical particles are placed in a fluidized bed reactor and subjected to pulsed chemical vapor deposition using methane as a carbon source to coat the particle surface with a 9-nanometer-thick graphene nanolayer. After raw material preparation, a 32-nanometer-thick tungsten-carbon composite film is sputtered onto the growth surface of a 4H-SiC single crystal seed crystal using magnetron sputtering. The sputtered tungsten-carbon composite film... The seed crystal of the film is fixed to the crucible lid, and the porous silicon carbide composite source material coated with the graphene nanolayer prepared above is laid at the bottom of the crucible. The crucible is placed in a physical vapor transport growth furnace, evacuated and then filled with argon gas. Then, gradient heating, crystal growth and controlled cooling steps are performed. The gradient heating step includes holding at a temperature of 1600℃ to allow the tungsten-carbon composite film to react in situ to generate a nano-tungsten carbide induced layer. In the crystal growth step, the source region temperature is controlled at 2358℃, the seed crystal region temperature is controlled at 2336℃, and a temperature difference of 22℃ is maintained between the source region and the seed crystal region. In the controlled cooling step, when the temperature drops below 600℃, the cooling rate is 2.5℃ / minute, and finally a high-quality silicon carbide ingot is obtained. The 8-inch silicon carbide substrate prepared in this embodiment has a microtube density controlled below 0.15 cm⁻², resulting in a high yield. This substrate is used to produce power factor correction (PFC) circuits in 5G communication base station power supplies. Its high crystal quality helps the device achieve higher conversion efficiency and power density, meeting the requirements of communication equipment for miniaturization and low power consumption.

[0024] Comparative Example 1: This comparative example provides a method for preparing a silicon carbide substrate. The process parameters are basically the same as those in Example 1. The difference is that, after standard cleaning, the 4H-SiC single crystal seed in this comparative example is not subjected to the step of magnetron sputtering tungsten-carbon composite thin film. Instead, it is directly fixed to the crucible lid for subsequent crystal growth. The resulting ingot was tested and found to have a microtube density exceeding 5 cm⁻². A large number of microtube defects were generated at the interface between the seed and the newly grown crystal and penetrated the entire crystal, making the core area of ​​the substrate almost unusable for manufacturing qualified power semiconductor devices. This indicates that the lack of an in-situ generated nano-tungsten carbide inducing layer, which cannot effectively suppress interface defects between the seed and the epitaxial layer, is the main reason for the poor crystal quality.

[0025] Comparative Example 2: This comparative example provides a method for preparing a silicon carbide substrate. The process parameters are basically the same as those in Example 1. The difference is that the bottom of the crucible in this comparative example is covered with traditional, untreated high-purity SiC powder source material, rather than a porous silicon carbide composite source material coated with graphene nanolayers. During the crystal growth process, the growth rate fluctuated drastically. The final ingot was tested and found to have a microtube density exceeding 8 cm⁻², and a large number of inclusions and dislocation cluster defects were present inside the crystal. This indicates that when using traditional SiC powder source material, its sublimation process at high temperature is unstable. The instantaneous supersaturated gas phase environment and particle ejection are the main reasons for the high crystal defect density and unstable growth process.

[0026] Comparative Example 3: This comparative example provides a method for preparing a silicon carbide substrate. The process parameters are basically the same as those in Example 1. The difference is that the target material used for magnetron sputtering in this comparative example is a pure graphite target, rather than a nano-tungsten / carbon composite target. A pure carbon thin film is sputtered on the seed crystal growth surface as an induction layer. The final ingot was tested and found to have a microtube density of more than 3 cm⁻². Although it is an improvement compared to Comparative Example 1, the defect suppression effect is still significantly different from that of Example 1. This indicates that the lattice mismatch between the pure carbon layer and 4H-SiC is still relatively large, and its ability to optimize the interface as an induction layer is limited, which is not as good as the in-situ generated nano-tungsten carbide induction layer.

[0027] In Examples 1-5 and Comparative Examples 1-3, the nano-tungsten powder was from Xiamen Tungsten Industry Co., Ltd., with an average particle size of 50 nm and a purity >99.9%; the graphite powder was from Qingdao Haida Graphite Co., Ltd., with a purity >99.95% and a particle size D50 of 5 μm; the high-purity α-SiC powder was from Shandong Tianyue Advanced Materials Technology Co., Ltd., with a purity >99.999%; the polyvinyl alcohol was from Shanghai Aladdin Biochemical Technology Co., Ltd., with a degree of alcoholysis of 98.0-99.0 mol / %, CAS No.: 9002-89-5; the 4H-SiC single crystal seed crystal was from Beijing Tianke Heda Semiconductor Co., Ltd., N-type, with a diameter of 6 inches or 8 inches; methane and argon were both purchased from Beijing Beiyang Special Gases Co., Ltd., with a purity of 99.999%; anhydrous ethanol was analytical grade, purchased from Sinopharm Chemical Reagent Co., Ltd., CAS No.: 64-17-5; other reagents or materials were commercially available analytical grade or industrial grade products.

[0028] The silicon carbide substrates prepared in Examples 1-5 and Comparative Examples 1-3 were tested accordingly, and the test results are shown below: (1) Crystal defect density test: The surface of the 6-inch wafer-level substrate was scanned using a laser scattering defect detector to identify and quantify microtube defects; according to the SEMIM55-0312 standard, the substrate was etched with molten potassium hydroxide at 500°C for 8 minutes to clearly display dislocations, and the etch pits were observed and counted using an optical microscope to calculate the density of thread dislocations; to ensure the reliability of the data, each substrate was measured in 5 different regions in the four quadrants of the center and edge, with the area of ​​each region being 1 mm², and the final result was the average value; the test results are shown in Table 1; Table 1. Crystal defect density test results for each substrate

[0029] As shown in Table 1, the silicon carbide substrates prepared in Examples 1-5 exhibit significant advantages over those in Comparative Examples 1-3 in terms of microtube density and threaded dislocation density, resulting in a substantial improvement in crystal quality. Example 1 has the lowest overall defect density, verifying the superiority of its process parameter combination. The core reason lies in the fact that this technical solution achieves synergistic defect control through two key improvements: by synthesizing a nano-tungsten carbide induction layer in situ on the seed crystal surface, an initial template with high lattice matching and low interface energy is provided for subsequent growth, effectively suppressing the extension of microtubes and dislocations caused by micro-defects on the seed crystal surface. This is the root cause of the persistently high defect densities in Comparative Examples 1 and 3. The key reason for this is the use of porous silicon carbide composite source material coated with graphene nanolayers. The graphene coating layer regulates the sublimation rate of SiC at ultra-high temperatures, transforming explosive sublimation into stable and controllable evaporative sublimation, thus providing a stable gas phase environment for crystal growth. This avoids the formation of polycrystalline nuclei and inclusions and high-density dislocation clusters caused by drastic fluctuations in gas phase concentration, as well as by the ejection of source material particles. This is precisely the mechanism behind the highest defect density and unstable growth in Comparative Example 2. Therefore, it is the synergistic effect of interface selection and source stabilization that constitutes the technical basis for the stable fabrication of low-defect-density silicon carbide substrates in this scheme.

[0030] (2) Crystal structure integrity test: A high-resolution X-ray diffractometer was used with CuKα1 rays as the radiation source to perform rocking curve tests on the crystal planes of each substrate to evaluate the structural integrity and internal stress of the crystal; the test voltage was 40kV and the current was 40mA; to ensure the universality of the results, five different positions were selected for testing on each substrate, and the average value of the full width at half maximum (FWHM) of the rocking curve was calculated; the smaller the FWHM value, the more regular the lattice arrangement and the higher the crystal quality; the test results are shown in Table 2. Table 2. Results of X-ray diffraction rocking curves (FWHM) for each substrate.

[0031] As shown in Table 2, the full width at half maximum (FWHM) of the rocking curves of the silicon carbide substrates prepared in Examples 1-5 are significantly lower than those of all comparative examples, indicating that they have higher crystal structure integrity and lower internal stress. Example 1 has the lowest FWHM value, reaching 15.53 arcsec, approaching the level of a high-quality homoepitaxial layer. The FWHM value of the rocking curve is directly related to the dislocation density and lattice distortion degree in the crystal. The nano-tungsten carbide inducing layer used in the examples provides a perfect initial lattice template, laying the foundation for low dislocations from the initial growth stage. Simultaneously, the porous silicon carbide composite source material coated with graphene nanolayers ensures a continuous and stable supply of gas phase components throughout the crystal growth process, avoiding… This approach avoids drastic fluctuations in growth rate, thereby suppressing the generation of new dislocations and the accumulation of lattice stress. In contrast, Comparative Examples 1 and 3, due to numerous interface defects, resulted in a large number of lattice dislocations in the grown crystals, forming a mosaic structure, which led to a sharp increase in the FWHM value. Comparative Example 2, due to the unstable sublimation of the source material, caused frequent changes in the supersaturation of the gas phase in front of the growth interface, resulting in severe compositional and structural inhomogeneities within the grown crystal and generating enormous growth stress, thus exhibiting the highest FWHM value. This approach, through the synergistic control of the initial growth interface and the mass transfer process, effectively reduces the microscopic strain and macroscopic stress within the crystal, which is key to obtaining crystals with high structural integrity.

[0032] (3) Substrate surface morphology test: The silicon carbide ingots prepared in each example and comparative example were cut and ground, and then processed into wafers by chemical mechanical polishing (CMP); the morphology of the polished substrate surface was characterized by atomic force microscopy in tapping mode; the scanning area size was 10μm×10μm; in order to comprehensively evaluate the surface quality, scanning was performed at 5 different positions on each wafer, and the average value of the root mean square roughness of the surface was calculated; a lower Ra value means a smoother surface, which is beneficial to the subsequent growth of high-quality epitaxial layers; the test results are shown in Table 3; Table 3. Surface roughness test results of each substrate after chemical mechanical polishing.

[0033] As shown in Table 3, the silicon carbide substrates prepared in Examples 1-5, after undergoing the same chemical mechanical polishing (CMP) process, exhibit significantly better surface roughness than the comparative examples, especially far superior to Comparative Example 2. Example 1 has the lowest surface roughness, at only 0.12 nm, achieving atomic-level flatness. The final surface flatness of the substrate depends not only on the polishing process but also, more profoundly, on the quality of its bulk crystal. The substrates in these examples have extremely low defect densities such as internal microtubes and dislocations, resulting in uniform material texture. Therefore, uniform material removal can be achieved during the CMP process, leading to a highly flat surface. Although Comparative Examples 1 and 3 have higher defect densities, the defect types are mainly line defects. While the surface roughness after CMP is acceptable due to pits and stacking faults, it is still inferior to that of the previous example. The problem in Comparative Example 2 is the most serious, as the unstable eruption of its source material leads to the formation of a large number of micron-sized inclusions and polycrystalline defects in the crystal. The hardness of these inclusions differs from that of the SiC matrix, causing selective polishing during CMP, resulting in pits or protrusions, which leads to a sharp deterioration in surface roughness to 0.83 nm. This rough surface will seriously affect the quality of subsequent epitaxial growth layers and ultimately lead to performance degradation and reliability issues in power devices. Therefore, this approach provides a solid foundation for obtaining an atomically flat substrate surface by preparing a high-purity, low-defect bulk crystal.

[0034] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the patent coverage of the present invention.

Claims

1. A method for preparing a silicon carbide substrate, characterized in that, Includes the following steps: A tungsten-carbon composite film was sputtered onto the growth surface of a 4H-SiC single crystal seed crystal using magnetron sputtering. The seed crystal sputtered with the tungsten-carbon composite film is fixed to the crucible lid, and a porous silicon carbide composite source material coated with a graphene nanolayer is laid at the bottom of the crucible. The crucible was placed in a physical vapor transport growth furnace, evacuated and then filled with argon gas. Gradient heating, crystal growth and controlled cooling were then performed to obtain silicon carbide ingots. The method for preparing the graphene nanolayer-coated porous silicon carbide composite source material includes: High-purity α-SiC powder was mixed with a binder, granulated by spray drying, and then subjected to gradient heating and high-temperature sintering in an argon atmosphere to obtain porous silicon carbide spherical particles. The porous silicon carbide spherical particles were placed in a fluidized bed reactor and subjected to pulsed chemical vapor deposition using methane as a carbon source to coat the particle surface with a graphene nanolayer. The method for preparing the nano-tungsten / carbon composite target for magnetron sputtering includes: Nano-tungsten powder and graphite powder were mixed with ball milling media and then subjected to planetary ball milling to obtain a mixed slurry; The mixed slurry is vacuum dried to obtain composite powder, and the composite powder is hot-pressed and sintered to obtain the nano-tungsten / carbon composite target.

2. The preparation method according to claim 1, characterized in that, The weight ratio of the high-purity α-SiC powder to the polyvinyl alcohol solution as the binder component is (480-520):(18-22).

3. The preparation method according to claim 1, characterized in that, The thickness of the graphene nanolayer deposited on the particle surface by chemical vapor deposition is 5-10 nanometers.

4. The preparation method according to claim 1, characterized in that, The weight ratio of the nano-tungsten powder to the graphite powder is (85-95):(5-15).

5. The preparation method according to claim 1, characterized in that, The thickness of the tungsten-carbon composite film formed by magnetron sputtering on the seed crystal growth surface is 25-35 nanometers.

6. The preparation method according to claim 1, characterized in that, The gradient heating step includes holding the temperature at 1600°C to allow the tungsten-carbon composite film to react in situ and generate a nano-tungsten carbide induction layer.

7. The preparation method according to claim 1, characterized in that, In the crystal growth step, the source region temperature is controlled at 2340-2360℃, the seed crystal region temperature is controlled at 2320-2340℃, and a temperature difference of 15-25℃ is maintained between the source region and the seed crystal region.

8. The preparation method according to claim 1, characterized in that, In the controlled cooling step, when the temperature drops below 600℃, the cooling rate is 2-4℃ / minute.

9. A silicon carbide substrate prepared by the preparation method according to any one of claims 1-8.

10. An application of the silicon carbide substrate of claim 9 in the fabrication of power semiconductor devices.

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