Fault detection method for circuit module of control panel

Abstract

The invention provides a control panel circuit module fault detection method, which relates to the technical field of electronic fault detection, and comprises the following steps: acquiring key electrical parameters of each functional unit of a control panel circuit module, establishing a dependency graph of the key electrical parameters, and constructing a multi-level parallel detection sequence; a variable-length window function is adopted to carry out synchronous sampling on detection items of the same level, a level feature matrix is generated, improved short-time Fourier transform is executed, a frequency spectrum deviation curve of each level is generated through sliding cross-correlation operation, a fault transmission chain is established, and a specific fault type is judged through a topological structure of the fault transmission chain; according to the method, the problems of low fault positioning efficiency and poor accuracy caused by difficulty in capturing fault transfer characteristics and insufficient capability of a traditional detection method in multi-level feature extraction and analysis can be solved.

Description

Technical Field

[0001] This invention relates to the field of electronic fault detection technology, and more specifically, to a method for detecting faults in a control board circuit module. Background Technology

[0002] As modern electronic devices become increasingly complex, control board circuit modules have gradually become the core components of various electronic systems, used to implement key functions such as signal processing, data transmission, and power management. Control board circuit modules typically consist of multiple functional units, such as power management units, signal processing units, and communication interface units, which work collaboratively through complex dependencies. However, with the improvement of electronic device performance and the increasing complexity of operating environments, the risk of failure in control board circuit modules has also increased. Once a failure occurs, it may lead to a decline in overall performance or even system failure. Therefore, how to quickly and accurately detect and locate faults in control board circuit modules has become an important research direction in the field of electronic technology. Existing fault detection methods mainly rely on signal analysis, status monitoring, and parameter diagnostics, but these methods suffer from low detection efficiency and insufficient fault location capabilities in complex circuit modules. Furthermore, as circuit module design develops towards higher integration and higher operating frequencies, traditional single-level fault detection methods are insufficient to meet the needs of current complex circuit systems.

[0003] Existing technologies for fault detection in control board circuit modules have the following shortcomings: First, traditional methods lack systematic analysis of key parameters of multiple functional units within the module, making it difficult to establish dependencies between functional units and effectively capture fault propagation characteristics. Second, existing technologies cannot adapt to the distribution characteristics of signals in different frequency bands, resulting in limited detection accuracy. Therefore, existing technologies still have significant room for improvement in fault detection efficiency, accuracy, and fault propagation characteristic analysis. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a method for fault detection of control board circuit modules. This method can, to some extent, solve the problems in the prior art where the lack of systematic analysis of key electrical parameters of functional units makes it impossible to accurately establish the dependencies between units, resulting in difficulty in capturing fault transmission characteristics. It also addresses the shortcomings of traditional detection methods in multi-level feature extraction and analysis, leading to low efficiency and poor accuracy in fault location.

[0005] According to one aspect of the present invention, a method for fault detection of a control board circuit module is provided, comprising:

[0006] Obtain the key electrical parameters of each functional unit of the control board circuit module, establish a dependency graph of the key electrical parameters, and construct a multi-level parallel detection sequence based on the dependency graph;

[0007] Based on the multi-level parallel detection sequence, a variable-length window function is used to synchronously sample the detection items at the same level to generate a hierarchical feature matrix.

[0008] An improved short-time Fourier transform is performed on the hierarchical feature matrix, and the spectral deviation curves of each level are generated through sliding cross-correlation operation;

[0009] A fault transmission chain is established based on the hierarchical distribution characteristics of the aforementioned spectral deviation curve, and the specific fault type is determined through the topological structure of the fault transmission chain.

[0010] Furthermore, the improved short-time Fourier transform achieves accurate time-frequency analysis of the multi-level parallel detection sequence by dynamically adjusting the window function type and parameters.

[0011] Furthermore, the multi-level parallel detection sequence includes four levels, corresponding to the power management unit, signal processing unit, and communication unit, respectively.

[0012] Furthermore, based on the aforementioned multi-level parallel detection sequence, a synchronous sampling strategy is constructed:

[0013] The first level adjusts the sampling period based on power input voltage fluctuations, sudden changes in bus impedance, and changes in signal channel reflected waves.

[0014] The second level dynamically optimizes the sampling period based on output voltage fluctuations, reference voltage deviations, and main control chip temperature changes.

[0015] The third level adjusts the sampling frequency to address the nonlinear characteristics of ADC / DAC levels, clock signal jitter, and communication level anomalies.

[0016] The fourth level adaptively adjusts the sampling period based on the characteristics of communication baud rate, signal integrity, and bit error rate.

[0017] Furthermore, based on the aforementioned synchronous sampling strategy, a hierarchical feature matrix is ​​constructed, where the rows of the matrix represent the detection levels and the columns represent the feature parameters of each detection item.

[0018] Furthermore, based on the hierarchical feature matrix, an improved short-time Fourier transform is used to dynamically adjust the window function type and parameters;

[0019] For the characteristics of the first-level power supply, an improved Hanning window segmentation is adopted, the window length is dynamically adjusted to adapt to frequency drift, and when a voltage transient change is detected, it switches to a short-time Gaussian window to handle the transient change;

[0020] For the second-level signal characteristics, a Kaiser window function with frequency compensation is used to calculate the instantaneous frequency characteristics. If the frequency component exceeds the main lobe range of the window function, frequency leakage is compensated iteratively. If there is interference between frequency components, an adaptive notch filter is used for separation.

[0021] For the third-level communication characteristics, a variable-length Gaussian window is used for signal segmentation. The window length is inversely proportional to the signal bandwidth. If the communication quality deteriorates, the time resolution is increased and the analysis window is shortened. If inter-symbol interference occurs, orthogonal transformation is used to eliminate signal overlap.

[0022] For the characteristics of the fourth-level system, a multi-resolution wavelet basis window function is adopted.

[0023] Furthermore, based on the improved short-time Fourier transform, the features of each level are converted into time-frequency domain expressions, and a spectral deviation curve is generated through sliding cross-correlation operation. When performing sliding cross-correlation operation, the power layer establishes a spectral template based on the power frequency, the signal layer dynamically adjusts the analysis range according to the main frequency, and the communication layer optimizes the window and step size according to the symbol period.

[0024] Furthermore, based on the results of the sliding cross-correlation operation, normalization is performed, abrupt data is processed with smoothing filtering, feature points are extracted through cubic spline interpolation, and interference components are denoised with wavelet thresholding to generate a smooth and high signal-to-noise ratio spectral deviation curve.

[0025] Furthermore, based on the aforementioned spectral deviation curve, a detection window is set to filter extreme points, denoise and verify effectiveness, weak feature points and invalid points are eliminated, and an extreme point sequence is constructed in chronological order.

[0026] Furthermore, based on the extreme point sequence analysis of each level characteristics, the power layer evaluates ripple, switching frequency and load regulation, the signal layer focuses on distortion, rejection ratio and sampling accuracy, the communication layer detects timing jitter and synchronization deviation, and combines timing correlation to construct a fault transmission chain to locate the fault source and path. Power faults spread from fundamental frequency to harmonics, signal faults have local frequency band anomalies, and communication faults propagate from high frequency to low frequency.

[0027] Compared with existing technologies, by constructing multi-level parallel detection sequences and hierarchical feature matrices, and combining improved short-time Fourier transform and sliding cross-correlation operations, accurate spectral deviation curves can be generated, revealing the correlation between fault features at each level. Furthermore, by constructing fault propagation chains based on the spectral deviation curves and performing topology analysis, specific fault types and their propagation paths can be quickly determined, improving the efficiency and accuracy of fault analysis for complex circuit modules. In addition, multi-level parallel detection and dynamic feature extraction further reduce analysis time, enhance adaptability to complex faults, and significantly improve detection efficiency and the reliability of results. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0029] Figure 1 This is a flowchart of a method for detecting faults in a control board circuit module according to an embodiment of the present invention;

[0030] Figure 2 This is a flowchart illustrating the generation of a hierarchical feature matrix in a method for fault detection of a control board circuit module according to an embodiment of the present invention. Detailed Implementation

[0031] Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein.

[0032] As mentioned in the background section above, the existing technology has two main problems: First, it lacks a systematic analysis of the key electrical parameters of each functional unit in the control board circuit module, making it impossible to accurately establish the dependencies between functional units, thus making it difficult to capture the transmission characteristics of faults, resulting in low fault location efficiency and poor accuracy; Second, traditional detection methods mostly use fixed window functions for signal sampling and analysis, which cannot adapt to the dynamic changes in signal characteristics of different frequency bands, especially in multi-level feature processing, lacking comprehensive analysis capabilities and making it difficult to reveal the correlation between fault characteristics at different levels.

[0033] Figure 1 This is a system block diagram of a method for detecting faults in a control board circuit module according to an embodiment of the present invention. Figure 1 As shown, the method for fault detection in the control board circuit module includes:

[0034] S1: Obtain the key electrical parameters of each functional unit of the control board circuit module, establish a dependency graph of the key electrical parameters, and construct a multi-level parallel detection sequence based on the dependency graph.

[0035] Key electrical parameters are obtained from the various functional units of the control board circuit module, including the power management unit, signal processing unit, and communication unit.

[0036] The power management unit mainly includes: main power input voltage, output voltage of each channel, ripple coefficient of each voltage channel, power stability index, power switching timing parameters, and power factor.

[0037] The signal processing unit mainly includes: reference voltage value, ADC sampling channel level, DAC output level, main control chip operating voltage, impedance parameters of each signal channel, clock signal frequency and duty cycle, data bus level, and chip temperature parameters.

[0038] The communication unit mainly includes: RS232 / 485 communication level, CAN bus differential voltage, I2C bus high and low levels, communication baud rate, signal integrity parameters, communication bit error rate, bus impedance matching parameters, etc.

[0039] Further, based on the interrelationships between key electrical parameters, a dependency graph is established, and the specific analysis is as follows: The main power input voltage of the power management unit directly affects the stability of each output voltage, which in turn affects the reference voltage of the signal processing unit and the operating voltage of the main control chip; the operating voltage of the main control chip affects the quality of the clock signal it generates, and the stability of the clock signal directly affects the sampling accuracy of the ADC and the communication baud rate; although the various communication levels of the communication unit depend on the power supply voltage, there is no direct dependency between them; signal integrity parameters are mainly affected by bus impedance matching and external interference, and have a low correlation with other electrical parameters, thus constructing a complete parameter dependency network.

[0040] Based on the established dependency graph, a multi-level parallel detection sequence is constructed, and the detection items are layered from source to end according to the dependency relationship.

[0041] The first level includes independent basic parameters such as main power input voltage detection, power stability detection, bus impedance detection of communication unit, and signal channel impedance detection.

[0042] The second level includes parameters that depend on the main power supply, such as the detection of output voltages for each channel, reference voltage detection, and the detection of the main control chip's operating voltage.

[0043] The third level includes parameters that depend on the secondary power supply, such as ADC / DAC level detection, clock signal parameter detection, and various communication level detection.

[0044] The fourth level includes system operating parameters such as communication baud rate detection, signal integrity detection, and bit error rate detection.

[0045] S2: Based on the multi-level parallel detection sequence, a variable-length window function is used to synchronously sample the detection items at the same level to generate a hierarchical feature matrix.

[0046] For each detection level in the multi-level parallel detection sequence, a corresponding synchronous sampling strategy is constructed. The specific implementation is as follows:

[0047] The first-level sampling strategy is designed as follows: When detecting the main power input voltage, a basic sampling period of 100μs is used. If a voltage fluctuation exceeding 5% of the rated value is detected, the sampling period is automatically adjusted to 50μs until the voltage stabilizes. When detecting bus impedance, a sampling period of 500μs is used. If a sudden change in impedance is detected, a 200μs fast sampling sequence is triggered. When detecting signal channel impedance, a normal sampling period of 400μs is used. If a large reflected wave appears on the channel, it switches to a high-speed sampling mode of 100μs. To ensure sampling synchronization, all first-level detection items use a hardware clock synchronization triggering mechanism, generating the required sampling period through a shared 100MHz main clock source to avoid timing deviations caused by sampling adjustments.

[0048] The second-level sampling strategy design is as follows: When detecting the output voltage of each channel, a standard sampling period of 200μs is used. If the output voltage of a certain channel fluctuates, the sampling period of that channel is automatically reduced to 50μs, and the relevant output voltage detection channel is also switched to the 50μs sampling mode. When detecting the reference voltage, a continuous sampling period of 100μs is used. If the reference voltage deviates from the nominal value by more than 0.1%, a dense sampling mode of 50μs is activated. When detecting the operating voltage of the main control chip, a fixed sampling period of 150μs is used. If the chip temperature exceeds the warning value, all voltage detection channels are switched to a sampling period of 75μs.

[0049] The third-level sampling strategy design is as follows: When detecting ADC / DAC levels, a basic sampling period of 50μs is used. If nonlinear characteristics occur during the conversion process, the sampling period is reduced to 20μs. When detecting clock signals, a standard sampling period of 20μs is used. If the clock signal jitters, a high-precision sampling mode of 5μs is activated. When detecting various communication levels, different sampling periods are used according to the specific protocol; for example, 40μs is used for RS232, 10μs for CAN bus, and 30μs for I2C bus. When any communication interface malfunctions, all related communication parameter detection channels synchronously switch to a higher sampling frequency.

[0050] The fourth-level sampling strategy design is as follows: When detecting the communication baud rate, an adaptive sampling period based on protocol characteristics is adopted, for example, a 100μs sampling period is adopted for a 9600 baud rate and a 10μs sampling period is adopted for a 115200 baud rate; when detecting signal integrity, a standard sampling period of 25μs is adopted, and if the signal quality deteriorates, it automatically switches to a fine sampling mode of 10μs; when detecting the bit error rate, a sampling period adapted to the communication rate is adopted, and the sampling accuracy is automatically increased when an error frame is detected.

[0051] To ensure the effective implementation of sampling strategies at each level, if an anomaly occurs in an upper-level detection item, the sampling frequency of the relevant lower-level detection items will be automatically increased. If a sudden fault is detected, the sampling strategy of the relevant detection items can temporarily break through the level limit to achieve a rapid response. If the system resource load is too high, the sampling frequency of non-critical detection items can be appropriately reduced to ensure the monitoring quality of important parameters.

[0052] Furthermore, a variable-length window function is applied for sampling for each detection item. The adaptive adjustment process of the window function length includes:

[0053] The power management unit uses a variable-length window function for sampling: When detecting the main power input voltage, the initial window length is set to 60ms. If the detected voltage frequency deviates from the nominal value of 50Hz by more than 0.5Hz, the window length is automatically adjusted to three times the frequency period. When monitoring the output voltage ripple, the initial window length is set to 20ms. If the ripple frequency exhibits harmonic components, the window length is extended to 40ms to capture the complete frequency characteristics. When analyzing the transient response of power switching, the window length is dynamically extended from 10ms before switching to 50ms after switching to ensure complete recording of the dynamic process. All power-related sampling uses the Hanning window function to reduce spectral leakage effects.

[0054] The signal processing unit uses a variable-length window function for sampling: When detecting a reference voltage, an initial window length of 30ms is used. If the voltage fluctuates periodically, the window length is automatically adjusted to four times the fluctuation period. When analyzing the ADC sampling channel, the window length is set to five times the input signal period. If the input signal frequency changes, the window length is dynamically adjusted accordingly. When monitoring a clock signal, the basic window length is 1000 clock cycles. If clock jitter occurs, the window length is extended to 2000 cycles to analyze jitter characteristics. Signal processing-related sampling uses a Blackman window function to provide better frequency resolution.

[0055] The communication unit uses a variable-length window function for sampling: When detecting CAN bus signals, the initial window length covers 20 complete data frames; if a bit timing error is detected, the window length is extended to 40 data frames. When analyzing RS485 communication quality, the window length is set to 100 bytes; if communication jitter occurs, the window length is extended to 200 bytes. When monitoring the I2C bus, the basic window length is 50 clock cycles; if a bus anomaly occurs, the window length is automatically adjusted to 100 clock cycles. All communication signal sampling uses a flat-top window function to provide more accurate amplitude measurement.

[0056] Variable-length window function sampling in the data processing channel: When detecting the data bus level, the window length covers 32 consecutive data cycles. If the data transmission rate changes, the window length is adjusted proportionally. When analyzing signal integrity, the initial window length is set to 10 times the rise time. If reflection or ringing occurs, the window length is extended to twice the settling time. When monitoring digital signals, the window length dynamically tracks the effective data segment of the signal to ensure that complete signal characteristics are acquired.

[0057] Variable window function sampling for temperature monitoring channel: When detecting chip temperature, a base window length of 10s is used. If the temperature change rate exceeds 1℃ / s, the window length is shortened to 5s. When analyzing thermal conductivity characteristics, the window length lasts from the start of temperature change to temperature stabilization, typically spanning 30s to 300s. When monitoring heat dissipation effect, the window length covers the complete heat dissipation cycle and is automatically adjusted according to the actual heat dissipation situation.

[0058] Similarly, to ensure the effective implementation of variable-length window function sampling, when the signal frequency changes abruptly, the window function length is adjusted in real time according to the new frequency characteristics, while maintaining coverage of 3-5 complete cycles; when multiple related signals are sampled simultaneously, the window length of each signal is uniformly adjusted according to the longest characteristic cycle to ensure data correlation; when the system detects an anomaly, the window length of the related channel can be dynamically extended until the complete anomaly characteristics are captured.

[0059] Furthermore, a synchronous sampling mechanism is implemented for detection items at the same level. A unified sampling clock source is used, and a frequency divider circuit generates the required sampling clocks for different detection items. Simultaneously, a buffer management mechanism is constructed to ensure synchronous data acquisition for all detection items at the same level. This includes:

[0060] The first-level synchronous sampling mechanism works as follows: When sampling the main power input voltage and bus impedance, a 100MHz main clock source is used as the reference, and a programmable frequency divider circuit generates sampling clocks of 100μs and 500μs respectively. If an abnormality is detected in any channel, the frequency division coefficient of the relevant channel is automatically adjusted. If multiple detection items need to be started simultaneously, the rising edge of the main clock is used as the trigger signal to ensure the synchronization of the sampling start time. If the main power supply voltage fluctuates, a synchronous trigger signal is automatically sent to the bus impedance detection channel to achieve synchronous acquisition of related parameters.

[0061] The second-level synchronous sampling mechanism works as follows: When detecting output voltages, the sampling clock of all voltage detection channels is uniformly set to 200μs; when an abnormality occurs in a certain output voltage, a synchronization signal is sent to the relevant reference voltage detection channel, triggering these channels to synchronously switch to a 50μs sampling mode; when the main control chip's operating voltage detection is initiated, its sampling clock is strictly synchronized with the reference voltage detection channel to ensure the accuracy of voltage correlation analysis. If a power system abnormality is detected, all second-level detection items synchronously increase their sampling frequency.

[0062] The third-level synchronous sampling mechanism is as follows: When performing ADC / DAC level detection, a uniform 50μs sampling period is used, and a shift register ensures phase synchronization of multi-channel sampling; when clock signal detection is initiated, its 20μs sampling period is generated from the master clock source through a frequency multiplier circuit to ensure timing correlation with other detection items; when communication level detection is performed, the sampling frequency division coefficient is set according to the characteristics of different protocols, but the timing alignment of sampling for all communication channels is maintained. If an anomaly occurs in a certain communication interface, all related detection channels are synchronously adjusted to a higher sampling frequency.

[0063] The fourth-level synchronous sampling mechanism works as follows: When detecting communication parameters at different baud rates, a unified clock source is used to generate the required sampling frequency through different frequency division coefficients; when signal integrity detection is initiated, a 25μs sampling clock is allocated to all relevant detection channels to ensure data timing consistency; when bit error rate detection is performed, the sampling clock is strictly synchronized with the communication clock to ensure accurate correspondence between sampling points and data bits. If a communication quality degradation is detected, all relevant detection channels synchronously increase their sampling accuracy.

[0064] The buffer management mechanism is as follows: When multiple detection items at the same level are sampled simultaneously, an independent double buffer is configured for each detection channel, and the buffer depth is determined according to the maximum sampling period. If the buffer of a certain detection channel reaches the preset trigger condition, a synchronous read signal is automatically sent to other channels at the same level. When the system performs data processing, an arbitration mechanism is used to ensure the synchronous reading of data at the same level and avoid data timing disorder. If there is a risk of buffer overflow, the sampling strategy is automatically adjusted to ensure data integrity.

[0065] A data synchronization processing mechanism is constructed: after collecting detection data at the same level, data alignment is first performed based on timestamps; when the sampling periods of different detection items are different, a data sequence with a unified time point is generated through interpolation algorithms; when extracting fault features, data within the same time window is used for analysis. If data is lost or damaged, a data compensation mechanism is activated to maintain the continuity of analysis.

[0066] Based on the above synchronous sampling strategy, a hierarchical feature matrix is ​​constructed. The rows of the matrix represent different detection levels, and the columns represent the feature parameters of each detection item. For each detection item, the following feature parameters are extracted: signal mean, variance, peak-to-peak value, rise time, fall time, overshoot, and setup time. Specifically, these include:

[0067] The first-level feature matrix includes the following feature parameters: when processing main power supply input voltage data, four basic features are extracted: average voltage, RMS voltage, ripple coefficient, and voltage stability; when analyzing bus impedance data, four feature parameters are calculated: average impedance, impedance fluctuation rate, reflection coefficient, and VSWR; when evaluating signal channel impedance, four feature quantities are extracted: characteristic impedance value, crosstalk coefficient, attenuation coefficient, and delay parameter. If these parameters exhibit abnormal fluctuations, the corresponding timestamp and fluctuation amplitude are marked in the feature matrix, forming a first-level feature vector group.

[0068] The feature parameters of the second-level feature matrix include: when analyzing the output voltage data of each channel, extracting four features: DC component, AC ripple, dynamic response time, and settling time; when processing reference voltage data, calculating four parameters: voltage accuracy, temperature coefficient, long-term stability, and noise level; and when evaluating the operating voltage of the main control chip, extracting four features: voltage margin, transient response, overshoot, and recovery time. If an anomaly occurs in a certain voltage channel, the feature changes of the relevant voltage channels are recorded synchronously, and a second-level feature correlation matrix is ​​constructed.

[0069] The feature parameters of the third-level feature matrix include: when processing ADC / DAC level data, extracting four features: conversion accuracy, linearity, offset voltage, and gain error; when analyzing clock signals, calculating four parameters: frequency stability, phase noise, jitter characteristics, and duty cycle; and when evaluating communication levels, extracting four features: level range, conversion rate, overshoot amplitude, and setup time. If a signal anomaly is detected, an anomaly mode descriptor is added to the feature matrix, forming a third-level feature distribution map.

[0070] The feature parameters of the fourth-level feature matrix include: when analyzing communication baud rate data, four features are extracted: rate accuracy, bit timing error, code pattern stability, and clock recovery characteristics; when processing signal integrity data, four parameters are calculated: signal quality factor, eye diagram opening degree, jitter margin, and inter-symbol interference; when evaluating bit error rate, four features are extracted: bit error distribution, burst error rate, recovery capability, and link quality. If communication quality degrades, the complete performance degradation process is recorded, and a fourth-level dynamic feature matrix is ​​constructed.

[0071] After feature extraction at each level is completed, an inter-layer feature correlation graph is established. If the upper-layer features change, the response characteristics of the lower-layer features are tracked. If multiple features change simultaneously, the correlation coefficient matrix between the features is calculated. If a strong correlation is found, the relevant feature pairs are marked in the feature matrix to facilitate fault propagation analysis.

[0072] After constructing the complete feature matrix, the basic weights of each feature are determined using the analytic hierarchy process (AHP); and historical data is used to verify the rationality of the weight allocation. If a significant deviation is found, the weight calculation process is returned to adjust, and the weight configuration scheme is updated when the optimization results meet the requirements.

[0073] Furthermore, if the amount of feature data is large, principal component analysis is used to reduce the feature dimensionality; if long-term storage of features is required, the feature matrix is ​​converted into a sparse representation; if storage space is limited, an incremental update strategy is adopted to maintain the real-time performance and representativeness of the feature library.

[0074] S3: Perform an improved short-time Fourier transform on the hierarchical feature matrix, and generate the spectral deviation curves of each level through sliding cross-correlation operation.

[0075] An improved short-time Fourier transform is performed on the hierarchical feature matrix, specifically including:

[0076] When processing the first level of power characteristics, an improved Hanning window is used for segmentation, with the window length initially covering three times the fundamental period of the signal. When voltage frequency drifts, the window length automatically adjusts with frequency changes, while a cosine smoothing factor is introduced to eliminate spectral leakage. When a transient voltage change is detected, the window function switches to a short-time Gaussian window, the window length is shortened to half the fundamental period, and a 75% overlap rate analysis mechanism is initiated. If the duration of the change exceeds a preset threshold, the window length is gradually extended until a steady-state analysis is achieved.

[0077] Simultaneously, a segmentation strategy is adopted: when processing analog signal characteristics, an adaptive segmentation threshold is set based on the signal variance; when the variance exceeds the threshold, the segment length is reduced to half of the original length, and the frequency of spectral averaging is increased; when digital signals in the communication layer exhibit abrupt changes, a threshold detection method is used to determine the segmentation boundaries, achieving natural signal segmentation. If the spectral correlation between adjacent segments is less than 0.8, an intermediate transition segment is added to ensure the continuity of spectral analysis.

[0078] When analyzing the second-level signal characteristics, a Kaiser window function with frequency compensation is selected. First, the instantaneous frequency characteristics of the signal are calculated. If a frequency component is not within the main lobe of the window function, frequency leakage is compensated through iterative calculation. If multiple frequency components interfere with each other, an adaptive notch filter is used for separation. If the amplitude of a certain frequency component changes by more than 20%, that frequency band is analyzed in detail.

[0079] When calculating the third-level communication characteristics, a variable-length Gaussian window is used for signal segmentation. The window length is inversely proportional to the signal bandwidth. If the communication quality deteriorates, the time resolution is increased and the analysis window is shortened. If inter-symbol interference occurs, orthogonal transformation is used to eliminate signal overlap. If the communication protocol changes, the analysis parameters are automatically adjusted to match the new signal characteristics.

[0080] When evaluating the characteristics of the fourth-level system, a multi-resolution wavelet basis window function is used to achieve time-frequency localization analysis.

[0081] Furthermore, when performing inter-layer feature correlation analysis, an eight-layer wavelet decomposition tree is constructed to achieve layered extraction of different frequency bands. If rapid changes above 200Hz occur in the high-frequency band, the sampling rate is increased and the analysis window length is reduced. If slow features below 20Hz need to be analyzed in the low-frequency band, the resolution is increased. If an abnormal concentration of energy is detected in a certain frequency band, narrowband scanning analysis is performed on that frequency band.

[0082] Simultaneously, the interlayer characteristic transmission relationship is analyzed, and the cross-spectral function between adjacent layers is calculated. If the cross-spectral coherence is below 0.6, the analysis density of the transition band is increased. If frequency coupling is found, nonlinear characteristics are determined through bispectral analysis. If significant deviations occur in the interlayer spectrum, possible fault propagation paths are marked.

[0083] Based on the improved short-time Fourier transform, the features at each level are converted into time-frequency domain representations. Then, a spectral deviation curve is generated through sliding cross-correlation, specifically including:

[0084] When receiving the short-time Fourier transform outputs from each level, the power layer characteristic spectrum is first processed, using three times the period of the 50Hz power frequency as the basic analysis interval, while a reference spectrum template is established within a 300Hz bandwidth. If higher harmonics are detected, the analysis bandwidth is extended to 500Hz.

[0085] Furthermore, when processing the characteristic spectrum of the signal layer, a cross-correlation reference is set based on the transformed 100Hz dominant frequency component; when calculating the spectral deviation, the sliding window step size is set to 1 / 4 of the signal period, consistent with the time resolution during transformation; when evaluating spectral changes, the ±0.1Hz frequency resolution accuracy after transformation is inherited. If the signal bandwidth expands, the frequency range for cross-correlation calculation is adjusted accordingly.

[0086] Furthermore, when processing the characteristic spectrum of the communication layer, the spectrum obtained by sampling at 1 kHz is used as the input for cross-correlation calculation; when setting the sliding window, the window length is set to 5 times the period of the basic symbol of the communication, corresponding to the smallest analysis unit during transformation; when dealing with sudden changes in the spectrum, the calculation step size is reduced to 1 / 10 of the symbol period. If the communication rate changes, the time parameter of the cross-correlation operation is adjusted synchronously.

[0087] Furthermore, when performing sliding cross-correlation calculations, if a spectral abrupt change occurs at any level, the calculation step size of that level is automatically reduced to improve analysis accuracy. When multiple levels experience anomalies simultaneously, the analysis is performed in the priority order of power layer, signal layer, and communication layer. The system uses a weighting coefficient of 0.5 in the low-frequency band (0-100Hz), a weighting coefficient of 0.3 in the mid-frequency band (100-500Hz), and a weighting coefficient of 0.2 in the high-frequency band (greater than 500Hz).

[0088] When synthesizing the transformation outputs of each layer, if a spectral deviation occurs at the power layer, the characteristics of the power frequency and its harmonic components should be evaluated first. If an anomaly is detected at the signal layer, the frequency band characteristics around 100Hz should be analyzed in detail. If fluctuations occur at the communication layer, the cross-correlation characteristics of the frequency bands above 1kHz should be considered. If anomalies occur at multiple layers simultaneously, the analysis should be performed in the order of priority: power layer, signal layer, and communication layer.

[0089] When summarizing the cross-correlation results of each level, a segmented weighted approach is used to construct the deviation curve. When a deviation occurs in the low-frequency band (0-100Hz), the initial weighting coefficient is set to 0.5; when a change occurs in the mid-frequency band (100-500Hz), the initial weighting coefficient is 0.3; and when an anomaly is detected in the high-frequency band (>500Hz), the initial weighting coefficient is 0.2. If the deviation of a certain frequency band exceeds a threshold, the weight of that frequency band is automatically increased by 50%.

[0090] After completing the cross-correlation calculations at each level, the deviation data is first normalized. If data jumps occur, a five-point smoothing filter is used. If feature points need to be extracted, cubic spline interpolation is used to ensure the curve is smooth and continuous. If the curve contains interference components, wavelet thresholding is used to improve the signal-to-noise ratio, thereby generating the spectral deviation curve.

[0091] S4: Establish a fault transmission chain based on the hierarchical distribution characteristics of the spectrum deviation curve, determine the fault source location through the topology of the fault transmission chain, and determine the specific fault type using the sub-waveform morphology characteristics of the corresponding level of the fault source.

[0092] After obtaining the spectral deviation curve, preliminary screening is performed. First, a basic detection window is set, with a window width covering three times the minimum feature period. Extreme points are searched within the window, and a three-point comparison method is used to determine local maximum and minimum values. If the interval between adjacent extreme points is less than the minimum feature period, the extreme point with the larger amplitude is retained. If the curve contains noise interference, wavelet denoising preprocessing is performed first.

[0093] After initial screening, the validity of each extreme point is verified. If the amplitude of an extreme point is less than 0.5 times the global mean square error, it is marked as a weak feature point. If the left-right asymmetry of an extreme point exceeds 20%, its location accuracy needs to be reassessed. If an extreme point is determined to be invalid, candidate points are searched again in its neighborhood.

[0094] After obtaining the effective set of extreme points, an extreme point sequence is constructed in chronological order. If the time interval between adjacent extreme points is too large, intermediate sampling points are added for interpolation calculation. If extreme points cluster, the optimal selection is made based on the magnitude of the extreme points. If the sequence is interrupted, a local resampling mechanism is initiated.

[0095] When analyzing the extreme point sequence, the hierarchical distribution characteristics are first established:

[0096] At the power layer, the power layer extreme point sequence of the control circuit module is analyzed. When output voltage ripple of the DC-DC converter circuit is detected, the extreme point corresponding to the ripple frequency is extracted. If the extreme point of the ripple amplitude exceeds 3% of the output voltage, power supply anomaly detection is initiated. If the extreme point sequence of the switching frequency drifts by more than ±5%, frequency stability degradation is recorded. If the extreme point corresponding to the load regulation rate of the LDO regulator circuit exceeds 0.1% / mA, it is marked as a power supply dynamic response anomaly.

[0097] At the signal layer, the focus is on the extreme point characteristics of analog signal conditioning circuits and digital control circuits. If the output signal of the operational amplifier is distorted, the distribution of extreme points in the frequency band corresponding to the gain-bandwidth product is analyzed. If the common-mode rejection ratio of the signal conditioning circuit decreases, the extreme point characteristics of 50 / 60Hz power frequency interference are extracted. If the effective bit depth of the ADC sampling data decreases, the degree of conversion accuracy degradation is assessed by quantizing the extreme points in the noise frequency band. If the duty cycle of the PWM control signal fluctuates, the rate of change of extreme points in the modulation depth is calculated.

[0098] At the communication layer, the main analysis focuses on the signal integrity of the control bus. If jitter occurs in the SPI bus clock signal, the extreme point characteristics of the timing jitter are extracted. If data transmission errors occur in the I2C bus, the extreme point sequence corresponding to the signal rise / fall time is analyzed. If the bit timing of the CAN bus deviates, the communication reliability is evaluated through the bit synchronization extreme points.

[0099] Once the hierarchical characteristics are clear, a fault propagation chain is constructed based on the temporal correlation of extreme point sequences. First, the timing of the occurrence of extreme points at each level is analyzed. If the extreme point anomaly at the power layer occurs earlier than at other levels, a propagation path originating from the power source is established. If changes in the extreme point at the signal layer cause a response at the communication layer, the propagation delay and attenuation characteristics are recorded. If multiple levels of extreme points change simultaneously, their correlation coefficients are calculated to determine the coupling strength. Subsequently, these temporal relationships and coupling characteristics are transformed into a quantitative propagation topology.

[0100] After establishing the fault propagation topology, the location of the fault source is determined through backtracking analysis. If the power layer is the fault source, its extreme point sequence usually exhibits the following characteristics: the extreme point corresponding to the fundamental frequency is abnormal first, and the abnormal features are propagated to the extreme points of the harmonic frequency band within 2ms; when the signal layer is the fault source, its extreme point sequence often shows continuous abnormalities within a local frequency band and affects the distribution of extreme points in adjacent frequency bands within 5ms; if the communication layer is the fault source, the extreme point sequence of the high-frequency band is disordered first and propagates to the low-frequency band within 3ms.

[0101] The extracted features are matched with a preset fault mode library: when the extreme point sequence of the switching power supply shows periodic decay (decay rate > 5% / s), it usually points to a decrease in the efficiency of the switching transistor or an increase in the ESR of the output capacitor; when the extreme points of the operational amplifier show temperature-related drift (drift rate > 0.1% / ℃), it may be due to device aging or poor heat dissipation in the PCB layout; when the extreme points of the digital signal show an increase in rise time (change rate > 20%), it is often related to signal integrity degradation or improper impedance matching.

[0102] In summary, the method for fault detection of control board circuit modules based on the embodiments of the present invention has been clarified. By constructing multi-level parallel detection sequences and hierarchical feature matrices, and combining improved short-time Fourier transform and sliding cross-correlation operations, it can generate accurate spectral deviation curves, revealing the correlation between fault features at each level. Based on the spectral deviation curves, a fault transmission chain is constructed and topology analysis is performed, which can quickly determine the specific fault type and its transmission path, improving the efficiency and accuracy of fault analysis of complex circuit modules.

Claims

1. A method for fault detection of a control board circuit module, characterized in that, include: Obtain the key electrical parameters of each functional unit of the control board circuit module, establish a dependency graph of the key electrical parameters, and construct a multi-level parallel detection sequence based on the dependency graph; Based on the multi-level parallel detection sequence, a variable-length window function is used to synchronously sample the detection items at the same level to generate a hierarchical feature matrix. An improved short-time Fourier transform is performed on the hierarchical feature matrix, and the spectral deviation curves of each level are generated through sliding cross-correlation operation; A fault transmission chain is established based on the hierarchical distribution characteristics of the spectral deviation curve, and the specific fault type is determined by the topology of the fault transmission chain.

2. The method for fault detection of control board circuit module according to claim 1, characterized in that, The improved short-time Fourier transform achieves accurate time-frequency analysis of the multi-level parallel detection sequence by dynamically adjusting the window function type and parameters.

3. The method for fault detection of control board circuit module according to claim 1, characterized in that, The multi-level parallel detection sequence includes four levels, corresponding to the power management unit, signal processing unit, and communication unit, respectively.

4. The method for fault detection of control board circuit module according to claim 3, characterized in that, Based on the aforementioned multi-level parallel detection sequence, a synchronous sampling strategy is constructed: The first level adjusts the sampling period based on power input voltage fluctuations, sudden changes in bus impedance, and changes in signal channel reflected waves. The second level dynamically optimizes the sampling period based on output voltage fluctuations, reference voltage deviations, and main control chip temperature changes. The third level adjusts the sampling frequency to address the nonlinear characteristics of ADC / DAC levels, clock signal jitter, and communication level anomalies. The fourth level adaptively adjusts the sampling period based on the characteristics of communication baud rate, signal integrity, and bit error rate.

5. The method for fault detection of control board circuit module according to claim 4, characterized in that, Based on the synchronous sampling strategy, a hierarchical feature matrix is ​​constructed, where rows represent detection levels and columns represent feature parameters of each detection item.

6. The method for fault detection of control board circuit module according to claim 5, characterized in that, Based on the hierarchical feature matrix, an improved short-time Fourier transform is used to dynamically adjust the window function type and parameters; For the characteristics of the first-level power supply, an improved Hanning window segmentation is adopted, the window length is dynamically adjusted to adapt to frequency drift, and when a voltage transient change is detected, it switches to a short-time Gaussian window to handle the transient change; For the second-level signal characteristics, a Kaiser window function with frequency compensation is used to calculate the instantaneous frequency characteristics. If the frequency component exceeds the main lobe range of the window function, frequency leakage is compensated iteratively. If there is interference between frequency components, an adaptive notch filter is used for separation. For the third-level communication characteristics, a variable-length Gaussian window is used for signal segmentation. The window length is inversely proportional to the signal bandwidth. If the communication quality deteriorates, the time resolution is increased and the analysis window is shortened. If inter-symbol interference occurs, orthogonal transformation is used to eliminate signal overlap. For the characteristics of the fourth-level system, a multi-resolution wavelet basis window function is adopted.

7. The method for fault detection of control board circuit module according to claim 6, characterized in that, Based on the improved short-time Fourier transform, the features of each level are converted into time-frequency domain expressions. The spectral deviation curve is generated by sliding cross-correlation operation. When performing sliding cross-correlation operation, the power layer establishes a spectral template based on the power frequency, the signal layer dynamically adjusts the analysis range according to the main frequency, and the communication layer optimizes the window and step size according to the symbol period.

8. The method for fault detection of control board circuit module according to claim 7, characterized in that, Based on the results of the sliding cross-correlation operation, normalization is performed, abrupt data is processed by smoothing filtering, feature points are extracted by cubic spline interpolation, and interference components are denoised by wavelet thresholding to generate a smooth and high signal-to-noise ratio spectral deviation curve.

9. The method for fault detection of control board circuit module according to claim 8, characterized in that, Based on the spectral deviation curve, a detection window is set to filter extreme points, denoise and verify effectiveness, weak feature points and invalid points are eliminated, and an extreme point sequence is constructed in chronological order.

10. The method for fault detection of control board circuit module according to claim 9, characterized in that, Based on the extreme point sequence analysis, the characteristics of each level are analyzed. The power layer evaluates ripple, switching frequency and load regulation. The signal layer focuses on distortion, rejection ratio and sampling accuracy. The communication layer detects timing jitter and synchronization deviation. By combining timing correlation, a fault transmission chain is constructed to locate the fault source and path. Power faults spread from the fundamental frequency to the harmonics. Signal faults have local frequency band anomalies. Communication faults propagate from high frequency to low frequency.

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