Carry chain calibration method, apparatus, time measurement unit and device

Abstract

The application relates to a carry chain calibration method, device, time measurement unit and equipment. The method comprises the following steps: acquiring a bit output sequence of a carry chain; segmenting the bit output sequence to obtain a plurality of to-be-processed segments; screening a target segment from each to-be-processed segment and counting the number of times that each bit carry output is 1 in the target segment; generating a remapping table of the physical bit position and the logical bit index of the carry chain based on the number of times that each bit carry output is 1 in each target segment, and remapping the bit output sequence of the carry chain. The method can improve the accuracy of a multi-stage carry chain, thereby inhibiting systematic jitter.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, and in particular to a carry chain calibration method and device, a time measurement unit, and equipment. BACKGROUND

[0002] In a semiconductor test device, a high-precision time measurement unit (TMU) is implemented through a time-to-digital converter (TDC) circuit, where the TDC circuit is constructed based on a carry chain in a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). As a signal propagation path, the carry chain has a linear relationship between the number of cascaded stages and the propagation delay, which directly determines the precision of the TMU. However, the following factors will cause uneven distribution of the propagation delay of the multi-stage carry chain: 1. Process deviation causes the difference in the propagation delay of adjacent carry stages; 2. Environmental interference, voltage noise, and other factors, which are particularly significant in high-frequency scenarios; 3. In a multi-stage carry chain (such as the -CARRY8 cascade of Xilinx UltraScale), the single-stage error increases with the number of cascaded stages, leading to global jitter deterioration.

[0003] In order to suppress the uneven distribution of the propagation delay of the carry chain, the existing technology mainly relies on three methods: static layout constraints, dynamic phase compensation, and hardware-assisted calibration. Among them, the first method relies on static layout constraint optimization, for example, by using EDA tools to force the layout and routing tools to optimize the delay consistency of the carry chain path. However, this method cannot dynamically compensate for the delay fluctuations caused by process deviations or environmental (temperature, voltage) changes, and the calibration accuracy is insufficient in high-frequency scenarios (> 500 MHz); the second method, dynamic phase compensation, uses programmable delay units of the FPGA to adjust the phase of the carry chain through closed-loop feedback. However, this method requires additional logic resources, has a long calibration period (requires multiple iterations), and cannot solve the problem of global timing offset accumulation in a multi-stage carry chain; the third method, hardware-assisted calibration (such as TDC implementation on-chip calibration), requires additional chip area and power consumption, which is costly, and the TDC itself may introduce measurement errors.

[0004] In summary, there is an urgent need for a solution that does not rely on additional hardware, has a short calibration period (no iteration required), and can solve the problem of global timing offset accumulation in a multi-stage carry chain, in order to meet the timing accuracy requirements of semiconductor test equipment. SUMMARY

[0005] Therefore, it is necessary to provide a carry chain calibration method and device for semiconductor test equipment, a time measurement unit, and equipment to solve the above technical problems.

[0006] In a first aspect, the application provides a carry chain calibration method, the method comprising:

[0007] obtaining a plurality of bit output sequences of a carry chain;

[0008] segmenting each of the bit output sequences to obtain a plurality of to-be-processed segments;

[0009] selecting target segments from each of the to-be-processed segments and counting the number of times of carry output of 1 for each bit in each of the target segments;

[0010] generating a remapping table of physical bit positions and logical bit indexes of the carry chain based on the number of times of 1 for each bit in each of the target segments, and remapping the bit output sequences of the carry chain.

[0011] In one of the embodiments, the probability of carry output of 1 for each bit monotonically increases from the least significant bit to the most significant bit, or the probability of carry output of 1 for each bit monotonically decreases from the most significant bit to the least significant bit.

[0012] In one of the embodiments, the segmenting each of the bit output sequences to obtain a plurality of to-be-processed segments comprises:

[0013] segmenting each of the bit output sequences to obtain a plurality of to-be-processed segments based on a segment rule and a guard interval rule, the segment rule comprising that the length of each of the to-be-processed segments is less than or equal to the shorter one of 1 and 0 in the current period of the to-be-processed segment, and the guard interval rule comprising that a target length of guard interval is set before and after the to-be-processed segment, and the bits other than the guard interval are effective bits of the to-be-processed segment, and the effective bits are used to count the number of times of carry output of 1.

[0014] In one of the embodiments, the selecting target segments from each of the to-be-processed segments comprises:

[0015] determining that the to-be-processed segment including only rising edges is a target segment; or

[0016] determining that the to-be-processed segment including only falling edges is a target segment.

[0017] In one of the embodiments, the segmenting each of the bit output sequences to obtain a plurality of to-be-processed segments comprises:

[0018] segmenting each of the bit output sequences to obtain a plurality of to-be-processed segments based on an overlap rule, wherein the overlap rule comprises that there are overlapping bits between the effective bits of adjacent to-be-processed segments;

[0019] The method further comprises:

[0020] obtaining a difference between the number of times of the carry output being 1 of the overlapping bits in adjacent target segments;

[0021] In the case that the differences between the number of times of the carry output being 1 of the overlapping bits in adjacent target segments are not equal, re-segmenting the bit output sequence to obtain a plurality of to-be-processed segments, and continuing to perform the step of screening target segments from the to-be-processed segments until the differences between the number of times of the carry output being 1 of the overlapping bits in adjacent target segments are equal.

[0022] In one embodiment, the re-segmenting the bit output sequence to obtain a plurality of to-be-processed segments comprises:

[0023] After reducing the segment length of the to-be-processed segment and / or increasing the guard interval, segmenting the bit output sequence based on the new segment length and / or the new guard interval to obtain a plurality of to-be-processed segments.

[0024] In one embodiment, the generating the remapping table of the physical bit position and the logical bit index of the carry chain based on the number of times of the carry output being 1 of each bit in each target segment, and remapping the bit output sequence of the carry chain comprises:

[0025] correcting the number of times of the carry output being 1 of the effective bits after the overlapping bits in a later target segment among adjacent target segments based on the difference between the number of times of the carry output being 1 of the overlapping bits in adjacent target segments;

[0026] generating the remapping table of the physical bit position and the logical bit index of the carry chain based on the corrected number of times of the carry output being 1 of each bit in each target segment, and remapping the bit output sequence of the carry chain.

[0027] In one embodiment, the correcting the number of times of the carry output being 1 of the effective bits after the overlapping bits in a later target segment among adjacent target segments based on the difference between the number of times of the carry output being 1 of the overlapping bits in adjacent target segments comprises:

[0028] starting from a first target segment, calculating the difference between the number of times of the carry output being 1 of the overlapping bits in adjacent target segments;

[0029] adding the difference to the number of times of the carry output being 1 of the effective bits after the overlapping bits in a later target segment among adjacent target segments to obtain the corrected number of times of the carry output being 1 of the effective bits after the overlapping bits, until each target segment is processed.

[0030] In one embodiment, the generating, based on the number of times that each bit in each target segment outputs a carry of 1, a remapping table of the physical bit position and the logical bit index of the carry chain, and remapping the bit output sequence of the carry chain, comprises:

[0031] sequentially sorting, in a low-to-high order or a high-to-low order, the bits based on the number of times that each bit in each target segment outputs a carry of 1;

[0032] remapping the bit output sequence of the carry chain based on the remapping table.

[0033] In a second aspect, the present application provides a carry chain calibration device, the device comprising:

[0034] a collection module configured to acquire each bit output sequence of a carry chain;

[0035] a segmentation module configured to segment each bit output sequence to obtain a plurality of to-be-processed segments;

[0036] a frequency counting module configured to filter each target segment from each to-be-processed segment and count the number of times that each bit in each target segment outputs a carry of 1;

[0037] a remapping calibration module configured to generate, based on the number of times that each bit in each target segment outputs a carry of 1, a remapping table of the physical bit position and the logical bit index of the carry chain, and remap the bit output sequence of the carry chain.

[0038] In a third aspect, the present application provides a time measurement unit comprising a carry chain, which executes the steps of the method in any one of the above embodiments.

[0039] In a fourth aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any one of the above embodiments.

[0040] The aforementioned carry chain calibration method, apparatus, time measurement unit, and device acquire the bit output sequence of the carry chain; segment the bit output sequence to obtain several segments to be processed; select target segments from the segments to be processed and count the number of times each bit in the target segment has a carry output of 1; generate a remapping table between the physical bit positions and logical bit indices of the carry chain based on the number of times each bit in the target segment has a carry output of 1, and remap the bit output sequence of the carry chain. In this way, by statistically analyzing the frequency distribution of carry outputs of logic 1 at each physical bit position, a remapping relationship between physical bit positions and logical bit indices is established, converting physical bit positions into logical bit indices, thereby improving the accuracy of time measurement. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a diagram illustrating the application environment of the carry chain calibration method in one embodiment;

[0043] Figure 2 This is a flowchart illustrating a carry chain calibration method in one embodiment;

[0044] Figure 3 This is a schematic diagram of the time-domain waveform corresponding to the three-bit output sequence in one embodiment;

[0045] Figure 4 This is a segmentation diagram in one embodiment;

[0046] Figure 5 This is a flowchart of the additive splicing step in one embodiment;

[0047] Figure 6 This is a schematic diagram of remapping in one embodiment;

[0048] Figure 7 for Figure 6 A schematic diagram showing the position of each bit in the illustrated embodiment;

[0049] Figure 8 A flowchart of the carry chain calibration method in another embodiment;

[0050] Figure 9 A schematic diagram showing the length and number of bubbles in each bit of the segmented calibration carry chain;

[0051] Figure 10A schematic diagram for calibrating the length and number of bubbles contained in each bit of the backward carry chain;

[0052] Figure 11 A structural block diagram of the carry chain calibration device in one embodiment;

[0053] Figure 12 An internal structural diagram of the computer device in one embodiment. DETAILED DESCRIPTION

[0054] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0055] It should be noted that the terms "first", "second", etc. used in the present application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "include" and "have" and any variations thereof used in the present application are intended to cover non-exclusive inclusion. The term "a plurality of" used in the present application refers to two or more. The term "and / or" used in the present application refers to one of the options or any combination of multiple options.

[0056] In the present application, the output carry of 1 refers to the value of the output of the carry being 1.

[0057] The carry chain calibration method provided by the embodiments of the present application can be applied to a time measurement unit as shown in the figure. Figure 1 The time measurement unit includes a carry chain, wherein the time measurement unit can calibrate the bit output sequence of the carry chain to optimize the jitter performance of the Test Measurement Unit (TMU) by dynamically counting the carry chain propagation delay distribution.

[0058] It should be noted that the jitter referred to in the present application refers to the deviation of the signal edge from the ideal timing, including timing delay of the carry chain, environmental noise / interference, and signal jitter.

[0059] In the present application, the time measurement unit can be a time measurement unit in an FPGA or an ASIC, and in other embodiments, it can also be a time measurement unit in other chips.

[0060] Due to timing delay and signal jitter, timing error accumulates; the time measurement unit can precisely measure timing error accumulation to quantify delay and jitter parameters, thereby optimizing system timing design.

[0061] wherein in the multi-stage carry chain structure, all carry outputs of bits have fixed ordering in physical layout. Once the hardware implementation is determined, the physical positions (i.e. bit indices) of the carry bits are also fixed. Taking an example of a carry chain with 8 taps (referred to as carry8), its 8 carry outputs correspond to bit positions 0 to 7 in sequence; the second carry8 follows the highest bit output (i.e. bit 7) of the previous stage carry chain, and the subsequent stages follow in the same manner, forming a continuous sequence of bit indices. This structure corresponds to a monotonically increasing curve in ideal case, where the horizontal axis represents bit position, the direction increases from LSB to MSB, and the vertical axis represents the probability of the carry output being logic 1. In actual hardware operation, due to factors such as timing jitter, process variation or environmental noise, the timing characteristics of the carry signal propagation will dynamically shift, and these timing variations will distort the probability distribution of the carry output being logic 1 - for example, process variation can cause an abnormally large delay in the carry propagation of physical bit 3, resulting in a lower-than-ideal probability of its carry output, but the physical position of this bit (bit index = 3) remains fixed. Therefore, the actual observed "probability-bit position" curve will deviate from the ideal monotonically increasing characteristic (e.g. local plateau or non-monotonic points will appear), but the overall trend will still maintain a monotonous upward trend from LSB to MSB. Based on this statistical regularity, the present application proposes a calibration method: by statistically counting the frequency of carry output 1 at each physical position in a large number of samples, a measured probability distribution curve is constructed; by comparing this curve with the ideal monotonically increasing model, a re-mapping table of physical bit position to logical bit index is established, which is used to perform a re-mapping operation on the carry chain output data - when physical bit k is re-mapped to logical bit n, the system writes the kth bit data of the original output to the nth bit of the result.

[0062] It should be noted that the present application relies on the randomness of the operands, and a large number of random carry chain bit output sequences need to be counted. When the sample size tends to infinity, the observed probability will converge to the theoretical probability. In the present application, the number of carry chain bit output sequences is greater than a threshold value, which can be determined artificially, and the sample size needs to be large enough.

[0063] In an exemplary embodiment, as shown in Figure 2 , a carry chain calibration method is provided, which is applied to the time measurement unit in Figure 1 , including steps 202 to 208. Wherein:

[0064] S202: Obtain each bit output sequence of the carry chain.

[0065] Specifically, the carry chain generates a bit output sequence when an input is present. For example, a periodic square wave signal can be input into the carry chain (R = N × K bits), where N represents the number of carry chains (N levels), K represents the number of taps in each carry chain level (which is also equal to the number of bits in each carry chain level), and R represents the total number of bits in each time-domain waveform. The frequency f of the periodic square wave is determined by the operating scenario of the Time Measurement Unit (TMU). R is greater than the number of bits in one period of the periodic square wave. R, N, and K are all positive integers greater than or equal to 1.

[0066] Combination Figure 3 As shown, the time measurement unit acquires M consecutive output sequences of R bits. Figure 3 In the illustrated embodiment, N=4, K=8, M=3, and R=32. In this embodiment, by acquiring a multi-level carry chain, the synchronization of all levels can be optimized, avoiding the accumulation of errors caused by cascading during single-level calibration.

[0067] In some optional embodiments, R bits are flipped from bit R-1, bit R-2, ..., bit 1, bit 0 to bit 0, bit 1, ..., bit R-2, bit R-1. This way, when the bit output sequence is subsequently judged, the rising edge is actually a falling edge. In other optional embodiments, this flipping step is omitted.

[0068] S204: Segment the output sequence of each bit to obtain several segments to be processed.

[0069] Specifically, the segment to be processed is obtained by segmenting each bit output sequence. The purpose of segmentation is to ensure that the statistical window does not span two level transitions and only includes rising or falling edges. The segment to be processed includes multiple bits, and the bits include 0 and 1, so that each segment to be processed includes either rising or falling edges.

[0070] The to-be-processed segments are continuous, and there is an overlap between adjacent to-be-processed segments, so that the difference correction can be performed based on the number of times of carry output of 1 of bits of the overlap. In some optional embodiments, the to-be-processed segments include a segmentation rule or a segmentation rule and a guard interval rule when segmented, the segmentation rule is to ensure that the statistical window does not cross 2 times of level jump, and only includes a rising edge or a falling edge. Especially in a high-frequency scenario, not only a plurality of carry chains are included, but also a plurality of periods with high and low level changes are included. However, only within a to-be-processed segment, the probability of carry output of 1 of bits strictly monotonically increases from an LSB to an MSB. If the to-be-processed segments are not segmented, the statistical range crosses the level, and at this time, the "bit-probability" monotonically increasing relationship is not met, and the statistical result is invalid, so the to-be-processed segments need to be segmented in the present application. The guard interval rule is to avoid the influence of adjacent to-be-processed segments on the current to-be-processed segment, so that only the middle effective bits can be counted. In other embodiments, the to-be-processed segments also include an overlap rule when segmented, the overlap rule is that there is an overlap bit between the effective bits of adjacent to-be-processed segments, so that the overlap bit can be checked to ensure the accuracy of the to-be-processed segments, thereby improving the checking efficiency.

[0071] S206: Select a target segment from the to-be-processed segments, and count the number of times of carry output of 1 of each bit in the target segment.

[0072] Specifically, the target segment is selected from the to-be-processed segments, and only includes a to-be-processed segment with a rising edge or a falling edge, wherein the target segment is also continuous and has an overlap.

[0073] The number of times of carry output of 1 of each bit in each target segment is counted, that is, the number of times of high level appearing in each target segment is counted. In other embodiments, the number of times of 0 appearing in each bit can also be counted. Or both the number of times of 1 appearing and the number of times of 0 appearing are counted.

[0074] S208: Generate a remapping table of a carry chain physical bit position and a logical bit index based on the number of times of carry output of 1 of each bit in each target segment, and remap a bit output sequence of the carry chain.

[0075] In some optional embodiments, the probability of carry output of 1 of a bit monotonically increases from a least significant bit to a most significant bit, or the probability of carry output of 1 of the bit monotonically decreases from the most significant bit to the least significant bit. The number of times of 0 appearing in the bit and the position of the bit in the carry chain are negatively correlated, that is, in a target segment, the number of times of carry output of 0 and the position of the bit monotonically decrease.

[0076] The probability of the bit carry output being 1 strictly monotonically increases from the least significant bit to the most significant bit (LSB→MSB) or monotonically decreases from the most significant bit to the least significant bit with the logical bit index. When factors such as process deviation cause the mapping between the physical bit position and the logical bit index to have a non-monotonic point, the theoretical characteristic is reconstructed after the carry chain bit output sequence is remapped by the remapping table, and the physical bit position with the lowest statistical frequency is mapped to the logical LSB, and the physical bit position with the highest statistical frequency is mapped to the logical MSB.

[0077] That is, the higher the bit position in the carry chain, the greater the delay, and the greater the probability of the carry output being 1. Therefore, the order of the bits in the carry chain can be determined according to the probability of each bit carry output being 1.

[0078] For a full adder at any position k,

[0079] When and , a carry is necessarily generated.

[0080] Carry propagation When , the low-bit carry is propagated to the high bit.

[0081] Carry output .

[0082] Therefore, there are two ways to generate a carry output, one is that the carry is directly generated: and , 1+1=10; and the other is that the carry is generated by propagation: When , the low-bit carry is propagated to the high bit, that is, 1+0+1=10.

[0083] Probability calculation (uniform random input)

[0084]

[0085]

[0086]

[0087] ( Depends on , and are mutually exclusive, so there is no overlapping part)

[0088] LSB (k=0), ,

[0089] ,

[0090]

[0091] …

[0092] By mathematical induction, we have:

[0093]

[0094] The larger k is (i.e. the higher bit in the carry chain), The larger it is.

[0095] Therefore, by counting the number of times the carry output is 1 to estimate the delay of each bit in the carry chain, it implies a key statistical mathematical basis: the number of times the carry output is 1 and the time of signal propagation to the bit are monotonically increasing. If there are rising and falling edges at the same time in a statistical window, the mathematical basis of this statistical method fails. Especially in high-frequency scenarios, the number of cycles of the multi-stage only chain output bit is large, and the multi-segment segmentation is the premise of calibration. In addition, according to the law of large numbers, when the sample size tends to infinity, the observed frequency will converge to the theoretical probability, so in practical applications, a large enough sample size (i.e. the value of M is large enough, i.e. a large enough bit output sequence needs to be obtained) is needed to approximate this limit.

[0096] Therefore, in this application, the number of times each bit in each target segment outputs 1 is used to generate a remapping table of the physical bit position and the logical bit index of the carry chain, and the bit output sequence of the carry chain is remapped to determine the accurate position of each bit, and calibration is achieved.

[0097] Wherein by inputting a periodic signal and grabbing multiple sets of bit sequences, the method of segmenting and counting the number of bits 1 is used to quantify the propagation delay difference of each bit, which can eliminate the statistical error introduced by level jump. In addition, the calibration process is completely realized by digital logic, without TDC or programmable delay unit, which is suitable for resource-sensitive FPGA / ASIC design.

[0098] Wherein the number of times each bit in each target segment outputs 1 can be realized by a counter, and the number of times the i-th segment is counted, and the bit-by-bit sum of this group of data is obtained, and the counter is 1xR.

[0099] For the convenience of understanding, the starting position and the ending position of each target segment can be determined after the segmentation, and the position of the valid bit (i.e. the position in the multi-stage carry chain, for example, the multi-stage carry chain is 32 bits, which can be any bit in 32 bits) is determined. Thus, the sum of the number of times that the carry output of the bit with the same position in all target segments is 1 can be obtained.

[0100] The above carry chain calibration method obtains a bit output sequence of the carry chain; segments the bit output sequence to obtain a plurality of to-be-processed segments; selects a target segment from the to-be-processed segments and counts the number of times that each bit of the target segment outputs 1; generates a remapping table of the physical bit position and the logical bit index of the carry chain based on the number of times that each bit of each target segment outputs 1, and remaps the bit output sequence of the carry chain to output 1. Thus, the dynamic segmentation frequency statistics of the bit output sequence of the multi-stage carry chain is performed first, and therefore the accuracy of the multi-stage carry chain can be improved, so as to suppress systematic jitter.

[0101] In some optional embodiments, the segmenting the bit output sequence to obtain a plurality of to-be-processed segments comprises: segmenting the bit output sequence based on a segmentation rule and a guard interval rule to obtain a plurality of to-be-processed segments, the segmentation rule comprising that the length of each to-be-processed segment is less than or equal to the duration of 1 or 0 in the current period of the to-be-processed segment, and the guard interval rule comprising that a target length of a guard interval is arranged before and after the to-be-processed segment, and the bits except the guard interval are valid bits of the to-be-processed segment, and the valid bits are used to count the number of times that the carry outputs 1.

[0102] In order to ensure that the to-be-processed segment does not cross two level transitions and only includes one rising edge or one falling edge, the segmentation rule is set in the present application, that is, the length of each to-be-processed segment is less than or equal to the duration of 1 or 0 in the current period of the to-be-processed segment, and the guard interval rule is combined with Figure 3 , wherein one period is 7 bits of high level and 5 bits of low level, and L≤5. Thus, at least one to-be-processed segment has the change of the carry output of the bit from 0 to 1.

[0103] The guard interval rule is to avoid the influence of adjacent to-be-processed segments. Because the first and last bits of each to-be-processed segment are influenced by the previous and subsequent bits, a target length G of a guard interval is arranged before and after each to-be-processed segment, wherein G is greater than or equal to 1, and the guard interval rule is combined with Figure 4 , as shown in Figure 4 , which is a segmentation schematic diagram in an embodiment. The length of each segment is L, the target length, that is, the length of the guard interval is G, and only the middle valid bits are counted subsequently, that is, the bits outside the guard interval length in each segment, wherein the length of the valid bit is .

[0104] In some optional embodiments, the target segment is selected from each of the to-be-processed segments, including: determining that the to-be-processed segment including only rising edges is the target segment; or determining that the to-be-processed segment including only falling edges is the target segment.

[0105] In a high-frequency scenario, there are many cycles, and the high and low levels will jump multiple times. Directly counting the entire segment will violate the aforementioned implicit statistical mathematical basis, so it is necessary to segment each segment to contain only one edge (rising edge or falling edge).

[0106] In some optional embodiments, the target segment is selected from each of the to-be-processed segments, including: determining that the to-be-processed segment including only rising edges is the target segment; or determining that the to-be-processed segment including only falling edges is the target segment.

[0107] In some optional embodiments, the target segment is selected from each of the to-be-processed segments, including: determining that the to-be-processed segment including only rising edges is the target segment; or determining that the to-be-processed segment including only falling edges is the target segment.

[0108] In some optional embodiments, the target segment is selected from each of the to-be-processed segments, including: determining that the to-be-processed segment including only rising edges is the target segment; or determining that the to-be-processed segment including only falling edges is the target segment. In some optional embodiments, the target segment is selected from each of the to-be-processed segments, including: determining that the to-be-processed segment including only rising edges is the target segment; or determining that the to-be-processed segment including only falling edges is the target segment. In some optional embodiments, the target segment is selected from each of the to-be-processed segments, including: determining that the to-be-processed segment including only rising edges is the target segment; or determining that the to-be-processed segment including only falling edges is the target segment. In some optional embodiments, the target segment is selected from each of the to-be-processed segments, including: determining that the to-be-processed segment including only rising edges is the target segment; or determining that the to-be-processed segment including only falling edges is the target segment. In some optional embodiments, the target segment is selected from each of the to-be-processed segments, including: determining that the to-be-processed segment including only rising edges is the target segment; or determining that the to-be-processed segment including only falling edges is the target segment. In some optional embodiments, the target segment is selected from each of the to-be-processed segments, including: determining that the to-be-processed segment including only rising edges is the target segment; or determining that the to-be-processed segment including only falling edges is the target segment.

[0109] In some optional embodiments, the target segment is selected from each of the to-be-processed segments, including: determining that the to-be-processed segment including only rising edges is the target segment; or determining that the to-be-processed segment including only falling edges is the target segment.

[0110] In the above embodiments, since the length L of each segment to be processed is less than or equal to the shorter duration of 1 and 0 in the current period of the segment to be processed, there is at least one segment to be processed that includes only a rising edge or only a falling edge. In this embodiment, based on the position of the bit carry output 0 and 1, the segments to be processed that only include a rising edge are selected as target segments, or the segments to be processed that only include a falling edge are selected as target segments.

[0111] In some optional embodiments, the bit output sequence is segmented to obtain several segments to be processed, including: segmenting the bit output sequence based on an overlap rule to obtain several segments to be processed, wherein the overlap rule is that there are overlapping bits between the effective bits of adjacent segments to be processed; after counting the number of times each bit in each target segment has a carry output of 1, the method further includes: obtaining the difference between the number of times the overlapping bits in adjacent target segments have a carry output of 1; if the difference between the number of times the overlapping bits have a carry output of 1 is not equal, the bit output sequence is re-segmented to obtain several segments to be processed, and the step of filtering target segments from each segment to be processed is continued until the difference between the number of times the overlapping bits have a carry output of 1 is equal.

[0112] The overlap rule is that there are overlapping bits between the effective bits of adjacent segments to be processed, and n bits are reserved between adjacent segments. >n≥2) bit overlap region, used to verify the correctness of segmentation. In order to improve the calibration efficiency, n takes the minimum value of 2. The last 2 bits in the effective length of the i-th segment overlap with the first 2 bits in the effective length of the (i+1)-th segment.

[0113] Combination Figure 4 As shown, it is divided into S segments. , This indicates rounding down, where 2 is the number of overlapping bits in the bit overlap region. In other embodiments, other values ​​can be used; here, only n=2 is used for illustration.

[0114] After all target segments have been statistically analyzed, the entire set of logical bits cannot be directly sorted. This is because although there are M sets of sample carry chains output sequences, the total number of test samples after each segmentation may be different. Therefore, the absolute count values ​​of the same bit in two adjacent target segments will not be equal, and the target segments will be discontinuous. However, in reality, the probability increments of two adjacent bits are equal (slopes are consistent) in different target segments.

[0115] Suppose the number of samples in the first target segment is M1 (M1≤M), the curve of the two overlapping bits and their carry output of "1" is y = k1*x + b1, and the statistical results of the overlapping bits x1 and x2 are y11 = k1*x1 + b1 and y12 = k1*x2 + b1, respectively.

[0116] The number of samples in the second target segment is M2 (M2≤M), the curve of the two overlapping bits and their carry output of "1" is y = k2*x + b2, and the statistical results of the overlapping bits x1 and x2 are y21 = k2*x1 + b2 and y22 = k2*x2 + b2, respectively.

[0117] Specifically, the probability increments of the carry output of "1" of the two overlapping bits in the first target segment and the second target segment are k1 = (y12 - y11) / (x2 - x1) and k2 = (y22 - y21) / (x2 - x1), respectively. Because the probability increments k1 = k2, y12 - y11 = y22 - y21, that is, the difference in the number of times of the carry output of "1" of the two overlapping bits in the first target segment and the second target segment is equal. Similarly, if there are three overlapping bits, the third bit x3 and its adjacent second bit also satisfy y13 - y12 = y23 - y22 in the first target segment and the second target segment, where y13 and y23 represent the number of times of the carry output of "1" of x3 in the first target segment and the second target segment, respectively. Similarly, if there are more overlapping bits, the difference in the carry output of "1" between each pair of adjacent bits in different target segments is equal. Moving the equation y12 - y11 = y22 - y21 gives y12 - y22 = y11 - y21, and moving the equation y13 - y12 = y23 - y22 gives y13 - y23 = y12 - y22. Obviously, y13 - y23 = y12 - y22 = y11 - y21, which has the physical meaning that the difference in the corresponding frequencies of adjacent segment overlapping bits is equal, that is, for adjacent target segments, the difference in the number of times of the carry output of "1" of the first overlapping bit in the two segments should be equal to the difference in the number of times of the carry output of "1" of the second overlapping bit in the two segments. If the number of overlapping bits is greater than or equal to 3, the difference in the number of times of the carry output of "1" of the first overlapping bit in the two segments should be equal to the difference in the number of times of the carry output of "1" of the second overlapping bit in the two segments, and also equal to the difference in the number of times of the carry output of "1" of the third overlapping bit in the two segments, that is, the difference in the number of times of the carry output of "1" of each overlapping bit in the two segments should be equal.

[0118] If the difference of the number of times that the carry output is 1 corresponding to the overlapping bits in at least one target segment is not equal, it is determined that the segment is wrong, and thus the bit output sequence needs to be segmented to obtain a plurality of to-be-processed segments. In some optional embodiments, the bit output sequence is re-segmented to obtain a plurality of to-be-processed segments, including: after reducing the segment length of the to-be-processed segment and / or increasing the guard interval, the bit output sequence is segmented based on the new segment length and / or the new guard interval to obtain a plurality of to-be-processed segments.

[0119] Wherein the segment error represents that the first and last bits of the current segment are still affected by the adjacent segments, and thus the guard interval G needs to be increased and / or the segment length L of the to-be-processed segment needs to be reduced to reduce the influence of the adjacent segments.

[0120] Wherein, still taking Figure 3 For example, assuming that L=5, G=1, n=2, taking waveform 1 as the bit output sequence, the first to-be-processed segment is 00001, the second to-be-processed segment is 00011, the third to-be-processed segment is 00111, the fourth to-be-processed segment is 01111, the fifth to-be-processed segment is 11111, the sixth to-be-processed segment is 11111, and the like, 32 to-be-processed segments can be obtained by analogy, and the target segment can be obtained by screening. Taking waveform 2 as the bit output sequence, the first to-be-processed segment is 00011, the second to-be-processed segment is 00111, the third to-be-processed segment is 01111, the fourth to-be-processed segment is 11111, the fifth to-be-processed segment is 11111, the sixth to-be-processed segment is 11111, and the like, 32 to-be-processed segments can be obtained by analogy.

[0121] Based on the selected target segment, the number of times that the carry output is 1 for each bit of the effective bit is counted. Assuming that only 12 to-be-processed segments obtained from waveform 1 to waveform 3 (more to-be-processed segments can be included in other embodiments, and this embodiment is only for illustration) are obtained, the positions corresponding to the two first segments are the same, and thus the number of times that the carry output is 1 for each effective bit can be counted: the number of times that the carry output is 1 for the second bit is 0, the number of times that the carry output is 1 for the third bit is 0, and the number of times that the carry output is 1 for the fourth bit is 1. The positions corresponding to the two second segments are the same, and thus the number of times that the carry output is 1 for each bit can be counted, and the number of times that the effective bit appears is counted: the number of times that the carry output is 1 for the third bit is 0, the number of times that the carry output is 1 for the fourth bit is 0, and the number of times that the carry output is 1 for the fifth bit is 2.

[0122] The target segments adjacent in position have overlapping bits in the valid bits due to the overlapping rule, and the number of times that the carry output of each target segment is 1 is counted, and the difference between the number of times that the carry output of the first overlapping bit of the two segments is 1 should be equal to the difference between the number of times that the carry output of the second overlapping bit of the two segments is 1. For example, the valid overlapping bits in the first to-be-processed segment and the second to-be-processed segment are the third bit and the fourth bit, and the difference between the number of times that the carry output of the third bit of the two segments is 1 should be equal to the difference between the number of times that the carry output of the fourth bit of the two segments is 1, but the above-mentioned is not equal, and therefore G and / or L need to be adjusted.

[0123] In the above embodiment, the accuracy of the segment is verified by the overlapping bits between the two adjacent ends, and the statistical error introduced by the level jump is eliminated.

[0124] In some optional embodiments, the bit output sequence of the carry chain is remapped based on the number of times that the carry output of each bit in each target segment is 1, including: correcting the number of times that the carry output of the valid bit after the overlapping bit in the latter target segment of the adjacent target segments is 1 based on the difference between the number of times that the carry output of the overlapping bit corresponding to the adjacent target segments is 1; and remapping the bit output sequence of the carry chain based on the corrected number of times that the carry output of each bit in each target segment is 1.

[0125] In the above embodiment, the accuracy of the segment is verified by the overlapping bits between the two adjacent ends, and the statistical error introduced by the level jump is eliminated.

[0126] In some optional embodiments, the bit output sequence of the carry chain is remapped based on the number of times that the carry output of each bit in each target segment is 1, including: correcting the number of times that the carry output of the valid bit after the overlapping bit in the latter target segment of the adjacent target segments is 1 based on the difference between the number of times that the carry output of the overlapping bit corresponding to the adjacent target segments is 1; and remapping the bit output sequence of the carry chain based on the corrected number of times that the carry output of each bit in each target segment is 1. Figure 5 As shown in the figure, Figure 5 is a flowchart of the additive splicing step in one embodiment, wherein the additive splicing step is mainly to compensate for the absolute value difference of the statistical frequency caused by the different total test sample quantities (M1≠M2) of the different target segments after screening, that is, the intercepts need to be equal, so the compensation difference Δ=b1-b2 of the second segment is compensated, that is, y21+Δ=y21+b1-b2=y11, and y22+Δ=y12 by analogy. Specifically, in this embodiment, the additive splicing step, that is, correcting the number of times that the carry output of the valid bit after the overlapping bit in the latter target segment of the adjacent target segments is 1 based on the difference between the number of times that the carry output of the overlapping bit corresponding to the adjacent target segments is 1, includes:

[0127] S502: Starting from the first target segment, calculate the difference between the number of times that the carry output of the overlapping bit in the adjacent target segments is 1.

[0128] During the segmentation process, the changing selection conditions for each segment cause the objective probability "absolute value" to become a "relative value," resulting in a difference in the frequency of identical bits appearing in two segments. Therefore, the probability of the first target segment is used as a benchmark to compensate for the "relative values" of all other target segments. Here, the relative value is the difference in the number of times overlapping bits in adjacent target segments output 1. The core of multi-segment additive concatenation is to normalize all "probability" calculations to a single standard; in this application, the probability of the first target segment is chosen as the benchmark.

[0129] Here, we assume that the frequencies of the overlapping bits at the end of the i-th target segment counter are respectively and The frequencies of the overlapping bits at the beginning of the (i+1)th target segment are respectively and And satisfy , here This is the difference in the number of times the overlapping bit carry outputs 1 in adjacent target segments.

[0130] S504: Add the difference to the number of times the carry output of the effective bits after the overlapping bits in the next target segment is 1, to obtain the corrected number of times the carry output of the effective bits after the overlapping bits is 1, until all target segments have been processed.

[0131] The number of times the carry output of the effective bit region after the first overlapping bit of the (i+1)th target segment is 1 is uniformly added. And update the global counter with the result. The count corresponding to the bit position is denoted as the i-th update.

[0132]

[0133] This represents the effective bits following the overlapping bits at the beginning of the (i+1)th target segment. express Compared with the i-th update The difference in the number of times the overlapping bit carry outputs 1 is used to update the final global counter segment by segment.

[0134] In the above embodiments, the difference in the number of times the carry output is 1 in the overlapping area of ​​adjacent segments is used for correction, and the segmented statistical results are concatenated into a global frequency table to ensure the consistency of the delay distribution of multi-level carry chains. The layout parameters are dynamically adjusted according to the frequency sorting to suppress systematic jitter.

[0135] In some optional embodiments, the method for generating the remapping table of the physical bit position and the logical bit index based on the number of times that the modified carry output of each bit in each target segment is 1, and remapping the bit output sequence of the carry chain, comprises: sorting the bits in order from low to high or from high to low based on the number of times that the modified carry output of each bit in each target segment is 1; and remapping the bit output sequence of the carry chain based on the sorted bits.

[0136] In the global modification of the number of times that the carry output of each bit in the counter is 1, the number of times that the carry output is 1 can be sorted from high to low or from low to high, and after the count value is sorted from low to high, the corresponding mapping order is from LSB->MSB; and after the count value is sorted from high to low, the corresponding mapping order is from MSB->LSB.

[0137] For the convenience of understanding, in combination with Figure 6 shown, Figure 6 is a waveform for the sorting of each bit in the output bit sequence 0-64, Figure 7 is a schematic diagram of the positions of each bit in the embodiment shown, Figure 6 Assuming that after remapping, the number of times that the carry output of the 5th bit is 1 is less than the number of times that the carry output of the 7th bit is 1, the number of times that the carry output of the 7th bit is 1 is less than the number of times that the carry output of the 3rd bit is 1, the number of times that the carry output of the 3rd bit is 1 is less than the number of times that the carry output of the 4th bit is 1, and the number of times that the carry output of the 4th bit is 1 is less than the number of times that the carry output of the 6th bit is 1, so the order of the bits from low to high after remapping is the 5th bit, the 7th bit, the 3rd bit, the 4th bit, and the 6th bit, and the processing of the 19th to 21st bits is similar and will not be described here.

[0138] For the convenience of understanding, in combination with Figure 8 shown, Figure 8 is a flowchart of the carry chain calibration method in another embodiment, in which a periodic square wave signal is first input to a multi-stage carry chain, and M groups of R bit output sequences are collected.

[0139] Then, each bit output sequence is segmented based on the segmentation rule and the guard interval rule to obtain a plurality of to-be-processed segments.

[0140] The plurality of to-be-processed segments are screened to obtain a plurality of target segments.

[0141] The number of times that each bit in the target segments with the same position outputs the carry 1 is counted, and the segmentation result is verified based on the fact that the difference in the number of times that each overlapping bit in the adjacent target segments outputs the carry 1 in the two target segments should be the same.

[0142] If the test is successful, then the additive splicing is performed to update the number of times each bit position output is 1 in the counter, and finally the sorting is performed based on the number of times each bit position output is 1, and the remapping is performed based on the sorted bit.

[0143] For the convenience of understanding, combined with Figure 9 , as shown in Figure 9 , it is a schematic diagram of the length and number of bubbles contained in each bit position of 98-stage CARRY8 carry chain 65536 groups of random carry output before segmented calibration, Figure 10 , it is a schematic diagram of the length and number of bubbles contained in each bit position of 65536 groups of random carry output of the carry chain after segmented calibration, wherein the bubble is an indicator of the jitter of the rising edge of the period, the deeper the color, the more bubbles, the more unstable the transition at the rising edge of the period, the longer the time represents the longer the time of the unstable rising edge, and the TMU is calculated based on this. Inaccuracy. It can be seen that the length and number of bubbles are significantly reduced after calibration, and the instability of the carry chain output can be greatly improved.

[0144] In the above embodiments, by inputting a periodic signal and capturing multiple groups of bit sequences, the method of segmenting and counting 1 frequency is used to quantify the propagation delay difference of each bit position, and the statistical error introduced by level transition is eliminated by combining with overlapping bit verification (verifying the validity of the segment). The difference between the frequency values in the overlapping area of adjacent segments is used for correction, and the segmented statistical results are spliced into a global frequency table to ensure the consistency of the time delay distribution of the multi-stage carry chain. According to the frequency sorting, the layout parameters are dynamically adjusted to suppress systematic jitter. The calibration process is completely realized by digital logic, without the need for TDC or programmable delay unit, and is suitable for resource-sensitive FPGA / ASIC design.

[0145] It should be understood that although each step in the flowchart involved in each of the above embodiments is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise stated herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in each of the above embodiments can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and various non-contradictory schemes formed by combination are within the scope of protection of the present application.

[0146] Based on the same inventive concept, the embodiments of the present application also provide a carry chain calibration device for implementing the above-mentioned carry chain calibration method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, and therefore the specific limitations in one or more carry chain calibration device embodiments provided below can refer to the limitations of the carry chain calibration method described above, which will not be described here again.

[0147] In one exemplary embodiment, as shown in Figure 11 a carry chain calibration device is provided, comprising: an acquisition module 1001, a segmentation module 1002, a frequency statistics module 1003, and a remapping calibration module 1004, wherein:

[0148] The acquisition module 1001 is configured to acquire each bit output sequence of the carry chain.

[0149] The segmentation module 1002 is configured to segment each bit output sequence to obtain a plurality of to-be-processed segments.

[0150] The frequency statistics module 1003 is configured to filter each target segment from each to-be-processed segment, and count the number of times that each bit outputs 1 in each target segment.

[0151] The remapping calibration module 1004 is configured to generate a remapping table of the physical bit position and the logical bit index of the carry chain based on the number of times that each bit outputs 1 in each target segment, and to remap the bit output sequence of the carry chain.

[0152] In some optional embodiments, the probability of the bit outputting 1 monotonically increases from the least significant bit to the most significant bit, or the probability of the bit outputting 1 monotonically decreases from the most significant bit to the least significant bit.

[0153] In some optional embodiments, the segmentation module 1002 specifically segments according to any of the following manners: or segments each bit output sequence according to a segmentation rule and a guard interval rule to obtain a plurality of to-be-processed segments, the segmentation rule comprises that the length of each to-be-processed segment is less than or equal to the duration of 1 or 0 that is shorter in the current period of the to-be-processed segment, and the guard interval rule is to set a target length of the guard interval before and after the to-be-processed segment, and the bits except the guard interval are effective bits of the to-be-processed segment, and the effective bits are used to count the number of times that the carry outputs 1.

[0154] In some optional embodiments, the frequency statistics module 1003 is specifically configured to determine that the to-be-processed segment including only rising edges is a target segment; or determine that the to-be-processed segment including only falling edges is a target segment.

[0155] In some optional embodiments, the segmentation module 1002 is specifically configured to segment the bit output sequence to obtain a plurality of to-be-processed segments based on an overlap rule, where the overlap rule is that there are overlapping bits between valid bits of adjacent to-be-processed segments.

[0156] The apparatus further includes a checking module configured to obtain a difference between the number of times that the carry output of the overlapping bits is 1 in adjacent target segments; in a case where the difference between the number of times that the carry output of the overlapping bits is 1 is not equal, re-segmenting the bit output sequence to obtain a plurality of to-be-processed segments, and continuing to perform the step of screening target segments from the to-be-processed segments until the difference between the number of times that the carry output of the overlapping bits is 1 is equal.

[0157] In some optional embodiments, the segmentation module 1002 is specifically configured to, after reducing the segmentation length of the to-be-processed segments and / or increasing the guard interval, segment the bit output sequence to obtain a plurality of to-be-processed segments based on the new segmentation length and / or the new guard interval.

[0158] In some optional embodiments, the remapping calibration module 1004 is specifically configured to, based on the difference between the number of times that the carry output of the overlapping bits is 1 in adjacent target segments, correct the number of times that the carry output of the valid bits after the overlapping bits in a latter target segment is 1; generate a remapping table of the physical bit position and the logical bit index of the carry chain based on the corrected number of times that the carry output of each bit in each target segment is 1, and remap the bit output sequence of the carry chain.

[0159] In some optional embodiments, the remapping calibration module 1004 is specifically configured to, starting from the first target segment, calculate the difference between the number of times that the carry output of the overlapping bits is 1 in adjacent target segments; add the number of times that the carry output of the valid bits after the overlapping bits in a latter target segment is 1 to the difference to obtain the corrected number of times that the carry output of the valid bits after the overlapping bits is 1, until each target segment is processed.

[0160] In some optional embodiments, the remapping calibration module 1004 is specifically configured to, based on the corrected number of times that the carry output of each bit in each target segment is 1, sequentially sort the bits in a low-to-high order or a high-to-low order; and remap the bit output sequence of the carry chain based on the sorted bits.

[0161] The modules in the above-described carry chain calibration apparatus can be implemented in whole or in part by software, hardware, or a combination thereof. The modules can be embedded in or independent of a processor in a computer device in hardware form, or stored in a memory in the computer device in software form, so as to be invoked by the processor to perform the operations corresponding to the modules.

[0162] In an exemplary embodiment, a computer device, which can be a terminal, is provided, and an internal structure diagram of the computer device can be as shown in Figure 12 The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to perform wired or wireless communication with external terminals, and the wireless communication can be implemented through WIFI, mobile cellular network, near field communication (NFC), or other technologies. The computer program is executed by the processor to implement a carry chain calibration method. The display unit of the computer device is configured to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer overlaid on the display screen, or a key, a trackball, or a touchpad arranged on the shell of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0163] Those skilled in the art can understand that Figure 12 The structure shown in the above

[0164] In an embodiment, a computer device is also provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0165] In an embodiment, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the steps of the above method embodiments.

[0166] In an embodiment, a computer program product is provided, which includes a computer program. The computer program is executed by a processor to implement the steps of the above method embodiments.

[0167] A person of ordinary skill in the art can understand that all or part of the processes in the above method embodiments can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, the computer program can include the processes of the above method embodiments. In each embodiment provided in the present application, any reference to a memory, a database or other medium can include at least one of a non-volatile memory and a volatile memory. The non-volatile memory can include a read-only memory (ROM), a magnetic tape, a floppy disk, a flash memory, an optical storage, a high-density embedded non-volatile memory, a resistive random access memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a graphene memory, etc. The volatile memory can include a random access memory (RAM) or an external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), etc. The database involved in each embodiment provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., and is not limited thereto. The processor involved in each embodiment provided in the present application can be a general processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., and is not limited thereto.

[0168] Any technical features in the above embodiments can be combined, and for the sake of brevity, not all possible combinations are described above, however, any combination of these technical features is deemed to be within the scope of the present application.

[0169] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A carry chain calibration method, characterized in that, The method includes: Obtain the output sequence of each bit in the carry chain; Each bit output sequence is segmented to obtain several segments to be processed; Each target segment is selected from each segment to be processed, and the number of times each bit in each target segment has a carry output of 1 is counted. Based on the number of times each bit in each target segment has a carry output of 1, a remapping table is generated between the physical bit position and the logical bit index of the carry chain, and the bit output sequence of the carry chain is remapped.

2. The method according to claim 1, characterized in that, The probability of the bit carry output being 1 increases monotonically with the logic bit index from the least significant bit to the most significant bit, or the probability of the bit carry output being 1 decreases monotonically with the logic bit index from the most significant bit to the least significant bit.

3. The method according to claim 1, characterized in that, The segmentation of each bit output sequence to obtain several segments to be processed includes: Based on segmentation rules and guard interval rules, each bit output sequence is segmented to obtain several segments to be processed. The segmentation rules include that the length of each segment to be processed is less than or equal to the shorter duration of 1 and 0 in the current period of the segment to be processed. The guard interval rule is to set a guard interval of target length before and after the segment to be processed, and the bits outside the guard interval are the valid bits of the segment to be processed. The valid bits are used to count the number of times the carry output is 1.

4. The method according to claim 1, characterized in that, The step of filtering the target segment from each of the segments to be processed includes: The segment to be processed, consisting only of rising edges, is identified as the target segment; or The segment to be processed, which includes only the rising edge, is identified as the target segment.

5. The method according to any one of claims 1 to 4, characterized in that, The segmentation of each bit output sequence to obtain several segments to be processed includes: The bit output sequences are segmented based on the overlap rule to obtain several segments to be processed, wherein the overlap rule is that there are overlapping bits between the effective bits of adjacent segments to be processed. After counting the number of times each bit carries out as 1 in each of the target segments, the method further includes: Obtain the difference in the number of times the overlapping bit in adjacent target segments has a carry output of 1; If the differences in the number of times the carry output is 1 corresponding to each of the overlapping bits are not equal, the bit output sequence is re-segmented to obtain several segments to be processed, and the step of filtering the target segment from each segment to be processed continues until the differences in the number of times the carry output is 1 corresponding to each of the overlapping bits are equal.

6. The method according to claim 5, characterized in that, The process of re-segmenting each bit output sequence to obtain several segments to be processed includes: After reducing the segment length of the segment to be processed and / or increasing the guard interval, the bit output sequence is segmented based on the new segment length and / or the new guard interval to obtain several segments to be processed.

7. The method according to any one of claims 1 to 4, characterized in that, The step of generating a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times each bit in each target segment has a carry output of 1, and remapping the bit output sequence of the carry chain, includes: Based on the difference in the number of times the carry output is 1 for the overlapping bits of the adjacent target segments, the number of times the carry output is 1 for the effective bits after the overlapping bits in the next target segment is corrected. Based on the number of times the corrected carry output of each bit in each target segment is 1, a remapping table of the physical bit position and logical bit index of the carry chain is generated, and the bit output sequence of the carry chain is remapped.

8. The method according to claim 7, characterized in that, The correction of the number of carry-outs of valid bits following the overlapping bits in the next target segment being 1, based on the difference in the number of carry-outs of overlapping bits in adjacent target segments, includes: Starting from the first target segment, calculate the difference in the number of times the carry output of the overlapping bits in adjacent target segments is 1; The number of times the carry-out of the effective bits after the overlapping bits in the next target segment is 1 is added to the difference to obtain the corrected number of times the effective bits after the overlapping bits are 1, until all target segments have been processed.

9. The method according to claim 7, characterized in that, The step of generating a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times the corrected carry output of each bit in each target segment is 1, and remapping the bit output sequence of the carry chain, includes: Based on the number of times the corrected carry output of each bit in each target segment is 1, the bits are sorted in order from low to high or from high to low to generate a remapping table of physical bit positions and logical bit indices of the carry chain. The bit output sequence of the carry chain is remapped based on the remapping table.

10. A carry chain calibration device, characterized in that, The device includes: The acquisition module is used to acquire the output sequence of each bit in the carry chain; The segmentation module is used to segment each bit output sequence to obtain several segments to be processed. The frequency statistics module is used to filter each target segment from each segment to be processed, and to count the number of times the carry output of each bit in each target segment is 1. The remapping calibration module is used to generate a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times the carry output of each bit in each target segment is 1, and to remap the bit output sequence of the carry chain.

11. A time measurement unit, characterized in that, Includes a carry chain, performing the steps of the method as described in any one of claims 1 to 9.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 9.

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