Circuit board tin leakage detection method, device and equipment and storage medium

Abstract

The invention provides a circuit board tin leakage detection method and device, equipment and a storage medium. The method comprises the steps that to-be-detected holes in a circuit board are classified into at least two types of detection objects based on electrical attribute parameters; expanding a preset distance by taking the geometric boundary of the to-be-detected hole as a reference to form a detection area, and screening target detection elements in the detection area; based on the detection object type to which the to-be-detected hole belongs, obtaining interlayer structure association features between the to-be-detected hole and the target detection element; and determining whether the to-be-detected hole has a tin leakage risk or not based on the interlayer structure association features and a preset rule. According to the scheme, differentiated accurate detection of different types of holes is realized, the detection efficiency can be improved, quantitative analysis can be carried out, the risk judgment accuracy can be improved, the manual reinspection cost is reduced, the manufacturing yield is optimized from the design source, and thus a standardized and parameterized tin leakage risk control scheme is provided for PCB manufacturing.

Description

Technical Field

[0001] This disclosure relates to the field of circuit board testing technology, and in particular to a method, apparatus, equipment and storage medium for detecting solder leakage on circuit boards. Background Technology

[0002] As electronic devices rapidly evolve towards miniaturization, high performance, and intelligence, the board-level circuit design of printed circuit boards (PCBs) is becoming increasingly complex, placing higher demands on the placement and routing capabilities of layout engineers. In PCB design, not only do the actual soldering areas where component pads are located need to have solder mask windows, but sometimes, based on structural assembly requirements, such as attaching conductive cloth, solder mask windows also need to be opened in specific areas of the board surface.

[0003] However, if a hole, such as a positioning hole or a via, is drilled through an area with solder mask windows on both sides, there is a risk that the solder paste used for soldering may leak through the hole during the surface mount technology (SMT) process.

[0004] Currently, in the PCB design process, layout engineers need to check each drill hole with this risk in all solder mask areas, which is not only inefficient but also carries the risk of missing some. Summary of the Invention

[0005] This disclosure provides a method, apparatus, device, and storage medium for detecting solder leakage on circuit boards, thereby at least solving the above-mentioned technical problems existing in the prior art.

[0006] According to a first aspect of this disclosure, a method for detecting solder leakage on a circuit board is provided, the method comprising:

[0007] Based on electrical property parameters, the holes to be inspected on the circuit board are classified into at least two types of inspection objects;

[0008] A detection area is formed by extending a preset distance based on the geometric boundary of the hole to be detected, and target detection elements within the detection area are screened.

[0009] Based on the detection object type to which the hole to be detected belongs, obtain the interlayer structure association features between the hole to be detected and the target detection element;

[0010] Based on the interlayer structure correlation features and preset rules, it is determined whether the hole to be tested has a risk of solder leakage.

[0011] In one possible implementation, the detection object includes a first type of hole and a second type of hole; wherein,

[0012] The first type of hole includes through holes where the test point attribute is empty;

[0013] The second type of hole includes a test point through hole with test point attributes set to preset values. The preset values ​​include a first preset value representing the top-level test point and a second preset value representing the bottom-level test point.

[0014] In one possible implementation, the step of extending a preset distance based on the geometric boundary of the hole to be detected to form a detection area, and filtering target detection elements within the detection area, includes:

[0015] Obtain the geometric boundary parameters of the hole to be detected;

[0016] A detection area is formed by extending a preset distance based on the geometric boundary parameters;

[0017] Based on preset element type conditions, elements that meet the preset element type conditions are selected as target detection elements within the detection area.

[0018] In one possible implementation, the hole to be detected is a first type of hole; based on the detection object type to which the hole to be detected belongs, the interlayer structural association features between the hole to be detected and the target detection element are obtained, including:

[0019] Determine whether the first dielectric layer and the second dielectric layer have vertical overlap in the axial extension direction of the hole to be tested;

[0020] If the vertical overlap exists, the distance between the hole to be detected and the target detection element is determined as the interlayer structure association feature.

[0021] In one possible implementation, the hole to be detected is a second type of hole; based on the detection object type to which the hole to be detected belongs, corresponding interlayer structure association detection is performed on the target detection element to obtain interlayer structure association features, including:

[0022] Determine whether a preset dielectric layer structure exists within a preset spatial region of the detection layer of the hole to be detected;

[0023] If the preset medium layer structure exists, the distance between the hole to be detected and the target detection element is determined as the interlayer structure association feature.

[0024] In one possible implementation, determining whether the via to be tested has a risk of solder leakage based on the interlayer structure correlation features and preset rules includes:

[0025] If the distance between the hole to be tested and the target detection element is less than a preset threshold, it is determined that the hole to be tested has a risk of solder leakage.

[0026] In one possible implementation, the method further includes:

[0027] All holes with potential solder leakage are mapped to the 3D model of the circuit board and marked visually.

[0028] According to a second aspect of this disclosure, a circuit board solder leakage detection device is provided, the device comprising:

[0029] A classification module is used to classify holes to be inspected on a circuit board into at least two categories of inspection objects based on electrical property parameters.

[0030] The filtering module is used to expand a detection area by a preset distance based on the geometric boundary of the hole to be detected, and to filter the target detection elements within the detection area.

[0031] The detection module is used to obtain the interlayer structural association features between the hole to be detected and the target detection element based on the detection object type to which the hole to be detected belongs;

[0032] The determination module is used to determine whether the hole to be tested has a risk of solder leakage based on the interlayer structure correlation characteristics and preset rules.

[0033] According to a third aspect of this disclosure, an electronic device is provided, comprising:

[0034] At least one processor; and

[0035] A memory communicatively connected to the at least one processor; wherein,

[0036] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the methods described in this disclosure.

[0037] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this disclosure.

[0038] The circuit board solder leakage detection method, apparatus, equipment, and storage medium disclosed herein first classify the holes to be inspected on the circuit board into at least two types of inspection objects based on electrical property parameters; then, a detection area is formed by extending a preset distance based on the geometric boundary of the hole to be inspected, and target inspection elements within the detection area are screened; next, based on the type of inspection object to which the hole to be inspected belongs, the interlayer structural correlation characteristics between the hole to be inspected and the target inspection elements are obtained; finally, based on the interlayer structural correlation characteristics and preset rules, it is determined whether the hole to be inspected has a solder leakage risk. This solution achieves differentiated and accurate detection of different types of holes, which can not only improve detection efficiency, but also improve the accuracy of risk judgment through quantitative analysis, reduce the cost of manual re-inspection, optimize manufacturing yield from the design source, and thus provide a standardized and parameterized solder leakage risk control solution for PCB manufacturing.

[0039] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0040] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which:

[0041] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0042] Figure 1 A schematic flowchart of a solder leakage detection method according to an embodiment of the present disclosure is shown;

[0043] Figure 2 A flowchart illustrating another method for detecting solder leakage according to an embodiment of this disclosure is shown;

[0044] Figure 3 A schematic diagram of a solder leakage monitoring device according to an embodiment of the present disclosure is shown;

[0045] Figure 4 A schematic diagram of the structure of another solder leakage monitoring device according to an embodiment of the present disclosure is shown;

[0046] Figure 5 A schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0047] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0048] In printed circuit board (PCB) manufacturing, reliable soldering of vias is crucial for ensuring electrical connectivity and long-term mechanical stability. However, solder leakage is a common process defect that significantly weakens the via's current-carrying capacity, reduces mechanical strength, accelerates thermal fatigue failure, and may lead to open circuits, abnormally high impedance, or even board-wide failure during subsequent assembly or use, posing a serious threat to high-reliability applications. Currently, it is difficult to predict potential solder leakage risks caused by improper copper foil distribution around the via, interlayer heat dissipation structures, or solder mask design during the design phase, resulting in delayed problem detection and increased rework or even scrap costs. In related technologies, manually inspecting vias for solder leakage risks is not only inefficient but also carries the risk of missing some. Therefore, there is an urgent need for a method that can intelligently predict solder leakage risks based on the physical structural characteristics of the PCB in the early stages of design or manufacturing, thereby improving process reliability and product yield from the source.

[0049] like Figure 1 This is a schematic diagram of a circuit board solder leakage detection method provided in this disclosure, the method comprising:

[0050] S1. Based on electrical property parameters, classify the holes to be tested on the circuit board into at least two types of test objects.

[0051] Electrical attribute parameters include test point attributes, network connection attributes, and physical parameters. Test point attributes record whether a hole is used as a test point and its location, such as "ETCH / TOP" for top-level test points, "ETCH / BOTTOM" for bottom-level test points, or blank values ​​for ordinary through holes. Network connection attributes identify the electrical network to which the hole belongs, such as power, ground, and signal networks, and also identify the signal type of the hole, such as high-speed differential signals or analog signals. Physical parameters include geometric parameters such as diameter, hole depth, and hole wall copper thickness. The complete attribute set of the hole to be tested is read using Electronic Design Automation (EDA) tools, such as Allegro, to obtain the above-mentioned electrical attribute parameters of the hole to be tested.

[0052] In one example, the detection object includes a first type of hole and a second type of hole; wherein,

[0053] The first type of hole includes through holes where the test point attribute is empty;

[0054] The second type of hole includes a test point through hole with test point attributes set to preset values. The preset values ​​include a first preset value representing the top-level test point and a second preset value representing the bottom-level test point.

[0055] Based on preset logic, the holes to be inspected are divided into different types of inspection objects. For example, the first type of hole is a normal through hole with an empty test point attribute, which mainly detects axial interlayer structural risks, such as interlayer short circuits. The second type of hole is a test point through hole with a test point attribute of "ETCH / TOP" or "ETCH / BOTTOM", which detects the risk of dielectric layer coverage on the corresponding surface layer, such as missing solder mask layer.

[0056] In one example, new classification criteria can be added through the configuration file, such as classifying the holes to be detected into different types of detection objects based on aperture size, network type, etc.

[0057] S2. Extend a preset distance based on the geometric boundary of the hole to be detected to form a detection area, and filter the target detection elements within the detection area.

[0058] To obtain the geometric boundary coordinates of the hole to be inspected, you can extend the outer boundary of the hole to be inspected outward by a preset distance, such as 1 mil. The area between the outer boundary of the hole to be inspected and the extended area is the inspection area.

[0059] The screening process involves identifying target detection elements within the detection area. These elements are key conductive structures spatially related to the holes to be inspected on the circuit board, and their state, position, and shape directly affect the risk of solder leakage. In one example, target detection elements include conductive vias, pads, lines, and shapes. Conductive vias include different types such as blind vias, buried vias, and through-holes; pads include component pads, test point pads, and heat dissipation pads; lines include copper conductors on the circuit board, categorized by width and spacing; and shape elements include polygonal shapes such as copper areas (e.g., ground planes) and isolation areas.

[0060] S3. Based on the detection object type to which the hole to be detected belongs, obtain the interlayer structure association features between the hole to be detected and the target detection element.

[0061] Based on the type of the via to be inspected, such as Type I or Type II vias, the interlayer structure correlation features that can quantitatively characterize solder leakage risk are extracted by analyzing the relative positional relationship, geometric shape, and interlayer dielectric distribution of the via and target inspection elements (conductive vias, pads, circuits, patterns) in three-dimensional space. This step achieves differentiated risk feature extraction for different via structures through a typified inspection strategy, providing a quantitative basis for subsequent solder leakage risk assessment.

[0062] S4. Based on the interlayer structure correlation features and preset rules, determine whether the hole to be tested has a risk of solder leakage.

[0063] Based on the interlayer structure correlation features between the hole to be detected and the target detection element, the features are matched and compared with the pre-set judgment rules. The feature parameters are comprehensively evaluated through threshold comparison, logical combination or algorithm analysis to determine whether there is a risk of solder leakage in the hole to be detected. Furthermore, the corresponding risk level result can be output.

[0064] In the above scheme, the holes to be inspected on the circuit board are first classified into at least two types of inspection objects based on electrical property parameters. Then, a detection area is formed by extending a preset distance based on the geometric boundary of the hole to be inspected, and target inspection elements within the detection area are screened. Next, based on the type of inspection object to which the hole to be inspected belongs, the interlayer structure correlation characteristics between the hole to be inspected and the target inspection elements are obtained. Finally, based on the interlayer structure correlation characteristics and preset rules, it is determined whether the hole to be inspected has a risk of solder leakage. This scheme achieves differentiated and accurate inspection of different types of holes, which can not only improve inspection efficiency, but also improve the accuracy of risk judgment through quantitative analysis, reduce the cost of manual re-inspection, optimize manufacturing yield from the design source, and thus provide a standardized and parameterized solder leakage risk control solution for PCB manufacturing.

[0065] In one example, the step of extending a preset distance based on the geometric boundary of the hole to be detected to form a detection area, and filtering target detection elements within the detection area, includes:

[0066] Obtain the geometric boundary parameters of the hole to be detected;

[0067] A detection area is formed by extending a preset distance based on the geometric boundary parameters;

[0068] Based on preset element type conditions, elements that meet the preset element type conditions are selected as target detection elements within the detection area.

[0069] The process involves acquiring geometric boundary parameters such as the center point coordinates, diameter, and axial depth of the hole to be inspected. For example, the bBOX (Bounding Box) of the hole can be obtained. The bBOX refers to the smallest spatial bounding box generated around the geometry of the hole, used to quickly define the physical extent of the hole structure in three-dimensional space. Then, using the outer boundary of the hole as a reference, a preset distance is extended outward to form the inspection area. Finally, within this area, elements that meet the preset element type conditions, such as conductive vias, pads, circuits, and graphics, are selected as target inspection elements.

[0070] In one example, the hole to be detected is a first type of hole; based on the detection object type to which the hole to be detected belongs, the interlayer structural association features between the hole to be detected and the target detection element are obtained, including:

[0071] Determine whether the first dielectric layer and the second dielectric layer have vertical overlap in the axial extension direction of the hole to be tested;

[0072] If the vertical overlap exists, the distance between the hole to be detected and the target detection element is determined as the interlayer structure association feature.

[0073] When the hole to be inspected is a type 1 hole, the first step is to determine whether the first dielectric layer and the second dielectric layer of the circuit board have perpendicular overlap in the axial extension direction of the hole to be inspected. Here, the first dielectric layer and the second dielectric layer refer to structural layers in the circuit board that provide isolation and protection, such as a stencil layer and a solder mask layer. The stencil layer is a metal template layer used to precisely distribute solder paste during soldering; the solder mask layer is an insulating coating covering the surface of the circuit board, used to define the solder area and prevent short circuits.

[0074] For example, the first dielectric layer can be the top solder mask layer to prevent solder from adhering to non-soldering areas, and the second dielectric layer can be the bottom stencil layer. Alternatively, the first dielectric layer can be the bottom stencil layer, and the second dielectric layer can be the top solder mask layer. The vertical overlap relationship is determined by calculating whether the projections of the two dielectric layers onto the hole axis overlap. If the projections of the two dielectric layers onto the hole axis intersect, vertical overlap is considered to exist. If vertical overlap exists, the distance between the boundary of the hole to be inspected and the boundaries of target inspection elements such as conductive vias, pads, lines, and graphics within the inspection area is further measured. For example, the axlAirGap function of Allegro tools can be used to obtain the distance between the boundary of the hole to be inspected and the boundary of the target inspection element. These distance parameters are extracted as interlayer structure correlation features for subsequent analysis of the solder leakage risk of the hole to be inspected. This is because when the dielectric layers exhibit abnormal vertical overlap, and the hole to be inspected is too close to the surrounding target inspection elements, the molten solder is more likely to break through the constraints of the dielectric layer during the soldering process, leading to solder leakage.

[0075] In one example, the hole to be detected is a second type of hole; based on the detection object type to which the hole to be detected belongs, the corresponding inter-layer structure association detection is performed on the target detection element to obtain inter-layer structure association features, including:

[0076] Determine whether a preset dielectric layer structure exists within a preset spatial region of the detection layer of the hole to be detected;

[0077] If the preset medium layer structure exists, the distance between the hole to be detected and the target detection element is determined as the interlayer structure association feature.

[0078] When the hole to be inspected is a Type II hole, it is necessary to determine whether a preset dielectric layer structure, such as a solder mask or stencil layer, exists within the preset space area of ​​its inspection layer. Here, the inspection layer refers to the top or bottom layer where the hole to be inspected is located, the preset space area is a three-dimensional range extending outwards from the hole, and the preset dielectric layer structure is a process layer directly related to the risk of solder leakage. For example, the preset dielectric layer of the top inspection layer can be a stencil layer, and the bottom inspection layer can be a solder mask. During specific inspection, the distribution of dielectric layers within the preset space area is scanned to determine whether a dielectric layer structure conforming to process standards exists. For example, if the top inspection layer of the hole to be inspected is a solder mask, it is necessary to determine whether the bottom layer is a stencil layer; if the top inspection layer of the hole to be inspected is a stencil layer, it is necessary to determine whether the bottom layer is a solder mask. If such a structure exists, the distance between the boundary of the hole to be inspected and the boundaries of target inspection elements such as conductive vias, pads, circuits, and patterns is further calculated. These distance parameters, together with the existence of the dielectric layer structure, constitute the interlayer structure correlation characteristics.

[0079] In one example, determining whether the via to be detected has a risk of solder leakage based on the interlayer structure correlation features and preset rules includes:

[0080] If the distance between the hole to be tested and the target detection element is less than a preset threshold, it is determined that the hole to be tested has a risk of solder leakage.

[0081] Based on the acquired interlayer structure correlation features and preset rules, when determining whether a hole to be inspected has a risk of solder leakage, if the distance between the boundary of the hole to be inspected and the boundary of the target inspection element is less than a preset threshold, such as 1 mil, then the hole is determined to have a risk of solder leakage. The preset threshold can be set in conjunction with circuit board process standards and actual production requirements.

[0082] In one example, such as Figure 2 As shown, the method also includes:

[0083] S5. Map all holes with potential solder leakage risk to the 3D model of the circuit board and mark them visually.

[0084] This method also includes post-processing visualization and interaction. First, all holes identified as having a risk of solder leakage are mapped onto the 3D model of the circuit board. Visual marking is achieved through color coding (e.g., red for high-risk holes, yellow for medium-risk holes) or 3D selection, intuitively presenting the risk distribution. Simultaneously, holes with solder leakage risk are displayed in a pop-up table containing key information such as hole ID, risk level, and distance parameters. When a user clicks on a problematic hole record in the table, the risk hole is quickly located in the circuit board design software (such as Allegro). For example, the view automatically zooms to the area where the hole is located and highlights it with a border, flashing, etc., assisting layout engineers in accurately locating the risk position and efficiently completing design modifications or process adjustments. This visualization and interaction mechanism transforms abstract risk data into intuitive spatial markers, significantly improving the efficiency and accuracy of PCB defect repair.

[0085] According to embodiments of this disclosure, a schematic diagram of a circuit board solder leakage detection device is also provided, as shown below. Figure 3 The device includes:

[0086] Classification module 10 is used to classify the holes to be inspected on the circuit board into at least two types of inspection objects based on electrical property parameters;

[0087] The screening module 20 is used to expand a preset distance based on the geometric boundary of the hole to be detected to form a detection area, and to screen the target detection elements within the detection area;

[0088] The detection module 30 is used to obtain the interlayer structural association features between the hole to be detected and the target detection element based on the detection object type to which the hole to be detected belongs;

[0089] The determination module 40 is used to determine whether there is a risk of solder leakage in the hole to be detected based on the interlayer structure correlation features and preset rules.

[0090] In one example, the detection object includes a first type of hole and a second type of hole; wherein,

[0091] The first type of hole includes through holes where the test point attribute is empty;

[0092] The second type of hole includes a test point through hole with test point attributes set to preset values. The preset values ​​include a first preset value representing the top-level test point and a second preset value representing the bottom-level test point.

[0093] In one example, the filtering module 20 is also used for:

[0094] Obtain the geometric boundary parameters of the hole to be detected;

[0095] A detection area is formed by extending a preset distance based on the geometric boundary parameters;

[0096] Based on preset element type conditions, elements that meet the preset element type conditions are selected as target detection elements within the detection area.

[0097] In one example, the hole to be detected is a first type of hole; the detection module 30 is also used for:

[0098] Determine whether the first dielectric layer and the second dielectric layer have vertical overlap in the axial extension direction of the hole to be tested;

[0099] If the vertical overlap exists, the distance between the hole to be detected and the target detection element is determined as the interlayer structure association feature.

[0100] In one example, the hole to be detected is a second type of hole; the detection module 30 is also used for:

[0101] Determine whether a preset dielectric layer structure exists within a preset spatial region of the detection layer of the hole to be detected;

[0102] If the preset medium layer structure exists, the distance between the hole to be detected and the target detection element is determined as the interlayer structure association feature.

[0103] In one example, module 40 is also used for:

[0104] If the distance between the hole to be tested and the target detection element is less than a preset threshold, it is determined that the hole to be tested has a risk of solder leakage.

[0105] In one example, such as Figure 4 The device also includes:

[0106] The marking module 50 is used to map all holes with the risk of solder leakage to the 3D model of the circuit board and mark them visually.

[0107] According to embodiments of this disclosure, an electronic device is also provided, comprising:

[0108] At least one processor; and

[0109] A memory communicatively connected to the at least one processor; wherein,

[0110] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the methods described in this disclosure.

[0111] According to embodiments of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the methods described in the present disclosure is also provided.

[0112] According to embodiments of this disclosure, this disclosure also provides an electronic device and a readable storage medium.

[0113] Figure 5 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0114] like Figure 5 As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 802 or a computer program loaded from storage unit 808 into random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0115] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of monitors, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0116] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the circuit board solder leakage detection method. For example, in some embodiments, the circuit board solder leakage detection method can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the circuit board solder leakage detection method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform the circuit board solder leakage detection method by any other suitable means (e.g., by means of firmware).

[0117] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0118] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0119] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0120] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0121] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0122] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0123] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0124] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0125] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for detecting solder leakage on a circuit board, characterized in that, The method includes: Based on electrical property parameters, the holes to be inspected on the circuit board are classified into at least two types of inspection objects; A detection area is formed by extending a preset distance based on the geometric boundary of the hole to be detected, and target detection elements within the detection area are screened. Based on the detection object type to which the hole to be detected belongs, obtain the interlayer structure association features between the hole to be detected and the target detection element; Based on the interlayer structure correlation features and preset rules, it is determined whether the hole to be tested has a risk of solder leakage.

2. The circuit board solder leakage detection method according to claim 1, characterized in that, The detection objects include a first type of hole and a second type of hole; wherein... The first type of hole includes through holes where the test point attribute is empty; The second type of hole includes a test point through hole with test point attributes set to preset values. The preset values ​​include a first preset value representing the top-level test point and a second preset value representing the bottom-level test point.

3. The circuit board solder leakage detection method according to claim 1, characterized in that, The step of expanding a detection area by a preset distance based on the geometric boundary of the hole to be detected, and filtering target detection elements within the detection area, includes: Obtain the geometric boundary parameters of the hole to be detected; A detection area is formed by extending a preset distance based on the geometric boundary parameters; Based on preset element type conditions, elements that meet the preset element type conditions are selected as target detection elements within the detection area.

4. The circuit board solder leakage detection method according to claim 2, characterized in that, The hole to be detected is a first type of hole; Based on the detection object type to which the hole to be detected belongs, the interlayer structural association features between the hole to be detected and the target detection element are obtained, including: Determine whether the first dielectric layer and the second dielectric layer have vertical overlap in the axial extension direction of the hole to be tested; If the vertical overlap exists, the distance between the hole to be detected and the target detection element is determined as the interlayer structure association feature.

5. The circuit board solder leakage detection method according to claim 2, characterized in that, The hole to be detected is a second type of hole; Based on the detection object type to which the hole to be detected belongs, corresponding inter-layer structure association detection is performed on the target detection element to obtain inter-layer structure association features, including: Determine whether a preset dielectric layer structure exists within a preset spatial region of the detection layer of the hole to be detected; If the preset medium layer structure exists, the distance between the hole to be detected and the target detection element is determined as the interlayer structure association feature.

6. The circuit board solder leakage detection method according to claim 4 or 5, characterized in that, The process of determining whether the via to be tested has a risk of solder leakage based on the interlayer structure correlation features and preset rules includes: If the distance between the hole to be tested and the target detection element is less than a preset threshold, then the hole to be tested is determined to have a risk of solder leakage.

7. The circuit board solder leakage detection method according to claim 1, characterized in that, The method also includes: All holes with potential solder leakage are mapped to the 3D model of the circuit board and marked visually.

8. A circuit board solder leakage detection device, characterized in that, The device includes: The classification module is used to classify the holes to be inspected on the circuit board into at least two categories of inspection objects based on electrical property parameters. The filtering module is used to expand a preset distance based on the geometric boundary of the hole to be detected to form a detection area, and to filter the target detection elements within the detection area; The detection module is used to obtain the interlayer structural association features between the hole to be detected and the target detection element based on the detection object type to which the hole to be detected belongs; The determination module is used to determine whether the hole to be tested has a risk of solder leakage based on the interlayer structure correlation characteristics and preset rules.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform: Based on electrical property parameters, the holes to be inspected on the circuit board are classified into at least two types of inspection objects; A detection area is formed by extending a preset distance based on the geometric boundary of the hole to be detected, and target detection elements within the detection area are screened. Based on the detection object type to which the hole to be detected belongs, obtain the interlayer structure association features between the hole to be detected and the target detection element; Based on the interlayer structure correlation features and preset rules, it is determined whether the hole to be tested has a risk of solder leakage.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute: Based on electrical property parameters, the holes to be inspected on the circuit board are classified into at least two types of inspection objects; A detection area is formed by extending a preset distance based on the geometric boundary of the hole to be detected, and target detection elements within the detection area are screened. Based on the detection object type to which the hole to be detected belongs, obtain the interlayer structure association features between the hole to be detected and the target detection element; Based on the interlayer structure correlation features and preset rules, it is determined whether the hole to be tested has a risk of solder leakage.

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