Apparatus, method, and medium for establishing a time test

Abstract

The application relates to the technical field of operational amplifier testing, and discloses an apparatus, a method and a medium for establishing time testing, the apparatus comprising: a first signal source module for emitting a first step signal; an inverting module for receiving the first step signal, performing phase inversion on the first step signal based on an inverting operational amplifier, and outputting a first inverted signal; a second signal source module for emitting a second step signal after the first step signal is emitted for a preset time length, wherein the preset time length is determined based on the response time of the inverting operational amplifier; a superposition module connected with the inverting module and the second signal source module respectively, the superposition module being used for receiving the first inverted signal and the second step signal, adding the first inverted signal and the second step signal, and outputting a first superposition signal; and a first signal analysis module for receiving the first superposition signal and obtaining the establishing time of the inverting operational amplifier based on the analysis result of the first superposition signal. The test result is more accurate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of operational amplifier testing, and particularly relates to a device, a method and a medium for setting time testing. BACKGROUND

[0002] The testing index of an operational amplifier (OPA) chip includes setting time. The setting time is used to represent the time required for the output of the operational amplifier to transit from one stable state to another stable state. The setting time is crucial for ensuring that the signal is accurately transmitted.

[0003] For the testing of the setting time, a step signal is usually applied to the input end of the operational amplifier, and an oscilloscope is used to capture the step signal of the output of the operational amplifier. The jump point of 50% of the value of the step signal applied to the input end of the operational amplifier can be taken as the starting point of the testing of the setting time, and the time from the jump point to the final stable state of the target value error band (for example, the target value ±0.01%) of the step signal of the output of the operational amplifier is measured, which is the setting time.

[0004] However, in the actual testing process, the step signal applied to the input end of the operational amplifier is not stable at the beginning, and there is slight jitter. The instability of the signal will affect the testing result of the setting time to some extent, resulting in inaccurate testing result of the setting time. SUMMARY

[0005] Therefore, the present application provides a device, a method and a medium for setting time testing to solve the problem that the step signal applied to the input end of the operational amplifier is unstable, resulting in inaccurate testing result of the setting time.

[0006] In a first aspect, the present application provides a device for setting time testing, which comprises: a first signal source module configured to emit a first step signal; an inverting module connected with the first signal source module, the inverting module being configured to receive the first step signal, perform phase inversion on the first step signal based on an inverting operational amplifier, and output a first inverted signal; a second signal source module configured to emit a second step signal after a preset time length of the emission of the first step signal, the preset time length being determined based on the response time of the inverting operational amplifier; a superposition module connected with the inverting module and the second signal source module respectively, the superposition module being configured to receive the first inverted signal and the second step signal, add the first inverted signal and the second step signal, and output a first superimposed signal; and a first signal analysis module connected with the superposition module, the first signal analysis module being configured to receive the first superimposed signal, and obtain the setting time of the inverting operational amplifier based on the analysis result of the first superimposed signal.

[0007] In an alternative embodiment, the device further comprises a first signal source conditioning module and a second signal source conditioning module; the first signal source conditioning module is connected with the first signal source module, and is configured to receive the first step signal and reduce the jitter amplitude of the first step signal to output a first test signal; the inverting module is connected with the first signal source conditioning module and the first signal source module, and is further configured to receive the first test signal, perform phase inversion on the first test signal based on the inverting operational amplifier, and output a second inverted signal; the second signal source conditioning module is connected with the second signal source module, and is configured to receive the second step signal and reduce the jitter amplitude of the second step signal to output a second test signal; the superposition module is connected with the second signal source conditioning module and the second signal source module, and is further configured to receive the second inverted signal and the second test signal, add the second inverted signal and the second test signal, and output a second superposition signal; the first signal analysis module is further configured to receive the second superposition signal and obtain the setup time of the inverting operational amplifier based on analysis of the second superposition signal.

[0008] In an alternative embodiment, the device further comprises a second signal analysis module connected with the first signal source conditioning module, which is configured to receive the first test signal; the second signal analysis module is also connected with the inverting module, and is configured to receive the second inverted signal; the second signal analysis module acquires a first time and a second time at which the absolute value of the voltage value in the first test signal and the second inverted signal is a preset voltage threshold value, respectively, and determines the preset time length based on the difference between the first time and the second time.

[0009] In an alternative embodiment, the first signal analysis module obtains the setup time of the inverting operational amplifier based on the analysis result of the first superposition signal, including: determining a test start time based on the time corresponding to the first preset voltage value in the first superposition signal, wherein the first preset voltage value is determined based on the first step signal; in the first superposition signal, traversing the voltage value in the direction of decreasing time starting from a first preset time until the absolute value of the traversed voltage value is greater than a second preset voltage value, to determine the time corresponding to the signal greater than the second preset voltage value as the first time, wherein the second preset voltage value is determined based on the test accuracy, and the first preset time is determined based on the standard value of the setup time; and obtaining the setup time of the inverting operational amplifier based on the first time minus the test start time plus the preset time length.

[0010] In an alternative embodiment, the inverting module comprises: a third resistor, a fourth resistor, a first inverting operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, a second inverting operational amplifier and an eighth resistor; one end of the third resistor is connected with the first signal source conditioning module, the other end of the third resistor is connected with one end of the fourth resistor and the inverting input terminal of the first inverting operational amplifier respectively, the other end of the fourth resistor and the output terminal of the first inverting operational amplifier are connected with one end of the seventh resistor, one end of the seventh resistor is also connected with the superposition module; one end of the fifth resistor is connected with the second signal source conditioning module, the other end of the fifth resistor is connected with one end of the sixth resistor and the inverting input terminal of the second inverting operational amplifier respectively, the other end of the sixth resistor and the output terminal of the second inverting operational amplifier are connected with one end of the eighth resistor; the non-inverting input terminal of the first inverting operational amplifier, the non-inverting input terminal of the second inverting operational amplifier, the other end of the seventh resistor and the other end of the eighth resistor are grounded.

[0011] In an alternative embodiment, the first signal source conditioning module comprises: a first Schottky diode, a second Schottky diode, a first resistor and a second resistor; wherein the first signal source module is connected with the anode of the first Schottky diode and the cathode of the second Schottky diode respectively, the cathode of the first Schottky diode is connected with one end of the first resistor, the anode of the second Schottky diode is connected with one end of the second resistor, the anode of the second Schottky diode is also connected with one end of the third resistor, the other end of the first resistor and the other end of the second resistor are grounded; the second signal source conditioning module comprises: a third Schottky diode, a fourth Schottky diode, a ninth resistor and a tenth resistor; wherein the second signal source module is connected with the anode of the third Schottky diode and the cathode of the fourth Schottky diode respectively, the cathode of the third Schottky diode is connected with one end of the ninth resistor, the anode of the fourth Schottky diode is connected with one end of the tenth resistor, the anode of the fourth Schottky diode is also connected with one end of the fifth resistor, the other end of the ninth resistor and the other end of the tenth resistor are grounded.

[0012] In an alternative embodiment, the superposition module comprises a sliding rheostat, a fifth Schottky diode and a sixth Schottky diode; one end of the sliding rheostat is connected to the anode of the fourth Schottky diode; the other end of the sliding rheostat is connected to the output of the first inverting operational amplifier; the middle sliding end of the sliding rheostat is connected to the cathode of the fifth Schottky diode and the anode of the sixth Schottky diode, respectively; the anode of the fifth Schottky diode and the cathode of the sixth Schottky diode are grounded.

[0013] In a second aspect, the present application provides a method for establishing time test, the method comprising: obtaining a first step signal emitted by a first signal source; inverting the phase of the first step signal based on an inverting operational amplifier to obtain a first inverted signal; obtaining a second step signal emitted by a second signal source after the first step signal is emitted for a preset time length; adding the first inverted signal and the second step signal to obtain a first superposition signal; and obtaining the establishing time of the inverting operational amplifier based on the analysis result of the first superposition signal.

[0014] In an alternative embodiment, the method further comprises: reducing the jitter amplitude of the first step signal to obtain a first test signal after the first step signal is obtained; inputting the first test signal into the inverting operational amplifier to invert the phase of the first test signal to obtain a second inverted signal; reducing the jitter amplitude of the second step signal to obtain a second test signal after the second step signal is obtained; adding the second inverted signal and the second test signal to obtain a second superposition signal; and obtaining the establishing time of the inverting operational amplifier after signal conditioning based on the analysis result of the second superposition signal.

[0015] In a third aspect, the present application provides a computer device, comprising: a memory and a processor, which are communicatively connected to each other, and the memory stores computer instructions; the processor executes the computer instructions to perform the method for establishing time test of the first aspect or any of the corresponding embodiments thereof.

[0016] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions for making a computer execute the method for establishing time test of the first aspect or any of the corresponding embodiments thereof.

[0017] In a fifth aspect, the present application provides a computer program product, which comprises computer instructions for making a computer execute the method for establishing time test of the first aspect or any of the corresponding embodiments thereof.

[0018] The device, method and medium for establishing time test provided by the application can eliminate the jitter caused by the step signal applied at the input end of the operational amplifier through the superposition cancellation mechanism of the first signal source and the second signal source, can significantly reduce the error, and makes the test result of the establishment time more accurate; meanwhile, the preset time length is adjusted based on the response time of the inverting operational amplifier, and the device is applicable to the operational amplifier with different response speeds, and can expand the test range. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments or related art, the drawings needed to be used in the specific embodiments or related art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 The structural schematic diagram of the device for establishing time test provided by the application is shown;

[0021] Figure 2 Another structural schematic diagram of the device for establishing time test provided by the embodiment of the application is shown;

[0022] Figure 3 Still another structural schematic diagram of the device for establishing time test provided by the embodiment of the application is shown;

[0023] Figure 4 The preset time determination process in the embodiment of the application is shown;

[0024] Figure 5 Still another structural schematic diagram of the device for establishing time test provided by the embodiment of the application is shown;

[0025] Figure 6 Still another structural schematic diagram of the device for establishing time test provided by the embodiment of the application is shown;

[0026] Figure 7 The generation process of the second superposition signal is shown;

[0027] Figure 8 The waveform schematic diagram of the second superposition signal is shown;

[0028] Figure 9 The flow schematic diagram of the method for establishing time test in the embodiment of the application is shown;

[0029] Figure 10 The hardware structure schematic diagram of the computer device in the embodiment of the application is shown. DETAILED DESCRIPTION

[0030] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0031] According to the embodiments of the present application, a device for establishing time test is provided, Figure 1 The structure of the device for establishing time test provided by the present application is shown in the figure. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware or a combination of software and hardware is also possible and contemplated.

[0032] As Figure 1 As shown in the figure, the device for establishing time test provided by the present application comprises: a first signal source module 101 for emitting a first step signal; an inverting module 102 connected with the first signal source module 101, the inverting module 102 being configured to receive the first step signal, perform phase inversion on the first step signal based on an inverting operational amplifier, and output a first inverted signal; a second signal source module 103 for emitting a second step signal after the first step signal is emitted for a preset time length, the preset time length being determined based on the response time of the inverting operational amplifier; a superposition module 104 connected with the inverting module 102 and the second signal source module 103, the superposition module 104 being configured to receive the first inverted signal and the second step signal, add the first inverted signal and the second step signal, and output a first superposition signal; and a first signal analysis module 105 connected with the superposition module 104, the first signal analysis module 105 being configured to receive the first superposition signal and obtain the setup time of the inverting operational amplifier based on the analysis result of the first superposition signal.

[0033] In the present embodiment, the first signal source module 101 and the second signal source module 103 can be electronic test equipment, which can be used to generate electrical signals of various frequencies, waveforms and amplitudes, and can be widely applied in the fields of communication, electronic research and development, and production test. The first signal source module 101 and the second signal source module 103 can output standard signals such as sine wave, square wave, triangular wave and pulse wave.

[0034] In the inverting module 102, an inverting operational amplifier, i.e. a device under test, is included. In the superposition module 104, a signal addition circuit is included, which can linearly superimpose the received first inverted signal and second step signal and output a first superposition signal.

[0035] The first signal analysis module can be an oscilloscope or the like. The oscilloscope can be an instrument for observing and analyzing the waveform of an electrical signal, and can display the change of voltage over time in a graphical manner, helping users to quickly diagnose circuit faults, measure signal parameters such as frequency, amplitude, phase, and the like.

[0036] In the device for establishing time test provided in the present application, during the process of testing the inverting operational amplifier, the first signal source module sends a first step signal to the inverting operational amplifier in the inverting module, the operational amplifier starts to respond and enters a dynamic establishment process, and outputs a first inverted signal. The second signal source module sends a second step signal after a preset time delay after the first step signal is sent. The first inverted signal and the second step signal are superimposed based on the superimposition module, which can eliminate the jitter influence caused by the first signal source and the second signal source themselves. Based on the waveform of the first superimposed signal, the time taken for the first superimposed signal to stabilize to a target value or to stabilize to a range allowed by the test error is determined as the establishment time of the inverting operational amplifier.

[0037] The device for establishing time test provided in the present application can eliminate the jitter caused by the step signal applied to the input end of the operational amplifier through the superimposition and cancellation mechanism of the first signal source and the second signal source, can significantly reduce the error, and can make the test result of the establishment time more accurate. At the same time, the preset time is adjusted based on the response time of the inverting operational amplifier, which is suitable for operational amplifiers with different response speeds and can expand the test range.

[0038] The step signals sent by the first signal source module and the second signal source module will have a large jitter before the step signals tend to be stable. In the present embodiment, before the first signal source module and the second signal source module are used to measure the measured operational amplifier, the signal source is conditioned through the signal source conditioning circuit, which can reduce the jitter amplitude of the step signal.

[0039] Figure 2 Another structural schematic diagram of the device for establishing time test provided in the present application is shown in FIG. 6. Figure 2As shown, in some optional embodiments, the device further comprises a first signal source conditioning module 201 and a second signal source conditioning module 202; the first signal source conditioning module 201 is connected with the first signal source module 101, and the first signal source conditioning module 201 is configured to receive the first step signal and reduce the jitter amplitude of the first step signal to output a first test signal; the inverting module 102 is connected with the first signal source conditioning module 201 based on the first signal source module 101, and the inverting module 102 is further configured to receive the first test signal, perform phase inversion on the first test signal based on an inverting operational amplifier, and output a second inverted signal; the second signal source conditioning module 202 is connected with the second signal source module 103, and the second signal source conditioning module 202 is configured to receive the second step signal and reduce the jitter amplitude of the second step signal to output a second test signal; the superposition module 104 is connected with the second signal source conditioning module 202 based on the second signal source module 103, and the superposition module 104 is further configured to receive the second inverted signal and the second test signal, add the second inverted signal and the second test signal, and output a second superposition signal; the first signal analysis module 105 is further configured to receive the second superposition signal and obtain the setup time of the inverting operational amplifier after signal source conditioning based on analysis of the second superposition signal.

[0040] In the present embodiment, before the first step signal is input into the inverting module 102, the first signal source conditioning module 201 is used to condition the first step signal to reduce the jitter amplitude of the first step signal, and obtain a first test signal with reduced jitter amplitude.

[0041] The first test signal is input into the inverting module 102, and the first test signal is phase-inverted by the measured inverting operational amplifier to obtain a second inverted signal.

[0042] The second step signal is output at intervals of a preset time length, and before the second step signal is input into the superposition module 104, the second signal source conditioning module 202 is used to condition the second step signal to reduce the jitter amplitude of the second step signal, and obtain a second test signal with reduced jitter amplitude.

[0043] The second inverted signal and the second test signal are added to output a second superposition signal, and the setup time of the inverting operational amplifier after signal source conditioning is obtained based on analysis of the second superposition signal.

[0044] In this way, by the signal source conditioning module, the jitter of the step signal is reduced, the input signal of the inverting operational amplifier is closer to the ideal state, and the accuracy of the setup time test result can be further improved. Meanwhile, based on the signal source conditioning module, the transition characteristics of the step signal are stabilized, the test results under the same conditions are more consistent, the repeatability and reliability of the test can be improved. In addition, by the signal source conditioning module, the step signal emitted by the signal source module with poor quality can be processed to meet the test requirements, without relying on a high-precision signal source, the dependence of the device for setup time test provided in the embodiment on external equipment can be reduced, and the applicability of the device is expanded.

[0045] Figure 3 Another structural schematic diagram of the device for setup time test provided in the embodiment of the application is shown. Figure 3 As shown in some optional embodiments, the device for setup time test described above further includes: a second signal analysis module 301 connected with the first signal source conditioning module 201, the second signal analysis module 301 is configured to receive the first test signal; the second signal analysis module 301 is also connected with the inverting module 102, and the second signal analysis module 301 is configured to receive the second inverted signal; the second signal analysis module 301 acquires the first time point and the second time point at which the absolute value of the voltage value in the first test signal and the second inverted signal is the preset voltage threshold value, respectively, and determines the preset time length based on the difference between the first time point and the second time point.

[0046] In the embodiment, the second signal analysis module 301 can be the same as or different from the first signal analysis module 105. Specifically, the second signal analysis module 301 can be changed from being connected with the superposition module 104 to being connected with the first signal source conditioning module 201 and the inverting module 102. A step signal is generated by the first signal source module 101, the step signal is conditioned by the first signal source conditioning module 201 to obtain the first test signal, the first test signal is received by the second signal analysis module 301, and the first test signal is phase-inverted by the inverting operational amplifier in the inverting module 102 to obtain the second inverted signal, which is received by the second signal analysis module 301. The second signal analysis module 301 determines the first time corresponding to the preset voltage threshold value in the first test signal, and determines the second time corresponding to the preset voltage threshold value in the second inverted signal. The time difference between the first time and the second time is calculated, and the calculation result is the preset time length.

[0047] In a specific test process, if the voltage value of the tested step signal is a first voltage value, the voltage value of the step signal sent by the signal source module is a second voltage value, and the absolute value of the second voltage value is greater than the absolute value of the first voltage value. In this way, the problem that the diode breakdown voltage existing in the circuit affects the voltage value of the step signal can be avoided.

[0048] Figure 4 A schematic diagram of a preset time determination process in the embodiment of the application is shown, as shown in Figure 4 Specifically, in the case of testing a 2V step signal, a first signal source module 101 can input a first step signal of -2.3V to 1V to a first signal source conditioning module 201. The first signal source conditioning module 201 can reduce the jitter amplitude of the first step signal of -2.3V to 1V to obtain a first test signal 401 of -2V to 0V. At the same time, the first test signal is phase-inverted in the inverting module 102 to obtain a second inverted signal 402 of 2V to 0V. Through a second signal analysis module 301, for example, an oscilloscope, the first time 403 at which the pulse in the first test signal 401 is 50% is determined, and the second time 404 at which the pulse in the second inverted signal 402 is 40% is determined. The time difference is calculated to obtain a preset time e.

[0049] In this way, the second signal analysis module dynamically determines the preset time e by capturing the first time and the second time at which the voltage absolute value reaches the preset threshold in the first test signal and the second inverted signal, and the difference between the two. The delay time is accurately matched with the actual response characteristics (such as signal transition speed) of the inverting operational amplifier, avoiding the problem of excessively long or short delay caused by manual setting or fixed value. At the same time, the preset time e is dynamically calculated and can automatically adapt to the response characteristics of different operational amplifiers, so that the preset time e matching the current measured operational amplifier can be generated without manual intervention, significantly improving the compatibility and versatility of the device.

[0050] Figure 5 Another structural schematic diagram of the device for establishing time test provided by the embodiment of the application is shown. As Figure 5As shown in some optional embodiments, the inverting module comprises: a third resistor R3, a fourth resistor R4, a first inverting operational amplifier N1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a second inverting operational amplifier N2 and an eighth resistor R8; one end of the third resistor R3 is connected with the first signal source conditioning module 201, the other end of the third resistor R3 is connected with one end of the fourth resistor R4 and the inverting input end of the first inverting operational amplifier N1 respectively, the other end of the fourth resistor R4 and the output end of the first inverting operational amplifier N1 are connected with one end of the seventh resistor R7, one end of the seventh resistor R7 is also connected with the superposition module; one end of the fifth resistor R5 is connected with the second signal source conditioning module 202, the other end of the fifth resistor R5 is connected with one end of the sixth resistor R6 and the inverting input end of the second inverting operational amplifier N2 respectively, the other end of the sixth resistor R6 and the output end of the second inverting operational amplifier N2 are connected with one end of the eighth resistor R8; the non-inverting input end of the first inverting operational amplifier N1, the non-inverting input end of the second inverting operational amplifier N2, the other end of the seventh resistor R7 and the other end of the eighth resistor R8 are grounded.

[0051] In the embodiment, D1, D2, D3, D4, D5 and D6 are Schottky diodes, which are only turned on when the anode voltage is greater than the cathode voltage; R1, R2, R3, R4, R5, R6, R7, R8, R9 and R10 are constant resistors. Among them, the seventh resistor R7 is used as an output load resistor on the one hand to stabilize the output voltage of the first inverting operational amplifier N1; on the other hand, by grounding, a direct current loop is formed to avoid noise interference caused by the floating output end of the first inverting operational amplifier N1. Similarly, the eighth resistor R8 is used to stabilize the output voltage of the second inverting operational amplifier N2 and provide a grounding loop.

[0052] Specifically, at one end of the third resistor R3, a first test signal of -2V to 0V is input, and at the other end of the fourth resistor R4, a second reverse signal of 0V to 2V can be collected after a certain degree of delay.

[0053] In this way, the phase inversion of the input signal is strictly guaranteed through the negative feedback structure of the inverting operational amplifier; at the same time, the grounding design of the non-inverting input end provides a stable direct current bias reference for the operational amplifier, avoids the output error caused by the common mode voltage drift, and makes the circuit stable and highly adaptive.

[0054] Figure 6 Another structure diagram of the device for establishing time test is shown. As shown in FIG. 6, the device for establishing time test comprises a first signal source conditioning module 201, a second signal source conditioning module 202, an inverting module, a superposition module and a test module. Figure 6As shown, in some optional embodiments, the first signal source conditioning module 201 comprises: a first Schottky diode D1, a second Schottky diode D2, a first resistor R1 and a second resistor R2; wherein the first signal source module 101 is connected with the anode of the first Schottky diode D1 and the cathode of the second Schottky diode D2 respectively, the cathode of the first Schottky diode D1 is connected with one end of the first resistor R1, the anode of the second Schottky diode D2 is connected with one end of the second resistor R2, and the anode of the second Schottky diode D2 is also connected with one end of a third resistor R3, the other end of the first resistor R1 and the other end of the second resistor R2 are grounded.

[0055] The second signal source conditioning module 202 comprises: a third Schottky diode D3, a fourth Schottky diode D4, a ninth resistor R9 and a tenth resistor R10; wherein the second signal source module 103 is connected with the anode of the third Schottky diode D3 and the cathode of the fourth Schottky diode D4 respectively, the cathode of the third Schottky diode D3 is connected with one end of the ninth resistor R9, the anode of the fourth Schottky diode D4 is connected with one end of the tenth resistor R10, and the anode of the fourth Schottky diode D4 is also connected with one end of a fifth resistor R5, the other end of the ninth resistor R9 and the other end of the tenth resistor R10 are grounded.

[0056] In the present embodiment, the first signal source conditioning module 201 and the second signal source conditioning module 202 have the same circuit structure and the same working principle. The working principle of the signal source conditioning circuit is exemplarily described below by taking the first signal source conditioning module 201 as an example.

[0057] The first signal source module 101 generates a first step signal of -2.3V to 1V. When the voltage value of the first step signal is -2.3V, D1 is off and D2 is on. However, since D2 has a small voltage drop, if the voltage drop is 0.3V, the voltage at B end is -2V.

[0058] When the voltage value of the first step signal jumps to 1V, D1 is on and D2 is off, and the voltage value at B end is 0V. B end can output a first test signal of -2V to 0V after conditioning, and the jitter of the first test signal is small.

[0059] The circuit structure of the second signal source conditioning module 202 is the same as that of the first signal source conditioning module 201. The second step signal output by the second signal source module 103 is subjected to the same bidirectional amplitude limiting and current limiting processing, so that the conditioning standards of the second test signal and the first test signal are consistent, and the subsequent superposition error caused by the difference in the preprocessing of the two signals can be avoided.

[0060] In this way, the low on-voltage and fast response characteristics of the Schottky diode can accurately clamp the positive or negative overshoot or random jitter of the step signal, especially the amplitude fluctuation during high-speed jumping, so that the first and second test signals output are closer to the ideal step waveform; at the same time, high-quality input can be provided for the accurate inversion processing of the inversion module and the signal cancellation of the superposition module, and the accuracy of the base signal of the setup time test can be improved.

[0061] As shown in Figure 6 In some optional embodiments, the superposition module 104 includes a sliding resistor R11, a fifth Schottky diode D5, and a sixth Schottky diode D6. One end of the sliding resistor R11 is connected to the anode of the fourth Schottky diode D4. The other end of the sliding resistor R11 is connected to the output terminal of the first inverting operational amplifier N1. The middle sliding end of the sliding resistor R11 is connected to the cathode of the fifth Schottky diode D5 and the anode of the sixth Schottky diode D6, respectively. The anode of the fifth Schottky diode D5 and the cathode of the sixth Schottky diode D6 are grounded.

[0062] In the present embodiment, the input signal of the superposition module 104 has two paths. One path is the second test signal from the second signal source conditioning module, which is connected to one end of the sliding resistor R11. The other path is the second inverted signal from the inversion module, which is connected to the other end of the sliding resistor R11. The sliding resistor R11 realizes the superposition of the two signals through the middle sliding end.

[0063] The fifth Schottky diode D5 and the sixth Schottky diode D6 constitute a bidirectional limiting circuit and are connected to the middle sliding end of the sliding resistor. When the superposition signal is a positive voltage and exceeds the on-voltage of D5, D5 is turned on, clamping the positive voltage near the on-voltage of D5, and suppressing positive overshoot or noise. When the superposition signal is a negative voltage and the absolute value exceeds the on-voltage of D6, D6 is turned on, clamping the negative voltage near the on-voltage of D6, and suppressing negative overshoot or noise. This can avoid measurement errors in the subsequent signal analysis module due to excessive signal amplitude or sudden noise.

[0064] The superposition module 104 can shorten the range of the original range of 2V to 0.8V, which can be -0.4V to 0.4V, and can meet the testing requirements of smaller resolution setup time.

[0065] In this way, the bidirectional limiting effect of the fifth and sixth Schottky diodes can effectively filter out positive or negative overshoot, high-frequency noise, or sudden interference in the superposition signal. At the same time, the fast response characteristics of the Schottky diode can adapt to high-speed superposition signals and avoid introducing additional delay or signal distortion during limiting.

[0066] In some optional embodiments, the first signal analysis module, based on the result of the analysis of the first superimposed signal, obtains the setting time of the inverting operational amplifier, comprising: determining a test starting time point based on the time point corresponding to the first preset voltage value in the first superimposed signal, wherein the first preset voltage value is determined based on the first step signal; in the first superimposed signal, traversing the voltage value in the direction of decreasing time starting from the first preset time, until the absolute value of the traversed voltage value is greater than the second preset voltage value, and determining the time corresponding to the signal greater than the second preset voltage value as the first time, wherein the second preset voltage value is determined based on the test accuracy, and the first preset time is determined based on the standard value of the setting time; and obtaining the setting time of the inverting operational amplifier based on the first time minus the test starting time point, plus a preset time length.

[0067] In the present embodiment, the setting time of the inverting operational amplifier after the signal source conditioning is more accurate than the setting time of the inverting operational amplifier. In the present embodiment, the analysis process of the second superimposed signal by the signal analysis module is taken as an example to exemplarily illustrate the testing process of the setting time.

[0068] As shown in Figure 6 , the first signal source module and the second signal source module can emit two identical step signals, for example, a step signal of -2.3V to 1V, but the second signal source module can emit the second step signal with a delay of a preset time length e. Then the signal at the B end is the first test signal of -2V to 0V after conditioning. The signal at the B1 end is the second test signal of -2V to 0V after conditioning with a delay of a preset time length e. The signal at the C end is the second inverted signal. The signal collected at the K end is the signal after adding the second test signal and the second inverted signal, i.e., the second superimposed signal.

[0069] In the analysis process of the first superimposed signal, there is no signal source conditioning process, and the principles of other parts are the same as those in the analysis process of the second superimposed signal, which will not be described here.

[0070] Figure 7 A schematic diagram of the generation process of the second superimposed signal is shown. As shown in Figure 7 , the first preset voltage value can be determined as 50% of the input pulse based on the voltage value of the first step signal, i.e., -1V. The time corresponding to the first preset voltage value -1V is determined as the test starting time t0.

[0071] Figure 8 A waveform diagram of the second superimposed signal is shown. The signal at the K end is viewed by an oscilloscope, and one possible result is as shown in Figure 8The jitter influence caused by the signal source itself can be removed by adding the reversed second test signal 701 and the second inverted signal 402, and only the jitter influence caused by the operational amplifier is left, so that the calculated establishment time of the inverted operational amplifier signal source after conditioning is more accurate.

[0072] Specifically, if the test precision requirement is to reach 0.01% of the range, the error band range can be-0.2mV~0.2mV, and the second preset voltage value can be determined as 0.2mV. Before testing an operational amplifier, the standard value or typical value of the establishment time in the index can be determined, for example, 50ns, so that the first preset time can be determined as twice the value, that is, 100ns, and then the first time t1 is finally determined by the following algorithm.

[0073] Firstly, the point of the second superimposed signal 801 at the time of 80ns is found, and it is obvious that the point is within the error band range, then the time is reduced little by little, and it is judged whether the voltage value of each point is within the error band-0.2mV~0.2mV, until the point just exceeds the interval, and the corresponding time is t1. If the establishment time is t, then t=t1-t0+e.

[0074] In this way, from the starting time positioning, the reverse traversal search to the final calculation, the whole process is automatically completed by the device, without manual marking of the time point or judging the stable moment, random errors caused by subjective experience differences of the operator are completely eliminated, the deviation of the test results of the same device multiple times is smaller, the repeatability and reliability of the test are significantly improved, and the method is especially suitable for consistency detection in batch production; meanwhile, the preset time length compensation logic is added in the calculation formula, the time difference between the second signal source and the first signal source is specially targeted, the additional delay caused by the different synchronization of the signal sources is eliminated, the final result only reflects the dynamic response characteristics of the inverted operational amplifier itself, the problem that the system delay is misjudged as the device establishment time is avoided, and the authenticity of the test result is ensured.

[0075] According to the embodiment of the present application, a method embodiment for establishment time test is provided, and it should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a group of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0076] In the embodiment, a method for establishment time test is provided, which can be used for the device for establishment time test described above, Figure 9 The flowchart of the method for establishment time test of the embodiment of the present application is shown as Figure 9As shown, the flow includes the following steps:

[0077] Step S901, a first step signal emitted by a first signal source is acquired.

[0078] Step S902, based on an inverting operational amplifier, the first step signal is phase-inverted to obtain a first inverted signal.

[0079] Step S903, after the first step signal is emitted for a preset time length, a second step signal emitted by a second signal source is acquired.

[0080] Step S904, the first inverted signal and the second step signal are added to obtain a first superimposed signal, and based on a result of analyzing the first superimposed signal, an establishment time of the inverting operational amplifier is obtained.

[0081] The method for establishment time testing provided by the embodiment can eliminate the jitter caused by the step signal applied to the input end of the operational amplifier through the superimposition and cancellation mechanism of the first signal source and the second signal source, can significantly reduce the error, and makes the test result of the establishment time more accurate; meanwhile, the preset time length is adjusted based on the response time of the inverting operational amplifier, which is applicable to operational amplifiers with different response speeds, and can expand the test range.

[0082] In some optional embodiments, the foregoing method for establishment time testing further includes: after the first step signal is acquired, the jitter amplitude of the first step signal is reduced to obtain a first test signal; the first test signal is input into the inverting operational amplifier to phase-invert the first test signal to obtain a second inverted signal; after the second step signal is acquired, the jitter amplitude of the second step signal is reduced to obtain a second test signal, the second inverted signal and the second test signal are added to obtain a second superimposed signal, and based on a result of analyzing the second superimposed signal, an establishment time of the inverting operational amplifier after signal source conditioning is obtained.

[0083] In some optional embodiments, the foregoing method for establishment time testing further includes: acquiring a first time and a second time at which the absolute value of the voltage value in the first test signal and the second inverted signal is a preset voltage threshold; based on a difference between the first time and the second time, the preset time length is determined.

[0084] In some optional implementations, the settling time of the inverting operational amplifier is obtained based on the analysis results of the first superimposed signal, including: determining the test start time based on the time corresponding to the voltage value in the first superimposed signal that is a first preset voltage value, wherein the first preset voltage value is determined based on the first step signal; in the first superimposed signal, starting from the first preset time, traversing the voltage values ​​in the direction of decreasing time until the absolute value of the traversed voltage values ​​is greater than the second preset voltage value, determining the time corresponding to the signal that is greater than the second preset voltage value as the first time, wherein the second preset voltage value is determined based on the test accuracy, and the first preset time is determined based on the standard value of the settling time; and obtaining the settling time of the inverting operational amplifier by subtracting the test start time from the first time and adding a preset duration.

[0085] In this embodiment, the apparatus for establishing time testing is presented in the form of a functional unit. Here, a unit refers to an application-specific integrated circuit (ASIC) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0086] This invention also provides a computer device having the above-described features. Figure 1 The apparatus shown is used to establish a time test.

[0087] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 10 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a graphical user interface on an external input / output device (such as a display device coupled to the interface). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 10 Take a processor 10 as an example.

[0088] The processor 10 can be a central processing unit, a network processing unit, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a general array logic, or any combination thereof.

[0089] The memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods illustrated in the above embodiments.

[0090] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system and application programs required by at least one function. The data storage area can store data created according to the use of the computer device, and the like. In addition, the memory 20 can include a high-speed random access memory, and can further include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some alternative embodiments, the memory 20 can optionally include a memory disposed remotely from the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0091] The memory 20 can include a volatile memory, such as a random access memory, and can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid state disk. The memory 20 can further include a combination of the above-mentioned types of memories.

[0092] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30, and the output device 40 can be connected through a bus or other means, Figure 10 For example, by way of a bus connection.

[0093] The input device 30 can receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, and the like. The output device 40 can include a display device, an auxiliary lighting device (such as a light-emitting diode), a tactile feedback device (such as a vibration motor), and the like. The display device includes, but is not limited to, a liquid crystal display, a light-emitting diode, a display, and a plasma display. In some alternative embodiments, the display device can be a touch screen.

[0094] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium through network, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0095] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present application can be called or provided. Those skilled in the art should understand that the form of computer program instructions in a computer readable medium includes but is not limited to source files, executable files, installation package files, etc. Correspondingly, the way of executing computer program instructions by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0096] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. An apparatus for establishing a time test, characterized by, The device comprises: A first signal source module for emitting a first step signal; An inverting module connected with the first signal source module, the inverting module being configured to receive the first step signal, perform phase inversion on the first step signal based on an inverting operational amplifier, and output a first inverted signal; A second signal source module for emitting a second step signal after the first step signal is emitted for a preset time length, the preset time length being determined based on a response time of the inverting operational amplifier; A superposition module connected with the inverting module and the second signal source module respectively, the superposition module being configured to receive the first inverted signal and the second step signal, add the first inverted signal and the second step signal, and output a first superposition signal; A first signal analysis module connected with the superposition module, the first signal analysis module being configured to receive the first superposition signal, and obtain a setup time of the inverting operational amplifier based on a result of analysis on the first superposition signal.

2. The apparatus of claim 1, wherein, The device further comprises a first signal source conditioning module and a second signal source conditioning module; The first signal source conditioning module is connected with the first signal source module, and is configured to receive the first step signal, reduce a jitter amplitude of the first step signal, and output a first test signal; The inverting module is connected with the first signal source conditioning module and the first signal source module, and is further configured to receive the first test signal, perform phase inversion on the first test signal based on the inverting operational amplifier, and output a second inverted signal; The second signal source conditioning module is connected with the second signal source module, and is configured to receive the second step signal, reduce a jitter amplitude of the second step signal, and output a second test signal; The superposition module is connected with the second signal source conditioning module and the second signal source module, and is further configured to receive the second inverted signal and the second test signal, add the second inverted signal and the second test signal, and output a second superposition signal; The first signal analysis module is further configured to receive the second superposition signal, and obtain a setup time of the inverting operational amplifier after conditioning based on analysis on the second superposition signal.

3. The apparatus of claim 2, wherein, The device further comprises: A second signal analysis module connected with the first signal source conditioning module, the second signal analysis module being configured to receive the first test signal; The second signal analysis module is further connected with the inverting module, and is configured to receive the second inverted signal; The second signal analysis module acquires a first time and a second time at which absolute values of voltage values in the first test signal and the second inverted signal are a preset voltage threshold value respectively, and determines the preset time length based on a difference between the first time and the second time.

4. The apparatus of claim 1, wherein, The first signal analysis module obtains the setup time of the inverting operational amplifier based on the result of analysis on the first superposition signal, which comprises: Determine a test starting time based on a time at which a voltage value in the first superimposed signal is a first preset voltage value, wherein the first preset voltage value is determined based on the first step signal; In the first superimposed signal, traverse voltage values in a direction of decreasing time starting from a first preset time, until an absolute value of a traversed voltage value is greater than a second preset voltage value, to determine a time corresponding to a signal greater than the second preset voltage value as a first time, wherein the second preset voltage value is determined based on test accuracy, and the first preset time is determined based on a standard value of the establishment time; Determine the establishment time of the inverting operational amplifier based on the first time minus the test starting time plus the preset time length.

5. The apparatus of claim 2, wherein, The inverting module comprises: A third resistor, a fourth resistor, a first inverting operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, a second inverting operational amplifier, and an eighth resistor; One end of the third resistor is connected to the first signal source conditioning module, and the other end of the third resistor is respectively connected to one end of the fourth resistor and an inverting input end of the first inverting operational amplifier. The other end of the fourth resistor and an output end of the first inverting operational amplifier are connected to one end of the seventh resistor, and one end of the seventh resistor is also connected to the superimposition module; One end of the fifth resistor is connected to the second signal source conditioning module, and the other end of the fifth resistor is respectively connected to one end of the sixth resistor and an inverting input end of the second inverting operational amplifier. The other end of the sixth resistor and an output end of the second inverting operational amplifier are connected to one end of the eighth resistor; The non-inverting input end of the first inverting operational amplifier, the non-inverting input end of the second inverting operational amplifier, the other end of the seventh resistor, and the other end of the eighth resistor are grounded.

6. The apparatus of claim 5, wherein The first signal source conditioning module comprises a first Schottky diode, a second Schottky diode, a first resistor, and a second resistor; The first signal source module is respectively connected to an anode of the first Schottky diode and a cathode of the second Schottky diode. A cathode of the first Schottky diode is connected to one end of the first resistor. An anode of the second Schottky diode is connected to one end of the second resistor. The anode of the second Schottky diode is also connected to one end of the third resistor. The other end of the first resistor and the other end of the second resistor are grounded. The second signal source conditioning module comprises a third Schottky diode, a fourth Schottky diode, a ninth resistor, and a tenth resistor; The second signal source module is connected with the anode of the third Schottky diode and the cathode of the fourth Schottky diode respectively, the cathode of the third Schottky diode is connected with one end of the ninth resistor, the anode of the fourth Schottky diode is connected with one end of the tenth resistor, the anode of the fourth Schottky diode is also connected with one end of the fifth resistor, and the other end of the ninth resistor and the other end of the tenth resistor are grounded.

7. The apparatus of claim 6, wherein, The superposition module comprises: a sliding rheostat, a fifth Schottky diode and a sixth Schottky diode; one end of the sliding rheostat is connected with the anode of the fourth Schottky diode; the other end of the sliding rheostat is connected with the output end of the first inverting operational amplifier; the middle sliding end of the sliding rheostat is connected with the cathode of the fifth Schottky diode and the anode of the sixth Schottky diode respectively, and the anode of the fifth Schottky diode and the cathode of the sixth Schottky diode are grounded.

8. A method for establishing a time test, characterized by, The method comprises: acquiring a first step signal emitted by a first signal source; inverting the phase of the first step signal based on an inverting operational amplifier to obtain a first inverted signal; acquiring a second step signal emitted by a second signal source after the first step signal is emitted for a preset time length; adding the first inverted signal and the second step signal to obtain a first superposition signal, and obtaining the setup time of the inverting operational amplifier based on the analysis result of the first superposition signal.

9. The method of claim 8, wherein, The method further comprises: after acquiring the first step signal, reducing the jitter amplitude of the first step signal to obtain a first test signal; inputting the first test signal into the inverting operational amplifier to invert the phase of the first test signal to obtain a second inverted signal; after acquiring the second step signal, reducing the jitter amplitude of the second step signal to obtain a second test signal; adding the second inverted signal and the second test signal to obtain a second superposition signal, and obtaining the setup time of the inverting operational amplifier after signal source conditioning based on the analysis result of the second superposition signal.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for causing a computer to execute the method for setup time testing according to claim 8 or 9. The computer readable storage medium stores computer instructions for causing a computer to execute the method for setup time testing according to claim 8 or 9.

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