Processor, floating-point number processing method, storage medium and program product

Abstract

The embodiment of the invention discloses a processor, a floating-point number processing method, a storage medium and a program product, and the processor comprises a multiplication and addition operation unit; the multiply-add operation unit is used for responding to a first signal for a target floating-point number, and determining the state of multiply-add operation matched with the target floating-point number based on the size relation between the target floating-point number and a floating-point number threshold value under the condition that the target floating-point number does not meet a preset condition; and outputting a decimal part of the target floating-point number based on the state of the multiply-add operation. Therefore, the processing of the FRC operation is realized by multiplexing the calculation path of the multiply-add operation unit, the circuit area consumption when the FRC calculation unit is independently arranged and the calculation power consumption when the FRC operation is performed are saved, and the processing efficiency is improved.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of computer technology, and in particular to a processor and floating-point number processing method, storage medium, and program product. Background Technology

[0002] FRC is an instruction that performs mathematical operations on floating-point numbers. It is used to obtain the fractional part of a floating-point number, that is, the fractional part between 0.0 and 1.0.

[0003] In related technologies, a separate FRC calculation unit is set up in the Arithmetic and Logic Unit (ALU) to complete the calculation of the FRC function. The FRC calculation unit is processed in parallel with other calculation units in the ALU, and a selector selects one of the calculation results from the FRC calculation unit and the calculation results from other calculation units for output.

[0004] However, this method of setting up a separate FRC computing unit will lead to an increase in circuit area, as well as an increase in computing power consumption and a decrease in computing efficiency. Summary of the Invention

[0005] In view of this, the present disclosure provides at least one processor and floating-point number processing method, storage medium, and program product.

[0006] The technical solution of this disclosure embodiment is implemented as follows: On one hand, embodiments of this disclosure provide a processor, the processor including: a multiply-accumulate unit; the multiply-accumulate unit is configured to respond to a first signal for a target floating-point number, and, when the target floating-point number does not meet a preset condition, determine a state of multiply-accumulate operation matching the target floating-point number based on the size relationship between the target floating-point number and a floating-point number threshold; and output the fractional part of the target floating-point number based on the state of the multiply-accumulate operation.

[0007] In some embodiments, the multiply-add unit includes: a window state detection module; the window state detection module is configured to output the state of the multiply-add operation as a first target state when the target floating-point number is greater than a first floating-point number threshold and less than a second floating-point number threshold; the floating-point number threshold includes the first floating-point number threshold and the second floating-point number threshold; the calculation window in the first target state contains the mantissa of the target floating-point number.

[0008] In some embodiments, the window state detection module is further configured to, when at least one of the target floating-point number being less than a first floating-point number threshold and the target floating-point number being greater than a second floating-point number threshold exists, and the number of bits shifted to the right is less than a number of bits threshold, the output multiplication-addition operation state is a second target state; the calculation window in the second target state contains the valid value of the mantissa portion of the target floating-point number whose corresponding exponent is less than or equal to 0.

[0009] In some embodiments, the window state detection module is further configured to output the state of the multiplication-addition operation as a third target state when at least one of the target floating-point number being less than a first floating-point number threshold and the target floating-point number being greater than a second floating-point number threshold exists, and the number of bits shifted to the right is greater than or equal to the number of bits threshold; the calculation window in the third target state does not contain a valid value of the mantissa portion of the target floating-point number whose corresponding exponent is less than or equal to 0.

[0010] In some embodiments, the multiply-accumulate unit includes: a displacement value calculation unit; the input port of the displacement value calculation unit is connected to the input port of the multiply-accumulate unit, and the output port of the displacement value calculation unit is connected to the input port of the window state detection module; the displacement value calculation unit is used to determine the number of right shifts of the target floating-point number based on the mantissa bit width of the target floating-point number, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the first bit width threshold.

[0011] In some embodiments, the multiply-add unit further includes: an addition exponent calculation module; the input port of the addition exponent calculation module is connected to the output port of the window state detection module; the addition exponent calculation module is used to determine the addition exponent based on the state of the multiply-add operation; the addition exponent is used to determine the fractional part of the target floating-point number; when the state of the multiply-add operation is a first target state, the addition exponent is the exponent of the target floating-point number; when the state of the multiply-add operation is a second target state or a third target state, the addition exponent is determined based on the exponent offset of the target floating-point number.

[0012] In some embodiments, the multiply-add unit further includes: an addition mantissa calculation module; the input port of the addition mantissa calculation module and the input port of the addition exponent calculation module are connected in parallel to the output port of the window state detection module; the addition mantissa calculation module is used to determine the addition mantissa based on the state of the multiply-add operation; the addition mantissa is used to determine the fractional part of the target floating-point number; when the state of the multiply-add operation is a first target state, the addition mantissa is determined based on the first addend and the second addend of the calculation window in the first target state; in the first target state, the first addend is a first floating-point value, and the second addend is the first number of bits truncated from the highest bit after the mantissa of the target floating-point number is placed in the highest bit of the calculation window; the first bit is determined based on the bit width of the calculation window in the first target state; when the state of the multiply-add operation is a second target state or a third target state, the addition mantissa is determined based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number, and the mantissa of the target floating-point number after placement is placed in the calculation window according to the right shift of the target floating-point number.

[0013] In some embodiments, the processor further includes: a selector; the selector is connected to the input of the processor and the output of the multiply-accumulate unit respectively; the selector is configured to output the floating-point value corresponding to the target floating-point number when the target floating-point number meets a preset condition; and to output the fractional part of the target floating-point number when the target floating-point number does not meet the preset condition.

[0014] On the other hand, embodiments of this disclosure provide a floating-point number processing method, which includes: responding to a first signal for a target floating-point number; if the target floating-point number does not meet a preset condition, determining the state of a multiplication-addition operation matching the target floating-point number based on the size relationship between the target floating-point number and a floating-point number threshold; and outputting the fractional part of the target floating-point number based on the state of the multiplication-addition operation.

[0015] In some embodiments, determining the state of a multiply-add operation matching the target floating-point number based on the relationship between the target floating-point number and a floating-point threshold includes at least one of the following steps: when the target floating-point number is greater than a first floating-point threshold and less than a second floating-point threshold, determining the state of the multiply-add operation as a first target state; the floating-point threshold includes a first floating-point threshold and a second floating-point threshold; the calculation window in the first target state contains the mantissa of the target floating-point number; when at least one of the target floating-point number being less than the first floating-point threshold and the target floating-point number being greater than the second floating-point threshold exists, determining the state of the multiply-add operation based on the relationship between the right shift bits of the target floating-point number and a bit threshold; the right shift bits are used to retain the mantissa portion of the target floating-point number whose corresponding exponent is less than or equal to 0 in the calculation window.

[0016] In some embodiments, determining the state of the multiply-add operation based on the relationship between the number of right-shifted bits of the target floating-point number and a bit threshold includes: determining the number of right-shifted bits of the target floating-point number based on the mantissa width of the target floating-point number, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the first bit width threshold; when the number of right-shifted bits is less than the bit threshold, the output state of the multiply-add operation is the second target state; the calculation window in the second target state contains a valid value of the mantissa portion corresponding to an exponent less than or equal to 0; when the number of right-shifted bits is greater than or equal to the bit threshold, the output state of the multiply-add operation is the third target state; the calculation window in the third target state does not contain a valid value of the mantissa portion corresponding to an exponent less than or equal to 0.

[0017] In some embodiments, the above-described output of the fractional part of the target floating-point number based on the state of the multiplication-addition operation includes: determining the mantissa and exponent of the addition operation based on the state of the multiplication-addition operation; and outputting the fractional part of the target floating-point number based on the sign bit, mantissa, and exponent of the addition operation.

[0018] In some embodiments, determining the mantissa and exponent based on the state of the multiplication-addition operation includes: when the state of the multiplication-addition operation is a first target state, assigning a first floating-point value to the first addend of the calculation window in the first target state; placing the mantissa of the target floating-point number in the highest bit of the calculation window in the first target state, and truncating the first bit from the highest bit and assigning it to the second addend of the calculation window in the first target state; the first bit is determined based on the bit width of the calculation window in the first target state, and the calculation window in the first target state contains the mantissa of the target floating-point number; determining the mantissa based on the first addend and the second addend; and using the exponent of the target floating-point number as the exponent.

[0019] In some embodiments, determining the mantissa and exponent based on the state of the multiplication-addition operation includes: when the state of the multiplication-addition operation is the second target state, placing the mantissa of the target floating-point number into the calculation window of the second target state according to the number of right shifts of the target floating-point number; determining the mantissa based on the mantissa and sign bit of the target floating-point number after placement; and determining the exponent based on the exponent offset of the target floating-point number.

[0020] In some embodiments, determining the addition mantissa based on the mantissa and sign bit of the target floating-point number after placement includes: if the target floating-point number is determined to be negative based on the sign bit, assigning the third floating-point value to the first addend of the calculation window in the second target state; truncating the second digit of the mantissa of the target floating-point number from the high-order bits downwards and assigning it to the second addend of the calculation window in the second target state; and performing subtraction on the first addend and the second addend to obtain the addition mantissa.

[0021] In some embodiments, determining the addition mantissa based on the mantissa and sign bit of the placed target floating-point number includes: if the target floating-point number is determined to be positive based on the sign bit, assigning the first floating-point value to the first addend of the calculation window in the second target state; truncating the third bit (excluding the highest bit) of the mantissa of the placed target floating-point number from the high bit downwards and assigning it to the second addend of the calculation window in the second target state; and performing addition on the first addend and the second addend to obtain the addition mantissa.

[0022] In some embodiments, determining the mantissa and exponent based on the state of the multiplication-addition operation includes: when the state of the multiplication-addition operation is the third target state, placing the mantissa of the target floating-point number into the calculation window of the third target state according to the number of right shift bits of the target floating-point number; determining the mantissa based on the mantissa and sign bit of the target floating-point number after placement; and determining the exponent based on the exponent offset of the target floating-point number.

[0023] In some embodiments, the floating-point number processing method further includes: outputting the floating-point value corresponding to the target floating-point number when the target floating-point number meets preset conditions.

[0024] In some embodiments, the floating-point number processing method further includes: determining that the target floating-point number satisfies a first preset condition when the target floating-point number is 0, or when the fractional part of the target floating-point number has no valid value but the integer part has a valid value; and determining that the target floating-point number satisfies a second preset condition when the target floating-point number is infinity (INF), or when the target floating-point number is not a number (NaN); the preset condition includes at least one of the first preset condition and the second preset condition.

[0025] In some embodiments, the above-mentioned outputting the floating-point value corresponding to the target floating-point number when the target floating-point number meets the preset conditions includes at least one of the following: outputting the first floating-point value when the target floating-point number meets the first preset conditions; and outputting the second floating-point value when the target floating-point number meets the second preset conditions.

[0026] In another aspect, embodiments of this disclosure provide a computer device including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the program to implement some or all of the steps in the above-described method.

[0027] In another aspect, embodiments of this disclosure provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above-described method.

[0028] In another aspect, embodiments of this disclosure provide a computer program including computer-readable code, which, when executed in a computer device, causes a processor in the computer device to perform some or all of the steps in the above-described method.

[0029] In another aspect, embodiments of this disclosure provide a computer program product, which includes a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above method.

[0030] In this embodiment, when the target floating-point number does not meet preset conditions, the state of the multiplication-addition operation is reused to implement the FRC operation for obtaining the fractional part of the floating-point number. Thus, by reusing the computational path of the multiplication-addition operation to implement the FRC operation, the circuit area consumption of setting up a separate FRC calculation unit is saved; by directly reusing the computational path of the multiplication-addition operation, the computational power consumption of the FRC operation is saved, and the processing efficiency is improved. Furthermore, when reusing the state of the multiplication-addition operation to implement the FRC operation, the relationship between the target floating-point number and the floating-point number threshold is considered, which can improve the processing accuracy of the FRC operation.

[0031] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this disclosure. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0033] Figure 1 A schematic diagram illustrating the composition structure of a floating-point number provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of a separately configured FRC computing unit provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of the structure of a multiply-accumulate operation unit provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of a calculation window for a multiply-accumulate unit provided in an embodiment of this disclosure; Figure 5 A schematic diagram of the implementation process of a floating-point number processing method provided in this embodiment of the present disclosure. Figure 1 ; Figure 6 A schematic diagram of the implementation process of a floating-point number processing method provided in this embodiment of the present disclosure. Figure 2 ; Figure 7A schematic diagram illustrating the implementation process of the addition mantissa in a floating-point number processing method provided in this embodiment of the present disclosure; Figure 8 A schematic diagram of the implementation flow of a processor provided in this disclosure embodiment. Figure 1 ; Figure 9 A schematic diagram of the implementation flow of a processor provided in this disclosure embodiment. Figure 2 ; Figure 10 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this disclosure. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0035] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0036] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this disclosure.

[0038] To better understand the floating-point number processing method provided in the embodiments of this disclosure, the solutions in related technologies will be described below.

[0039] A floating-point number consists of 1 sign bit, n exponent bits, and m mantissa bits. The sign bit indicates whether the floating-point number is positive or negative (e.g., 0 for positive, 1 for negative). The exponent bits represent the range of the value. The mantissa bits represent the precision of the value, that is, the decimal part. n and m are both positive integers greater than or equal to 1. Figure 1As shown, taking a 32-bit floating point (FP32) as an example, the 32-bit width includes 23 mantissa bits (bits 0-23), 8 exponent bits (bits 24-30), and 1 sign bit (bit 31).

[0040] The FRC operation is a commonly used floating-point instruction that takes any floating-point number x as input and outputs the fractional part of x as the result in floating-point format. If x is equal to INF or NAN, then FRC(x) equals NAN.

[0041] The following formula describes the calculation method when x is not equal to INF and NAN: FRC(x) = x - FLOOR(x); FLOOR is the floor function. The following examples demonstrate several typical methods for calculating FRC functions.

[0042] 1. x = +3.0f, FLOOR(x) = +3.0f, FRC(x) = x - FLOOR(x) = +0.0f, indicating that the decimal part of x is 0.

[0043] 2. x = -5.0f, FLOOR(x) = -5.0f, FRC(x) = x - FLOOR(x) = +0.0f, indicating that the decimal part of x is 0.

[0044] 3. x=+3.8f, FLOOR(x)=+3.0f, FRC(x)=x-FLOOR(x)=+0.8f.

[0045] 4. x = -3.8f, FLOOR(x) = -4.0f, FRC(x) = x - FLOOR(x) = +0.2f. It's important to note that the FRC result is always positive, so x < 0 means x consists of the sum of a negative integer and a positive decimal.

[0046] 5. x=±0.0f, FLOOR (x)=±0.0f, FRC(x)=x-FLOOR(x)=+0.0f.

[0047] 6. x=inf, FLOOR(x)=inf, FRC(x)=x-FLOOR(x)=NAN.

[0048] 7. x=NAN, FLOOR(x)=NAN, FRC(x)=x-FLOOR(x)=NAN.

[0049] In related technologies, such as Figure 2As shown, a separate FRC calculation unit is set up in the ALU to complete the calculation of the FRC function. A selector selects one of the calculation results from the FRC calculation unit and the calculation results from other calculation units for output.

[0050] The use of independent FRC computing units in related technologies has the following problems: 1. Independent FRC calculation units lead to an increase in circuit area; 2. Adding a selector on the critical path increases computation time; 3. The independent FRC computing unit leads to increased computational power consumption in Fused Multiply-Add (FMA).

[0051] This disclosure provides a floating-point number processing method that reuses the computational path of the multiply-accumulate unit (used for FMA operations) during calculation, enabling FRC operations without increasing power consumption or circuit overhead. The multiply-accumulate unit will be described below.

[0052] Suppose that the multiply-accumulate unit to be designed is used to calculate the multiplication and addition of three floating-point numbers. These three floating-point numbers are src0, src1, and src2, and the calculation method is defined as src0 * src1 + src2. Correspondingly, the sign bits of these three floating-point numbers are named sgn0, sgn1, and sgn2, the exponents are named exp0, exp1, and exp2, and the mantissas are named mat0, mat1, and mat2.

[0053] Figure 3 It is an FMA (Floating-Point Arithmetic) path that supports mixed operations of FP32 (32-bit floating-point numbers) and FP16 (16-bit floating-point numbers). Details are as follows: Figure 3 The source operand extraction module is used to extract the FP32 or FP16 data to be calculated from each input source operand.

[0054] Figure 3 The exponent adjustment module is used to adjust the exponent offset of each source operand according to the data format of the source operand, so that floating-point numbers of different formats are unified under the FP32 format.

[0055] Figure 3 The leading zero detection module in the src2 is used to calculate the number of leading zeros in the mantissa.

[0056] Figure 3 The exponential subtraction module in the code is used to calculate the difference between exp2 and exp01 (the sum of exp0 and exp1).

[0057] Figure 3 The window state detection module is used to detect whether the current instruction is running in state one, state two, state three, or state four.

[0058] Figure 3 The mantissa shift module in the code is used to right-shift mat2 based on the window state and the difference between exp2 and exp01.

[0059] Figure 3 The mantissa multiplication module is used to calculate mat0*mat1 to obtain mat01.

[0060] Figure 3 The addition exponent calculation module is used to select exp2 or exp01 as the exponent after exponent alignment, i.e., exp_add, according to the window state.

[0061] Figure 3 The window selection module is used to extract the parts addin0 and addin1 to be added and subtracted from mat2 and mat01 after displacement, according to the window state.

[0062] Figure 3 The mantissa addition module in the code is used to perform addition or subtraction operations on addin0 and addin1.

[0063] Figure 3 The leading zero prediction module in the code is used to calculate the number of leading zeros in the result after adding or subtracting addin0 and addin1.

[0064] Figure 3 The normalization operation module in the code is used to normalize the exponent and mantissa after addition.

[0065] The total bit width of the calculation window is mat_width_tmp*4+7 bits. The bit width of the addition window when the multiplication and addition operation is in state one and state two is mat_width_tmp*2+6 bits, and the bit width of the addition window when the multiplication and addition operation is in state three and state four is mat_width_tmp*2+6 bits.

[0066] like Figure 4 As shown, taking single-precision floating-point numbers as an example, mat_width_tmp is 23. In this case, the total bit width of the calculation window is 99 bits. The bit width of the addition window is 52 bits when the multiplication-addition operation is in state one and state two, and also 52 bits when the multiplication-addition operation is in state three and state four. From high to low, the calculation window is divided into three parts, each with a length of 26 bits (highest part), 50 bits (second highest part), and 23 bits respectively.

[0067] Initially, mat2 is placed at the highest position of the highest part of the calculation window, and mat01 is placed at the highest position of the second highest part of the calculation window. Then, according to the size relationship between exp2 and the multiply-accumulate unit, mat2 is shifted downwards within the calculation window.

[0068] If exp01+27-exp2<0, then exp2 is considered to be much greater than exp01, and mat2 is not shifted. Otherwise, mat2 needs to be shifted right by exp01+27-exp2 positions. After the shift, the mantissa mat_add is calculated.

[0069] State 1: If 0 > exp01 + 27 - exp2, then set addin0 = 0, and extract the highest and second-highest bits (51 bits) of mat2 from the shifted window as addin1. Then, perform addition or subtraction operations on addin0 and addin1 to obtain mat_add. Treat all mat01 bits as sticky bits. Correspondingly, select the addition exponent as exp_add = exp2.

[0070] State 2: If 26 > exp01 + 27 - exp2 >= 0, and the highest and second-highest bits of the shifted window (51 bits total) are truncated to mat01 as addin0 = 0, then the highest and second-highest bits of the shifted window (51 bits total) are truncated to mat2 as addin1. Then, addin0 and addin1 are added or subtracted to obtain mat_add. The untruncated mat01 bits in the second-highest part are considered sticky bits. Correspondingly, the addition exponent is chosen as exp_add = exp01 + 27. The highest and second-highest bits of the shifted window (51 bits total) are truncated to mat2 as addin1, that is, addin1 = shf_mat2[mat_width_tmp*4 + 6: mat_width_tmp*2 + 2].

[0071] State 3: If 76 > exp01 + 27 - exp2 >= 26, then truncate the second-highest portion of the window after displacement (50 bits total, mat01) as addin0, and truncate the second-highest portion of the window after displacement (50 bits total, mat2) as addin1. Then perform addition or subtraction operations on addin0 and addin1 to obtain mat_add. Treat mat2 in the lowest part of the window as sticky bits. And correspondingly, choose the addition exponent as exp_add = exp01.

[0072] State 4: If exp01 + 27 - exp2 >= 76, then extract the second-highest portion of the window after displacement, totaling 50 bits (mat01), as addin0, and set addin1 = 0. Then, perform addition or subtraction operations on addin0 and addin1 to obtain mat_add. Treat all mat2 bits as sticky bits. Correspondingly, select the addition exponent as exp_add = exp01.

[0073] Finally, after checking for leading zeros in the mantissa of the addition, the mantissa and exponent of the addition are adjusted according to the specific situation to obtain the floating-point result after normalization.

[0074] The floating-point number processing method provided in the embodiments of this disclosure will be described in detail below.

[0075] This disclosure provides a floating-point number processing method, which can be executed by a processor of a computer device. The computer device refers to a device with data processing capabilities, such as a server, laptop, tablet, desktop computer, smart TV, set-top box, or mobile device (e.g., mobile phone, portable video player, personal digital assistant, dedicated messaging device, portable gaming device). Figure 5 This is a schematic diagram illustrating the implementation flow of a floating-point number processing method provided in an embodiment of this disclosure, as shown below. Figure 5 As shown, the method includes the following steps 501 to 502: Step 501: In response to the first signal for the target floating-point number, if the target floating-point number does not meet the preset conditions, determine the state of the multiplication-addition operation that matches the target floating-point number based on the size relationship between the target floating-point number and the floating-point number threshold.

[0076] The first signal is used to obtain the fractional part of the target floating-point number. For example, the first signal can be a signal used to perform an FRC operation on the target floating-point number. The target floating-point number is any floating-point number that needs to be processed.

[0077] The preset conditions are used to determine whether the floating-point value corresponding to the floating-point number can be directly output. For example, the floating-point value can include: 0, NAN. Here, NAN means that it is not a number, that is, it is not a valid numeric value; this situation usually occurs in certain mathematical operations, such as 0 divided by 0, or certain illegal mathematical operations, the result of which is NAN.

[0078] In one feasible implementation, the preset conditions may include: a condition for determining whether to directly output 0, and a condition for determining whether to directly output the special value NAN.

[0079] The target floating-point number does not meet the preset conditions, meaning that the target floating-point number is neither 0, INF, NaN, nor a pure integer; that is, the target floating-point number can be a pure decimal or a floating-point number that contains both integers and decimals. The floating-point number threshold is used to determine the status of multiplication and addition operations that match the floating-point number.

[0080] In some implementations, step 501 can be specifically implemented as follows: if the target floating-point number meets the floating-point threshold, it is determined that it meets the state one of multiplication and addition operations. If the target floating-point number does not meet the floating-point threshold, the number of right shifts of the target floating-point number is determined; the state of the multiplication operation matching the target floating-point number is determined based on the number of right shifts.

[0081] In some implementations, the specific way to "determine the state of the product operation matching the target floating-point number based on the number of right shifts" can be: determine the state of the product operation matching the target floating-point number based on the relationship between the number of right shifts and the number of bits threshold.

[0082] Furthermore, the specific implementation of "determining the state of the product operation matching the target floating-point number based on the relationship between the number of right shifts and the number of bits threshold" can be as follows: if the number of right shifts meets the number of bits threshold, the state of the product operation matching the target floating-point number is determined as the second target state; if the number of right shifts does not meet the number of bits threshold, the state of the product operation matching the target floating-point number is determined as the third target state.

[0083] Step 502: Based on the state of the multiplication-addition operation, output the fractional part of the target floating-point number.

[0084] In some implementations, step 502 can be specifically implemented as follows: If the target floating-point number meets the floating-point threshold, it is determined that it meets the state one of multiplication and addition operation, and the target floating-point number is processed according to the state one of multiplication and addition operation, and the decimal part of the target floating-point number is output. If the target floating-point number does not meet the floating-point threshold, the number of right shifts of the target floating-point number is determined; the state of the product operation matching the target floating-point number is determined according to the number of right shifts; the target floating-point number is processed according to the state of the product operation matching the target floating-point number, and the decimal part of the target floating-point number is output.

[0085] In this embodiment, when the target floating-point number does not meet preset conditions, the state of the multiplication-addition operation is reused to implement the FRC operation for obtaining the fractional part of the floating-point number. Thus, by reusing the computational path of the multiplication-addition operation to implement the FRC operation, the circuit area consumption of setting up a separate FRC calculation unit is saved; by directly reusing the computational path of the multiplication-addition operation, the computational power consumption of the FRC operation is saved, and the processing efficiency is improved. Furthermore, when reusing the state of the multiplication-addition operation to implement the FRC operation, the relationship between the target floating-point number and the floating-point number threshold is considered, which can improve the processing accuracy of the FRC operation.

[0086] This disclosure provides a floating-point number processing method, which can be executed by the processor of a computer device. For example... Figure 6 As shown, the method includes the following steps 601 to 603: Step 601: In response to the first signal for the target floating-point number, if the target floating-point number does not meet the preset condition, determine the state of the multiplication-addition operation that matches the target floating-point number based on the size relationship between the target floating-point number and the floating-point number threshold.

[0087] Step 602: Based on the state of the multiplication-addition operation, output the fractional part of the target floating-point number.

[0088] Here, steps 601 to 602 correspond to the aforementioned steps 501 to 502, and can be implemented with reference to the specific implementation methods of the aforementioned steps 501 to 502.

[0089] Step 603: If the target floating-point number meets the preset conditions, output the floating-point value corresponding to the target floating-point number.

[0090] In some implementations, determining that a target floating-point number meets a preset condition can be achieved as follows: when the target floating-point number is 0, or when the fractional part of the target floating-point number has no valid value but the integer part has a valid value, the target floating-point number is determined to meet a first preset condition; when the target floating-point number is infinity (INF), or when the target floating-point number is not a number (NaN), the target floating-point number is determined to meet a second preset condition; the preset condition includes the first preset condition and the second preset condition.

[0091] If the fractional part of the target floating-point number has no valid value but the integer part has a valid value, it means that the target floating-point number is a pure integer.

[0092] The first preset condition is used to determine whether 0 can be directly output. For example, the first preset condition can be whether the floating-point number is 0 or whether the floating-point number is a pure integer. If the target floating-point number is 0, then the target floating-point number is determined to satisfy the first preset condition; if the target floating-point number is a pure integer, then the target floating-point number is determined to satisfy the first preset condition.

[0093] The second preset condition is used to determine whether to directly output NaN. For example, the second preset condition can be that the floating-point number is INF (infinity) or NaN (not a number). If the target floating-point number is INF, then the target floating-point number is determined to meet the second preset condition; if the target floating-point number is NaN, then the target floating-point number is determined to meet the second preset condition.

[0094] In some implementations, the specific way to determine whether the target floating-point number is 0 can be: if the mantissa and exponent of the target floating-point number are both equal to 0, then the target floating-point number is determined to be 0.

[0095] In some implementations, the specific way to determine whether the target floating-point number is a pure integer is as follows: if the target floating-point number is greater than the exponent threshold, then the target floating-point number is determined to be a pure integer; wherein, the exponent threshold is determined based on the exponent bit width and mantissa bit width of the data format of the floating-point number supported by the multiplication and addition operation.

[0096] For example, if multiply-accumulate operations support single-precision floating-point (FP32) calculations, and the single-precision floating-point number has an 8-bit exponent and a 23-bit mantissa, then the exponent offset of the target floating-point number is 2. 8 -1, the exponential threshold is 2 8 -1 + 23 - 1 = 149. If the exponent of the target floating-point number is greater than 149 (the exponent threshold), then the integer part of the target floating-point number is determined to have a valid value, but the fractional part does not have a valid value; that is, it indicates that the target floating-point number is a pure integer.

[0097] In some implementations, step 503 can be implemented as follows: when the target floating-point number meets the first preset condition, output a first floating-point value; when the target floating-point number meets the second preset condition, output a second floating-point value.

[0098] The first floating-point value is 0.0, and the second floating-point value is NaN.

[0099] For example, if the target floating-point number is 0 or a pure integer, output 0 directly. If the target floating-point number is INF or NaN, output NaN directly.

[0100] In this embodiment, the processing of FRC operations for obtaining the fractional part of a floating-point number is divided into two cases: one where the constant corresponding to the floating-point number can be directly output, and the other where the multiplication-accumulation module needs to be reused for processing. These two cases are distinguished by preset conditions. When the target floating-point number meets the preset conditions, the constant corresponding to the target floating-point number is directly output. When the target floating-point number does not meet the preset conditions, the state of the multiplication-accumulation operation is reused to implement the FRC operation. Thus, by reusing the computational path of the multiplication-accumulation operation to implement the FRC operation, the circuit area consumption of setting up a separate FRC computation unit is saved. During processing, the computational path of the multiplication-accumulation operation is directly reused without using a separate FRC computation unit, which saves computational power consumption and improves processing efficiency. Furthermore, when reusing the state of the multiplication-accumulation operation to implement the FRC operation, both the size relationship between the target floating-point number and the floating-point number threshold, and the size relationship between the number of bits shifted right of the target floating-point number and the number of bits threshold are considered, further improving the processing accuracy of the FRC operation.

[0101] In some embodiments, the step 601, "determining the state of the multiplication-addition operation matching the target floating-point number based on the size relationship between the target floating-point number and the floating-point number threshold," can be implemented through the following steps 6011 or 6012: Step 6011: If the target floating-point number is greater than the first floating-point number threshold and less than the second floating-point number threshold, determine the state of the multiplication-addition operation as the first target state.

[0102] The floating-point threshold includes the first floating-point threshold and the second floating-point threshold; the calculation window in the first target state includes the mantissa of the target floating-point number.

[0103] The first floating-point threshold is 0.0, and the second floating-point threshold is 1.0. The first target state refers to... Figure 4 State one of multiplication and addition operations. From Figure 4 As can be seen from the data, the first target state includes all the mantissas of the target floating-point number. The target floating-point number is greater than the first floating-point threshold and less than the second floating-point threshold, indicating that the target floating-point threshold meets the floating-point threshold requirements.

[0104] For example, if 0.0f < target floating-point number < +1.0f, then the target floating-point number is determined to be a decimal, and should be output as is. Therefore, the state of the multiplication-addition operation matching the target floating-point number is the first target state. Figure 4 (State 1 in the middle).

[0105] Step 6012: If at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, determine the state of the multiplication-addition operation based on the relationship between the number of bits shifted right of the target floating-point number and the number of bits threshold.

[0106] The right shift bit is used to retain the mantissa portion of the target floating-point number whose exponent is less than or equal to 0 in the calculation window.

[0107] If the target floating-point number is less than the first floating-point threshold or greater than the second floating-point threshold, it means that the target floating-point number does not meet the floating-point threshold. The right shift bits are used both to determine the status of the multiplication-addition operation that matches the target floating-point number and to retain the mantissa portion of the target floating-point number whose exponent is less than or equal to 0 in the calculation window.

[0108] Based on the above technical solution, the first floating-point threshold and the second floating-point threshold can be used to determine whether the target floating-point number is a decimal. If the target floating-point number is greater than the first floating-point threshold and less than the second floating-point threshold, it is determined that the target floating-point number is a decimal. In this case, the target floating-point number should be output as is, and the state of the multiplication-addition operation should be considered the first target state. Figure 4 In state one, the target floating-point number is processed. If the target floating-point number is less than the first floating-point threshold or greater than the second floating-point threshold, it is determined that the target floating-point number is not entirely a decimal. In this case, the state of the multiplication-addition operation corresponding to the target floating-point number needs to be further determined based on the relationship between the number of bits shifted right and the bit threshold. In this way, determining the state of the multiplication-addition operation hierarchically can improve the processing efficiency of FRC operations.

[0109] In some implementations, step 6012 can be achieved by the following steps 6012a to 6012c: Step 6012a: Determine the number of bits to right shift the target floating-point number based on the mantissa width of the target floating-point number, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the first bit width threshold.

[0110] During multiplication and addition operations, mat2 is shifted to the right based on the state of the calculation window; similarly, when reusing the calculation path of multiplication and addition operations to process FRC operations, the target floating-point number also needs to be shifted to the right.

[0111] like Figure 4 As shown, in the initial state, mat2 is placed in the highest position of the calculation window, and then the right shift number is calculated according to the value of exp2, so as to retain the mantissa part of the target floating-point number whose exponent is less than or equal to 0 in the calculation window.

[0112] In some implementations, the specific method for "determining the number of right shifts of the target floating-point number based on the mantissa width of the target floating-point number, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the first width threshold" can be as follows: adjust the mantissa of the target floating-point number according to the exponent offset of the target floating-point number to obtain the first right shift; perform an addition operation on the mantissa width and the first width threshold of the target floating-point number to obtain the second right shift; and perform a subtraction operation on the second right shift and the first right shift to obtain the third right shift.

[0113] For example, using single-precision floating-point numbers as an example, refer to... Figure 4 The mantissa width of the target floating-point number is 23, the first bit width threshold is the extended bit width of 3, and the exponent offset of the target floating-point number is 2. 8 -1; At this point, the number of bits shifted to the right should be 23 + 3 - (exp2 - (2 8 -1))=153-exp2.

[0114] In some implementations, the bit width threshold can be determined by performing an addition operation on the bit width of the calculation window in states one and two, and the bit width of the calculation window in states three and four, and then removing the overlapping bit width of the two calculation windows to obtain the bit width threshold.

[0115] For example, using single-precision floating-point numbers as an example, refer to... Figure 4 The bit width of the calculation window in states one and two, and the bit width of the calculation window in states three and four are all 23*2+6. The bit width of the two windows overlaps by 28. At this time, the bit threshold is: (23*2+6)*2-28=76.

[0116] Step 6012b: If the number of right shifts is less than the number of bits threshold, output the state of the multiplication-addition operation as the second target state; the calculation window in the second target state contains the valid value of the mantissa portion of the corresponding exponent which is less than or equal to 0.

[0117] The second target state refers to Figure 4 State three of the multiplication and addition operation.

[0118] If the right shift bits are less than the bit threshold, it means that after the target floating-point number is right-shifted by the number of bits, states three and four will still contain the mantissa of the target floating-point number. Figure 7 State 3 is shown; at this time, the calculation window under State 3 and State 4 contains the valid values ​​of the mantissa portion of the corresponding exponent less than or equal to 0 (exp≤0).

[0119] For example, taking a single-precision floating-point number as an example, the right shift bits are 153 - exp2, and the bit threshold is 76. If the right shift bits are less than 76, then the state of the multiply-accumulate operation that matches the target floating-point number is determined to be state three (second target).

[0120] Step 6012c: If the number of right shifts is greater than or equal to the number of bits threshold, output the state of the multiplication-addition operation as the third target state; the calculation window in the third target state does not contain the valid value of the mantissa part with the corresponding exponent less than or equal to 0.

[0121] The third objective state refers to Figure 4 State four of multiplication and addition operations.

[0122] If the right shift by a number of bits is greater than or equal to the bit threshold, it means that after the target floating-point number is right-shifted by the number of bits, states three and four do not contain the mantissa of the target floating-point number. Figure 7 State four is shown.

[0123] For example, taking a single-precision floating-point number as an example, the right shift bits are 153 - exp2, and the bit threshold is 76. If the right shift bits are greater than or equal to 76, then the state of the multiplication-addition operation that matches the target floating-point number is determined to be state three (second target).

[0124] Based on the above technical solution, the state of the multiplication and addition operation corresponding to the target floating-point number can be clearly determined according to the relationship between the number of bits shifted to the right of the target floating-point number and the bit threshold. Then, the FRC operation on the target floating-point number can be realized based on the state of the multiplication and addition operation corresponding to the target floating-point number.

[0125] In some implementations, step 602 above can be achieved by the following steps 6021 to 6022: Step 6021: Based on the state of the multiplication-addition operation, determine the mantissa and exponent of the addition.

[0126] In some implementations, step 6021 can be specifically implemented as follows: when the target floating-point number is a pure decimal (the target floating-point number is greater than the first floating-point number threshold and less than the second floating-point number threshold), the target floating-point number is processed according to the state one of multiplication and addition to obtain the addition mantissa; the exponent of the target floating-point number is used as the addition exponent.

[0127] In some implementations, step 6021 can also be implemented as follows: when the target floating-point number is less than the first floating-point number threshold and the number of bits shifted to the right is less than the number of bits threshold, the target floating-point number is processed according to the state three of the multiplication-addition operation to obtain the mantissa of the addition; the exponent offset of the target floating-point number is used as the addition exponent.

[0128] In some implementations, step 6021 can also be implemented as follows: when the target floating-point number is greater than the first floating-point number threshold and the number of bits shifted to the right is less than the number of bits threshold, the target floating-point number is processed according to the state three of the multiplication-addition operation to obtain the mantissa of the addition; the exponent offset of the target floating-point number is used as the addition exponent.

[0129] In some implementations, step 6021 can also be implemented as follows: when the target floating-point number is less than the first floating-point number threshold and the number of bits shifted to the right is greater than the number of bits threshold, the target floating-point number is processed according to the state four of the multiplication-addition operation to obtain the mantissa of the addition; the exponent offset of the target floating-point number is used as the addition exponent.

[0130] In some implementations, step 6021 can also be implemented as follows: when the target floating-point number is greater than the first floating-point number threshold and the number of bits shifted to the right is greater than the number of bits threshold, the target floating-point number is processed according to the state four of the multiplication-addition operation to obtain the mantissa of the addition; the exponent offset of the target floating-point number is used as the addition exponent.

[0131] Step 6022: Based on the sign bit of the target floating-point number, the mantissa of the addition, and the exponent of the addition, output the fractional part of the target floating-point number.

[0132] In one feasible implementation, the sign bit, mantissa, and exponent of the target floating-point number are organized into a floating-point data format through a normalization module to obtain the output result of the target instruction.

[0133] In some embodiments, when the state of the multiplication-addition operation is the first target state, the above step 6021 can be implemented by the following steps A1 to A4: Step A1: When the state of the multiplication-addition operation is the first target state, assign the first floating-point value to the first addend of the calculation window in the first target state.

[0134] The first floating-point value is 0. For example, the state in the multiplication-addition operation is the first target state ( Figure 4 In state one, assign 0 to Figure 4 In state one, addmin0 (the first addend).

[0135] Step A2: Place the mantissa of the target floating-point number in the highest bit of the calculation window in the first target state, and truncate the first bit from the highest bit and assign it to the second addend of the calculation window in the first target state; the first bit is determined based on the bit width of the calculation window in the first target state, and the calculation window in the first target state contains the mantissa of the target floating-point number.

[0136] The first digit is used to extract the valid part of the mantissa of the target floating-point number after it has been arranged.

[0137] Taking single-precision floating-point numbers as an example, when the state of the multiplication and addition operation that matches the target floating-point number is state one, the truncation bits of addin1 are 51 bits from high to low in the calculation window of the first target state.

[0138] For example, such as Figure 7 The state shown is the first target state in the multiplication-addition operation. Figure 4 In state one, the mantissa of the target floating-point number is placed as mat2 in the highest bit of the calculation window, and 51 bits are truncated from the highest bit and assigned to it. Figure 4 In state one, addmin1 (the second addend).

[0139] Step A3: Determine the mantissa based on the first addend and the second addend.

[0140] In some implementations, the state during the multiplication-addition operation is the first target state ( Figure 4 In state one, the first addend and the second addend are added to obtain the mantissa.

[0141] For example, the state in the multiplication-addition operation is the first target state ( Figure 4 In state one, the first addend is 0, the second addend is mat2, and the mantissa of the addition is mat2+0.

[0142] Step A4: Use the exponent of the target floating-point number as the addition exponent.

[0143] For example, the state in the multiplication-addition operation is the first target state ( Figure 4 In state one, set the addition exponent exp_add=exp2.

[0144] The FRC operation operates on a single floating-point number, while the multiply-accumulate operation operates on three floating-point numbers. During processing, the FRC operation's operand is treated as the third floating-point number in the multiply-accumulate operation. Figure 3 In src2), the first floating-point number ( Figure 3 src0 in the second floating-point number ( Figure 3 In the implementation, if the target floating-point number is a pure decimal, then the state of the multiplication-addition operation is state one (…). Figure 4 In the method described in State 1, addin0=0 is set, the target floating-point number is placed in the highest bit of the calculation window in State 1, and mat2 within the first 51 bits is used as addin1. Then, the addition operation of addin0 and addin1 is performed to obtain mat_add (the mantissa of the addition). Here, all mat01 are regarded as sticky bits, and the addition exponent is selected as exp_add=exp2.

[0145] In some embodiments, when the multiplication-addition operation is in the second target state, step 6021 can be implemented by the following steps B1 to B3: Step B1: When the multiplication-addition operation is in the second target state, the mantissa of the target floating-point number is placed in the calculation window of the second target state according to the number of right shifts of the target floating-point number.

[0146] If the target floating-point number is less than the first floating-point threshold and the number of right shift bits is less than the number of bits threshold, or if the target floating-point number is greater than the first floating-point threshold and the number of right shift bits is less than the number of bits threshold, then it is processed according to the state of multiplication and addition operation as state three. The processing logic is to extract only the valid value of the mantissa part of mat2 with an exponent less than or equal to 0 (exp≤0) through the calculation window, and assign the first addend of the calculation window according to the size relationship between the number of right shift bits and the number of bits threshold.

[0147] like Figure 7 As shown in state three, based on the number of right shifts of the target floating-point number, the mantissa of the target floating-point number is placed in the calculation window under the second target state (state three), so that the bit corresponding to the exponent 0 in mat2 is shifted to the highest bit of the calculation window under the second target state. At this time, the calculation window under the second target state only retains the valid value of the mantissa part corresponding to the exponent of mat2 that is less than or equal to 0 (exp≤0).

[0148] Step B2: Determine the addition mantissa based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number.

[0149] In some implementations, when the target floating-point number is negative, step B2 can be implemented as follows: if the target floating-point number is determined to be negative based on the sign bit of the target floating-point number, the third floating-point value is assigned to the first addend of the calculation window in the second target state; the second digit of the mantissa of the target floating-point number after placement is truncated from the high digit downwards and assigned to the second addend of the calculation window in the second target state; the first addend and the second addend are subtracted to obtain the mantissa.

[0150] The third floating-point value is 1 << 49. The second bit is the second highest 50 bits.

[0151] For example, when the target floating-point number is negative, set addin0 to 1<<49, extract all 50 bits of the second highest part of mat2 after it is right-shifted within the calculation window, and subtract addin1 from addin0 to obtain the mantissa of the addition.

[0152] In some implementations, when the target floating-point number is positive, step B2 can be implemented as follows: if the target floating-point number is determined to be positive based on the sign bit of the target floating-point number, the first floating-point value is assigned to the first addend of the calculation window in the second target state; the second bit excluding the highest bit of the mantissa of the target floating-point number after it is placed is truncated from the high bit downwards and assigned to the second addend of the calculation window in the second target state; the first addend and the second addend are added to obtain the mantissa.

[0153] The first floating-point value is 0. The third bit is the lower 49 bits of the second-highest part (the highest bit is discarded).

[0154] For example, when the target floating-point number is positive, set addin0 to 0, extract the lower 49 bits of the second highest part of mat2 after it is right-shifted within the calculation window, and then addin0+addin1 to obtain the mantissa of the addition.

[0155] Step B3: Determine the addition exponent based on the exponent offset of the target floating-point number.

[0156] In some implementations, step B3 can be specifically implemented by using the exponent offset of the target floating-point number as the addition exponent.

[0157] In some embodiments, when the multiplication-addition operation is in the third target state, step 6021 can be implemented by the following steps C1 to C3: Step C1: When the multiplication-addition operation is in the third target state, the mantissa of the target floating-point number is placed in the calculation window of the third target state according to the number of right shifts of the target floating-point number.

[0158] If the target floating-point number is less than the first floating-point threshold and the number of bits shifted to the right is greater than the number of bits threshold, or if the target floating-point number is greater than the first floating-point threshold and the number of bits shifted to the right is greater than the number of bits threshold, then it is processed according to the state of multiplication and addition operation as state four. The processing logic is that mat2 is very small at this time, which has exceeded the calculation window under state four, and can be regarded as 0; however, at this time, it is still necessary to assign a value to the first addend of the calculation window according to the relationship between the number of bits shifted to the right and the number of bits threshold.

[0159] like Figure 7 As shown in state four, after right-shifting the target floating-point number according to the number of right shifts, the mantissa of the target floating-point number will exceed the calculation window under the third target state (state four).

[0160] Step C2: Determine the addition mantissa based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number.

[0161] In some implementations, when the target floating-point number is negative, step B2 can be implemented as follows: if the target floating-point number is determined to be negative based on the sign bit of the target floating-point number, assign the third floating-point value to the first addend of the calculation window in the third target state; truncate the second digit of the mantissa of the target floating-point number after placement from the high bit downwards, and assign it to the second addend of the calculation window in the third target state; perform subtraction on the first addend and the second addend to obtain the mantissa.

[0162] For example, such as Figure 7 In the fourth state shown, when the multiplication and addition operation matching the target floating-point number is in the third target state (state four), the placed target floating-point number has exceeded the calculation window under state four. At this time, the second addend addedin1 is 0. When the target floating-point number is negative, addin0 is set to 1<<49, and addin0-addin1 is performed to obtain the mantissa of the addition.

[0163] In some implementations, when the target floating-point number is positive, step B2 can be implemented as follows: if the target floating-point number is determined to be positive based on the sign bit of the target floating-point number, the first floating-point value is assigned to the first addend of the calculation window in the third target state; the second bit excluding the highest bit of the mantissa of the target floating-point number after it is placed is truncated from the high bit downwards and assigned to the second addend of the calculation window in the third target state; the first addend and the second addend are added to obtain the mantissa.

[0164] For example, such as Figure 7 In the fourth state shown, when the multiplication and addition operation matching the target floating-point number is in the third target state (state four), the placed target floating-point number has exceeded the calculation window under state four. At this time, the second addend addedin1 is 0. When the target floating-point number is positive, the first addend addedin0 is set to 0, and addin0+addin1 is performed to obtain the mantissa of the addition.

[0165] Step C3: Determine the addition exponent based on the exponent offset of the target floating-point number.

[0166] In some implementations, step C3 can be specifically implemented by using the exponent offset of the target floating-point number as the addition exponent.

[0167] This disclosure provides a processor, such as... Figure 8 and Figure 9 As shown, Figure 8 The diagram mainly illustrates the various units required to implement FRC operations by using the multiplexing multiplication-addition computational path. Figure 9The main focus is on a more specific structural configuration, whereby the processor includes: a multiply-accumulate unit; The multiply-accumulate unit is used to determine the state of the multiply-accumulate operation that matches the target floating-point number based on the size relationship between the target floating-point number and the floating-point number threshold when the target floating-point number does not meet the preset conditions; and to output the decimal part of the target floating-point number based on the state of the multiply-accumulate operation.

[0168] In some embodiments, such as Figure 8 and Figure 9 As shown, the multiply-accumulate operation unit includes: a window state detection module; The window state detection module is used to output the state of the multiplication-addition operation as a first target state when the target floating-point number is greater than a first floating-point number threshold and less than a second floating-point number threshold; the floating-point number threshold includes the first floating-point number threshold and the second floating-point number threshold; the calculation window in the first target state includes the mantissa of the target floating-point number.

[0169] In some embodiments, the window state detection module is further configured to output the state of the multiplication-addition operation as a second target state when at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, and the number of right shift bits is less than the number of bits threshold; the calculation window in the second target state contains the valid values ​​of the mantissa portion of the target floating-point number whose exponent is less than or equal to 0.

[0170] In some embodiments, the window state detection module is further configured to output the state of the multiplication-addition operation as a third target state when at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, and the number of right shift bits is greater than or equal to the number of bits threshold; the calculation window in the third target state does not contain a valid value of the mantissa portion of the target floating-point number whose corresponding exponent is less than or equal to 0.

[0171] In some embodiments, such as Figure 8 and Figure 9 As shown, the processor includes: a displacement value calculation unit; the input port of the displacement value calculation unit is connected to the input port of the multiply-accumulate operation unit, and the output port of the displacement value calculation unit is connected to the input port of the window state detection module; the displacement value calculation unit is used to determine the number of right shifts of the target floating-point number based on the mantissa bit width of the target floating-point number, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the first bit width threshold.

[0172] In some embodiments, such as Figure 8 and Figure 9As shown, the multiplication-addition unit further includes: an addition exponent calculation module; the input port of the addition exponent calculation module is connected to the output port of the window state detection module; the addition exponent calculation module is used to determine the addition exponent based on the state of the multiplication-addition operation; the addition exponent is used to determine the fractional part of the target floating-point number; when the state of the multiplication-addition operation is a first target state, the addition exponent is the exponent of the target floating-point number; when the state of the multiplication-addition operation is a second target state or a third target state, the addition exponent is determined based on the exponent offset of the target floating-point number.

[0173] In some embodiments, such as Figure 8 and Figure 9 As shown, the multiplication-addition unit further includes: an addition mantissa calculation module; the input port of the addition mantissa calculation module and the input port of the addition exponent calculation module are connected in parallel to the output port of the window state detection module; the addition mantissa calculation module is used to determine the addition mantissa based on the state of the multiplication-addition operation; the addition mantissa is used to determine the fractional part of the target floating-point number; when the state of the multiplication-addition operation is a first target state, the addition mantissa is determined based on the first addend and the second addend of the calculation window in the first target state; in the first target state, the first addend is a first floating-point value, and the second addend is the first number of bits truncated from the highest bit after the mantissa of the target floating-point number is placed in the highest bit of the calculation window; the first number of bits is determined based on the bit width of the calculation window in the first target state; when the state of the multiplication-addition operation is a second target state or a third target state, the addition mantissa is determined based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number, and the mantissa of the target floating-point number after placement is placed in the calculation window according to the right shift of the target floating-point number.

[0174] In some embodiments, such as Figure 8 and Figure 9 As shown, the processor further includes: a selector; the selector is connected to the input of the processor and the output of the multiply-accumulate unit respectively; the selector is used to output the floating-point value corresponding to the target floating-point number when the target floating-point number meets the preset condition; and to output the decimal part of the target floating-point number when the target floating-point number does not meet the preset condition.

[0175] The following describes the application of the floating-point number processing method provided in this disclosure in a real-world scenario, using single-precision floating-point numbers as an example.

[0176] The embodiments disclosed herein embed FRC operations into the algorithm of FMA instructions, implementing both FRC and FMA instructions with the same set of circuitry without increasing power consumption or circuit overhead.

[0177] In the embodiments of the present disclosure, src2 of FMA is used as the input of the FRC operation, and src0 and src1 are set to 0. The FRC operation is calculated using the FMA path according to the following method: If both exp2 and mat2 are equal to 0, it is determined that src2 is equal to 0, and 0 can be directly output.

[0178] Otherwise, if src2 is INF or NAN, NAN can be directly output.

[0179] If the corresponding exponents of all mat2 are greater than or equal to 0, it is considered that this floating-point number has no fractional part, and 0 can be directly output. Taking single-precision floating-point numbers as an example, if exp2 > 149, it is determined that src2 has no fraction, and 0 is directly output.

[0180] For the cases other than the above three, the FMA path needs to be reused to calculate the FRC result.

[0181] If 0.0f < src2 < +1.0f, that is, all of src2 are fractions, src2 should be output as it is. Therefore, mat2 is placed at the highest bit of the calculation window, the right shift bit number of mat2 is set to 0, and the addition exponent exp_add = exp2 is set, and it is determined that it belongs to state one of the FMA calculation path. According to state one of the FMA calculation path, after truncation, addin0 is equal to 0, that is, the mantissa addition is mat2 + 0, and after normalization, src2 will be output as it is finally.

[0182] If it is not 0.0f < src2 < +1.0f, it is necessary to determine that it belongs to state three or state four of the FMA calculation path, and it is stipulated that the highest bit corresponding exponent of the calculation window truncated according to state three or state four of the FMA calculation path is 0. According to the requirement that the high-order exponent of the calculation window is 0, mat2 needs to be right-shifted to achieve exponent alignment. Initially, mat2 is placed at the highest bit of the calculation window, and then the right shift bit number is calculated according to the value of exp2. Taking single-precision floating-point numbers as an example, the right shift bit number should be equal to 153 - exp2. If the right shift bit number is less than 76, the window is set to state three, otherwise the window is set to state four. Whether it is state three or state four, exp_add needs to be set to 127 (corresponding to the real exponent of 0). After the right shift of mat2, the part of mat2 with a corresponding exponent greater than 0 is left in the highest part of the window, and through window truncation, only the part of mat2 with a corresponding exponent less than or equal to 0 is retained.

[0183] If src2 is positive, following the window truncation methods of states three and four, addin0 is truncated to 0, and addin1 is truncated to the lower 49 bits of the second highest part of mat2 after right shift within the window (discarding the highest bit), and then addition is performed. After normalization, the FRC calculation result is obtained.

[0184] If src2 is negative, following the window truncation methods of states three and four, addin1 is truncated to the second-highest 50 bits of mat2 shifted right within the window, and addin0 is set to 1<<49, then addin0-addin1 is subtracted. After normalization, the FRC calculation result is obtained.

[0185] In summary, the approach to implementing FRC operations in this disclosed embodiment involves the following steps: 1. Determine if src2 is a special value that can be directly output, such as 0, NAN, INF, or a pure positive number. If so, directly output the corresponding floating-point value.

[0186] 2. Set src0 and src1 to 0, and place mat2 at the highest position in the window.

[0187] 3. If src2 is a positive decimal, then no shifting is required.

[0188] 4. If src2 is not a positive decimal, set the highest exponent of the second-highest part of the window to 0, and shift mat2 to the right to align the exponent.

[0189] 5. If src2 is positive, the lower 49 bits of the second highest part of the window are truncated for addition and subtraction calculations. If src2 is negative, all 50 bits of the second highest part of the window are truncated, and addin0 is set to 1<<49 before the addin0-addin1 operation is performed.

[0190] 6. After setting up exp_add, perform the normalization operation.

[0191] In order to Figure 3 FRC operations are embedded in the FMA pathway in this disclosure embodiment. Figure 3 The circuit structure shown has the following modules added, such as Figure 8 and Figure 9 As shown.

[0192] The FRC operation floating-point value output detection module is used to detect whether src2 is 0, NaN, or INF. If src2 is 0, then 0 should be output. If src2 is NaN or INF, then NaN should be output.

[0193] The selector is used to select the corresponding floating-point value for output when the floating-point value output detection module of the FRC operation detects that a floating-point value needs to be output; otherwise, it selects the result from the normalization module. In fact, the FMA instruction usually also needs to output floating-point values ​​such as 0, INF, and NAN, and this selector does not add any circuit overhead.

[0194] The FRC operation displacement calculation module calculates the value of right shifting mat2 in the FRC operation. If mat2 is a positive decimal, it sets s2_pos_frc=1 and outputs frc_shf_val=0; otherwise, it outputs frc_shf_val=153-exp2. It also sends s2_pos_frc and frc_shf_val to the window detection module to modify the window detection result. The sign bit s2_sgn of src2 is sent to the window selection module to set addin0 and addin1. When performing the FRC operation, the window state detection module sets the window state to state one upon receiving s2_pos_frc=1; otherwise, if frc_shf_val<76, it sets the window state to state three; if frc_shf_val>=76, it sets the window state to state four. When performing the FRC operation, the addition exponent calculation module sets exp_add = exp2 upon receiving s2_pos_frc=1; otherwise, it sets exp_add=127. When performing FRC operations, if s2_pos_frc=1, then mat2 is not shifted to the right; otherwise, the mantissa shifting module shifts mat2 to the right according to frc_shf_val.

[0195] It should be noted that the embodiments disclosed herein can achieve at least the following technical effects: 1. The embodiments of this disclosure save the area of ​​a separate FRC computing unit by embedding FRC operations into the FMA path.

[0196] 2. In this embodiment of the present disclosure, since a separate FRC calculation unit is not used, the power consumption of this part of the circuit is saved when calculating FRC operations.

[0197] It should be noted that, in the embodiments of this disclosure, if the above-described floating-point number processing method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this disclosure, or the part that contributes to related technologies, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk. Thus, the embodiments of this disclosure are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0198] This disclosure provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0199] This disclosure provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium may be transient or non-transient.

[0200] This disclosure provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a computer device, a processor in the computer device performs some or all of the steps in the above-described method.

[0201] This disclosure provides a computer program product comprising a computer program that, when read and executed by a computer, implements some or all of the steps in the above-described method. The computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied in a computer storage medium; in other embodiments, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0202] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referenced interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this disclosure, please refer to the descriptions of the method embodiments of this disclosure for understanding.

[0203] It should be noted that, Figure 10 This is a schematic diagram of a hardware entity of a computer device in an embodiment of this disclosure, such as... Figure 10 As shown, the hardware entity of the computer device 1000 includes: a processor 1001, a communication interface 1002, and a memory 1003, wherein: Processor 1001 typically controls the overall operation of computer device 1000.

[0204] The communication interface 1002 enables computer devices to communicate with other terminals or servers via a network.

[0205] The memory 1003 is configured to store instructions and applications executable by the processor 1001, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 1001 and various modules in the computer device 1000. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 1001, the communication interface 1002, and the memory 1003 can be performed via bus 1004.

[0206] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0207] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0208] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0209] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0210] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0211] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0212] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0213] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A processor, characterized in that, The processor includes: a multiply-accumulate unit; The multiply-accumulate unit is used to respond to a first signal for a target floating-point number, and when the target floating-point number does not meet a preset condition, to determine the state of a multiply-accumulate operation that matches the target floating-point number based on the size relationship between the target floating-point number and a floating-point number threshold; and to output the fractional part of the target floating-point number based on the state of the multiply-accumulate operation.

2. The processor according to claim 1, characterized in that the multiply-accumulate unit comprises: Window status detection module; The window state detection module is used to output the state of the multiplication-addition operation as a first target state when the target floating-point number is greater than a first floating-point number threshold and less than a second floating-point number threshold; the floating-point number threshold includes the first floating-point number threshold and the second floating-point number threshold; the calculation window in the first target state includes the mantissa of the target floating-point number.

3. The processor according to claim 2, characterized in that, The window state detection module is further configured to output the state of the multiplication-addition operation as a second target state when at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, and the number of right shift bits is less than the number of bits threshold; the calculation window in the second target state contains the valid values ​​of the mantissa portion of the target floating-point number whose corresponding exponent is less than or equal to 0.

4. The processor according to claim 2, characterized in that, The window state detection module is further configured to output the state of the multiplication-addition operation as a third target state when at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, and the number of right shift bits is greater than or equal to the number of bits threshold; the calculation window in the third target state does not contain the valid value of the mantissa part of the target floating-point number whose corresponding exponent is less than or equal to 0.

5. The processor according to claim 3 or 4, characterized in that the processor comprises: Displacement calculation unit; The input port of the displacement value calculation unit is connected to the input port of the multiply-accumulate operation unit, and the output port of the displacement value calculation unit is connected to the input port of the window state detection module. The displacement calculation unit is used to determine the number of right shifts of the target floating-point number based on the mantissa bit width of the target floating-point number, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the first bit width threshold.

6. The processor according to any one of claims 2 to 4, characterized in that the multiply-accumulate unit further comprises: Addition exponent calculation module; The input port of the addition exponent calculation module is connected to the output port of the window state detection module; The addition exponent calculation module is used to determine the addition exponent based on the state of the multiplication-addition operation; the addition exponent is used to determine the fractional part of the target floating-point number. The state of the multiplication-addition operation is the first target state, and the addition exponent is the exponent of the target floating-point number; When the multiplication-addition operation is in either the second or third target state, the addition exponent is determined based on the exponent offset of the target floating-point number.

7. The processor according to any one of claims 2 to 4, characterized in that the multiply-accumulate unit further comprises: Addition mantissa calculation module; The input port of the addition mantissa calculation module and the input port of the addition exponent calculation module are connected in parallel to the output port of the window state detection module; The addition mantissa calculation module is used to determine the addition mantissa based on the state of the multiplication-addition operation; the addition mantissa is used to determine the fractional part of the target floating-point number. In the first target state of the multiplication-addition operation, the mantissa of the addition is determined based on the first addend and the second addend of the calculation window in the first target state. In the first target state, the first addend is a first floating-point value, and the second addend is the first number of bits truncated from the highest bit after the mantissa of the target floating-point number is placed to the highest bit of the calculation window. The first number of bits is determined based on the bit width of the calculation window in the first target state. When the multiplication-addition operation is in either the second target state or the third target state, the mantissa of the addition is determined based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number. The mantissa of the target floating-point number after placement is placed in the calculation window according to the right shift of the target floating-point number.

8. The processor according to any one of claims 2 to 4, characterized in that the processor further comprises: Selector; The selector is connected to the input of the processor and the output of the multiply-accumulate unit, respectively. The selector is used to output the floating-point value corresponding to the target floating-point number when the target floating-point number meets the preset conditions, and to output the decimal part of the target floating-point number when the target floating-point number does not meet the preset conditions.

9. A floating-point number processing method, characterized in that, The floating-point number processing method further includes: In response to a first signal for a target floating-point number, if the target floating-point number does not meet a preset condition, the state of a multiply-accumulate operation matching the target floating-point number is determined based on the size relationship between the target floating-point number and a floating-point number threshold. Based on the state of the multiplication-addition operation, the fractional part of the target floating-point number is output.

10. The floating-point number processing method according to claim 9, characterized in that, Determining the state of the multiply-accumulate operation matching the target floating-point number based on the size relationship between the target floating-point number and the floating-point number threshold includes at least one of the following steps: When the target floating-point number is greater than a first floating-point threshold and less than a second floating-point threshold, the state of the multiplication-addition operation is output as a first target state; the floating-point threshold includes the first floating-point threshold and the second floating-point threshold; the calculation window in the first target state includes the mantissa of the target floating-point number; If at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, the state of the multiplication-addition operation is determined based on the relationship between the number of bits shifted right of the target floating-point number and the number of bits threshold; the number of bits shifted right is used to retain the mantissa portion of the target floating-point number whose corresponding exponent is less than or equal to 0 in the calculation window.

11. The floating-point number processing method according to claim 10, characterized in that, Determining the state of the multiply-accumulate operation based on the relationship between the right shift bits of the target floating-point number and the bit threshold includes: The number of bits to right shift the target floating-point number is determined based on the mantissa bit width of the target floating-point number, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the first bit width threshold. If the number of right shifts is less than the number of bits threshold, the output state of the multiplication-addition operation is the second target state; the calculation window in the second target state contains the valid value of the mantissa portion of the corresponding exponent which is less than or equal to 0; If the number of right shifts is greater than or equal to the number of bits threshold, the output state of the multiplication-addition operation is the third target state; the calculation window in the third target state does not contain a valid value of the mantissa portion of the corresponding exponent which is less than or equal to 0.

12. The floating-point number processing method according to any one of claims 9 to 11, characterized in that, The step of outputting the fractional part of the target floating-point number based on the state of the multiplication-addition operation includes: Based on the state of the multiplication-addition operation, the mantissa and exponent of the addition are determined; Based on the sign bit of the target floating-point number, the mantissa of the addition, and the exponent of the addition, the fractional part of the target floating-point number is output.

13. The floating-point number processing method according to claim 12, characterized in that, Determining the mantissa and exponent based on the state of the multiplication-addition operation includes: When the state of the multiplication-addition operation is the first target state, the first floating-point value is assigned to the first addend of the calculation window in the first target state; The mantissa of the target floating-point number is placed in the highest bit of the calculation window in the first target state, and the first bit is truncated from the highest bit and assigned to the second addend of the calculation window in the first target state; the first bit is determined based on the bit width of the calculation window in the first target state, and the calculation window in the first target state contains the mantissa of the target floating-point number. Based on the first addend and the second addend, determine the last digit of the addition; Use the exponent of the target floating-point number as the addition exponent.

14. The floating-point number processing method according to claim 12, characterized in that, Determining the mantissa and exponent based on the state of the multiplication-addition operation includes: When the multiplication-addition operation is in the second target state, the mantissa of the target floating-point number is placed in the calculation window in the second target state according to the number of right shifts of the target floating-point number; The addition mantissa is determined based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number; The addition exponent is determined based on the exponent offset of the target floating-point number.

15. The floating-point number processing method according to claim 14, characterized in that, The step of determining the addition mantissa based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number includes: If the target floating-point number is determined to be negative based on the sign bit of the target floating-point number, the third floating-point value is assigned to the first addend of the calculation window in the second target state; Extract the second digit from the mantissa of the target floating-point number after it has been placed from the highest bit down, and assign it to the second addend of the calculation window in the second target state; Subtract the first addend and the second addend to obtain the last digit of the addition.

16. The floating-point number processing method according to claim 14, characterized in that, The step of determining the addition mantissa based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number includes: If the target floating-point number is determined to be positive based on the sign bit of the target floating-point number, the first floating-point value is assigned to the first addend of the calculation window in the second target state; Extract the third bit from the mantissa of the target floating-point number after it has been placed, excluding the highest bit, and assign it to the second addend of the calculation window in the second target state. The first addend and the second addend are added together to obtain the last digit of the addition.

17. The floating-point number processing method according to claim 12, characterized in that, Determining the mantissa and exponent based on the state of the multiplication-addition operation includes: When the multiplication-addition operation is in the third target state, the mantissa of the target floating-point number is placed in the calculation window in the third target state according to the number of right shifts of the target floating-point number. The addition mantissa is determined based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number; The addition exponent is determined based on the exponent offset of the target floating-point number.

18. The floating-point number processing method according to claim 9, characterized in that, The floating-point number processing method further includes: If the target floating-point number meets the preset conditions, the floating-point value corresponding to the target floating-point number is output.

19. The floating-point number processing method according to claim 18, characterized in that, The floating-point number processing method further includes: If the target floating-point number is 0, or if the fractional part of the target floating-point number has no valid value but the integer part has a valid value, then the target floating-point number is determined to meet the first preset condition. If the target floating-point number is infinity (INF) or is not a number (NaN), then the target floating-point number is determined to satisfy a second preset condition; the preset condition includes at least one of the first preset condition and the second preset condition.

20. The floating-point number processing method according to claim 18, characterized in that, When the target floating-point number meets the preset condition, the floating-point value corresponding to the target floating-point number is output, including at least one of the following: If the target floating-point number satisfies the first preset condition, output the first floating-point value; If the target floating-point number meets the second preset condition, the second floating-point value is output.

21. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program performs the steps of the method according to any one of claims 9 to 20.

22. A computer program product, characterized in that, The computer program product includes a computer program that, when read and executed by a computer, implements the steps of the method according to any one of claims 9 to 20.

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