Data processing method, programmable logic device and processor

Abstract

The embodiment of the invention provides a data processing method, which comprises the following steps of: converting an e index calculation task into an index calculation task aiming at a target fixed point number, and splitting the index calculation task aiming at the target fixed point number into a shift task and index calculation aiming at a target decimal part, an index calculation task aiming at the target decimal part is approximate to linear function calculation (namely addition and multiplication based on calculation parameters), so that the calculation process can be greatly simplified, and simple multiplication and addition are executed by utilizing a digital signal processor based on the calculation parameters corresponding to the target decimal part; compared with the prior art, the method has the advantages that operation steps and required computing resources are reduced, all computing resources of one digital signal processor are fully utilized in the process, the whole task process can be performed in series, judgment branches and data rereading do not exist, the overall computing efficiency is improved, and hardware resource consumption is reduced.

Description

Technical Field

[0001] This specification relates to the field of computer technology, specifically to artificial intelligence technology within the field of computer technology, and more specifically to a data processing method, a programmable logic device, and a processor. Background Technology

[0002] With the rise of deep learning, the number of layers in neural networks is constantly increasing, and the parameter scale is becoming increasingly large. Training models also requires a large amount of computational resources. As the basic operation of each neuron in a neural network, the computational efficiency of the activation function directly affects the training speed of the model. In particular, the computational overhead of complex nonlinear activation functions is enormous, severely restricting the real-time performance of neural networks. Therefore, it is necessary to optimize the calculation method of activation functions and improve their computational efficiency. Summary of the Invention

[0003] This specification provides a data processing method, a programmable logic device, and a processor to improve the computational efficiency of activation functions.

[0004] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0005] Firstly, a data processing method is provided, applied to a special function unit, the special function unit including a digital signal processor, the digital signal processor including a multiplier, an adder, and a pre-subtractor; the data processing method includes:

[0006] In response to an e-exponential calculation task containing input data, the e-exponential calculation task is converted into an exponential calculation task for a target fixed-point number; the target fixed-point number corresponds to the input data.

[0007] Based on the target fixed-point number and its integer part, the target decimal part is obtained using the pre-subtractor; the target decimal part includes the difference between the target fixed-point number and the rounding result, and the difference in the rounding result includes the result of rounding the target fixed-point number down;

[0008] Based on the calculation parameters corresponding to the target decimal part, the first part of the exponentiation calculation task is calculated using the adder and the multiplier; the calculation parameters include the coefficients of the linear function corresponding to the exponentiation calculation task.

[0009] The first part is shifted based on the integer part of the target fixed-point number to obtain the calculation result of the e-exponential calculation task.

[0010] Secondly, one embodiment of this specification provides a programmable logic device, including a computing unit and a digital signal processor, wherein the digital signal processor includes a multiplier, an adder, and a pre-subtractor, wherein...

[0011] The computing unit is configured to: in response to an e-exponential calculation task containing input data, convert the e-exponential calculation task into an exponential calculation task for a target fixed-point number; the target fixed-point number corresponds to the input data;

[0012] The digital signal processor is configured to: obtain the target fractional part based on the target fixed-point number and its integer part using the pre-subtractor; the target fractional part includes the difference between the target fixed-point number and the rounding result, the difference in the rounding result including the result of rounding down the target fixed-point number; and calculate the first part of the exponentiation calculation task based on the calculation parameters corresponding to the target fractional part using the adder and the multiplier; the calculation parameters include the coefficients of the linear function corresponding to the exponentiation calculation task.

[0013] The calculation unit is further configured to: shift the first part based on the integer part of the target fixed-point number to obtain the calculation result of the e-exponential calculation task.

[0014] Thirdly, one embodiment of this specification also provides a processor including a programmable logic device as described in any of the preceding claims, wherein the programmable logic device serves as a special function unit in the processor.

[0015] Fourthly, one embodiment of this specification also provides a computing device including a processor as described in any of the preceding claims.

[0016] As can be seen from the above technical solutions, the data processing method provided in this specification optimizes the e-exponential calculation task involved in the calculation of special functions such as activation functions, improving the computational efficiency and hardware friendliness of the e-exponential calculation task. Specifically, in the data processing method, when executing the e-exponential calculation task, the e-exponential calculation task is converted into an exponential calculation task for a target fixed-point number. Then, based on the target fixed-point number and its integer part, the target fractional part is obtained using the pre-subtraction unit. The target fractional part includes the difference between the target fixed-point number and the rounding result. The difference in the rounding result includes the result of rounding down the target fixed-point number. This step allows the target fractional part to be obtained without considering whether the target fixed-point number is positive or negative. Finally, based on the calculation parameters corresponding to the target fractional part, the first part of the exponential calculation task is calculated using the adder and the multiplier, and the first part is shifted based on the integer part of the target fixed-point number to obtain the calculation result of the e-exponential calculation task. In other words, in this data processing method, after converting the e-exponential calculation task into an exponential calculation task for a target fixed-point number, the exponential calculation task for the target fixed-point number is further divided into a shift task and an exponential calculation task for the target decimal part. The exponential calculation task for the target decimal part is approximately a linear function calculation (i.e., addition and multiplication operations based on calculation parameters), which greatly simplifies the calculation process. It only requires performing simple multiplication and addition operations using a digital signal processor based on the calculation parameters corresponding to the target decimal part, reducing the number of calculation steps and the required computing resources. At the same time, the above process makes full use of all the computing resources of a digital signal processor. The entire task process can be performed serially without decision branches or rereading of data, which helps to improve the overall computing efficiency and reduce hardware resource consumption. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 A schematic diagram of a feasible system architecture for implementing the data processing methods provided in this specification, as part of the embodiments of this specification;

[0019] Figure 2 A flowchart illustrating a data processing method provided for embodiments of this specification;

[0020] Figure 3This is a schematic diagram of the structure of a programmable logic device provided for embodiments of this specification. Detailed Implementation

[0021] Unless otherwise defined, the technical or scientific terms used in the embodiments of this specification shall have the ordinary meaning understood by one of ordinary skill in the art to which this specification pertains. The terms "first," "second," and similar terms used in the embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to avoid confusion of constituent elements.

[0022] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two," and "including" is interpreted as open-ended or encompassing, that is, "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this specification. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0023] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0024] System Architecture

[0025] refer to Figure 1 , Figure 1 A schematic diagram of a feasible system architecture for implementing the data processing method provided in this specification is shown. This system architecture may include a computing core and special function units (SFUs). The computing core can perform arithmetic and logical operations, including integer and floating-point operations; the special function units can perform complex mathematical functions, such as exponential, trigonometric, and logarithmic functions, and can be used to accelerate the calculation of these functions. In some cases, special function units can work in conjunction with the computing core to complete computational tasks such as deep learning and inference acceleration. There can be multiple computing cores and special function units.

[0026] In some implementations, in order to optimize task processing efficiency and internal communication / scheduling efficiency, the system architecture may also include any one or more of the following structures: instruction cache, wrap scheduler, dispatch unit, register file, load / store unit, interconnect network, shared memory, and cache.

[0027] Figure 1 The system architecture shown can be implemented as various types of processors such as Graphics Processing Unit (GPU), Neural Processing Unit (NPU), and Tensor Processing Unit (TPU). This specification does not limit this; the specific implementation depends on the actual situation.

[0028] Overview

[0029] With the continuous development of artificial intelligence technology, AI models inevitably involve a large number of activation function calculations during inference and training. Activation function calculations are complex and difficult to optimize, thus consuming significant computational and hardware resources. Many activation functions include exponential (e) calculations, which account for the majority of computational and hardware overhead in activation function calculations. Reducing the computational and hardware overhead of exponential (e) calculations is crucial for accelerating activation function computation.

[0030] Explicitly calculating the exponential function e is difficult in hardware, possibly due to the following reasons: 1. Hardware calculation of the exponential function e involves infinite expansion or complex iterative operations (such as Taylor expansion), requiring a large amount of resources for multiplication, addition, and registers to store intermediate results, and the calculation process is quite cumbersome. 2. The exponential function e has nonlinear characteristics; its output value increases or decreases exponentially with changes in the input value, making it difficult to directly model this nonlinear relationship using simple linear circuits or combinations of logic gates.

[0031] To address the hardware challenges of explicitly calculating the exponent e, and to reduce the computational resources and hardware overhead required for e-exponent calculation, the inventors provide a data processing method applicable to tasks such as... Figure 1The special function unit in the system architecture shown considers that the main purpose of the activation function is to introduce nonlinearity, enabling the artificial intelligence model to learn complex nonlinear relationships. Therefore, even if there is some error in the calculation result of the exponent e in the activation function, as long as the nonlinear characteristics are preserved, the requirements of the artificial intelligence model for the activation function can be met. That is, the calculation result of the exponent e calculation task can be allowed to have a certain degree of error in the calculation process of the activation function. Based on the above characteristics, when processing the exponent e calculation task, this data method first converts the exponent e calculation task into an exponent calculation task for the target fixed-point number. Since fixed-point number arithmetic requires a smaller circuit scale and has a faster operation speed than floating-point number arithmetic, converting the exponent e calculation task into an exponent calculation task for the target fixed-point number can greatly reduce the data storage requirements and computational complexity, and reduce hardware resource consumption and computation time.

[0032] Then, by fully utilizing all the hardware resources of the digital signal processor in the special function unit, the steps required for calculating the e-exponent are implemented. Specifically, based on the target fixed-point number and its integer part, the target fractional part is obtained using the pre-subtractor. The target fractional part includes the difference between the target fixed-point number and the rounding result, where the difference includes the result of rounding down the target fixed-point number. This step allows the target fractional part to be obtained without considering the sign of the target fixed-point number. Finally, based on the calculation parameters corresponding to the target fractional part, the first part of the exponent calculation task is calculated using the adder and the multiplier, and the first part is shifted based on the integer part of the target fixed-point number to obtain the calculation result of the e-exponent calculation task. In other words, in this data processing method, after converting the e-exponential calculation task into an exponential calculation task for a target fixed-point number, the exponential calculation task for the target fixed-point number is further divided into a shift task and an exponential calculation task for the target decimal part. The exponential calculation task for the target decimal part is approximately a linear function calculation (i.e., addition and multiplication operations based on calculation parameters), which greatly simplifies the calculation process. It only requires performing simple multiplication and addition operations using a digital signal processor based on the calculation parameters corresponding to the target decimal part, reducing the number of calculation steps and the required computing resources. At the same time, the above process makes full use of all the computing resources of a digital signal processor. The entire task process can be performed serially without decision branches or rereading of data, which helps to improve the overall computing efficiency and reduce hardware resource consumption.

[0033] Based on the above concept, this specification provides a data processing method, which will be described exemplarily below with reference to the accompanying drawings.

[0034] Exemplary methods

[0035] To be applied Figure 1 Taking a special function unit as an example, this specification provides a data processing method. The special function unit includes a digital signal processor, which includes a multiplier, an adder, and a pre-subtractor. Figure 2 As shown, the data processing method includes:

[0036] S201: In response to an e-exponential calculation task containing input data, the e-exponential calculation task is converted into an exponential calculation task for a target fixed-point number; the target fixed-point number corresponds to the input data;

[0037] S202: Based on the target fixed-point number and the integer part of the target fixed-point number, the target decimal part is obtained using the pre-subtractor; the target decimal part includes the difference between the target fixed-point number and the rounding result, and the difference between the rounding results includes the result of rounding the target fixed-point number down;

[0038] S203: Based on the calculation parameters corresponding to the target decimal part, calculate the first part of the exponentiation calculation task using the adder and the multiplier; the calculation parameters include the coefficients of the linear function corresponding to the exponentiation calculation task;

[0039] S204: Shift the first part based on the integer part of the target fixed-point number to obtain the calculation result of the e-exponential calculation task.

[0040] In step S201, the e-exponential calculation task containing the input data can be... Figure 1 The computational core in the middle sends the data to a special function unit, or it can be... Figure 1 This specification does not limit the input data sent to the special function unit by other external processors; the specific implementation depends on the actual situation. The input data can be represented in floating-point form. When converting the exponentiation task of e into an exponentiation task for a target fixed-point number, the change-of-base formula can be used. The exponentiation task for the target fixed-point number can be an integer exponentiation task for the target fixed-point number, such as an exponentiation task for the target fixed-point number of 2. This simplifies the complexity of the computation task. This is because e is an irrational number and cannot be accurately represented by simple fractions or finite decimals. Calculating the exponentiation of e requires more approximation and iteration steps. Integer computation tasks, especially exponentiation tasks for the number of 2, can be efficiently implemented through operations such as bit shifting, thereby reducing the complexity of the computation task and reducing the consumption of computing resources.

[0041] The pre-subtractor is an important component within a digital signal processor (DSP). It can be located at the beginning of the data path to preprocess data before multiplication operations. In step S202, leveraging the pre-subtractor's location at the beginning of the data path, a subtraction operation can be performed to obtain the target decimal part. This target decimal part includes the difference between the target fixed-point number and the rounding result. The difference includes the result of rounding down the target fixed-point number. This eliminates the need to determine whether the target fixed-point number is positive or negative when obtaining the target decimal part. Even if the target fixed-point number is negative, a positive target decimal part can be obtained after rounding down and subtraction. This avoids introducing positive / negative fixed-point number judgment logic into the DSP's internal data processing, simplifying the processing flow and improving adaptability to the DSP's internal hardware structure.

[0042] In step S203, the calculation parameters corresponding to the target decimal part can be the calculation parameters of a linear function (i.e., the calculation parameters can include the slope and bias). Thus, the exponent calculation of the target decimal part can be approximated as a linear function calculation, and the multipliers and adders inside the digital signal processor can meet the requirements of linear function calculation. In some embodiments, the correspondence between the decimal part and the calculation parameters can be pre-stored in memory. After the target decimal part is determined, the memory can be queried using the target decimal part as an index to obtain the calculation parameters corresponding to the target decimal part. More specifically, in some embodiments, the correspondence between the decimal part and the calculation parameters stored in memory can be obtained by segmented storage, that is, dividing the value range of the (0,1) decimal part into multiple intervals, each interval corresponding to a calculation parameter, which can greatly reduce the amount of data stored.

[0043] In step S204, the integer part of the target fixed-point number determines the number of shifts. The final calculation result is obtained by shifting the first part calculated above. In steps S201-S204, step S201 can be considered a preprocessing procedure for the input data, which can be performed outside the digital signal processor (DSP). The rounding process that may be involved in step S202 and step S204 can also be performed outside the DSP. Apart from these steps, all other steps can be performed serially within the DSP. Thus, by utilizing the existing hardware resources within the DSP to preprocess the input data and shift the DSP's output, the final result can be obtained. This achieves serial execution of the calculation process, eliminating the need for judgment processes and secondary data readings, thereby improving the method's execution efficiency, reducing computational resource consumption, and achieving the goal of providing a hardware-friendly data processing method.

[0044] In summary, to address the hardware challenges of explicitly calculating the exponent e, and to reduce the computational resources and hardware overhead required for e-exponent calculation, the inventors provide a data processing method applicable to tasks such as... Figure 1 The special function unit in the system architecture shown considers that the main purpose of the activation function is to introduce nonlinearity, enabling the artificial intelligence model to learn complex nonlinear relationships. Therefore, even if there is some error in the calculation result of the exponent e in the activation function, as long as the nonlinear characteristics are preserved, the requirements of the artificial intelligence model for the activation function can be met. That is, the calculation result of the exponent e calculation task can be allowed to have a certain degree of error in the calculation process of the activation function. Based on the above characteristics, when processing the exponent e calculation task, this data method first converts the exponent e calculation task into an exponent calculation task for the target fixed-point number. Since fixed-point number arithmetic requires a smaller circuit scale and has a faster operation speed than floating-point number arithmetic, converting the exponent e calculation task into an exponent calculation task for the target fixed-point number can greatly reduce the data storage requirements and computational complexity, and reduce hardware resource consumption and computation time.

[0045] Then, by fully utilizing all the hardware resources of the digital signal processor in the special function unit, the steps required for calculating the e-exponent are implemented. Specifically, based on the target fixed-point number and its integer part, the target fractional part is obtained using the pre-subtractor. The target fractional part includes the difference between the target fixed-point number and the rounding result, where the difference includes the result of rounding down the target fixed-point number. This step allows the target fractional part to be obtained without considering the sign of the target fixed-point number. Finally, based on the calculation parameters corresponding to the target fractional part, the first part of the exponent calculation task is calculated using the adder and the multiplier, and the first part is shifted based on the integer part of the target fixed-point number to obtain the calculation result of the e-exponent calculation task. In other words, in this data processing method, after converting the e-exponential calculation task into an exponential calculation task for a target fixed-point number, the exponential calculation task for the target fixed-point number is further divided into a shift task and an exponential calculation task for the target decimal part. The exponential calculation task for the target decimal part is approximately a linear function calculation (i.e., addition and multiplication operations based on calculation parameters), which greatly simplifies the calculation process. It only requires performing simple multiplication and addition operations using a digital signal processor based on the calculation parameters corresponding to the target decimal part, reducing the number of calculation steps and the required computing resources. At the same time, the above process makes full use of all the computing resources of a digital signal processor. The entire task process can be performed serially without decision branches or rereading of data, which helps to improve the overall computing efficiency and reduce hardware resource consumption.

[0046] As described above, one embodiment of this specification provides a feasible way to determine calculation parameters. Specifically, the special function unit further includes a memory that stores a correspondence table to describe the correspondence between the decimal part and the calculation parameters, which include slope and bias.

[0047] The process of obtaining the calculation parameters corresponding to the target decimal part includes:

[0048] Based on the target decimal part, the corresponding relationship table is queried to obtain the calculation parameters corresponding to the target decimal part;

[0049] The first part of the exponentiation calculation task, based on the calculation parameters corresponding to the target decimal part and utilizing the adder and the multiplier, includes:

[0050] The multiplier is used to calculate the product of the target decimal part and the slope to obtain the product result;

[0051] The product result is added to the bias using the adder to obtain the first part of the exponent calculation task.

[0052] The memory can be a non-volatile memory such as ROM (Read-Only Memory), and the mapping table in the memory can be pre-designed and stored in the memory according to requirements. Since the mapping table is persistently stored in the memory, the data processing method only needs to load or read the mapping table from the memory and perform a lookup each time it is executed, without the need for frequent read, write and update, thus reducing the complexity and power consumption of the storage system.

[0053] In the calculation of the first part, due to the approximation of a linear function, subsequent calculations are performed based on the calculation parameters corresponding to the decimal part of the target. This allows the first part to be performed serially using adders and multipliers. While making full use of the internal computing resources of the digital signal processor, this avoids the data rereading that may be involved in the activation function calculation process in related technologies, thus improving the execution efficiency of the method. For example, for the Sigmoid activation function, in related technologies, when the input data is a very large negative number, the calculation result of the exponent e may overflow (the calculation result is INF), while when the input data is a very large positive number, the calculation result of the exponent e may approach 0 and will not overflow. However, direct implementation may lead to numerical problems due to extreme inputs. Therefore, in the calculation process of this activation function, the method avoids overflow by segmenting the calculation: when the input data is greater than or equal to 0, the calculation is performed directly based on the Sigmoid activation function expression; when the input data is less than 0, a modified expression of the Sigmoid activation function is calculated to avoid calculating the exponent of large negative numbers. However, in this case, it may involve rereading the data. In other words, if the activation function calculation method in the relevant technology is followed, it not only involves the judgment logic, but may also involve the rereading of data, which makes the calculation process complicated.

[0054] Accordingly, as described above, in one embodiment, the exponential calculation task for the target fixed-point number includes:

[0055] The task of calculating the exponent for the integer part of the target fixed-point number and the task of calculating the exponent for the fractional part of the target fixed-point number;

[0056] The first part of the exponent calculation task includes the calculation results of the exponent calculation task for the decimal part of the target fixed-point number.

[0057] In this embodiment, the exponentiation calculation task for the target fixed-point number is divided into two parts. The exponentiation calculation task for the integer part of the target fixed-point number can be completed by shifting operations, while the exponentiation calculation task for the fractional part of the target fixed-point number can be completed by the linear function approximation method described above. In this way, the complex exponentiation calculation task is simplified into two hardware-friendly calculation tasks, which helps to simplify the complexity of the method and reduce the computing resources required to execute the method.

[0058] In one implementation, a feasible representation of a correspondence table is provided, specifically, the correspondence table includes:

[0059] Multiple decimal intervals and calculation parameters corresponding to each decimal interval.

[0060] In this embodiment, in addition to approximating the exponent calculation task for the decimal part as a linear function, the correspondence table storing the calculation parameters of the linear function and the correspondence of the decimal part is optimized. Specifically, the correspondence table is stored in a segmented manner, dividing the value interval (0,1) into multiple decimal intervals, such as (0,0.001], (0.001,0.002], (0.002,0.003], ..., (0.991,0.992], ..., (0.999,1). Each interval corresponds to a calculation parameter. In this way, the continuous function value can be discretized into a finite piecewise function. The number of parameters required to be stored is much smaller than that of the lookup method that directly stores the function value, which helps to reduce the amount of data to be stored and lowers the hardware requirements of this method.

[0061] In one implementation, converting the e-exponential calculation task into an exponential calculation task for a target fixed-point number in response to the e-exponential calculation task containing input data includes:

[0062] The e-exponential calculation task is converted into a base-2 exponential calculation task for a target fixed-point number, which is the product of the input data and log2e.

[0063] As mentioned earlier, the task of calculating the exponent of a target fixed-point number with base 2 can be transformed into a task of calculating the exponent of the integer part and a task of calculating the exponent of the fractional part. The task of calculating the exponent of the integer part can be transformed into a task of calculating the exponent of the fractional part, which can be approximated as a task of calculating a linear function, thereby greatly reducing the computational resources required for the calculation process.

[0064] In one implementation, obtaining the target decimal part using the pre-subtractor based on the target fixed-point number and its integer part includes:

[0065] The target fixed-point number is rounded down to obtain the rounding result;

[0066] Using the pre-subtractor, the difference between the target fixed-point number and the rounding result is calculated to obtain the target decimal part.

[0067] In this embodiment, as mentioned above, by first rounding down and then subtracting from the rounded result to obtain the target decimal part, it is not necessary to distinguish between the positive and negative signs of the target fixed-point number, thus achieving a unified calculation process, avoiding the introduction of logical judgments and rereading of data, thereby simplifying the complexity of the method and reducing the computational resources required for the calculation process.

[0068] For example, assuming the target fixed-point number is 2.3, the exponent calculation task for the target fixed-point number includes 2...2.3 The integer part of the target fixed-point number is 2. 2.3 rounded down to 2 gives the decimal part of the target fixed-point number as 2.3 - 2 = 0.3. Therefore, the task of calculating the exponent of the target fixed-point number is ultimately transformed into 2. 2 ×2 0.3 =2 2.3 .

[0069] Assuming the target fixed-point number is -2.3, the exponent calculation task for the target fixed-point number includes 2... -2.3 The integer part of the target fixed-point number is -2. Rounding -2.3 down to -3, the decimal part of the target fixed-point number is -2.3 - (-3) = 0.7. Therefore, the task of calculating the exponent of the target fixed-point number is ultimately transformed into 2. -3 ×2 0.7 =2 2.3 .

[0070] Exemplary devices

[0071] Accordingly, embodiments of this specification also provide a programmable logic device, including: a computing unit and a digital signal processor, wherein the digital signal processor includes a multiplier, an adder, and a pre-subtractor, wherein,

[0072] The computing unit is configured to: in response to an e-exponential calculation task containing input data, convert the e-exponential calculation task into an exponential calculation task for a target fixed-point number; the target fixed-point number corresponds to the input data;

[0073] The digital signal processor is configured to: obtain the target fractional part based on the target fixed-point number and its integer part using the pre-subtractor; the target fractional part includes the difference between the target fixed-point number and the rounding result, the difference in the rounding result including the result of rounding down the target fixed-point number; and calculate the first part of the exponentiation calculation task based on the calculation parameters corresponding to the target fractional part using the adder and the multiplier; the calculation parameters include the coefficients of the linear function corresponding to the exponentiation calculation task.

[0074] The calculation unit is further configured to: shift the first part based on the integer part of the target fixed-point number to obtain the calculation result of the e-exponential calculation task.

[0075] The computing unit can be hardware within a programmable logic device. This computing unit, in conjunction with a digital signal processor, can implement the data processing method described in any of the above embodiments. The programmable logic device can include at least one of a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), etc., as long as the programmable logic device includes a digital signal processor and a computing unit. This specification does not impose any limitations on this; the specific choice depends on the actual situation.

[0076] In one embodiment, the programmable logic device further includes a memory storing a correspondence table describing the correspondence between the fractional part and calculation parameters, the calculation parameters including slope and bias.

[0077] In one implementation, reference is still made to Figure 3 The computation unit includes: a multiplication unit, a rounding unit, a decoding unit, and a shifting unit; wherein,

[0078] The multiplication unit is configured to calculate the product of the input data and log2e to obtain the target fixed-point number;

[0079] The rounding unit is configured to: round down the target fixed-point number to obtain the integer part of the target fixed-point number, and transmit the integer part of the target fixed-point number to the digital signal processor and the shift unit;

[0080] The digital signal processor is further configured to transmit the target fractional part to the decoding unit after obtaining the target fractional part using the pre-subtractor; and to transmit the product of the target fractional part and the slope to the shift unit after calculating the product result using the multiplier.

[0081] The decoding unit is configured to: query the corresponding relationship table according to the target decimal part to obtain the calculation parameters corresponding to the target decimal part, and transmit the calculation parameters corresponding to the target decimal part to the digital signal processor;

[0082] The shift unit is configured to shift the first part based on the integer part of the target fixed-point number to obtain the calculation result of the e-exponential calculation task.

[0083] As mentioned above, the computing unit and digital signal processor in the programmable logic device can cooperate to implement the data processing method described in any of the above embodiments. For the relevant limitations of each step, please refer to the relevant descriptions above, which will not be repeated here.

[0084] This specification provides a specific feasible implementation of a data processing method, based on, for example, the execution process of a data processing method. Figure 3 The illustrated programmable logic device implementation may include a digital signal processor, such as a DSP48E1. Prior to deployment, a mapping table may be stored in the programmable logic device's memory (e.g., ROM). This process may include:

[0085] Step 1: Preprocess the data in the multiplication unit outside the digital signal processor to obtain the input value required by the digital signal processor. The data in the preprocessing process can be in fixed-point format to reduce hardware resource overhead.

[0086] The preprocessing process may include:

[0087] Step 1.1: Among nonlinear activation functions, the e-exponential function has a large computational cost. In this embodiment, the e-exponential function is transformed into a base-2 exponential function using a base-2 substitution formula, enabling efficient computation on the DSP48E1. The formula is as follows:

[0088]

[0089] In the above formula, the left side e x In this implementation, 'x' represents the floating-point input; 'q' represents the integer part of 'x*log₂e'; and 'r' represents the fractional part of 'x*log₂e'. 'qr' is the target fixed-point number. This implementation first calculates the product of the input 'x' and the constant 'log₂e' in the multiplication unit. To reduce storage requirements, this implementation uses a fixed-point number 'qr' instead of the floating-point result. Here, 'q' represents the integer part, and 'r' represents the fractional part.

[0090] Step 1.2: The target fixed-point number mentioned above will be output to the rounding unit and the digital signal processor. The rounding unit performs a round-down operation on this embodiment to obtain the integer part q, which will be output to the digital signal processor and the shift unit.

[0091] Step 2: The digital signal processor receives the target fixed-point number and the integer part q. After calculation by the pre-subtractor, the output r is obtained, which is the target fractional part. r will be output to the decoding unit.

[0092] Step 3: The decoding unit can calculate the subscript value of the memory (e.g., the memory address) based on the value of r. Based on the calculation result, it finds the calculation parameters (slope and bias) corresponding to the subscript value in the memory and outputs the calculation parameters to the digital signal processor.

[0093] Step 4: The digital signal processor uses its internal multipliers and adders to calculate the product of r and Slope, and adds the product result to Bias to obtain the first part;

[0094] Step 5: The first part enters the shift unit to perform the shift operation and outputs the final result. The shift parameter is the integer part q obtained in step 1.2.

[0095] Exemplary processor

[0096] This specification also provides a processor that includes a programmable logic device as described in any of the above embodiments, wherein the programmable logic device serves as a special function unit in the processor.

[0097] As mentioned above, the processor can be a graphics processor, tensor processor, or other processor suitable for tasks such as inference calculations. The processor can also be a general-purpose processor or other similar processor. This specification does not limit the specific type of processor and the choice depends on the actual situation.

[0098] Exemplary computing device

[0099] This specification also provides a computing device including a processor as described in any of the above embodiments. The number of processors can be one or more, and the types of the multiple processors can be the same or different; this specification does not limit this, but depends on the specific circumstances.

[0100] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods outlined in this specification. While the descriptions are specific and detailed, they should not be construed as limiting the scope of the solutions provided in this specification. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection for this patent should be determined by the appended claims.

Claims

1. A data processing method, characterized in that, The method is applied to a special function unit, which includes a digital signal processor (DSP) comprising a multiplier, an adder, and a pre-subtractor; the data processing method includes: In response to an e-exponential calculation task containing input data, the e-exponential calculation task is converted into an exponential calculation task for a target fixed-point number; the target fixed-point number corresponds to the input data. Based on the target fixed-point number and its integer part, the target decimal part is obtained using the pre-subtractor; the target decimal part includes the difference between the target fixed-point number and the rounding result, and the difference in the rounding result includes the result of rounding the target fixed-point number down; Based on the calculation parameters corresponding to the target decimal part, the first part of the exponentiation calculation task is calculated using the adder and the multiplier; the calculation parameters include the coefficients of the linear function corresponding to the exponentiation calculation task. The first part is shifted based on the integer part of the target fixed-point number to obtain the calculation result of the e-exponential calculation task.

2. The method according to claim 1, characterized in that, The special function unit also includes a memory that stores a correspondence table. The correspondence table describes the correspondence between the decimal part and the calculation parameters, which include the slope and the bias. The process of obtaining the calculation parameters corresponding to the target decimal part includes: Based on the target decimal part, the corresponding relationship table is queried to obtain the calculation parameters corresponding to the target decimal part; The first part of the exponentiation calculation task, based on the calculation parameters corresponding to the target decimal part and utilizing the adder and the multiplier, includes: The multiplier is used to calculate the product of the target decimal part and the slope to obtain the product result; The product result is added to the bias using the adder to obtain the first part of the exponent calculation task.

3. The method according to claim 2, characterized in that, The exponential calculation task for the target fixed-point number includes: The task of calculating the exponent for the integer part of the target fixed-point number and the task of calculating the exponent for the fractional part of the target fixed-point number; The first part of the exponent calculation task includes the calculation results of the exponent calculation task for the decimal part of the target fixed-point number.

4. The method according to claim 2, characterized in that, The correspondence table includes: Multiple decimal intervals and calculation parameters corresponding to each decimal interval.

5. The method according to claim 1, characterized in that, The step of converting the e-exponential calculation task into an exponential calculation task for a target fixed-point number in response to the e-exponential calculation task containing input data includes: The e-exponential calculation task is converted into a base-2 exponential calculation task for a target fixed-point number, which is the product of the input data and log2e.

6. The method according to any one of claims 1 to 5, characterized in that, The step of obtaining the target decimal part based on the target fixed-point number and its integer part using the pre-subtractor includes: The target fixed-point number is rounded down to obtain the rounding result; Using the pre-subtractor, the difference between the target fixed-point number and the rounding result is calculated to obtain the target decimal part.

7. A programmable logic device, characterized in that, It includes a computing unit and a digital signal processor, wherein the digital signal processor includes multipliers, adders, and pre-subtractors, wherein... The computing unit is configured to: in response to an e-exponential calculation task containing input data, convert the e-exponential calculation task into an exponential calculation task for a target fixed-point number; the target fixed-point number corresponds to the input data; The digital signal processor is configured to: obtain the target fractional part based on the target fixed-point number and its integer part using the pre-subtractor; the target fractional part includes the difference between the target fixed-point number and the rounding result, the difference in the rounding result including the result of rounding down the target fixed-point number; and calculate the first part of the exponentiation calculation task based on the calculation parameters corresponding to the target fractional part using the adder and the multiplier; the calculation parameters include the coefficients of the linear function corresponding to the exponentiation calculation task. The calculation unit is further configured to: shift the first part based on the integer part of the target fixed-point number to obtain the calculation result of the e-exponential calculation task.

8. The programmable logic device according to claim 7, characterized in that, Also includes: The memory stores a correspondence table that describes the correspondence between the decimal part and the calculation parameters, including the slope and the bias.

9. The programmable logic device according to claim 8, characterized in that, The computation unit includes: a multiplication unit, a rounding unit, a decoding unit, and a shifting unit; wherein... The multiplication unit is configured to calculate the product of the input data and log2e to obtain the target fixed-point number; The rounding unit is configured to: round down the target fixed-point number to obtain the integer part of the target fixed-point number, and transmit the integer part of the target fixed-point number to the digital signal processor and the shift unit; The digital signal processor is further configured to transmit the target fractional part to the decoding unit after obtaining the target fractional part using the pre-subtractor; and to transmit the product of the target fractional part and the slope to the shift unit after calculating the product result using the multiplier. The decoding unit is configured to: query the corresponding relationship table according to the target decimal part to obtain the calculation parameters corresponding to the target decimal part, and transmit the calculation parameters corresponding to the target decimal part to the digital signal processor; The shift unit is configured to shift the first part based on the integer part of the target fixed-point number to obtain the calculation result of the e-exponential calculation task.

10. A processor, characterized in that, include: The programmable logic device according to any one of claims 7 to 9, wherein the programmable logic device serves as a special function unit in the processor.

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